Analog Electronic Circuits (18EI33), 3rd Sem EIE

Analog Electronic
Circuits
(18EI33)
rd
3 Sem EIE
Module - 1:
DC Biasing - BJTs
DC Biasing - FETs

P Manohar
Associate Professor
Dept. of EIE
RNSIT
P Manohar, Associate Professor, Dept. of EIE, RNSIT Page 1
 Analog Electronic Circuits (18EI33), 3rd Sem EIE

Syllabus

P Manohar, Associate Professor, Dept. of EIE, RNSIT Page 2

 Analog Electronic Circuits (18EI33), 3rd Sem EIE

1. DC Biasing - BJTs (Problems)

1. Fixed-Bias configuration
2. Emitter-bias configuration
3. Voltage-Divider Biasing
4. Emitter Follower configuration

2. DC Biasing - FETs (Problems)

1. Fixed-Bias configuration
2. Self-Bias configuration
3. Voltage-Divider Biasing

P Manohar, Associate Professor, Dept. of EIE, RNSIT Page 3

 Analog Electronic Circuits (18EI33), 3rd Sem EIE

1 DC Biasing - BJTs
Introduction:
Common Emitter (CE) configuration

Fig.1.1: Common Emitter Configuration

I E  I B  IC VBE  0.7V Emitter Base Junction - Forward biased

Collector Base Junction - Reverse biased
I C   dc I B I E  (  1) I B  I C

1. Fixed Bias Configuration:

Fixed Bias Circuit:

Fig. 1.2: Fixed Bias Circuit

P Manohar, Associate Professor, Dept. of EIE, RNSIT Page 4

 Analog Electronic Circuits (18EI33), 3rd Sem EIE

Fig. 1.3: DC equivalent of Fig. 1.6

Base Emitter Loop:

 VCC  I B RB  VBE  0

-----(1)
VBE  VB  VE
Since VE  0V

---------(2)
Fig.1.4: Base-Emitter Loop

Collector–Emitter Loop:

---------(3)

 VCC  I C RC  VCE  0

-------(4)

VCE  VC  VE
Since VE = 0 V,
Fig.1.5: Collector-Emitter Loop
--------(5)

P Manohar, Associate Professor, Dept. of EIE, RNSIT Page 5

 Analog Electronic Circuits (18EI33), 3rd Sem EIE

Load Line Analysis:

The network equation that relates IC and VCE is

-----------(1)
By substituting IC = 0 mA in Eq (1), we find that
VCE  VCC  (0) RC

-------(2) defines one point for the load line

By substituting VCE = 0 V in Eq (1), we find that
0  VCC  I C RC

---------(3) defines another point for the load line

Fig. 1.6. Fixed Bias Load line

P - 1.1 Determine the following for the fixed-bias configuration of Fig. 1.7.
(a) IBQ and ICQ.
(b) VCEQ.
(c) VB and VC.
(d) VBC.

Fig. 1.7: Fixed Bias Circuit

P Manohar, Associate Professor, Dept. of EIE, RNSIT Page 6

 Analog Electronic Circuits (18EI33), 3rd Sem EIE

a)

b)

c)

d)

e)

P - 1.2 Sketch the DC load line and mark the operating point of the circuit shown in Fig.1.7

Fig. 1.8. Fixed Bias Load line

= 12 V

12V
 = 5.45 mA
2.2k

P Manohar, Associate Professor, Dept. of EIE, RNSIT Page 7

 Analog Electronic Circuits (18EI33), 3rd Sem EIE
P - 1.3 For the fixed-bias configuration of Fig. 1.10, determine:
(a) IBQ.
(b) ICQ.
(c) VCEQ.
(d) VC.
(e) VB.
(f) VE.

Fig. 1.9. Fixed Bias Circuit

2. Emitter Bias Configuration:

Emitter Bias Circuit:

Fig. 1.10. Emitter Bias Circuit.

Base Emitter Loop:

 VCC  I B RB  VBE  I E RE  0
But, I E  (  1) I B
 VCC  I B RB  VBE  (  1) I B RE  0

-----(1)

----------(2)

Fig.1.11: Base-Emitter Loop

P Manohar, Associate Professor, Dept. of EIE, RNSIT Page 8

 Analog Electronic Circuits (18EI33), 3rd Sem EIE

Collector–Emitter Loop:
------(2)
 VCC  I C RC  VCE  I E RE  0
But, I E  I C
 VCC  I C ( RC  RE )  VCE  0

-------(3)

--------(4)

--------(5)
Fig.1.12: Collector-Emitter Loop

Load Line Analysis:

-----------(1)
By substituting IC = 0 mA in Eq (1), we find that
VCE  VCC  (0)( RC  RE )

-------(2) defines one point for the load line

By substituting VCE = 0 V in Eq (1), we find that
0  VCC  I C ( RC  RE )

---------(3) defines another point for the load line

Fig. 1.13. Emitter Bias Load line

P Manohar, Associate Professor, Dept. of EIE, RNSIT Page 9

 Analog Electronic Circuits (18EI33), 3rd Sem EIE
P - 2.1 For the emitter bias network of Fig.
1.14, determine:
(a) IB.
(b) IC.
(c) VCE.
(d) VC.
(e) VE.
(f) VB.
(g) VBC.

Fig. 1.14. Emitter Bias circuit

a)

b)

c)

d)

e)

f)

g)

P Manohar, Associate Professor, Dept. of EIE, RNSIT Page 10

 Analog Electronic Circuits (18EI33), 3rd Sem EIE
P - 2.2 Sketch the DC load line and mark the operating point of the circuit shown in Fig.1.14

Fig. 1.8. Emitter Bias Load line

-----------(1)

-------(2) defines one point for the load line

= 20 V

---------(3) defines another point for the load line

20V
 = 6.67 mA
3k
P - 2.3 For the emitter bias network of Fig.
1.15, determine:
(a) IB.
(b) IC.
(c) VCE.
(d) VC.
(e) VE.
(f) VB.
(g) VBC.

Fig. 1.15. Emitter Bias circuit

P Manohar, Associate Professor, Dept. of EIE, RNSIT Page 11

 Analog Electronic Circuits (18EI33), 3rd Sem EIE

3. Voltage Divider Bias Configuration:

Voltage Divider Bias Circuit:

Fig. 1.16. Voltage Divider Bias Circuit

Methods to analyze Voltage Divider Bias Configuration
There are two methods that can be applied to analyze the voltage divider configuration. They are
i) Exact Method: can be applied to any voltage-divider configuration.
ii) The Approximate Method: can be applied only if specific conditions are satisfied.
i) Exact Method:
Base Emitter Loop:

Fig. 1.17. Voltage Divider Bias Circuit Fig. 1.18. Redrawing the input side of the network of
Fig. 1.17.

Applying the voltage-divider rule:

P Manohar, Associate Professor, Dept. of EIE, RNSIT Page 12

 Analog Electronic Circuits (18EI33), 3rd Sem EIE

Thevenin Voltage, Eth:

------(1)

Fig. 1.18(a). Determining ETh.

Thevenin Resistance, Rth:

---------(2)

Fig. 1.18(b). Determining RTh.

ETH  I B RTh  VBE  I E RE  0

Substituting IE = (β+1)IB and solving for IB
yields

-------(3)

Fig. 1.19. Inserting the Thevenin equivalent circuit

---------(4)
Collector–Emitter Loop:

The magnitude of the collector current is related directly to

IB through

------(5)

 VCC  I C RC  VCE  I E RE  0
Substituting I E  I C
 VCC  I C ( RC  RE )  VCE  0

Fig.1.20: Collector-Emitter Loop ------(6)

------(7)

P Manohar, Associate Professor, Dept. of EIE, RNSIT Page 13

 Analog Electronic Circuits (18EI33), 3rd Sem EIE
P-3.1: Determine the dc bias voltage VCE and
the current IC for the voltage-divider
configuration of Fig. 1.21.

Fig.1.21: Voltage Divider Bias CE amplifier

a)

b)

c)

d)

e)

P Manohar, Associate Professor, Dept. of EIE, RNSIT Page 14

 Analog Electronic Circuits (18EI33), 3rd Sem EIE
P - 3.2: For the voltage-divider bias configuration of Fig. 4.80, determine:
(a) IBQ.
(b) ICQ.
(c) VCEQ.
(d) VC.
(e) VE.
(f) VB.

Fig.1.22: Voltage Divider Bias CE

amplifier

ii) Approximate Method:

Base Emitter Loop

Fig. 1.23. Voltage Divider Bias Circuit Fig. 1.24. Partial-bias circuit for calculating the
approximate base voltage VB.

------(1)
The condition that will define whether the approximate approach can be applied will be the
following:

-----(2)

-------(3)

P Manohar, Associate Professor, Dept. of EIE, RNSIT Page 15

 Analog Electronic Circuits (18EI33), 3rd Sem EIE

---------(4)

-------(5)
Collector–Emitter Loop:
 VCC  I C RC  VCE  I E RE  0
Substituting I E  I CQ
 VCC  I C ( RC  RE )  VCE  0

------(6)

-------(7)

Fig.1.25: Collector-Emitter Loop

P-3.3: Determine the dc bias voltage VCE and

the current IC for the voltage-divider
configuration of Fig. 1.26.

Fig.1.26: Voltage Divider Bias CE amplifier

a)

b)

P Manohar, Associate Professor, Dept. of EIE, RNSIT Page 16

 Analog Electronic Circuits (18EI33), 3rd Sem EIE

c)

d)

e)

P-3.4: Determine the following for the voltage-divider configuration of Fig. 1.27 using the
approximate approach.
(a) IC.
(b) VCE.
(c) IB.
(d) VE.
(e) VB.

Fig.1.27: Voltage Divider Bias CE amplifier

Load Line Analysis:
The network equation that relates IC and VCE is

-----------(1)
By substituting IC = 0 mA in Eq (1), we find that
VCE  VCC  (0)( RC  RE )

-------(2) defines one point for the load line

By substituting VCE = 0 V in Eq (1), we find that

P Manohar, Associate Professor, Dept. of EIE, RNSIT Page 17

 Analog Electronic Circuits (18EI33), 3rd Sem EIE

0  VCC  I C ( RC  RE )

---------(3) defines another point for the load line

Fig. 1.28. Voltage Divider Bias Load line

P - 3.5 Sketch the DC load line and mark the operating point of the circuit shown in Fig.1.26

Fig. 1.29. Voltage Divider Bias Load line

-----------(1)

-------(2) defines one point for the load line

= 22 V

---------(3) defines another point for the load line

20V
 = 6.67 mA
3k

P Manohar, Associate Professor, Dept. of EIE, RNSIT Page 18

 Analog Electronic Circuits (18EI33), 3rd Sem EIE

4. Emitter Follower Configuration:

Fig. 1.30.(a) Common collector (emitter follower configuration) (b) DC equivalent circuit
Base-emitter loop:
 I B RB  VBE  I E RE  VEE  0
But, I E  (  1) I B
 I B RB  VBE  (  1) I B RE  VEE  0

------(1)
Collector emitter loop:
I c  I B
------(2)
 VCE  I E RE  VEE  0
But, I E  (  1) I B

------(2)

P-4.1 Determine VCEQ and IE for the network of Fig. 1.31.

1.1
Fig.1.31 Emitter follower configuration

P Manohar, Associate Professor, Dept. of EIE, RNSIT Page 19

 Analog Electronic Circuits (18EI33), 3rd Sem EIE

a)

b)

c)

P-4.1 Determine VCEQ and IE for the network of Fig. 1.32.

Fig.1.32 Emitter follower configuration

P Manohar, Associate Professor, Dept. of EIE, RNSIT Page 20

 Analog Electronic Circuits (18EI33), 3rd Sem EIE

2. DC Biasing - FETs
Introduction
Common Source (CS) Configuration:

Fig. 2.1: JFET

ID  IS IG  0 A

 V 
2 When VGS = 0 V and VDS ≥ |VP| then ID = IDSS
I D  I DSS 1  GS 
 VP  When VGS < VP, then ID = 0 A.

Transfer Characteristics
The relationship between ID and VGS is defined by Shockley’s equation:

2
I D  I DSS 1  GS 
V
 VP 

Fig. 2.2: The Transfer curve

P Manohar, Associate Professor, Dept. of EIE, RNSIT Page 21

 Analog Electronic Circuits (18EI33), 3rd Sem EIE

A short hand method to sketch the transfer curve.

The transfer curve can be sketched to a satisfactory level of accuracy simply using the four plot
points defined in Table 1.3.3.

1. FET Biasing - Fixed Bias Configuration

Fig. 2.3: Fixed Bias CS amplifier.

The voltage drop across RG is given by

VRG  I G RG
But, I G  0 A
Therefore, VRG  (0 A) RG  0V
The zero-volt drop across RG permits replacing RG by a short-circuit equivalent.
Fig. 2.4 is the network redrawn for dc analysis.

P Manohar, Associate Professor, Dept. of EIE, RNSIT Page 22

 Analog Electronic Circuits (18EI33), 3rd Sem EIE

Fig. 2.4: Network for dc analysis

Gate to source voltage, VGS:

 VGG  VGS  0
and VGS  VGG

Drain current ID:

2
I D  I DSS 1  GS 
V
 VP 
Drain to source voltage, VDS:
 VDS  I D RD  VDD  0

VDS  VDD  I D RD

Drain voltage, VD:

VDS  VD  VS

VDS  VD  0V

Therefore, VD  VDS

Gate voltage VG:

VGS  VG  VS

VGS  VG  0V

VG  VGS

P Manohar, Associate Professor, Dept. of EIE, RNSIT Page 23

 Analog Electronic Circuits (18EI33), 3rd Sem EIE

Mathematical approach:
 VGS  VGG
2
I D  I DSS 1  GS 
V

 VP 

 VDS  VDD  I D RD

 VD  VDS

 VG  VGS

Graphical approach:
 Obtain the transfer curve by applying Shockley's equation.

 Draw the vertical line at VGS = - VGG

 Mark the Quiescent operating point IDQ, the point where the two curves intersect.
 Draw a horizontal line from the Q-point to the vertical ID axis to determine the quiescent
level of ID.

P Manohar, Associate Professor, Dept. of EIE, RNSIT Page 24

 Analog Electronic Circuits (18EI33), 3rd Sem EIE
P - 1.1: Determine the following for the network of Fig. 2.5
(a) VGSQ.
(b) IDQ.
(c) VDS.
(d) VD.
(e) VG.
(f) VS.

.
Fig. 2.5: Fixed Bias Circuit

Mathematical Approach:

a)

b)

c)

d)

e)

f)

P Manohar, Associate Professor, Dept. of EIE, RNSIT Page 25

 Analog Electronic Circuits (18EI33), 3rd Sem EIE

Graphical Approach:

a)

b)

c)

d)

e)

f)

P Manohar, Associate Professor, Dept. of EIE, RNSIT Page 26

 Analog Electronic Circuits (18EI33), 3rd Sem EIE
P-1.2: For the fixed-bias configuration of Fig. 2.6, determine:
(a) IDQ and VGSQ using a purely mathematical approach.
(b) Repeat part (a) using a graphical approach and compare results.
(c) Find VDS, VD, VG, and VS using the results of part (a).

Fig. 2.6: Fixed Bias Circuit

2. Self Bias Configuration

Fig. 2.7: Self Bias Configuration.

 The voltage drop across RG is given by
VRG  I G RG
But, I G  0 A
Therefore, VRG  (0 A)  RG  0V
The zero-volt drop across RG permits replacing RG by a short-circuit equivalent.

P Manohar, Associate Professor, Dept. of EIE, RNSIT Page 27

 Analog Electronic Circuits (18EI33), 3rd Sem EIE
Fig. 2.7 is the network redrawn for dc analysis.

Fig. 2.8: Network for dc analysis

Gate to source voltage, VGS:
 VGS  VRS  0
and VGS  VRS
VGS   I D RS (1)
Drain current ID:
2
 V 
I D  I DSS 1  GS 
 VP 
where VGS   I D RS
Drain to source voltage, VDS:
VRS  VDS  VRD  VDD  0

VDS  VDD  VRS  VRD

 VDD  I S RS  I D RD

VDS  VDD  I D ( RS  RD ) [since I S  I D ]

Drain voltage, VD:

VDS  VD  VS

Therefore, VD  VDS  VS  VDD  VRD

Gate voltage VG:

VGS  0V

P Manohar, Associate Professor, Dept. of EIE, RNSIT Page 28

 Analog Electronic Circuits (18EI33), 3rd Sem EIE

Source voltage VS:

VS  I D RS

Graphical approach:
Obtain the transfer curve by applying Shockley's equation.

 Identify two points on the graph that are on the line. Draw a straight line passing through
the two points.
VGS   I D RS

1) For I D  0 A , VGS  0V

I DSS I R
2) For I D  , VGS   DSS S
2 2

 Mark the Quiescent operating point IDQ, the point where the two curves intersect.
 Draw a horizontal line from the Q-point to the vertical ID axis to determine the quiescent
level of ID.
 VDS  VDD  I D ( RS  RD )

 VD  VDS  VS

 VS  I D RS

P Manohar, Associate Professor, Dept. of EIE, RNSIT Page 29

 Analog Electronic Circuits (18EI33), 3rd Sem EIE
P-2.1: Determine the following for the network of
Fig. 2.9.
(a) VGSQ.
(b) IDQ.
(c) VDS.
(d) VS.
(e) VG.
(f ) VD.

Fig. 2.9: Self Bias Configuration.

Graphical approach:

VGS   I D RS

1) For I D  0 A , VGS  0V

2) For I D  4mA , VGS   I D RS  4V

a)
b) At the Quiescent point,

P Manohar, Associate Professor, Dept. of EIE, RNSIT Page 30

 Analog Electronic Circuits (18EI33), 3rd Sem EIE

c)

d)

e)
f)

P- 2.2: For the self-bias configuration of Fig. 2.10:

(a) Sketch the transfer curve for the device.
(b) Superimpose the network equation on the same graph.
(c) Determine IDQ and VGSQ.
(d) Calculate VDS, VD, VG, and VS.

Fig. 2.10: Self Bias Configuration.

3. Voltage Divider Bias Configuration

Fig. 2.11: Voltage divider Configuration.

P Manohar, Associate Professor, Dept. of EIE, RNSIT Page 31

 Analog Electronic Circuits (18EI33), 3rd Sem EIE
Since IG = 0 A, Kirchhoff’s current law requires that IR1 = IR2.

Gate voltage VG:

The voltage VG, equal to the voltage across
R2, can be found using the voltage divider
rule as follows:

VDD R2
VG 
R1  R2

Fig. 2.12: Series equivalent circuit

Fig. 2.13 is the network redrawn for dc analysis.

Fig. 2.13: Redrawn Network for dc analysis

Gate to source voltage VGS:
VG  VGS  VRS  0
and VGS  VG  VRS
Substituting VRS = ISRS = IDRS
VGS  VG  I D RS -------(1)
Drain current ID:
2
 V 
I D  I DSS 1  GS 
 VP 
where VGS  VG  I D RS

P Manohar, Associate Professor, Dept. of EIE, RNSIT Page 32

 Analog Electronic Circuits (18EI33), 3rd Sem EIE

Drain to source voltage, VDS:

VRS  VDS  VRD  VDD  0

VDS  VDD  VRS  VRD

 VDD  I S RS  I D RD

VDS  VDD  I D ( RS  RD ) [since I S  I D ]

Drain voltage, VD:

VDS  VD  VS

Therefore, VD  VDS  VS  VDD  VRD

Source voltage VS:

VS  I D RS

Graphical approach:
Obtain the transfer curve by applying Shockley's equation.

 Identify two points on the graph that are on the line. Draw a straight line passing through
the two points.
VGS  VG  I D RS

1) For I D  0 A , VGS  VG

2) For VGS  0 , VG  I D RS

VG
and I D 
RS VGS 0V

P Manohar, Associate Professor, Dept. of EIE, RNSIT Page 33

 Analog Electronic Circuits (18EI33), 3rd Sem EIE

 Mark the Quiescent operating point IDQ, the point where the two curves intersect.
 Draw a horizontal line from the Q-point to the vertical ID axis to determine the quiescent
level of ID.
 VDS  VDD  I D ( RS  RD )

 VD  VDS  VS

 VS  I D RS

P- 3.1: Determine the following for the network

of Fig. 2.14.
(a) IDQ and VGSQ.
(b) VD.
(c) VS.
(d) VDS.
(e) VDG.

Fig. 2.13: Voltage Divider Bias CS amplifier

P Manohar, Associate Professor, Dept. of EIE, RNSIT Page 34

 Analog Electronic Circuits (18EI33), 3rd Sem EIE

a)
and
b)

c)

d)

e)

P Manohar, Associate Professor, Dept. of EIE, RNSIT Page 35

 Analog Electronic Circuits (18EI33), 3rd Sem EIE

P Manohar, Associate Professor, Dept. of EIE, RNSIT Page 36

 Analog Electronic Circuits (18EI33), 3rd Sem EIE

P Manohar, Associate Professor, Dept. of EIE, RNSIT Page 37