UNIVERSITI TEKNOLOGI MARA

FACULTY OF ELECTRICAL ENGINEERING

DIGITAL DESIGN AND COMPUTER ARCHITECTURE

LABORATORY 1

(ELE558)

TITLE:

TESTBENCH AND FSM

DATE:

29/12/2020

PREPARED BY:

NAME STUDENT NO. GROUP

MUHAMAD AISAMUDDIN BIN SUBANI 2019542193 B2

MUHAMMAD HANZALAH BIN NORMAZLI 2019554667 B1

PREPARED FOR:

DR. NOR SHAHANIM MOHAMAD HADIS

Table of Contents
1. Experiment 1: Design and Simulation of a sequential module......................................................1
1.1. Verilog code...........................................................................................................................1
1.2. Testbench code......................................................................................................................2
1.3. Report Summary of the compilation......................................................................................4
1.4. Synthesized circuit in RTL viewer and Technology viewer.....................................................5
1.5. Timing diagram......................................................................................................................7
2. EXPERIMENT 2: DESIGN AND SIMULATION OF A FSM MODULE......................................................15
2.1. Block diagram and Moore FSM architecture diagram.........................................................15
2.2. State transition diagram......................................................................................................15
2.3. State transition table, state encoding table, state transition encoded table.......................16
2.4. State output table, output encoding table and state output encoded table.......................17
2.5. Simplified expressions for Next State Combinational Logic and Output Combinational Logic.
17
2.6. Logic circuits for Next State Combinational Logic and Output Combinational Logic............18
2.7. Complete Moore FSM architecture.....................................................................................18
2.8. FSM Verilog code.................................................................................................................19
2.9. Testbench code....................................................................................................................20
2.10. Synthesized circuit in RTL viewer and Technology viewer...................................................20
2.11. Report Summary of the compilation....................................................................................22
2.12. Timing diagram....................................................................................................................23
3. Discussion....................................................................................................................................24
4. Conclusion...................................................................................................................................25
 1. Experiment 1: Design and Simulation of a sequential module

1.1. Verilog code

module lab2 (D0, D1, D2, D3, Y0, Y1, Y2, Y3, rst, clk);

input D0, D1, D2, D3;

input rst, clk;
output Y0, Y1, Y2, Y3;
reg Y0, Y1, Y2, Y3;

always @ (posedge clk or negedge rst)

begin
if(!rst)
begin
Y0 <= 0;
Y1 <= 0;
Y2 <= 0;
Y3 <= 0;
end
else
begin
Y0 <= D0;
Y1 <= D1;
Y2 <= D2;
Y3 <= D3;
end
end
endmodule

1
 1.2. Testbench code

`timescale 1ns/1ps
module lab2_tb;

reg d0,d1,d2,d3,RST,CLK;
wire y0,y1,y2,y3;

lab2
A1(.D0(d0),.D1(d1),.D2(d2),.D3(d3),.rst(RST),.clk(CLK),.Y0(y0),.Y1(y1),.Y2(y2),.Y3(y3));

initial begin
RST=1;
CLK=0;
d0=0;
d1=0;
d2=0;
d3=0;
end

initial begin
#85;
RST=0;
#5;
RST=1;
end

always begin
#5 CLK=~CLK;
end

2
always begin
#80
d0=~d0;
end

always begin
#40
d1=~d1;
end

always begin
#20
d2=~d2;
end

always begin
#10
d3=~d3;
end

endmodule

3
1.3. Report Summary of the compilation

4
 1.4. Synthesized circuit in RTL viewer and Technology viewer

a. RTL viewer

b. Technology viewer

5
c. RTL viewer testbench

6
1.5. Timing diagram

7
8
9
10
11
12
13
14
2. EXPERIMENT 2: DESIGN AND SIMULATION OF A FSM MODULE

2.1. Block diagram and Moore FSM architecture diagram

2.2. State transition diagram

Up, U

Up, U

Reset S0 S1
Red off Red on
Green on Green off

Down,D
Down,D

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2.3. State transition table, state encoding table, state transition encoded table

Input
Current State Next State
U D
0 x Ground
Ground (s0)
1 x First floor
x 0 First floor
First floor (s1)
x 1 Ground
Table 1: State transition table

Input
Current State Next State
Up Down
0 x s0
s0 1 x s1
x 0 s1
s1
x 1 s0
Table 2: State encoded table

State Encoding
Ground 0
First floor 1
Table 3: State encoding table

TA TB
S 00 01 11 10

0
0 0 1 1
1
1 0 0 1

Simplified expression, S’ = S0TA+TATB+S1TB

16
2.4. State output table, output encoding table and state output encoded table.

Output
Current state
s0 s1 ledr ledg
0 1 1 0
0 1 0 1
1 0 0 1
1 0 1 0
Table 4: State output table

State Encoding
s0 0
s1 1
Table 5: State output encoded table

State Encoding
off 0
on 1
Table 6: State output encoding table

2.5. Simplified expressions for Next State Combinational Logic and Output
Combinational Logic.

Next State Combinational Logic Output Combinational Logic

s' =S Up x SDown ledr=S1 S0

ledg=S 1 S 0

Table 7: combinational logic table

17
2.6. Logic circuits for Next State Combinational Logic and Output Combinational
Logic.

Figure 5: Next State combinational logic

ledr

ledg

Figure 6: Output combinational logic

2.7. Complete Moore FSM architecture.

ledr

ledg

Figure 7: Complete Moore FSM architecture

18
2.8. FSM Verilog code

19
2.9. Testbench code

20
2.10. Synthesized circuit in RTL viewer and Technology viewer

Figure 8: Synthesized circuit in RTL viewer for Experiment 2

Figure 9: Synthesized circuit in Technology viewer (Post Mapping)

21
Figure 10: Synthesized circuit in Technology viewer (Post Fitting)

Figure 11: State machine

22
2.11. Report Summary of the compilation

Figure 11: Flow summary and Project compiled successfully for experiment 2

Figure 12: Flow summary and Project compiled successfully for experiment 2

23
2.12. Timing diagram

Figure 13: output waveform when Up = 1, led RED = ON

Figure 14: output waveform when Down = 1, led GREEN = ON

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3. Discussion

For experiment 1, the students need to program a Verilog code and testbench code by
using Quartus II and record the timing by using Modelsim altera. After completing the code
for the Verilog and testbench, the students must figure out the technology viewer and RTL
viewer for the program. Before generate the RTL viewer and technology viewer, the students
need to complete the compilation for Verilog and run RTL for testbench. Next, this
experiment should be in sequential format, non-blocking and 4-bit input data. Lastly, 4 D flip
flop with 4 inputs as D for (data) along with RST, CLK and 4 outputs was appeared.

In experiment 2, on Figure 10 and 11 shows the block diagram of Moore fsm. The block
diagram consists of next state combinational logic, state register and output combinational
logic. This experiment has 4 inputs and 2 output where the outputs is RED LED (ledr) and
GREEN LED (ledg), while the input is Clock, Reset, Ground floor (down) and First floor
(up). In first floor the red led will turn on and green led will turn off, and vice versa on
ground floor. In Table 1, we create the FSM Moore transition table, from that table it shows
the inputs for every current state and next state, as we can see if the input 1 during current
state S0, the next state will change to S1, on the current state of S1 will depends on inputs of
Down in order to change the current state into S0. In this experiment 2, from the table we
know that the LED RED will turn on when the current state on S0 and the LED GREEN will
turn on when the current state on S1. After that, we create the Truth table from the output and
K Map. Then, from the K Map we can produce the expressions for Next State Combinational
Logic and Output Combinational Logic. Furthermore, coding has created as module elevator,
the module contain the declarations of inputs and outputs. For declaration, input is used for
clk, rst , up and down. For LED that declared as ledr and ledg has assign as output red, while
the S0, S1, ON and OFF assign as parameter. The condition has been written as in state
register and next state register in command window. The default go with 00 because we want
both led turn off when in default situation. For testbench, input for clk, rst, up and down has
been inserted to obtain the timing diagram in ModelSim software. The problem that faced
during coded testbench is the timer that set not suit in this oroject condition, where the led
RED will turn on simultaneously when the input Up = 1 and same goes when Down
condition.

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4. Conclusion

To recapitulate, the students will be able to learn about sequential type, non-blocking
for Verilog code and generate the desired timing diagram by using Modelsim altera. Next, the
students also be able to produce the RTL viewer for Verilog code and technology viewer for
testbench for their architectural design. Furthermore, students also able to understand FSM in
practically, from the problem statement, transfer to state machine and state table, until
convert to testbench and Verilog code. Then, students also able to learn deeply basic
command and condition from Verilog code and testbench code.

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