A B C D E

1 1

Compal Confidential
2 2

VALEA/VALEB Schematics Document

AMD APU Richland FS1r2 + FCH Bolton-M3 + GPU Sun Pro M2

2012-11-22
3
REV:1.0 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/22 Deciphered Date 2015/11/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Cover Page
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-8127P
Tuesday, March 12, 2013 Sheet 1 of 51
A B C D E
 A B C D E

Compal confidential
File Name : VALEA/VALEB
Sun Pro M2

1
VRAM PCIE x 8 Gen2 1

128M16/256M16 Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X2

DDR3 x 4
Page 17 ～24 AMD FS1r2 APU Dual Channel BANK 0, 1, 2 Page 10 ～11
1.5V DDRIII 1600 (1866)
DP Port0 Richland
LVDS uPGA 722 pin
translator DP Port2 35mm x 35mm
RTD2132S HDMI Conn.
～9
Page 27
Page 25 DP Port1 Page 5

4 * x1 PCI-E 2.0 x4 UMI Gen. 1

LVDS Conn. 2.5GT/s per lane
Page 26 GPP3 GPP1 GPP0 2Channel Speaker
CardReader LAN
RTL 8111F
2 4 in 1 Conn. IC AZALIA Audio Codec Internal MIC 2

RTS5229 Bolton M3 CX20671-21Z

Page 29
uFCBGA-656 Audio Jacks
PCI Express USB(BT) 24.5mm x 24.5mm 14*USB2.0/
Combo jack
Mini card Slot 1 PCI-E(WLAN) 4*USB3.0,10*USB2.0
WLAN
FCH CRT (VGA DAC)
CMOS Camera Page 26
Page 33
CRT CONN
Page 28
Page 12 ～16 6*SATA serial BlueTooth CONN Page 32
USB PORT 3.0 x3 Page 34
SPI ROM LPC BUS USB PORT 2.0 x1 +Charger
4MB
Sub board WLAN Page 33
3
Page 35 Page 13
EC 3

ENE KB9012
Page 31 Finger Printer
Power Board 15" only G Sensor UPEK TCS5DA6C0
ST LIS34ALTR
Page 30
SATA0
ODD board SATA3.0 HDD CONN
LAN Track Point
Page 30

SATA1
Page 33 SATA ODD CONN
Int.KBD Page 30
Audio Jack+ Click Pad
Page 33

USB2.0 Page 33

FingerPrint Thermal Sensor

4 Fintek 5303 4

Page 32

Card reader Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/11/22 Deciphered Date 2015/11/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Block Diagrams
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-8127P
Tuesday, March 12, 2013 Sheet 2 of 51
A B C D E
 A B C D E

Voltage Rails
FCH Hudson-M2/3 Comal FCH Hudson-M2/3
Power Plane Description S0 S3 S5
SATA Port List PCIE Port List USB Port List
VIN Adapter power supply (19V) N/A N/A N/A
B+ AC or battery power rail for power circuit. N/A N/A N/A
USB1.1
SATA0 HDD PCIE0 LAN
+APU_CORE Core voltage for APU ON OFF OFF Port0 NC
SATA1 ODD PCIE1 WLAN

APU
1 +APU_CORE_NB Voltage for On-die VGA of APU ON OFF OFF 1

+1.5V 1.5V power rail for APU VDDIO and DDR ON ON OFF
Port1 NC
SATA2 NC PCIE2 NC
+0.75VS 0.75V switched power rail for DDR terminator ON OFF OFF USB2.0
+1.2VS 1.2V (VDDR, VDDP) switched power rail for APU ON OFF OFF
SATA3 NC PCIE3 Card Reader
+2.5VS 2.5V for APU VDDA ON OFF OFF
Port0 USB2.0 Port
SATA4 NC PCIE0 NC
+1.1VALW 1.1V switched power rail for FCH ON ON ON* Port1 NC
SATA5 NC PCIE1 NC

FCH
+1.1VS 1.1V switched power rail for FCH ON OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF
Port2 NC
PCIE2 NC
+VGA_CORE 0.95-1.2V switched power rail ON OFF OFF Port3 NC
+1.5VGS 1.5V switched power rail ON OFF OFF
PCIE3 NC
+1.8VGS 1.8V switched power rail ON OFF OFF
Port4 NC
+0.95VGS 0.95V switched power rail for VGA ON OFF OFF Port5 WLAN
+3VALW 3.3V always on power rail ON ON ON*
+3VS_WLAN 3.3V power rail for WLAN ON OFF OFF
Port6 CMOS
+3VS 3.3V switched power rail ON OFF OFF Port7 FP
2 +5VALW 5V always on power rail ON ON ON* 2

+5VS 5V switched power rail ON OFF OFF

Port8 BT
+VSB VSB always on power rail ON ON ON* Port9 NC
+RTCVCC RTC power ON ON ON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Port10 USB 3.0
Port11 USB 3.0
Port12 USB 3.0

EC SM Bus1 address EC SM Bus2 address BOM Structure Port13 NC

Device Address HEX Device Address HEX

UMA@ : UMA only
DIS@ : DIS muxless
Smart Battery 0001-011xb 15H F75303 (DDR,VRAM,CPUCORE)1001-101xb 9AH
SB-TSI 1001-100xb 98H
Sun Pro M2 1000-0010b 82H CMOS@ : USB camera
LVDS translator
3 3
CONN@ : ME components
X76@, H1G@, S1G@ : VRAM

BOM option and stencil

SDV:
CMOS@/DIS@ + X76@
FCH SMB0 (FCH_SMB0)

Device Address HEX PJ201,PJ401,PJ502,PJ503,PJ504,PJ601,PJ603,PJ604,

PJ701,PJ702,PJ703,PJ704,J1,J2301,J2401,J2402,J2403
DDR DIMM1 (FCH_SMB0) 1001-000xb 90 PJ402,PJ403,PJ501,PJ602,PJ801,PJ802,PJ803,PJ805
DDR DIMM2 (FCH_SMB0) 1001-001xb 92
4 WLAN (FCH_SMB0) 4

Security ROM

Stencil Memo
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/11/22 Deciphered Date 2015/11/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Notes List
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-8127P
Tuesday, March 12, 2013 Sheet 3 of 51
A B C D E
 5 4 3 2 1

Power-Up/Down Sequence
‧nominal
All the ASIC supplies, except for VDDR3, must fully reach their respective
voltages within 20 ms of the start of the ramp-up sequence, though a
shorter ramp-up duration is preferred. There is no timing requirement on the

‧ramp APU APU_PCIE_RST#

up of VDDR3 relative to other power rails.
The external pull-up resistors on the DDC/AUX signals (if applicable) should

D ‧should
ramp up before or after both VDDC and VDD_CT have ramped up.
VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC D

‧ For reach 90% before VDD_CT starts to ramp up (or vice versa). AND
power down, reversing the ramp-up sequence is recommended. GPIO191 PXS_RST#
GATE
GPU_RST# PERSTB GPU
FCH

VDDR3(3.3VGS) PXS_PWREN
GPIO192

PCIE_VDDC(0.95VGS) GPIO51 VGA_PWRGD

VDDR1(1.5VGS)
PXS_PWREN

VDDC/VDDCI(1.12V)

+3VS +3VGS
VDD_CT(1.8VGS)
C
MOS 1 C

PERSTb
+3VALW +0.95VGS +1.8VS +1.8VGS
Regulator 2 MOS 5
REFCLK
B+ +VGA_CORE +1.5VS +1.5VGS
Straps Reset PWM 4 MOS 3

Straps Valid

Global ASIC Reset

T4+16clock

SUN PRO VRAM STRAP

B
Vendor PS_3[ 2 ] PS_3[ 1 ] PS_3[ 0 ] R_pu R_pd ZZZ1 ZZZ2 B

H5TQ2G63DFR-11C R1430 R1436

SA00003YO70 0 0 0
NC 4.75K S1G H1G
S1G@ H1G@
K4W2G1646E-BC11 R1430 R1436 X7635939L09 X7635939L10
1G SA00005SH00 0 0 1 ZZZ4 ZZZ5
8.45K 2K
MT41J128M16JT-093G
SA000067510 R1430 R1436
0 1 0
FBGA Code:D9PTD 4.53K 2K S2G M2G
S2G@ M2G@
K4W4G1646B-HC11 R1430 R1436 X7635939L11 X7635939L12

SA000068R00 0 1 1
6.98K 4.99K
2G
MT41K256M16HA-107G
SA000065D00 R1430 R1436
1 0 0
FBGA Code:D9PZD 4.53k 4.99K
MT41J128M16JT-107G R1430 R1436
SA00005SM30 1 0 1
3.24k 5.62k
A 1G FBGA Code:D9PRS A

K4W2G1646E-BC1A 1 1 0 R1430 R1436

SA000068U10 3.4k 10k
1 1 1 R1430 R1436
4.75K NC
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/11/22 Deciphered Date 2015/11/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
dGPU Block Diagram
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-8127P
Tuesday, March 12, 2013 Sheet 4 of 51
5 4 3 2 1
 A B C D E

[17] PCIE_CRX_GTX_P[0..7] PCIE_CTX_GRX_P[0..7] [17]

[17] PCIE_CRX_GTX_N[0..7] PCIE_CTX_GRX_N[0..7] [17]

JCPU1A
PCI EXPRESS
PCIE_CRX_GTX_P0 AB8 AB2 PCIE_CTX_C_GRX_P0 C1 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_P0
PCIE_CRX_GTX_N0 AB7 P_GFX_RXP0 P_GFX_TXP0 AB1 PCIE_CTX_C_GRX_N0 C2 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_N0
PCIE_CRX_GTX_P1 AA9 P_GFX_RXN0 P_GFX_TXN0 AA3 PCIE_CTX_C_GRX_P1 C3 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_P1
1 P_GFX_RXP1 P_GFX_TXP1 1
PCIE_CRX_GTX_N1 AA8 AA2 PCIE_CTX_C_GRX_N1 C4 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_N1
PCIE_CRX_GTX_P2 AA5 P_GFX_RXN1 P_GFX_TXN1 Y5 PCIE_CTX_C_GRX_P2 C5 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_P2
PCIE_CRX_GTX_N2 AA6 P_GFX_RXP2 P_GFX_TXP2 Y4 PCIE_CTX_C_GRX_N2 C6 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_N2
PCIE_CRX_GTX_P3 Y8 P_GFX_RXN2 P_GFX_TXN2 Y2 PCIE_CTX_C_GRX_P3 C7 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_P3
PCIE_CRX_GTX_N3 Y7 P_GFX_RXP3 P_GFX_TXP3 Y1 PCIE_CTX_C_GRX_N3 C8 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_N3
PCIE_CRX_GTX_P4 W9 P_GFX_RXN3 P_GFX_TXN3 W3 PCIE_CTX_C_GRX_P4 C9 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_P4
PCIE_CRX_GTX_N4 W8 P_GFX_RXP4 P_GFX_TXP4 W2 PCIE_CTX_C_GRX_N4 C10 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_N4
PCIE_CRX_GTX_P5 W5 P_GFX_RXN4 P_GFX_TXN4 V5 PCIE_CTX_C_GRX_P5 C11 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_P5
PCIE_CRX_GTX_N5 W6 P_GFX_RXP5 P_GFX_TXP5 V4 PCIE_CTX_C_GRX_N5 C12 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_N5
PCIE_CRX_GTX_P6 V8 P_GFX_RXN5 P_GFX_TXN5 V2 PCIE_CTX_C_GRX_P6 C13 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_P6
V7 P_GFX_RXP6 P_GFX_TXP6 V1 1 2

GRAPHICS
PCIE_CRX_GTX_N6 PCIE_CTX_C_GRX_N6 C14 DIS@ .1U_0402_16V7K PCIE_CTX_GRX_N6
PCIE_CRX_GTX_P7 U9 P_GFX_RXN6 P_GFX_TXN6 U3 PCIE_CTX_C_GRX_P7 C15 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_P7
PCIE_CRX_GTX_N7 U8 P_GFX_RXP7 P_GFX_TXP7 U2 PCIE_CTX_C_GRX_N7 C16 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_N7
U5 P_GFX_RXN7 P_GFX_TXN7 T5
SDV/FVT, NO.1 U6 P_GFX_RXP8 P_GFX_TXP8 T4 SDV/FVT, NO.1
T8 P_GFX_RXN8 P_GFX_TXN8 T2
T7 P_GFX_RXP9 P_GFX_TXP9 T1
R9 P_GFX_RXN9 P_GFX_TXN9 R3
R8 P_GFX_RXP10 P_GFX_TXP10 R2
R5 P_GFX_RXN10 P_GFX_TXN10 P5
R6 P_GFX_RXP11 P_GFX_TXP11 P4
P8 P_GFX_RXN11 P_GFX_TXN11 P2
P7 P_GFX_RXP12 P_GFX_TXP12 P1
N9 P_GFX_RXN12 P_GFX_TXN12 N3
N8 P_GFX_RXP13 P_GFX_TXP13 N2
N5 P_GFX_RXN13 P_GFX_TXN13 M5
N6 P_GFX_RXP14 P_GFX_TXP14 M4
2 P_GFX_RXN14 P_GFX_TXN14 2
M8 M2
M7 P_GFX_RXP15 P_GFX_TXP15 M1
P_GFX_RXN15 P_GFX_TXN15
AE5 AD5 PCIE_CTX_C_DRX_P0 C33 1 2 .1U_0402_16V7K
[35] PCIE_CRX_DTX_P0 P_GPP_RXP0 P_GPP_TXP0 PCIE_CTX_DRX_P0 [35]
AE6 AD4 PCIE_CTX_C_DRX_N0 C34 1 2 .1U_0402_16V7K
LAN [35] PCIE_CRX_DTX_N0
AD8 P_GPP_RXN0 P_GPP_TXN0 AD2 PCIE_CTX_C_DRX_P1 C123 1 2 .1U_0402_16V7K
PCIE_CTX_DRX_N0 [35]
[33] PCIE_CRX_DTX_P1 P_GPP_RXP1 P_GPP_TXP1 PCIE_CTX_DRX_P1 [33]
AD7 AD1 PCIE_CTX_C_DRX_N1 C124 1 2 .1U_0402_16V7K
WLAN [33] PCIE_CRX_DTX_N1
AC9 P_GPP_RXN1 P_GPP_TXN1 AC3
PCIE_CTX_DRX_N1 [33]
P_GPP_RXP2 P_GPP_TXP2
GPP
AC8 AC2
AC5 P_GPP_RXN2 P_GPP_TXN2 AB5 PCIE_CTX_C_DRX_P3 C35 1 2 .1U_0402_16V7K
[35] PCIE_CRX_DTX_P3 P_GPP_RXP3 P_GPP_TXP3 PCIE_CTX_DRX_P3 [35]
AC6 AB4 PCIE_CTX_C_DRX_N3 C36 1 2 .1U_0402_16V7K
Card Reader [35] PCIE_CRX_DTX_N3 P_GPP_RXN3 P_GPP_TXN3 PCIE_CTX_DRX_N3 [35]
AG8 AG2 UMI_TXP0_C C37 1 2 .1U_0402_16V7K
[12] UMI_RXP0 P_UMI_RXP0 P_UMI_TXP0 UMI_TXP0 [12]
AG9 AG3 UMI_TXN0_C C38 1 2 .1U_0402_16V7K
[12] UMI_RXN0 P_UMI_RXN0 P_UMI_TXN0 UMI_TXN0 [12]
AG6 AF4 UMI_TXP1_C C39 1 2 .1U_0402_16V7K
[12] UMI_RXP1 P_UMI_RXP1 P_UMI_TXP1 UMI_TXP1 [12]
AG5 AF5 UMI_TXN1_C C40 1 2 .1U_0402_16V7K
[12] UMI_RXN1 P_UMI_RXN1 P_UMI_TXN1 UMI_TXN1 [12]
AF7 AF1 UMI_TXP2_C C41 1 2 .1U_0402_16V7K
[12] UMI_RXP2 P_UMI_RXP2 P_UMI_TXP2 UMI_TXP2 [12]
AF8 AF2 UMI_TXN2_C C42 1 2 .1U_0402_16V7K
[12] UMI_RXN2 P_UMI_RXN2 P_UMI_TXN2 UMI_TXN2 [12]
AE8 AE2 UMI_TXP3_C C43 1 2 .1U_0402_16V7K
[12] UMI_RXP3 UMI_TXP3 [12]
UMI

AE9 P_UMI_RXP3 P_UMI_TXP3 AE3 UMI_TXN3_C C44 1 2 .1U_0402_16V7K

[12] UMI_RXN3 P_UMI_RXN3 P_UMI_TXN3 UMI_TXN3 [12]

+1.2VS 1 2 P_ZVDDP AG11 AH11 P_ZVSS 1 2

R1 196_0402_1% P_ZVDDP P_ZVSS R2 196_0402_1%

LOTES_ACA-ZIF-109-P12-A_FS1R2
CONN@
3
Power Sequence of APU 3

+1.5V

+2.5VS Group A

+1.5VS

+APU_CORE

Group B
+APU_CORE_NB

+1.2VS
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/22 Deciphered Date 2015/11/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FS1r2 PCIE/UMI
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-8127P
Tuesday, March 12, 2013 Sheet 5 of 51
A B C D E
 A B C D E

1 1

JCPU1B JCPU1C
MEMORY CHANNEL A MEMORY CHANNEL B
[10] DDRA_SMA[15..0] U20 E13 DDRA_SDQ[63..0] [10] [11] DDRB_SMA[15..0] T27 A14 DDRB_SDQ[63..0] [11]
DDRA_SMA0 DDRA_SDQ0 DDRB_SMA0 DDRB_SDQ0
DDRA_SMA1 R20 MA_ADD0 MA_DATA0 J13 DDRA_SDQ1 DDRB_SMA1 P24 MB_ADD0 MB_DATA0 B14 DDRB_SDQ1
DDRA_SMA2 R21 MA_ADD1 MA_DATA1 H15 DDRA_SDQ2 DDRB_SMA2 P25 MB_ADD1 MB_DATA1 D16 DDRB_SDQ2
DDRA_SMA3 P22 MA_ADD2 MA_DATA2 J15 DDRA_SDQ3 DDRB_SMA3 N27 MB_ADD2 MB_DATA2 E16 DDRB_SDQ3
DDRA_SMA4 P21 MA_ADD3 MA_DATA3 H13 DDRA_SDQ4 DDRB_SMA4 N26 MB_ADD3 MB_DATA3 B13 DDRB_SDQ4
DDRA_SMA5 N24 MA_ADD4 MA_DATA4 F13 DDRA_SDQ5 DDRB_SMA5 M28 MB_ADD4 MB_DATA4 C13 DDRB_SDQ5
DDRA_SMA6 N23 MA_ADD5 MA_DATA5 F15 DDRA_SDQ6 DDRB_SMA6 M27 MB_ADD5 MB_DATA5 B16 DDRB_SDQ6
DDRA_SMA7 N20 MA_ADD6 MA_DATA6 E15 DDRA_SDQ7 DDRB_SMA7 M24 MB_ADD6 MB_DATA6 A16 DDRB_SDQ7
DDRA_SMA8 N21 MA_ADD7 MA_DATA7 DDRB_SMA8 M25 MB_ADD7 MB_DATA7
DDRA_SMA9 M21 MA_ADD8 H17 DDRA_SDQ8 DDRB_SMA9 L26 MB_ADD8 C17 DDRB_SDQ8
DDRA_SMA10 U23 MA_ADD9 MA_DATA8 F17 DDRA_SDQ9 DDRB_SMA10 U26 MB_ADD9 MB_DATA8 B18 DDRB_SDQ9
DDRA_SMA11 M22 MA_ADD10 MA_DATA9 E19 DDRA_SDQ10 DDRB_SMA11 L27 MB_ADD10 MB_DATA9 B20 DDRB_SDQ10
DDRA_SMA12 L24 MA_ADD11 MA_DATA10 J19 DDRA_SDQ11 DDRB_SMA12 K27 MB_ADD11 MB_DATA10 A20 DDRB_SDQ11
DDRA_SMA13 AA25 MA_ADD12 MA_DATA11 G16 DDRA_SDQ12 DDRB_SMA13 W26 MB_ADD12 MB_DATA11 E17 DDRB_SDQ12
DDRA_SMA14 L21 MA_ADD13 MA_DATA12 H16 DDRA_SDQ13 DDRB_SMA14 K25 MB_ADD13 MB_DATA12 B17 DDRB_SDQ13
DDRA_SMA15 L20 MA_ADD14 MA_DATA13 H19 DDRA_SDQ14 DDRB_SMA15 K24 MB_ADD14 MB_DATA13 B19 DDRB_SDQ14
MA_ADD15 MA_DATA14 F19 DDRA_SDQ15 MB_ADD15 MB_DATA14 C19 DDRB_SDQ15
DDRA_SBS0# U24 MA_DATA15 DDRB_SBS0# U27 MB_DATA15
[10] DDRA_SBS0# DDRA_SBS1# U21 MA_BANK0 H20 DDRA_SDQ16 [11] DDRB_SBS0# DDRB_SBS1# T28 MB_BANK0 C21 DDRB_SDQ16
[10] DDRA_SBS1# DDRA_SBS2# L23 MA_BANK1 MA_DATA16 F21 DDRA_SDQ17 [11] DDRB_SBS1# DDRB_SBS2# K28 MB_BANK1 MB_DATA16 B22 DDRB_SDQ17
[10] DDRA_SBS2# MA_BANK2 MA_DATA17 J23 DDRA_SDQ18 [11] DDRB_SBS2# MB_BANK2 MB_DATA17 C23 DDRB_SDQ18
[10] DDRA_SDM[7..0] DDRA_SDM0 E14 MA_DATA18 H23 DDRA_SDQ19 [11] DDRB_SDM[7..0] DDRB_SDM0 D14 MB_DATA18 A24 DDRB_SDQ19
DDRA_SDM1 J17 MA_DM0 MA_DATA19 G20 DDRA_SDQ20 DDRB_SDM1 A18 MB_DM0 MB_DATA19 D20 DDRB_SDQ20
DDRA_SDM2 E21 MA_DM1 MA_DATA20 E20 DDRA_SDQ21 DDRB_SDM2 A22 MB_DM1 MB_DATA20 B21 DDRB_SDQ21
DDRA_SDM3 F25 MA_DM2 MA_DATA21 G22 DDRA_SDQ22 DDRB_SDM3 C25 MB_DM2 MB_DATA21 E23 DDRB_SDQ22
DDRA_SDM4 AD27 MA_DM3 MA_DATA22 H22 DDRA_SDQ23 DDRB_SDM4 AF25 MB_DM3 MB_DATA22 B23 DDRB_SDQ23
DDRA_SDM5 AC23 MA_DM4 MA_DATA23 DDRB_SDM5 AG22 MB_DM4 MB_DATA23
2 DDRA_SDM6 AD19 MA_DM5 G24 DDRA_SDQ24 DDRB_SDM6 AH18 MB_DM5 E24 DDRB_SDQ24 2
DDRA_SDM7 AC15 MA_DM6 MA_DATA24 E25 DDRA_SDQ25 DDRB_SDM7 AD14 MB_DM6 MB_DATA24 B25 DDRB_SDQ25
MA_DM7 MA_DATA25 G27 DDRA_SDQ26 MB_DM7 MB_DATA25 B27 DDRB_SDQ26
DDRA_SDQS0 G14 MA_DATA26 G26 DDRA_SDQ27 DDRB_SDQS0 C15 MB_DATA26 D28 DDRB_SDQ27
[10] DDRA_SDQS0 DDRA_SDQS0# H14 MA_DQS_H0 MA_DATA27 F23 DDRA_SDQ28 [11] DDRB_SDQS0 DDRB_SDQS0# B15 MB_DQS_H0 MB_DATA27 B24 DDRB_SDQ28
[10] DDRA_SDQS0# DDRA_SDQS1 G18 MA_DQS_L0 MA_DATA28 H24 DDRA_SDQ29 [11] DDRB_SDQS0# DDRB_SDQS1 E18 MB_DQS_L0 MB_DATA28 D24 DDRB_SDQ29
[10] DDRA_SDQS1 MA_DQS_H1 MA_DATA29 [11] DDRB_SDQS1 MB_DQS_H1 MB_DATA29
DDRA_SDQS1# H18 E28 DDRA_SDQ30 DDRB_SDQS1# D18 D26 DDRB_SDQ30
[10] DDRA_SDQS1# J21 MA_DQS_L1 MA_DATA30 F27 [11] DDRB_SDQS1# E22 MB_DQS_L1 MB_DATA30 C27
DDRA_SDQS2 DDRA_SDQ31 DDRB_SDQS2 DDRB_SDQ31
[10] DDRA_SDQS2 DDRA_SDQS2# H21 MA_DQS_H2 MA_DATA31 [11] DDRB_SDQS2 DDRB_SDQS2# D22 MB_DQS_H2 MB_DATA31
[10] DDRA_SDQS2# DDRA_SDQS3 E27 MA_DQS_L2 AB28 DDRA_SDQ32 [11] DDRB_SDQS2# DDRB_SDQS3 B26 MB_DQS_L2 AG26 DDRB_SDQ32
[10] DDRA_SDQS3 DDRA_SDQS3# E26 MA_DQS_H3 MA_DATA32 AC27 DDRA_SDQ33 [11] DDRB_SDQS3 DDRB_SDQS3# A26 MB_DQS_H3 MB_DATA32 AH26 DDRB_SDQ33
[10] DDRA_SDQS3# MA_DQS_L3 MA_DATA33 [11] DDRB_SDQS3# MB_DQS_L3 MB_DATA33
DDRA_SDQS4 AE26 AD25 DDRA_SDQ34 DDRB_SDQS4 AG24 AF23 DDRB_SDQ34
[10] DDRA_SDQS4 MA_DQS_H4 MA_DATA34 [11] DDRB_SDQS4 MB_DQS_H4 MB_DATA34
DDRA_SDQS4# AD26 AA24 DDRA_SDQ35 DDRB_SDQS4# AG25 AG23 DDRB_SDQ35
[10] DDRA_SDQS4# DDRA_SDQS5 AB22 MA_DQS_L4 MA_DATA35 AE28 DDRA_SDQ36 [11] DDRB_SDQS4# DDRB_SDQS5 AG21 MB_DQS_L4 MB_DATA35 AG27 DDRB_SDQ36
[10] DDRA_SDQS5 DDRA_SDQS5# AA22 MA_DQS_H5 MA_DATA36 AD28 DDRA_SDQ37 [11] DDRB_SDQS5 DDRB_SDQS5# AF21 MB_DQS_H5 MB_DATA36 AF27 DDRB_SDQ37
[10] DDRA_SDQS5# DDRA_SDQS6 AB18 MA_DQS_L5 MA_DATA37 AB26 DDRA_SDQ38 [11] DDRB_SDQS5# DDRB_SDQS6 AG17 MB_DQS_L5 MB_DATA37 AH24 DDRB_SDQ38
[10] DDRA_SDQS6 MA_DQS_H6 MA_DATA38 [11] DDRB_SDQS6 MB_DQS_H6 MB_DATA38
DDRA_SDQS6# AA18 AC25 DDRA_SDQ39 DDRB_SDQS6# AG18 AE24 DDRB_SDQ39
[10] DDRA_SDQS6# MA_DQS_L6 MA_DATA39 [11] DDRB_SDQS6# MB_DQS_L6 MB_DATA39
DDRA_SDQS7 AA14 DDRB_SDQS7 AH14
[10] DDRA_SDQS7 MA_DQS_H7 [11] DDRB_SDQS7 MB_DQS_H7
DDRA_SDQS7# AA15 Y23 DDRA_SDQ40 DDRB_SDQS7# AG14 AE22 DDRB_SDQ40
[10] DDRA_SDQS7# MA_DQS_L7 MA_DATA40 AA23 DDRA_SDQ41 [11] DDRB_SDQS7# MB_DQS_L7 MB_DATA40 AH22 DDRB_SDQ41
DDRA_CLK0 T21 MA_DATA41 Y21 DDRA_SDQ42 DDRB_CLK0 R26 MB_DATA41 AE20 DDRB_SDQ42
[10] DDRA_CLK0 T22 MA_CLK_H0 MA_DATA42 AA20 DDRA_SDQ43 [11] DDRB_CLK0 R27 MB_CLK_H0 MB_DATA42 AH20 DDRB_SDQ43
DDRA_CLK0# DDRB_CLK0#
[10] DDRA_CLK0# DDRA_CLK1 R23 MA_CLK_L0 MA_DATA43 AB24 DDRA_SDQ44 [11] DDRB_CLK0# DDRB_CLK1 P27 MB_CLK_L0 MB_DATA43 AD23 DDRB_SDQ44
[10] DDRA_CLK1 R24 MA_CLK_H1 MA_DATA44 AD24 DDRA_SDQ45 [11] DDRB_CLK1 P28 MB_CLK_H1 MB_DATA44 AD22 DDRB_SDQ45
DDRA_CLK1# DDRB_CLK1#
[10] DDRA_CLK1# MA_CLK_L1 MA_DATA45 AA21 DDRA_SDQ46 [11] DDRB_CLK1# MB_CLK_L1 MB_DATA45 AD21 DDRB_SDQ46
DDRA_CKE0 H28 MA_DATA46 AC21 DDRA_SDQ47 DDRB_CKE0 J26 MB_DATA46 AD20 DDRB_SDQ47
[10] DDRA_CKE0 H27 MA_CKE0 MA_DATA47 [11] DDRB_CKE0 J27 MB_CKE0 MB_DATA47
DDRA_CKE1 DDRB_CKE1
[10] DDRA_CKE1 MA_CKE1 AA19 DDRA_SDQ48 [11] DDRB_CKE1 MB_CKE1 AF19 DDRB_SDQ48
DDRA_ODT0 Y25 MA_DATA48 AC19 DDRA_SDQ49 DDRB_ODT0 W27 MB_DATA48 AE18 DDRB_SDQ49
[10] DDRA_ODT0 DDRA_ODT1 AA27 MA_ODT0 MA_DATA49 AC17 DDRA_SDQ50 [11] DDRB_ODT0 DDRB_ODT1 Y28 MB_ODT0 MB_DATA49 AE16 DDRB_SDQ50
[10] DDRA_ODT1 MA_ODT1 MA_DATA50 AA17 DDRA_SDQ51 [11] DDRB_ODT1 MB_ODT1 MB_DATA50 AH16 DDRB_SDQ51
DDRA_SCS0# V22 MA_DATA51 AB20 DDRA_SDQ52 DDRB_SCS0# V25 MB_DATA51 AG20 DDRB_SDQ52
3 [10] DDRA_SCS0# AA26 MA_CS_L0 MA_DATA52 Y19 DDRA_SDQ53 [11] DDRB_SCS0# Y27 MB_CS_L0 MB_DATA52 AG19 DDRB_SDQ53 3
DDRA_SCS1# DDRB_SCS1#
[10] DDRA_SCS1# MA_CS_L1 MA_DATA53 AD18 DDRA_SDQ54 [11] DDRB_SCS1# MB_CS_L1 MB_DATA53 AF17 DDRB_SDQ54
DDRA_SRAS# V21 MA_DATA54 AD17 DDRA_SDQ55 DDRB_SRAS# V24 MB_DATA54 AD16 DDRB_SDQ55
[10] DDRA_SRAS# DDRA_SCAS# W24 MA_RAS_L MA_DATA55 [11] DDRB_SRAS# DDRB_SCAS# V27 MB_RAS_L MB_DATA55
[10] DDRA_SCAS# W23 MA_CAS_L AA16 DDRA_SDQ56 [11] DDRB_SCAS# V28 MB_CAS_L AG15 DDRB_SDQ56
DDRA_SWE# DDRB_SWE#
[10] DDRA_SWE# MA_WE_L MA_DATA56 Y15 DDRA_SDQ57 [11] DDRB_SWE# MB_WE_L MB_DATA56 AD15 DDRB_SDQ57
MEM_MA_RST# H25 MA_DATA57 AA13 DDRA_SDQ58 MEM_MB_RST# J25 MB_DATA57 AG13 DDRB_SDQ58
[10] MEM_MA_RST# MEM_MA_EVENT# T24 MA_RESET_L MA_DATA58 AC13 DDRA_SDQ59 [11] MEM_MB_RST# MEM_MB_EVENT# T25 MB_RESET_L MB_DATA58 AD13 DDRB_SDQ59
[10] MEM_MA_EVENT# MA_EVENT_L MA_DATA59 Y17 DDRA_SDQ60 [11] MEM_MB_EVENT# MB_EVENT_L MB_DATA59 AG16 DDRB_SDQ60
W20 MA_DATA60 AB16 DDRA_SDQ61 MB_DATA60 AF15 DDRB_SDQ61
+MEM_VREF M_VREF MA_DATA61 AB14 DDRA_SDQ62 MB_DATA61 AE14 DDRB_SDQ62
1 2 M_ZVDDIO W21 MA_DATA62 Y13 DDRA_SDQ63 MB_DATA62 AF13 DDRB_SDQ63
+1.5V M_ZVDDIO MA_DATA63 MB_DATA63
R3 39.2_0402_1%

15mil Place them close to APU within 1" LOTES_ACA-ZIF-109-P12-A_FS1R2

LOTES_ACA-ZIF-109-P12-A_FS1R2 CONN@
CONN@

EVENT# pull high 0.75V reference voltage

+1.5V

+1.5V
2

4 R4 4
1K_0402_1%
R5 1 2 1K_0402_5% MEM_MA_EVENT# 15mil
1

R6 1 2 1K_0402_5% MEM_MB_EVENT# +MEM_VREF

2

1 2
R7
1K_0402_1% C45
1000P_0402_50V7K
C46 Security Classification Compal Secret Data Compal Electronics, Inc.
2 1
.1U_0402_16V7K Issued Date 2012/11/22 Deciphered Date 2015/11/22 Title

FS1r2 DDRIII Memory I/FRev

1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-8127P
Tuesday, March 12, 2013 Sheet 6 of 51
A B C D E
 A B C D E

JCPU1D
Place near APU
ANALOG/DISPLAY/MISC
C52 1 2 .1U_0402_16V7K DP0_TXP0 L3 D1 DP0_AUXP C53 1 2 .1U_0402_16V7K To LVDS If not used, pins are left unconnected (DG ref.)
[25] DP0_TXP0_C 1 2 .1U_0402_16V7K DP0_TXP0 DP0_AUXP DP0_AUXP_C [25]
C47 DP0_TXN0 L2 D2 DP0_AUXN C48 1 2 .1U_0402_16V7K 20101111
[25] DP0_TXN0_C DP0_TXN0 DP0_AUXN DP0_AUXN_C [25] Translater
K5 LVDS E1 ML_VGA_AUXP C54 1 2 .1U_0402_16V7K To FCH ML_VGA_AUXP R9 2 1 1.8K_0402_5%
K4 DP0_TXP1 DP1_AUXP E2 ML_VGA_AUXN C49 1 2 .1U_0402_16V7K ML_VGA_AUXP_C [13]
DP0_TXN1 DP1_AUXN ML_VGA_AUXN_C [13] MainLink ML_VGA_AUXN R8 2 1 1.8K_0402_5%
K2 D5 HDMI_CLK
K1 DP0_TXP2 DP2_AUXP D6 HDMI_DATA HDMI_CLK [27] DP0_AUXP 2 1 1.8K_0402_5%
To HDMI R79
DP0_TXN2 DP2_AUXN HDMI_DATA [27]

DISPLAY PORT 0
J3 E5 DP0_AUXN R81 2 1 1.8K_0402_5%
J2 DP0_TXP3 DP3_AUXP E6
DP0_TXN3 DP3_AUXN
To FCH
C61 1 2 .1U_0402_16V7K DP1_TXP0 H5 F5
1 [13] ML_VGA_TXP0 1 2 .1U_0402_16V7K DP1_TXP0 DP4_AUXP +1.5V 1
C62 DP1_TXN0 H4 F6
[13] ML_VGA_TXN0 DP1_TXN0 DP4_AUXN
Asserted as an input to force the

DISPLAY PORT MISC.

C63 1 2 .1U_0402_16V7K DP1_TXP1 H2 G5
[13] ML_VGA_TXP1 1 2 .1U_0402_16V7K DP1_TXN1 H1 DP1_TXP1 DP5_AUXP G6
processor into the HTC-active state
[13] ML_VGA_TXN1
C64
DP1_TXN1 DP5_AUXN H_PROCHOT#_EC: default low/active high

2
C65 1 2 .1U_0402_16V7K DP1_TXP2 G3 D3 LVDS_HPD R12
APU_PROCHOT# : default high/ active low
[13] ML_VGA_TXP2 DP1_TXP2 To FCH DP0_HPD LVDS_HPD [25]
C66 1 2 .1U_0402_16V7K DP1_TXN2 G2 E3 ML_VGA_HPD 1K_0402_5% H_PROCHOT#: default high/ active low
[13] ML_VGA_TXN2 DP1_TXN2 DP1_HPD D7 HDMI_DET ML_VGA_HPD [13]

DISPLAY PORT 1
1 2 .1U_0402_16V7K DP1_TXP3 F2 DP2_HPD E7 HDMI_DET [27]
C67
[13] ML_VGA_TXP3

1
C68 1 2 .1U_0402_16V7K DP1_TXN3 F1 DP1_TXP3 DP3_HPD F7 Q7
[13] ML_VGA_TXN3 DP1_TXN3 DP4_HPD

1
G7 2N7002K_SOT23-3
C50 1 2 .1U_0402_16V7K DP2_TXP0 L9 DP5_HPD D
[27] HDMI_TX2P 1 2 .1U_0402_16V7K DP2_TXN0 L8 DP2_TXP0 C6 APU_PROCHOT# 2
C51
[27] HDMI_TX2N DP2_TXN0 DP_BLON B6 H_PROCHOT#_EC [31,38]
G
C55 1 2 .1U_0402_16V7K DP2_TXP1 L5 DP_DIGON A6 DP_INT_PWM
[27] HDMI_TX1P DP_INT_PWM [9] S
C56 1 2 .1U_0402_16V7K DP2_TXN1 L6 DP2_TXP1 DP_VARY_BL
[27] HDMI_TX1N HDMI

3
DP2_TXN1 C1 DP_AUX_ZVSS R13 1 2 150_0402_1%
C57 1 2 .1U_0402_16V7K DP2_TXP2 K8 DP_AUX_ZVSS
[27] HDMI_TX0P 1 2 .1U_0402_16V7K DP2_TXN2 K7 DP2_TXP2 AD12
C58
[27] HDMI_TX0N DP2_TXN2 TEST6 M18 1 2 0_0402_5%
R78 @

DISPLAY PORT 2
TEST9 T1 H_PROCHOT# [38,45]
C59 1 2 .1U_0402_16V7K DP2_TXP3 J6 N18
[27] HDMI_CLKP DP2_TXP3 TEST10 T2
C60 1 2 .1U_0402_16V7K DP2_TXN3 J5 F11
[27] HDMI_CLKN DP2_TXN3 TEST14 T3
G11 T30
TEST15 T4
APU_CLK AE11 H11 T31
[12] APU_CLK CLKIN_H TEST16 T5
APU_CLK# AD11 J11
[12] APU_CLK# CLKIN_L TEST17 T6
F12 APU_TEST18 R14 1 2 1K_0402_5% Indicates to the FCH that a thermal trip

CLK
APU_DISP_CLK AB11 TEST18 G12 APU_TEST19 R15 1 2 1K_0402_5%
[12] APU_DISP_CLK APU_DISP_CLK# AA11 DISP_CLKIN_H TEST19 J12 APU_TEST20 1 2 THERMTRIP shutdown +1.5V has occurred. Its assertion will cause the
R16 1K_0402_5%
[12] APU_DISP_CLK# DISP_CLKIN_L TEST20 FCH to transition the system to S5 immediately
H12 APU_TEST24 1 2 Temperature: 125 degree

TEST
R17 1K_0402_5%
B3 TEST24 AE10 TEST25_H R20 1 2 510_0402_1%
[45] APU_SVC A3 SVC TEST25_H AD10 TEST25_L 1 2
R23 510_0402_1% +1.2VS
[45] APU_SVD SVD TEST25_L

1
L10 TEST28_H
2 TEST28_H T14 2
C3 M10 TEST28_L R21 R18

SER.
[45] APU_SVT SVT TEST28_L T15
P19 TEST30_H 1K_0402_5% 10K_0402_5%
TEST30_H T7
APU_SIC AG12 R19 TEST30_L
SIC TEST30_L T8
APU_SID AH12 K22 APU_TEST31 R25 1 2 39.2_0402_1%

2 2
T32 SID TEST31 T19
TEST32_H

B
APU_RST# AF10 N19
[12] APU_RST# AB12 RESET_L TEST32_L AA12 APU_TEST35 1 2 300_0402_5%
APU_PWRGD R26 +1.5V Q2
[12,45] APU_PWRGD PWROK TEST35

E
R27 1 @ 2 300_0402_5% APU_THERMTRIP# 3 1

CTRL
H_THERMTRIP# [14]

C
T33 APU_PROCHOT# AC10 W10 FS1R2 R28 1 2 10K_0402_5%
[12] APU_PROCHOT# PROCHOT_L FS1R2 +3VALW
APU_THERMTRIP# AE12 AC12 ALLOW_STOP MMBT3904_NL_SOT23-3
ALERT_L AF12 THERMTRIP_L DMAACTIVE_L ALLOW_STOP [12]
ALERT_L P18
TEST4 T9
T23 APU_TDI H10 R18
TDI TEST5 T10 +1.5V
T24 APU_TDO J10
T25 APU_TCK F10 TDO
T26 APU_TMS G10 TCK JTAG

T27 APU_TRST# F9 TMS Y10

TRST_L RSVD1

1
T28 APU_DBRDY G9 AA10
DBRDY RSVD2
RSVD
T29 APU_DBREQ# H9 Y12 R29
DBREQ_L RSVD3 K21 @ 10K_0402_5%
APU_VDD_SEN_L B4 RSVD4
[45] APU_VDD_SEN_L C5 VSS_SENSE

2 2
APU_VDDNB_SEN A4 VDDP_SENSE
[45] APU_VDDNB_SEN VDDNB_SENSE
SENSE

B
Route as differential A5
T20 C4 VDDIO_SENSE @ Q3
with VSS_SENSE VDD_SENSE

E
APU_VDD_SEN_H B5 ALERT_L 3 1 R30 1 @ 2 0_0402_5%
[45] APU_VDD_SEN_H VDDR_SENSE APU_ALERT#_FCH [13]

C
T21 LOTES_ACA-ZIF-109-P12-A_FS1R2 MMBT3904_NL_SOT23-3
CONN@ R31 1 @ 2 0_0402_5%
APU_ALERT#_EC [31]

+1.5V
3
CPU TSI interface level shift 3
R49 1 2 1K_0402_5% ALLOW_STOP SIT, NO.3
R52 1 2 1K_0402_5% APU_DBREQ#
C69 1 2 0.1U_0402_16V4Z
R32 1 2 1K_0402_5% APU_TCK BSH111, the Vgs is:
1 2 1K_0402_5% APU_TMS 1 R34 2 1 R35 2
min = 0.4V
R37 +3VS Max = 1.3V
R39 1 2 1K_0402_5% APU_TDI 31.6K_0402_1% 30K_0402_1%

R36 2 1 1K_0402_5% APU_TRST#

2

R33 1 @ 2 1K_0402_5% APU_SVT

G

Q4
R38 1 @ 2 1K_0402_5% APU_SVC
APU_SID 3 1 EC_SMB_DA R44 1 @ 2 0_0402_5% To EC
1 2 1K_0402_5% APU_SVD EC_SMB_DA2 [18,25,31,32]
R40 @
S

R47 1
@R47
@ 2 To FCH
1 2 1K_0402_5% APU_SIC FCH_SID [14]
R41 BSH111_SOT23-3 0_0402_5%

R43 1 2 1K_0402_5% APU_SID 1 @ R50 2

@R50
0_0402_5%
R46 1 2 1K_0402_5% ALERT_L
2

+1.5VS
G

Q5

R54 1 2 300_0402_5% APU_RST# APU_SIC 3 1 EC_SMB_CK R55 1 @ 2 0_0402_5% To EC

EC_SMB_CK2 [18,25,31,32]
S

R57 1 2 300_0402_5% APU_PWRGD R58 1

@R58
@ 2 To FCH
FCH_SIC [14]
0_0402_5%
4 BSH111_SOT23-3 4

1 @R59
@ R59 2
+3VS 0_0402_5%

R60 1 2 10K_0402_5% HDMI_CLK

R61 1 2 10K_0402_5% HDMI_DATA Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/11/22 Deciphered Date 2015/11/22 Title

Aux signal are re-configured as I2C signals for DDC. APU AUX pin are 3.3V tolerant THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL FS1r2
Size Document Number
Display/MISC/HDT Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Default follow PAWGX setting for pull-high resistor value Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-8127P
Tuesday, March 12, 2013 Sheet 7 of 51
A B C D E
 A B C D E

Power Name Consumption

VDD
+APU_CORE 60A JCPU1F
VDDNB J20 A19
+APU_CORE L4 VSS_1 VSS_73 A21
+APU_CORE_NB 44A R7 VSS_2 VSS_74 A23
W18 VSS_3 VSS_75 A25
VDDIO VSS_4 VSS_76
A15 A7
+1.5V 3.2A VSS_5 VSS_77

C73

0.22U_0402_6.3V6K

C74

0.22U_0402_6.3V6K

C70

0.01U_0402_16V7K

C71

0.01U_0402_16V7K

C75

0.01U_0402_16V7K

C72

180P_0402_50V8J

C76

180P_0402_50V8J
AB17 AA4
AC22 VSS_6 VSS_78 AA7
VDDP / VDDR +APU_CORE JCPU1E +APU_CORE
1 1 1 1 1 1 1 VSS_7 VSS_79
AE21 AB13
+1.2VS 5A / 3.5A AF24 VSS_8 VSS_80 AB15
F8 R11 AH23 VSS_9 VSS_81 AB19
1
VDDA VDD_1 VDD_32 2 2 2 2 2 2 2 VSS_10 VSS_82 1
H6 T10 AH25 AB21
+2.5VS 0.5A J1 VDD_2 VDD_33 H8 B7 VSS_11 VSS_83 AB23
J14 VDD_3 VDD_34 G1 C14 VSS_12 VSS_84 AB25
P6 VDD_4 VDD_35 U11 C16 VSS_13 VSS_85 AB27
P10 VDD_5 VDD_36 W11 C2 VSS_14 VSS_86 AB9
J16 VDD_6 VDD_37 W13 C20 VSS_15 VSS_87 AC14
J18 VDD_7 VDD_38 W15 +APU_CORE_NB C22 VSS_16 VSS_88 AC16
J9 VDD_8 VDD_39 W17 C24 VSS_17 VSS_89 AC18
K19 VDD_9 VDD_40 W19 C26 VSS_18 VSS_90 AC20
K3 VDD_10 VDD_41 AB3 C28 VSS_19 VSS_91 AC24
VDD_11 VDD_42 VSS_20 VSS_92

C77

0.22U_0402_6.3V6K

C78

0.22U_0402_6.3V6K

C79

180P_0402_50V8J

C80

180P_0402_50V8J

C81

180P_0402_50V8J
K17 AD3 D13 AC26
M3 VDD_12 VDD_43 AD6 D15 VSS_21 VSS_93 AC28
VDD_13 VDD_44 1 1 1 1 1 VSS_22 VSS_94
K6 AE1 D17 AC4
V10 VDD_14 VDD_45 L1 D19 VSS_23 VSS_95 AC7
V18 VDD_15 VDD_46 Y6 D23 VSS_24 VSS_96 AD9
V3 VDD_16 VDD_47 M6 2 2 2 2 2 D25 VSS_25 VSS_97 AE13
F3 VDD_17 VDD_48 N11 D27 VSS_26 VSS_98 AE15
L18 VDD_18 VDD_49 N1 E4 VSS_27 VSS_99 AE17
V6 VDD_19 VDD_50 T3 E9 VSS_28 VSS_100 M9
W1 VDD_20 VDD_51 T6 F14 VSS_29 VSS_101 N10
T18 VDD_21 VDD_52 U19 F16 VSS_30 VSS_102 N4
Y14 VDD_22 VDD_53 U1 +1.5V F18 VSS_31 VSS_103 N7
AA1 VDD_23 VDD_54 Y16 F20 VSS_32 VSS_104 R10
AB6 VDD_24 VDD_55 Y18 F22 VSS_33 VSS_105 R4
AC1 VDD_25 VDD_56 Y3 F26 VSS_34 VSS_106 T11
VDD_26 VDD_57 VSS_35 VSS_107

C82

22U_0603_6.3V6M

C83

22U_0603_6.3V6M

C84

22U_0603_6.3V6M

C85

22U_0603_6.3V6M

C86

22U_0603_6.3V6M

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

C91

0.22U_0402_6.3V6K

C92

0.22U_0402_6.3V6K

C93

0.22U_0402_6.3V6K

C94

0.22U_0402_6.3V6K

C95

0.22U_0402_6.3V6K

C96

0.22U_0402_6.3V6K

C97

180P_0402_50V8J

C136

180P_0402_50V8J

C98

330U_D2_2.5VY_R9M
R1 D4 1 F28 T9
VDD_27 VDD_58 VSS_36 VSS_108

C87

C88

C89

C90
P3 F4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 G13 U10
K10 VDD_28 VDD_59 AF6 + G15 VSS_37 VSS_109 U18
H3 VDD_29 VDD_60 AF3 @ G17 VSS_38 VSS_110 U4
M19 VDD_30 VDD_61 L11 G19 VSS_39 VSS_111 U7
VDD_31 VDD_62 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 G21 VSS_40 VSS_112 V11
G23 VSS_41 VSS_113 AE19
2 C8 C11 G25 VSS_42 VSS_114 AE23 2
+APU_CORE_NB VDDNB_1 VDDNB_13 +APU_CORE_NB VSS_43 VSS_115
D10 C12 G4 AE25
B8 VDDNB_2 VDDNB_14 D9 J22 VSS_44 VSS_116 AE27
B12 VDDNB_3 VDDNB_15 D8 J24 VSS_45 VSS_117 AE4
C9 VDDNB_4 VDDNB_16 D12 J4 VSS_46 VSS_118 AE7
A9 VDDNB_5 VDDNB_17 D11 J7 VSS_47 VSS_119 AF14
A10 VDDNB_6 VDDNB_18 B11 K11 VSS_48 VSS_120 AF16
A8 VDDNB_7 VDDNB_19 A12 +APU_CORE_NB_CAP K14 VSS_49 VSS_121 AF18
A11 VDDNB_8 VDDNB_20 B10 +1.5V K9 VSS_50 VSS_122 AF20
VDDNB_9 VDDNB_21 Across VDDIO and VSS VSS_51 VSS_123
E10 E12 AC11 AF22
E11 VDDNB_10 VDDNB_22 B9
split L19 VSS_52 VSS_124 AF26
C10 VDDNB_11 VDDNB_23 L7 VSS_53 VSS_125 AF28
VDDNB_12 VSS_54 VSS_126

C99

0.22U_0402_6.3V6K

C100

0.22U_0402_6.3V6K

C101

180P_0402_50V8J

C102

180P_0402_50V8J

C216

22U_0603_6.3V6M

C214

22U_0603_6.3V6M

C215

22U_0603_6.3V6M

C217

180P_0402_50V8J
K13 M11 AF9
VDDNB_CAP_1 +APU_CORE_NB_CAP VSS_55 VSS_127
K12 1 1 1 1 1 1 1 1 AF11 AG4
VDDNB_CAP_2 V19 VSS_56 VSS_128 AG7
@ V9 VSS_57 VSS_129 AH13
W16 VSS_58 VSS_130 AH15
H26 T23 2 2 2 2 2 2 2 2 W4 VSS_59 VSS_131 AH17
+1.5V VDDIO_1 VDDIO_19 +1.5V VSS_60 VSS_132
K20 T26 W7 AH19
J28 VDDIO_2 VDDIO_20 U22 Y11 VSS_61 VSS_133 AH21
K23 VDDIO_3 VDDIO_21 U25 Y20 VSS_62 VSS_134 P9
K26 VDDIO_4 VDDIO_22 U28 Y22 VSS_63 VSS_135 C18
L22 VDDIO_5 VDDIO_23 Y26 Y9 VSS_64 VSS_136 D21
L25 VDDIO_6 VDDIO_24 T20 A17 VSS_65 VSS_137 W14
L28 VDDIO_7 VDDIO_25 R28 A13 VSS_66 VSS_138 P11
M20 VDDIO_8 VDDIO_26 R25 K16 VSS_67 VSS_139 C7
M23 VDDIO_9 VDDIO_27 R22 F24 VSS_68 VSS_140 E8
M26 VDDIO_10 VDDIO_28 V20 G8 VSS_69 VSS_141 K18
N22 VDDIO_11 VDDIO_29 V23 H7 VSS_70 VSS_142 W12
N25 VDDIO_12 VDDIO_30 V26 J8 VSS_71 VSS_143
N28 VDDIO_13 VDDIO_31 W22 VSS_72
P20 VDDIO_14 VDDIO_32 W25 LOTES_ACA-ZIF-109-P12-A_FS1R2
3 P23 VDDIO_15 VDDIO_33 W28 CONN@ 3
P26 VDDIO_16 VDDIO_34 Y24
AA28 VDDIO_17 VDDIO_35 G28
+1.2VS VDDIO_18 VDDIO_36
VDDR decoupling
AH6 AG10
AH5 VDDP_1 VDDR_1 AH8
VDDP_2 VDDR_2 VDDR decoupling
180P_0402_50V8J

180P_0402_50V8J

AH4 AH9
VDDP_3 VDDR_3
C103

C104

C105

0.22U_0402_6.3V6K

C106

0.22U_0402_6.3V6K

AH3 AH10
VDDP_4 VDDR_4 +1.2VS
1 1 1 1 AH7
VDDP_5
C107

180P_0402_50V8J

C108

180P_0402_50V8J

C109

1000P_0402_50V7K

C110

1000P_0402_50V7K

C111

1000P_0402_50V7K

C112

1000P_0402_50V7K

C113

0.22U_0402_6.3V6K

C114

0.22U_0402_6.3V6K

AB10 1 1 1 1 1 1 1 1
VDDA
2 2 2 2

LOTES_ACA-ZIF-109-P12-A_FS1R2 2 2 2 @2 @2 @2 2 2
Demo Board Capacitor
CONN@
APU_CORE CORE_NB CORE_NB_CAP VDDIO_SUS
22uF x 10 22uF x 2 22uF x 2 (CPU side)
0.22uF x 2 10uF x 1 180pF x 1 22uF x 4
0.01uF x 3 0.22uF x 2 4.7uF x 4
180pF x 2 180pF x 3 0.22uF x 6 +2(split)
180pF x 1 + 2(split)

VDDP VDDR VDDA VDDIO_SUS

4 4
+2.5VS L1
0.22uF x 2 0.22uF x 2 4.7uF x 1 (DIMM x2)
40mil
FBMA-L11-201209-221LMA30T_0805 180pF x 2 1nF x 4 0.22uF x 1 100uF x 2
2 1 +VDDA
180pF x 2 3.3nF x 1 0.1uF x 12
C115

3300P_0402_50V7-K

C116

0.22U_0402_6.3V6K

C117

4.7U_0402_6.3V6M

1 1 1
Security Classification Compal Secret Data Compal Electronics, Inc.
2 2 2 Issued Date 2012/11/22 Deciphered Date 2015/11/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
FS1r2 PWR/GND Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-8127P
Tuesday, March 12, 2013 Sheet 8 of 51
A B C D E
 5 4 3 2 1

D D
+3VS
Panel PWM

1
R62 R63
47K_0402_5% 4.7K_0402_5%

2
APU_INVT_PWM [25]

1
D Q6
2
C G C

MMBT3904_NL_SOT23-3
S 2N7002K_SOT23-3

1
Q8 C

3
1 2 2
[7] DP_INT_PWM
R66 2.2K_0402_5% B
E

3
1

R67
4.7K_0402_5%
2

B B

A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/11/22 Deciphered Date 2015/11/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL FS1r2 Signal Level Shifter
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-8127P
Tuesday, March 12, 2013 Sheet 9 of 51
5 4 3 2 1
 A B C D E

+VREF_DQ +1.5V +1.5V

JDIMM2
1 2
3 VREF_DQ VSS1 4 DDRA_SDQ4
DDRA_SDQ0 5 VSS2 DQ4 6 DDRA_SDQ5
DDRA_SDQ1 7 DQ0 DQ5 8
9 DQ1 VSS3 10 DDRA_SDQS0#
11 VSS4 DQS#0 12 DDRA_SDQS0# [6]
DDRA_SDM0 DDRA_SDQS0
DM0 DQS0 DDRA_SDQS0 [6]
13 14
DDRA_SDQ2 15 VSS5 VSS6 16 DDRA_SDQ6
DDRA_SDQ3 17 DQ2 DQ6 18 DDRA_SDQ7
19 DQ3 DQ7 20
DDRA_SDQ8 21 VSS7 VSS8 22 DDRA_SDQ12 DDRA_SDQ[0..63]
DDRA_SDQ9 23 DQ8 DQ12 24 DDRA_SDQ13 DDRA_SDQ[0..63] [6]
1
25 DQ9 DQ13 26 DDRA_SDM[0..7] 1
VSS9 VSS10 DDRA_SDM[0..7] [6]
DDRA_SDQS1# 27 28 DDRA_SDM1
[6] DDRA_SDQS1# DQS#1 DM1 DDRA_SMA[0..15]
DDRA_SDQS1 29 30 MEM_MA_RST# DDRA_SMA[0..15] [6]
[6] DDRA_SDQS1 31 DQS1 RESET# 32 MEM_MA_RST# [6]
DDRA_SDQ10 33 VSS11 VSS12 34 DDRA_SDQ14
DDRA_SDQ11 35 DQ10 DQ14 36 DDRA_SDQ15
37 DQ11 DQ15 38
DDRA_SDQ16 39 VSS13 VSS14 40 DDRA_SDQ20
DDRA_SDQ17 41 DQ16 DQ20 42 DDRA_SDQ21
43 DQ17 DQ21 44
DDRA_SDQS2# 45 VSS15 VSS16 46 DDRA_SDM2
[6] DDRA_SDQS2# 47 DQS#2 DM2 48
DDRA_SDQS2
[6] DDRA_SDQS2 DQS2 VSS17
49 50 DDRA_SDQ22
DDRA_SDQ18 51 VSS18 DQ22 52 DDRA_SDQ23
DDRA_SDQ19 53 DQ18 DQ23 54 +1.5V
Place near DIMM1
55 DQ19 VSS19 56 DDRA_SDQ28
DDRA_SDQ24 57 VSS20 DQ28 58 DDRA_SDQ29 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SDQ25 59 DQ24 DQ29 60
DQ25 VSS21 2 2 2 2 2 2
61 62 DDRA_SDQS3#
VSS22 DQS#3 DDRA_SDQS3# [6]
DDRA_SDM3 63 64 DDRA_SDQS3 C2001 C2002 C2003 C2004 C2005 C2006
DM3 DQS3 DDRA_SDQS3 [6]
65 66
DDRA_SDQ26 67 VSS23 VSS24 68 DDRA_SDQ30 1 1 1 1 1 1
DDRA_SDQ27 69 DQ26 DQ30 70 DDRA_SDQ31 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
71 DQ27 DQ31 72
VSS25 VSS26

DDRA_CKE0 73 74 DDRA_CKE1
[6] DDRA_CKE0 75 CKE0 CKE1 76 DDRA_CKE1 [6]
77 VDD1 VDD2 78 DDRA_SMA15
DDRA_SBS2# 79 NC1 A15 80 DDRA_SMA14
[6] DDRA_SBS2# 81 BA2 A14 82
DDRA_SMA12 83 VDD3 VDD4 84 DDRA_SMA11
DDRA_SMA9 85 A12/BC# A11 86 DDRA_SMA7
87 A9 A7 88
DDRA_SMA8 89 VDD5 VDD6 90 DDRA_SMA6
DDRA_SMA5 91 A8 A6 92 DDRA_SMA4
93 A5 A4 94
2 2
DDRA_SMA3 95 VDD7 VDD8 96 DDRA_SMA2
DDRA_SMA1 97 A3 A2 98 DDRA_SMA0
99 A1 A0 100
DDRA_CLK0 101 VDD9 VDD10 102 DDRA_CLK1
[6] DDRA_CLK0 CK0 CK1 DDRA_CLK1 [6]
DDRA_CLK0# 103 104 DDRA_CLK1#
[6] DDRA_CLK0# 105 CK0# CK1# 106 DDRA_CLK1# [6]
DDRA_SMA10 107 VDD11 VDD12 108 DDRA_SBS1#
A10/AP BA1 DDRA_SBS1# [6]
DDRA_SBS0# 109 110 DDRA_SRAS#
[6] DDRA_SBS0# 111 BA0 RAS# 112 DDRA_SRAS# [6]
DDRA_SWE# 113 VDD13 VDD14 114 DDRA_SCS0# +1.5V
[6] DDRA_SWE# 115 WE# S0# 116 DDRA_SCS0# [6] +1.5V
DDRA_SCAS# DDRA_ODT0
[6] DDRA_SCAS# CAS# ODT0 DDRA_ODT0 [6]
117 118
VDD15 VDD16

2
DDRA_SMA13 119 120 DDRA_ODT1
A13 ODT1 DDRA_ODT1 [6]

2
DDRA_SCS1# 121 122 R2002
[6] DDRA_SCS1# 123 S1# NC2 124 R2001 +VREF_CA 1K_0402_1%
125 VDD17 VDD18 126 +VREF_DQ 1K_0402_1%
NCTEST VREF_CA +VREF_CA
127 128 15mil

1
DDRA_SDQ32 129 VSS27 VSS28 130 DDRA_SDQ36 +VREF_CA
15mil

1
DDRA_SDQ33 131 DQ32 DQ36 132 DDRA_SDQ37 +VREF_DQ
133 DQ33 DQ37 134

1000P_0402_50V7K
0.1U_0402_16V4Z
DDRA_SDQS4# 135 VSS29 VSS30 136 DDRA_SDM4

1000P_0402_50V7K
[6] DDRA_SDQS4#

0.1U_0402_16V4Z
DQS#4 DM4

2
DDRA_SDQS4 137 138 1 1
[6] DDRA_SDQS4 DQS4 VSS31

2
139 140 DDRA_SDQ38 1 1 C2000 C2009 R2004
DDRA_SDQ34 141 VSS32 DQ38 142 DDRA_SDQ39 C2007 C2008 R2003 1K_0402_1%
DDRA_SDQ35 143 DQ34 DQ39 144 1K_0402_1%
145 DQ35 VSS33 146 DDRA_SDQ44 2 2

1
DDRA_SDQ40 147 VSS34 DQ44 148 DDRA_SDQ45 2 2

1
DDRA_SDQ41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDRA_SDQS5#
VSS36 DQS#5 DDRA_SDQS5# [6]
DDRA_SDM5 153 154 DDRA_SDQS5
155 DM5 DQS5 156 DDRA_SDQS5 [6]
DDRA_SDQ42 157 VSS37 VSS38 158 DDRA_SDQ46
DDRA_SDQ43 159 DQ42 DQ46 160 DDRA_SDQ47
161 DQ43 DQ47 162
DDRA_SDQ48 163 VSS39 VSS40 164 DDRA_SDQ52
DDRA_SDQ49 165 DQ48 DQ52 166 DDRA_SDQ53
167 DQ49 DQ53 168
3
DDRA_SDQS6# 169 VSS41 VSS42 170 DDRA_SDM6 +1.5V
3
[6] DDRA_SDQS6# 171 DQS#6 DM6 172
DDRA_SDQS6
[6] DDRA_SDQS6 DQS6 VSS43
173 174 DDRA_SDQ54
DDRA_SDQ50 175 VSS44 DQ54 176 DDRA_SDQ55
DDRA_SDQ51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDRA_SDQ60
VSS46 DQ60 1
DDRA_SDQ56 181 182 DDRA_SDQ61
DDRA_SDQ57 183 DQ56 DQ61 184 + C2025
185 DQ57 VSS47 186 DDRA_SDQS7# 330U_D2_2V_Y
VSS48 DQS#7 DDRA_SDQS7# [6]
DDRA_SDM7 187 188 DDRA_SDQS7
DM7 DQS7 DDRA_SDQS7 [6] 2
189 190
DDRA_SDQ58 191 VSS49 VSS50 192 DDRA_SDQ62
DDRA_SDQ59 193 DQ58 DQ62 194 DDRA_SDQ63
R2005 10K_0402_5% 195 DQ59 DQ63 196
1 2 197 VSS51 VSS52 198 MEM_MA_EVENT#
SA0 EVENT# MEM_MA_EVENT# [6]
199 200
+3VS 201 VDDSPD SDA 202 FCH_SDATA0 [11,14,31,33]
SA1 SCL FCH_SCLK0 [11,14,31,33]
203 204 +0.75VS
VTT1 VTT2
1

1 1
205 206
C2010 C2011 R2000 G1 G2
2.2U_0603_6.3V6K 0.1U_0402_16V4Z 10K_0402_5% FOX_AS0A626-U2RN-7F
2 2 CONN@
2

Reverse H:5.2mm
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/22 Deciphered Date 2015/11/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
DDRIII SO-DIMM 1
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-8127P
Tuesday, March 12, 2013 Sheet 10 of 51
A B C D E
 A B C D E

DDRB_SDQ[0..63]
DDRB_SDQ[0..63] [6]
DDRB_SDM[0..7]
DDRB_SDM[0..7] [6]
+1.5V +1.5V DDRB_SMA[0..15]
DDRB_SMA[0..15] [6]
+VREF_DQ JDIMM1
1 2
3 VREF_DQ VSS1 4 DDRB_SDQ4
DDRB_SDQ0 5 VSS2 DQ4 6 DDRB_SDQ5 +VREF_DQ
DDRB_SDQ1 7 DQ0 DQ5 8 +VREF_CA
9 DQ1 VSS3 10 DDRB_SDQS0#
1
DDRB_SDM0 11 VSS4 DQS#0 12 DDRB_SDQS0
DDRB_SDQS0# [6] 15mil 15mil 1
13 DM0 DQS0 14 DDRB_SDQS0 [6]
+VREF_DQ +VREF_CA
DDRB_SDQ2 15 VSS5 VSS6 16 DDRB_SDQ6
DQ2 DQ6

1000P_0402_50V7K

1000P_0402_50V7K
DDRB_SDQ3 17 18 DDRB_SDQ7
DQ3 DQ7

0.1U_0402_16V4Z

0.1U_0402_16V4Z
19 20
DDRB_SDQ8 21 VSS7 VSS8 22 DDRB_SDQ12
DQ8 DQ12 1 1 1 1

C2012

C2013

C2014
DDRB_SDQ9 23 24 DDRB_SDQ13 C2015
25 DQ9 DQ13 26
DDRB_SDQS1# 27 VSS9 VSS10 28 DDRB_SDM1
[6] DDRB_SDQS1# DQS#1 DM1 2 2 2 2
DDRB_SDQS1 29 30 MEM_MB_RST#
[6] DDRB_SDQS1 DQS1 RESET# MEM_MB_RST# [6]
31 32
DDRB_SDQ10 33 VSS11 VSS12 34 DDRB_SDQ14
DDRB_SDQ11 35 DQ10 DQ14 36 DDRB_SDQ15
37 DQ11 DQ15 38
DDRB_SDQ16 39 VSS13 VSS14 40 DDRB_SDQ20
DDRB_SDQ17 41 DQ16 DQ20 42 DDRB_SDQ21
43 DQ17 DQ21 44
DDRB_SDQS2# 45 VSS15 VSS16 46 DDRB_SDM2
[6] DDRB_SDQS2# 47 DQS#2 DM2 48
DDRB_SDQS2
[6] DDRB_SDQS2 DQS2 VSS17
49 50 DDRB_SDQ22
DDRB_SDQ18 51 VSS18 DQ22 52 DDRB_SDQ23
DDRB_SDQ19 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDRB_SDQ28
DDRB_SDQ24 57 VSS20 DQ28 58 DDRB_SDQ29
DDRB_SDQ25 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDRB_SDQS3#
DDRB_SDM3 63 VSS22 DQS#3 64 DDRB_SDQS3
DDRB_SDQS3# [6] Place near DIMM2
DM3 DQS3 DDRB_SDQS3 [6]
65 66 +1.5V
DDRB_SDQ26 67 VSS23 VSS24 68 DDRB_SDQ30
DDRB_SDQ27 69 DQ26 DQ30 70 DDRB_SDQ31 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
71 DQ27 DQ31 72
VSS25 VSS26 2 2 2 2 2 2
C2016 C2017 C2018 C2019 C2020 C2021

DDRB_CKE0 73 74 DDRB_CKE1 1 1 1 1 1 1
[6] DDRB_CKE0 CKE0 CKE1 DDRB_CKE1 [6]
75 76 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
77 VDD1 VDD2 78 DDRB_SMA15
DDRB_SBS2# 79 NC1 A15 80 DDRB_SMA14
2 2
[6] DDRB_SBS2# 81 BA2 A14 82
DDRB_SMA12 83 VDD3 VDD4 84 DDRB_SMA11
DDRB_SMA9 85 A12/BC# A11 86 DDRB_SMA7
87 A9 A7 88
DDRB_SMA8 89 VDD5 VDD6 90 DDRB_SMA6
DDRB_SMA5 91 A8 A6 92 DDRB_SMA4
93 A5 A4 94
DDRB_SMA3 95 VDD7 VDD8 96 DDRB_SMA2 +0.75VS
DDRB_SMA1 97 A3 A2 98 DDRB_SMA0 +1.5V
99 A1 A0 100
DDRB_CLK0 101 VDD9 VDD10 102 DDRB_CLK1
[6] DDRB_CLK0 CK0 CK1 DDRB_CLK1 [6]
DDRB_CLK0# 103 104 DDRB_CLK1# 2 1
[6] DDRB_CLK0# CK0# CK1# DDRB_CLK1# [6]
105 106
DDRB_SMA10 107 VDD11 VDD12 108 DDRB_SBS1# C2022 C2023
A10/AP BA1 DDRB_SBS1# [6] 1
DDRB_SBS0# 109 110 DDRB_SRAS# 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
[6] DDRB_SBS0# 111 BA0 RAS# 112 DDRB_SRAS# [6] 1 2 + C2024
DDRB_SWE# 113 VDD13 VDD14 114 DDRB_SCS0# 330U_D2_2V_Y
[6] DDRB_SWE# WE# S0# DDRB_SCS0# [6]
DDRB_SCAS# 115 116 DDRB_ODT0 @
[6] DDRB_SCAS# 117 CAS# ODT0 118 DDRB_ODT0 [6] 2
VDD15 VDD16
8/25
DDRB_SMA13 119 120 DDRB_ODT1
121 A13 ODT1 122 DDRB_ODT1 [6]
DDRB_SCS1#
[6] DDRB_SCS1# 123 S1# NC2 124
125 VDD17 VDD18 126
NCTEST VREF_CA +VREF_CA
127 128
DDRB_SDQ32 129 VSS27 VSS28 130 DDRB_SDQ36
DDRB_SDQ33 131 DQ32 DQ36 132 DDRB_SDQ37
133 DQ33 DQ37 134
DDRB_SDQS4# 135 VSS29 VSS30 136 DDRB_SDM4
[6] DDRB_SDQS4# 137 DQS#4 DM4 138
DDRB_SDQS4
[6] DDRB_SDQS4 DQS4 VSS31
139 140 DDRB_SDQ38
DDRB_SDQ34 141 VSS32 DQ38 142 DDRB_SDQ39
DDRB_SDQ35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDRB_SDQ44
DDRB_SDQ40 147 VSS34 DQ44 148 DDRB_SDQ45
DDRB_SDQ41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDRB_SDQS5#
VSS36 DQS#5 DDRB_SDQS5# [6]
DDRB_SDM5 153 154 DDRB_SDQS5
3 DM5 DQS5 DDRB_SDQS5 [6] 3
155 156
DDRB_SDQ42 157 VSS37 VSS38 158 DDRB_SDQ46
DDRB_SDQ43 159 DQ42 DQ46 160 DDRB_SDQ47
161 DQ43 DQ47 162
DDRB_SDQ48 163 VSS39 VSS40 164 DDRB_SDQ52
DDRB_SDQ49 165 DQ48 DQ52 166 DDRB_SDQ53
167 DQ49 DQ53 168
DDRB_SDQS6# 169 VSS41 VSS42 170 DDRB_SDM6
[6] DDRB_SDQS6# 171 DQS#6 DM6 172
DDRB_SDQS6
[6] DDRB_SDQS6 DQS6 VSS43
173 174 DDRB_SDQ54
DDRB_SDQ50 175 VSS44 DQ54 176 DDRB_SDQ55
DDRB_SDQ51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDRB_SDQ60
DDRB_SDQ56 181 VSS46 DQ60 182 DDRB_SDQ61
DDRB_SDQ57 183 DQ56 DQ61 184
185 DQ57 VSS47 186 DDRB_SDQS7#
187 VSS48 DQS#7 188 DDRB_SDQS7# [6]
DDRB_SDM7 DDRB_SDQS7
DM7 DQS7 DDRB_SDQS7 [6]
189 190
DDRB_SDQ58 191 VSS49 VSS50 192 DDRB_SDQ62
DDRB_SDQ59 193 DQ58 DQ62 194 DDRB_SDQ63
R2006 10K_0402_5% 195 DQ59 DQ63 196
1 2 197 VSS51 VSS52 198 MEM_MB_EVENT#
SA0 EVENT# MEM_MB_EVENT# [6]
199 200
+3VS 201 VDDSPD SDA 202 FCH_SDATA0 [10,14,31,33]
SA1 SCL FCH_SCLK0 [10,14,31,33]
203 204 +0.75VS
VTT1 VTT2
1

R2007 205 206

G1 G2
10K_0402_5% FOX_AS0A626-UARN-7F
CONN@
2

4 4
Reverse H:9.2mm

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/22 Deciphered Date 2015/11/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
DDRIII SO-DIMM 2
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-8127P
Tuesday, March 12, 2013 Sheet 11 of 51
A B C D E
 A B C D E

C125 SDV/FVT, NO.12

1 2 U2A

R90/ C146 close to FCH 150P_0402_50V8J HUDSON-2

APU_PCIE_RST#_C AE2 AF3
PLT_RST# 1 R72 2 33_0402_5% A_RST# AD5 PCIE_RST# PCICLK0 AF1

PCI CLKS
A_RST# PCICLK1/GPO36 AF5 PCI_CLK1 [16]
C126 1 2 .1U_0402_16V7K UMI_RXP0_C AE30 PCICLK2/GPO37 AG2
[5] UMI_RXP0 1 2 UMI_RXN0_C AE32 UMI_TX0P PCICLK3/GPO38 AF6 PCI_CLK3 [16]
C118 .1U_0402_16V7K
[5] UMI_RXN0 1 2 UMI_RXP1_C AD33 UMI_TX0N PCICLK4/14M_OSC/GPO39 PCI_CLK4 [16]
C119 .1U_0402_16V7K
[5] UMI_RXP1 1 2 AD31 UMI_TX1P AB5
C120 .1U_0402_16V7K UMI_RXN1_C
[5] UMI_RXN1 1 2 UMI_RXP2_C AD28 UMI_TX1N PCIRST#
C127 .1U_0402_16V7K
[5] UMI_RXP2 1 2 UMI_RXN2_C AD29 UMI_TX2P
C121 .1U_0402_16V7K
[5] UMI_RXN2 1 2 UMI_RXP3_C AC30 UMI_TX2N AJ3
C128 .1U_0402_16V7K
[5] UMI_RXP3 1 2 AC32 UMI_TX3P AD0/GPIO0 AL5
C122 .1U_0402_16V7K UMI_RXN3_C
1 [5] UMI_RXN3 UMI_TX3N AD1/GPIO1 AG4 1
AB33 AD2/GPIO2 AL6
[5] UMI_TXP0 AB31 UMI_RX0P AD3/GPIO3 AH3
[5] UMI_TXN0 UMI_RX0N AD4/GPIO4

PCI EXPRESS INTERFACES

AB28 AJ5
[5] UMI_TXP1 AB29 UMI_RX1P AD5/GPIO5 AL1
[5] UMI_TXN1 Y33 UMI_RX1N AD6/GPIO6 AN5
[5] UMI_TXP2 Y31 UMI_RX2P AD7/GPIO7 AN6
[5] UMI_TXN2 Y28 UMI_RX2N AD8/GPIO8 AJ1
[5] UMI_TXP3 Y29 UMI_RX3P AD9/GPIO9 AL8
[5] UMI_TXN3 UMI_RX3N AD10/GPIO10 AL3
R71 1 2 590_0402_1% PCIE_CALRP AF29 AD11/GPIO11 AM7
R73 1 2 2K_0402_1% PCIE_CALRN AF31 PCIE_CALRP AD12/GPIO12 AJ6
+VDDAN_11_PCIE PCIE_CALRN AD13/GPIO13 AK7
V33 AD14/GPIO14 AN8
V31 GPP_TX0P AD15/GPIO15 AG9
C129 1 2 32K_X1 W30 GPP_TX0N AD16/GPIO16 AM11
W32 GPP_TX1P AD17/GPIO17 AJ10
22P_0402_50V8J AB26 GPP_TX1N AD18/GPIO18 AL12
GPP_TX2P AD19/GPIO19
1

AB27 AK11
Y1 AA24 GPP_TX2N AD20/GPIO20 AN12
R75 AA23 GPP_TX3P AD21/GPIO21 AG12
32.768KHZ_12.5PF_CM31532768DZFT GPP_TX3N AD22/GPIO22
20M_0402_5% AE12
PCI_AD23 [16]
2

AA27 AD23/GPIO23 AC12

PCI_AD24 [16]
2

AA26 GPP_RX0P AD24/GPIO24 AE13

GPP_RX0N AD25/GPIO25 PCI_AD25 [16]
C130 1 2 32K_X2 W27 AF13
V27 GPP_RX1P AD26/GPIO26 AH13 PCI_AD26 [16]

PCI INTERFACE
V26 GPP_RX1N AD27/GPIO27 AH14 PCI_AD27 [16]
22P_0402_50V8J Close to HUDSON-M2/3 GPP_RX2P AD28/GPIO28
W26 AD15
W24 GPP_RX2N AD29/GPIO29 AC15
W23 GPP_RX3P AD30/GPIO30 AE16
GPP_RX3N AD31/GPIO31 AN3
CBE0# AJ8
2 R74 CBE1# AN10 2
1 2 2K_0402_1% CLK_CALRN F27 CBE2# AD12
+1.1VS_CKVDD CLK_CALRN CBE3# AG10
FRAME# AK9
10P_0402_50V8J DEVSEL# AL10
1 2 25M_X1 G30 IRDY# AF10
G28 PCIE_RCLKP TRDY# AE10
C131 X1 PCIE_RCLKN PAR AH1
25MHZ_10PF_X3G025000DA1H-X R26 STOP# AM9
[7] APU_DISP_CLK T26 DISP_CLKP PERR# AH8
1 3 [7] APU_DISP_CLK# DISP_CLKN SERR# AG15
R88
1 3 H33 REQ0# AG13
1M_0402_5% DISP2_CLKP REQ1#/GPIO40
GND GND H31 AF15
DISP2_CLKN REQ2#/CLK_REQ8#/GPIO41 AM17
2 4 REQ3#/CLK_REQ5#/GPIO42 T11
C134 T24 AD16
1 2 [7] APU_CLK T23 APU_CLKP GNT0# AD13
25M_X2 R209 1 @ 2 0_0402_5%
[7] APU_CLK# APU_CLKN GNT1#/GPO44 AD21 PXS_RST# [14,17]
R208 1 @ 2 0_0402_5%
1 2 0_0402_5% J30 GNT2#/SD_LED/GPO45 AK17 PXS_PWREN [14,19,43,44]
10P_0402_50V8J R76 @ CLK_PCIE_VGA_R
[17] CLK_PCIE_VGA SLT_GFX_CLKP GNT3#/CLK_REQ7#/GPIO46 T22
R77 1 @ 2 0_0402_5% CLK_PCIE_VGA#_R K29 AD19
[17] CLK_PCIE_VGA# SLT_GFX_CLKN CLKRUN# AH9
H27 LOCK#
H28 GPP_CLK0P AF18
GPP_CLK0N INTE#/GPIO32 AE18
J27 INTF#/GPIO33 AC16
K26 GPP_CLK1P INTG#/GPIO34 AD18
GPP_CLK1N INTH#/GPIO35

WLAN R150 1 @ 2 0_0402_5% CLK_PCIE_WLAN_R F33 R110 1 @ 2 0_0402_5%

[33] CLK_PCIE_WLAN GPP_CLK2P CLK_PCI_DB [33,35]
R142 1 @ 2 0_0402_5% CLK_PCIE_WLAN#_R F31

CLOCK GENERATOR
[33] CLK_PCIE_WLAN# GPP_CLK2N B25 LPCCLK0 R215 1 2 33_0402_5%
1 2 33_0402_5% CLK_PCIE_LAN_R E33 LPCCLK0 CLK_PCI_EC [16,31]
R80
[35] CLK_PCIE_LAN 1 2 33_0402_5% CLK_PCIE_LAN#_R E31 GPP_CLK3P D25
R82
LAN [35] CLK_PCIE_LAN# GPP_CLK3N LPCCLK1 D27 LPC_CLK1 [16]
3 M23 LAD0 C28 LPC_AD0 [31,33,35] 3
M24 GPP_CLK4P LAD1 A26 LPC_AD1 [31,33,35]
GPP_CLK4N LAD2 LPC_AD2 [31,33,35]
A29 LPC_AD3 [31,33,35]
M27 LAD3 A31

LPC
M26 GPP_CLK5P LFRAME# B27 LPC_FRAME# [31,33,35]
GPP_CLK5N LDRQ0# AE27
R83 1 2 33_0402_5% CLK_PCIE_CARD_R N25 LDRQ1#/CLK_REQ6#/GPIO49 AE19
[35] CLK_PCIE_CARD GPP_CLK6P SERIRQ/GPIO48 SERIRQ [31]
R84 1 2 33_0402_5% CLK_PCIE_CARD#_R N26
Card Reader[35] CLK_PCIE_CARD# GPP_CLK6N
R23
R24 GPP_CLK7P G25
GPP_CLK7N DMA_ACTIVE# E28 APU_PROCHOT#_R 1 2 0_0402_5% ALLOW_STOP [7]
R85 @
N27 PROCHOT# E26 APU_PROCHOT# [7]
R27 GPP_CLK8P APU_PG G26 APU_PWRGD [45,7]
GPP_CLK8N LDT_STP# F26
APU

APU_RST# APU_RST# [7]

R86 1 @ 2 22_0402_5% CLK_LAN_25M_R J26
[35] CLK_LAN_25M 14M_25M_48M_OSC H7
S5_CORE_EN F1 +RTCBATT
RTCCLK F3 RTC_CLK [16,31]
25M_X1 C31 INTRUDER_ALERT# E6 1 2
W=20mils
25M_X1 VDDBT_RTC_G R87 510_0402_5%

1U_0402_6.3V6K
G2 32K_X1
S5 PLUS

32K_X1 1

1
25M_X2 C33 C132 JCMOS1 @
25M_X2 SHORT PADS
For PCIE device reset on FS1

2
+3V_FCH G4 32K_X2 2
(GFX,GLAN,WLAN,LVDS Travis) C133 32K_X2
APU_PCIE_RST #: Reset PCIE device on APU 1 2

0.1U_0402_16V4Z 218-0844000 A0 BOLTON-M3

5

MC74VHC1G08DFT2G_SC70-5
4 2 4
R89 for Clear CMOS
P

APU_PCIE_RST#_C 1 2 B 4
1 Y APU_PCIE_RST# [17,33,35]
33_0402_5%
A
G
8.2K_0402_5%

U3
2
150P_0402_50V8J

R89/ C135 close to FCH 1

3

1
C135

R90

R91
@ 0_0402_5%
2
@
Security Classification Compal Secret Data Compal Electronics, Inc.
1

Issued Date 2012/11/22 Deciphered Date 2015/11/22 Title

2

@ R92
1
0_0402_5%
2 PLT_RST# [31,35]
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL FCH PCIE/CLK/PCI/LPC/RTCRev
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-8127P
Tuesday, March 12, 2013 Sheet 12 of 51
A B C D E
 A B C D E

4MB SPI ROM

& Non-share ROM. SPI_CLK_FCH

1
R93
33_0402_5%
@
+3VALW

2
U2B
R95 1 2 SPI_HOLD# +3VALW C138
1 HUDSON-2 10K_0402_5% 1
22P_0402_50V8J
C139 1 2 0.01U_0402_16V7K SATA_FTX_C_DRX_P0 AK19 AL14 C141 @
[30] SATA_FTX_DRX_P0 SATA_TX0P SD_CLK/SCLK_2/GPIO73
C140 1 2 0.01U_0402_16V7K SATA_FTX_C_DRX_N0AM19 AN14 1 2
[30] SATA_FTX_DRX_N0 SATA_TX0N SD_CMD/SLOAD_2/GPIO74 AJ12 +3VALW R101
HDD AL20 SD_CD/GPIO75 AH12 10K_0402_5% U4 0.1U_0402_16V4Z
[30] SATA_FRX_C_DTX_N0 AN20 SATA_RX0N SD_WP/GPIO76 AK13 1 2 SPI_SB_CS0# 1 8
[30] SATA_FRX_C_DTX_P0 SATA_RX0P SD_DATA0/SDATI_2/GPIO77 CS# VCC

SD CARD
AM13 SPI_SO 2 7 SPI_HOLD#
C143 1 2 0.01U_0402_16V7K SATA_FTX_C_DRX_P1AN22 SD_DATA1/SDATO_2/GPIO78 AH15 1 2 SPI_WP# 3 DO HOLD# 6 SPI_CLK_FCH 1 @ 2 SPI_CLK_FCH_R
[30] SATA_FTX_DRX_P1 SATA_TX1P SD_DATA2/GPIO79 WP# CLK
C142 1 2 0.01U_0402_16V7K SATA_FTX_C_DRX_N1 AL22 AJ14 R94 10K_0402_5% 4 5 SPI_SI R99
[30] SATA_FTX_DRX_N1 SATA_TX1N SD_DATA3/GPIO80 GND DI 0_0402_5%
ODD AH20 AC4 W25Q32BVSSIG_SO8
[30] SATA_FRX_C_DTX_N1 AJ20 SATA_RX1N GBE_COL AD3
[30] SATA_FRX_C_DTX_P1 SATA_RX1P GBE_CRS AD9
AJ22 GBE_MDCK W10
AH22 SATA_TX2P GBE_MDIO AB8 FCH SCLv1.20 19:
SATA_TX2N GBE_RXCLK AH7 GBE_COL/GBE_CRS/GBE_RXERR NC +3V_FCH
AM23 GBE_RXD3 AF7
AK23 SATA_RX2N GBE_RXD2 AE7 GBE_PHY_INTR R100 1 2 10K_0402_5%
SATA_RX2P GBE_RXD1 AD7
AH24 GBE_RXD0 AG8
AJ24 SATA_TX3P GBE_RXCTL/RXDV AD1
SATA_TX3N GBE_RXERR AB7
AN24 GBE_TXCLK AF9

GBE LAN
AL24 SATA_RX3N GBE_TXD3 AG6
SATA_RX3P GBE_TXD2 AE8
AL26 GBE_TXD1 AD8
AN26 SATA_TX4P GBE_TXD0 AB9
SATA_TX4N GBE_TXCTL/TXEN AC2

SERIAL ATA
AJ26 GBE_PHY_PD AA7
AH26 SATA_RX4N GBE_PHY_RST# W9 GBE_PHY_INTR
SATA_RX4P GBE_PHY_INTR
AN29
2 AL28 SATA_TX5P V6 SPI_SO 2
SATA_TX5N SPI_DI/GPIO164 V5 SPI_SI
AK27 SPI_DO/GPIO163 V3 SPI_CLK_FCH_R
SATA_RX5N SPI_CLK/GPIO162

SPI ROM
AM27 T6 SPI_SB_CS0#
SATA_RX5P SPI_CS1#/GPIO165 V1 SPI_WP#
AL29 ROM_RST#/SPI_WP#/GPIO161
AN31 NC6
NC7 L30
AL31 VGA_RED DAC_RED [28]
R104 1 2 150_0402_1%
AL33 NC8
NC9 L32
AH33 VGA_GREEN DAC_GRN [28]
R105 1 2 150_0402_1%
AH31 NC10
NC11 M29
AJ33 VGA_BLUE DAC_BLU [28]
R106 1 2 150_0402_1%
AJ31 NC12

VGA DAC
NC13 M28
VGA_HSYNC/GPO68 N30 CRT_HSYNC [28]
VGA_VSYNC/GPO69 CRT_VSYNC [28]
M33
VGA_DDC_SDA/GPO70 CRT_DDC_DATA [28]
1K_0402_1% 2 1 R107 SATA_CALRP AF28 N32
SATA_CALRP VGA_DDC_SCL/GPO71 CRT_DDC_CLK [28]

+AVDD_SATA 931_0402_1%2 1 R108 SATA_CALRN AF27

SATA_CALRN K31 R109 1 2 715_0402_1%
VGA_DAC_RSET

+3VS 10K_0402_5%2 1 R214 AD22

SATA_ACT#/GPIO67 V28
AUX_VGA_CH_P V29 ML_VGA_AUXP_C [7]
AF21 AUX_VGA_CH_N ML_VGA_AUXN_C [7]
VGA MAINLINK
SATA_X1 U28 AUXCAL R111 1 2 100_0402_1%
AUXCAL +VDDAN_11_ML
T31
3 ML_VGA_L0P T33 ML_VGA_TXP0 [7] 3
AG21 ML_VGA_L0N T29 ML_VGA_TXN0 [7]
SATA_X2 ML_VGA_L1P T28 ML_VGA_TXP1 [7]
ML_VGA_L1N R32 ML_VGA_TXN1 [7]
ML_VGA_L2P R30 ML_VGA_TXP2 [7]
ML_VGA_L2N P29 ML_VGA_TXN2 [7]
ML_VGA_L3P P28 ML_VGA_TXP3 [7] +FCH_VDDAN_33_DAC
ML_VGA_L3N ML_VGA_TXN3 [7] 2 1
10K_0402_5% R112
C29
ML_VGA_HPD/GPIO229 ML_VGA_HPD [7]

AH16 N2 1 2
AM15 FANOUT0/GPIO52 VIN0/GPIO175 R113 10K_0402_5%
BT_ON# AJ16 FANOUT1/GPIO53 HW MONITOR M3 1 2
[32] BT_ON# FANOUT2/GPIO54 VIN1/GPIO176 R114 10K_0402_5%
WLBT_OFF# AK15 L2 1 2
[33] WLBT_OFF# WL_OFF# AN16 FANIN0/GPIO56 VIN2/SDATI_1/GPIO177 R115 10K_0402_5%
[33] WL_OFF# AL16 FANIN1/GPIO57 N4 1 2
FANIN2/GPIO58 VIN3/SDATO_1/GPIO178 R116 10K_0402_5%
P1 1 2
ODD_EN K6 VIN4/SLOAD_1/GPIO179 R117 10K_0402_5%
[30] ODD_EN TEMPIN0/GPIO171 P3 1 2
VIN5/SCLK_1/GPIO180 R118 10K_0402_5%
1 2 K5 M1 1 2 Used as GPIO181 or configure as one of the following:
R119 10K_0402_5% TEMPIN1/GPIO172 VIN6/GBE_STAT3/GPIO181 R120 10K_0402_5% -> 10-KΩ 5% pull-down resistor.
M5 1 2 -> 10-KΩ 5% pull-up resistor to +3.3V_S5.
1 2 K3 VIN7/GBE_LED3/GPIO182 R121 10K_0402_5%
R122 10K_0402_5% TEMPIN2/GPIO173 -> Enabled integrated pull-down/up and left unconnected.
AG16
1 2 M6 NC1 AH10
R123 10K_0402_5% TEMPIN3/TALERT#/GPIO174 NC2 A28
4 NC3 G27 4
NC4
Follow Comal ORB Rework Memo
L4
NC5

[7] APU_ALERT#_FCH 218-0844000 A0 BOLTON-M3

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/22 Deciphered Date 2015/11/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL FCH SATA/SPI/VGA/HWM/SD Rev
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-8127P
Tuesday, March 12, 2013 Sheet 13 of 51
A B C D E
 A B C D E

R124 2 @ 1 0_0402_5% PCIE_RST2 : Reset PCIE device on Hudson2/3 U2D

R125 2 1 0_0402_5% HUDSON-2

T13 AB6 G8

USB MISC
R2 PCIE_RST2#/PCI_PME#/GEVENT4# USBCLK/14M_25M_48M_OSC
+3VS @ [31] EC_LID_OUT# W7 RI#/GEVENT22# B9 USB_RCOMP R127 1 2 11.8K_0402_1%
C144 .1U_0402_16V7K T3 SPI_CS3#/GBE_STAT1/GEVENT21# USB_RCOMP
1 2 [31] PM_SLP_S3# W2 SLP_S3# H1
[31] PM_SLP_S5# J4 SLP_S5# USB_FSD1P/GPIO186 H3
[31] PBTN_OUT# PWR_BTN# USB_FSD1N

5
FCH_PWRGD N7
2 PWR_GOOD H6

P
FCH_POK [31]

USB 1.1
4 B TEST0 T9 USB_FSD0P/GPIO185 H5

ACPI / WAKE UP EVENTS

[45] FCH_PWRGD Y 1 T10 TEST0 USB_FSD0N
TEST1
A VGATE [31,45] TEST1/TMS

G
1 TEST2 V9 H10 1
2 TEST2 USB_HSD13P
@ MC74VHC1G08DFT2G_SC70-5 G10

3
C145 AE22 USB_HSD13N
U5 @ [31] GATEA20 GA20IN/GEVENT0#
.1U_0402_16V7K K10
1
[31] KB_RST#
AG19
KBRST#/GEVENT1#
USB_HSD12P
USB_HSD12N
J12 USB30_P12 [34]
USB30_N12 [34]
LP3
R9
[31] EC_SCI# C26 LPC_PME#/GEVENT3# G12
[31] EC_SMI# T5 LPC_SMI#/GEVENT23#
LPC_PD#/GEVENT5#
USB_HSD11P
USB_HSD11N
F12 USB30_P11 [34]
USB30_N11 [34]
LP2
+3V_FCH R126 1 @ 2 10K_0402_5% SYS_RESET# U4
K1 SYS_RESET#/GEVENT19# K12
For ODD Power Leakage issue
+3VS +3VS
[35] FCH_PCIE_WAKE# V7 WAKE#/GEVENT8#
IR_RX1/GEVENT20#
USB_HSD10P
USB_HSD10N
K13 USB30_P10 [34]
USB30_N10 [34]
LP1
R10
[7] H_THERMTRIP# WD_PWRGD AF19 THRMTRIP#/SMBALERT#/GEVENT2# B11
WD_PWRGD USB_HSD9P D11
U2 USB_HSD9N
[31] EC_RSMRST# RSMRST#
2

E10
R213 AG24
CLK_REQ4#/SATA_IS0#/GPIO64
USB_HSD8P
USB_HSD8N
F10 BT
10K_0402_5% AE24
[35] LAN_CLKREQ# CLK_REQ3#/SATA_IS1#/GPIO63
2

AE26 C10
SMARTVOLT1/SATA_IS2#/GPIO50 USB_HSD7P USB20_P7 [35] FP
G

AF22 A10
[35] CARD_CLKREQ# USB20_N7 [35]
1

AH17 CLK_REQ0#/SATA_IS3#/GPIO60 USB_HSD7N

USB 2.0
3 1 ODD_DA#_FCH_R AG18 SATA_IS4#/FANOUT3/GPIO55 H9
[30] ODD_DA#_FCH AF24 SATA_IS5#/FANIN3/GPIO59 USB_HSD6P G9 USB20_P6 [26] CMOS
S

[29] FCH_SPKR FCH_SCLK0 AD26 SPKR/GPIO66 USB_HSD6N USB20_N6 [26]

GPIO
[10,11,31,33] FCH_SCLK0 FCH_SDATA0 AD25 SCL0/GPIO43 A8
Q43
2N7002K_SOT23-3
[10,11,31,33]
[33]
FCH_SDATA0
FCH_SCLK1
FCH_SCLK1 T7 SDA0/GPIO47
SCL1/GPIO227
USB_HSD5P
USB_HSD5N
C8 USB20_P5 [33]
USB20_N5 [33]
WLAN
FCH_SDATA1 R7
[33] FCH_SDATA1 AG25 SDA1/GPIO228 F8
AG22 CLK_REQ2#/FANIN4/GPIO62 USB_HSD4P E8
[33] WLAN_CLKREQ#
Near Device
J2 CLK_REQ1#/FANOUT4/GPIO61 USB_HSD4N
AG26 IR_LED#/LLB#/GPIO184 C6 USB30_N12 R230 1 @ 2 300_0402_5% C222 1 @ 2 10P_0402_50V8J
[44] VGA_PWRGD V8 SMARTVOLT2/SHUTDOWN#/GPIO51 USB_HSD3P A6 USB30_N11 1 2 1 2
R231 @ 300_0402_5% C223 @ 10P_0402_50V8J
2 W8 DDR3_RST#/GEVENT7#/VGA_PD USB_HSD3N USB30_N10 R232 1 @ 2 300_0402_5% C224 1 @ 2 10P_0402_50V8J 2
+3V_FCH Y6 GBE_LED0/GPIO183 C5 USB20_N6 R233 1 @ 2 300_0402_5% C225 1 @ 2 10P_0402_50V8J
For FCH internal debug use SPI_HOLD#/GBE_LED1/GEVENT9# USB_HSD2P
V10 A5 USB20_N0 R234 1 @ 2 300_0402_5% C226 1 @ 2 10P_0402_50V8J
R128 1 @ 2 2.2K_0402_5% TEST0 AA8 GBE_LED2/GEVENT10# USB_HSD2N
R131 2 @ 1 0_0402_5% PEG_CLKREQ#_R AF25 GBE_STAT0/GEVENT11# C1
[18] PEG_CLKREQ# CLK_REQG#/GPIO65/OSCIN/IDLEEXIT# USB_HSD1P
R129 1 @ 2 2.2K_0402_5% TEST1 C3
USB_HSD1N
R130 1 @ 2 2.2K_0402_5% TEST2 M7 E1
ODD_DA#_FCH_R R8 BLINK/USB_OC7#/GEVENT18#
USB_OC6#/IR_TX1/GEVENT6#
USB_HSD0P
USB_HSD0N
E3 USB20_P0 [35]
USB20_N0 [35]
RP1
THERMTRIP T1

USB OC
ODD_DETECT# P6 USB_OC5#/IR_TX0/GEVENT17# C16 USBSS_CALRP R132 1 2 1K_0402_1%
8/16 AMD confirmed: The FCH already have internal PU resistor
[30] ODD_DETECT# F5 USB_OC4#/IR_RX0/GEVENT16# USBSS_CALRP A16
and don't need external PU resistor. USB_OC3# USBSS_CALRN R133 1 2 1K_0402_1%
+FCH_VDD_11_SSUSB_S
+3V_FCH [35] USB_OC3# P5 USB_OC3#/AC_PRES/TDO/GEVENT15# USBSS_CALRN
Note: need BIOS check: Ensure FCH internal pull-up resistor to T19
USB_OC1# J7 USB_OC2#/TCK/GEVENT14# A14
+3.3V S5 is disabled to prevent leakage when APU is powered down. [34] USB_OC1# USB_OC1#/TDI/GEVENT13# USB_SS_TX3P
USB_OC0# T8 C14
1 2 10K_0402_5% USB_OC3# [34] USB_OC0# USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12# USB_SS_TX3N
R154
C12
USB_SS_RX3P A12
USB_SS_RX3N
R134 1 2 33_0402_5% HDA_BITCLK AB3 D15 USB30_FTX_DRX_P2_C C212 1 2 .1U_0402_16V7K
[29] HDA_BITCLK_AUDIO AZ_BITCLK USB_SS_TX2P USB30_FTX_DRX_P2 [34]
R135 1 2 33_0402_5% HDA_SDOUT AB1 B15 USB30_FTX_DRX_N2_C C213 1 2 .1U_0402_16V7K
1 2 10K_0402_5% [29] HDA_SDOUT_AUDIO AA2 AZ_SDOUT USB_SS_TX2N USB30_FTX_DRX_N2 [34]
R137 USB_OC1# HDA_SDIN0
LP3

HD AUDIO
[29] HDA_SDIN0 Y5 AZ_SDIN0/GPIO167 E14 USB30_FRX_DTX_P2
1 2 10K_0402_5% Y3 AZ_SDIN1/GPIO168 USB_SS_RX2P F14 USB30_FRX_DTX_P2 [34]
USB_OC0# USB30_FRX_DTX_N2

USB 3.0
R139
Y1 AZ_SDIN2/GPIO169 USB_SS_RX2N USB30_FRX_DTX_N2 [34]
R205 1 @ 2 10K_0402_5% ODD_DETECT# R138 1 2 33_0402_5% HDA_SYNC AD6 AZ_SDIN3/GPIO170 F15 USB30_FTX_DRX_P1_C C218 1 2 .1U_0402_16V7K
[29] HDA_SYNC_AUDIO AZ_SYNC USB_SS_TX1P USB30_FTX_DRX_P1 [34]
R140 1 2 33_0402_5% HDA_RST# AE4 G15 USB30_FTX_DRX_N1_C C219 1 2 .1U_0402_16V7K
1 2 10K_0402_5% [29] HDA_RST_AUDIO# AZ_RST# USB_SS_TX1N USB30_FTX_DRX_N1 [34]
R143 @ H_THERMTRIP#
USB_SS_RX1P
H13 USB30_FRX_DTX_P1
USB30_FRX_DTX_P1 [34]
LP2
R145 1 @ 2 100K_0402_5% EC_LID_OUT# G13 USB30_FRX_DTX_N1
USB_SS_RX1N USB30_FRX_DTX_N1 [34]
R149 1 2 10K_0402_5% FCH_PCIE_WAKE# K19 J16 USB30_FTX_DRX_P0_C C220 1 2 .1U_0402_16V7K
3 PS2_DAT/SDA4/GPIO187 USB_SS_TX0P USB30_FTX_DRX_P0 [34] 3
0_0402_5% 2 @ 1 R146 GPIO188 J19 H16 USB30_FTX_DRX_N0_C C221 1 2 .1U_0402_16V7K
1 2 10K_0402_5% [12,17] PXS_RST# PS2_CLK/CEC/SCL4/GPIO188 USB_SS_TX0N USB30_FTX_DRX_N0 [34]
R155 @ ODD_DA#_FCH_R 0_0402_5% 2 @ 1 R148 J21
[12,19,43,44] PXS_PWREN SPI_CS2#/GBE_STAT2/GPIO166
USB_SS_RX0P
J15 USB30_FRX_DTX_P0
USB30_FRX_DTX_P0 [34]
LP1
DIS@ K15 USB30_FRX_DTX_N0
USB_SS_RX0N USB30_FRX_DTX_N0 [34]
Q44A
DMN66D0LDW-7_SOT363-6 GPIO189 D21
1 6 GPIO190 C20 PS2KB_DAT/GPIO189 H19 R144 1 2 10K_0402_5%
+3VS DIS@ D23 PS2KB_CLK/GPIO190 SCL2/GPIO193 G19 R147 1 2 10K_0402_5%
+3V_FCH Q44B C22 PS2M_DAT/GPIO191 EMBEDDED CTRL SDA2/GPIO194 G22 FCH_SIC
PS2M_CLK/GPIO192 SCL3_LV/GPIO195 G21 FCH_SIC [7]
DMN66D0LDW-7_SOT363-6 FCH_SID
FCH_SID [7]
2

R174 1 2 10K_0402_5% WLAN_CLKREQ# R211 1 DIS@ 2 10K_0402_5% 3 4 SDA3_LV/GPIO196 E22

EC_PWM0/EC_TIMER0/GPIO197 H22
R156 1 2 10K_0402_5% CARD_CLKREQ# T34 F21 EC_PWM1/EC_TIMER1/GPIO198 J22 EC_PWM2
EC_PXCONTROL T35 E20 KSO_0/GPIO209 EC_PWM2/EC_TIMER2/WOL_EN/GPIO199 H21 EC_PWM2 [16] strap pin
[31] EC_PXCONTROL
5

R151 1 2 2.2K_0402_5% FCH_SCLK0 T36 F20 KSO_1/GPIO210 EC_PWM3/EC_TIMER3/GPIO200

T37 A22 KSO_2/GPIO211 K21
R152 1 2 2.2K_0402_5% FCH_SDATA0 T38 E18 KSO_3/GPIO212 KSI_0/GPIO201 K22
T39 A20 KSO_4/GPIO213 KSI_1/GPIO202 F22
R153 1 2 10K_0402_5% WD_PWRGD SCL1/SDA1: ASF-Capable LAN Devices Not Implemented: Used as T43 J18 KSO_5/GPIO214 KSI_2/GPIO203 F24
GPIO227 or configured for one of the following options: 10-KΩ 5% pull-up T44 H18 KSO_6/GPIO215 KSI_3/GPIO204 E24
R159 1 2 8.2K_0402_5% LAN_CLKREQ# resistor to +3.3V_S5; 10-KΩ 5% pull-down resistor. T45 G18 KSO_7/GPIO216 KSI_4/GPIO205 B23
T40 B21 KSO_8/GPIO217 KSI_5/GPIO206 C24
T41 K18 KSO_9/GPIO218 KSI_6/GPIO207 F18
+3V_FCH 8/26 T42 D19 KSO_10/GPIO219 KSI_7/GPIO208
T49 A18 KSO_11/GPIO220
T50 C18 KSO_12/GPIO221
T51 B19 KSO_13/GPIO222
KSO_14/GPIO223
2 UMA@ 1

2 UMA@ 1

@ 1
10K_0402_5%

10K_0402_5%

10K_0402_5%

R160 1 @ 2 10K_0402_5% FCH_SCLK1 T46 B17

T47 A24 KSO_15/GPIO224
KSO_16/GPIO225
R157

R158

R206

R161 1 @ 2 10K_0402_5% FCH_SDATA1 T48 D17

KSO_17/GPIO226
R162 1 2 10K_0402_5% EC_RSMRST#
2

4 4
218-0844000 A0 BOLTON-M3
R163 1 @ 2 10K_0402_5% HDA_BITCLK GPIO188
GPIO189
R166 1 @ 2 10K_0402_5% HDA_SDIN0 GPIO190

R167 1 @ 2 10K_0402_5%PEG_CLKREQ#_R GPIO188 GPIO189 GPIO190 Function

DIS@ 1

2 DIS@ 1

1
10K_0402_5%

10K_0402_5%

10K_0402_5%

CLKREQG Not Implemented: 0 0 0 PX

Used as GPIO65, IDLEEXIT#, or left unconnected. Security Classification Compal Secret Data Compal Electronics, Inc.
R164

R165

R210

0 0 1 Reserved Issued Date 2012/11/22 Deciphered Date 2015/11/22 Title

0 1 0 DISCRET FCH SATA/SPI/VGA/HWM/SD Rev

2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0 1 1 UMA Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-8127P
Tuesday, March 12, 2013 Sheet 14 of 51
A B C D E
 A B C D E

+3VS +1.1VS
L2 U2C 1007mA
1 2 +VDDPL_33_SYS +VCC_VDDCR_11 0_0805_5% 1 @ 2 R170
MBK1608221YZF_2P 102mA HUDSON-2

C154

2.2U_0402_6.3V6M

C147

.1U_0402_16V7K

C155

.1U_0402_16V7K

C148

.1U_0402_16V7K

C149

1U_0402_6.3V6K

C150

1U_0402_6.3V6K

C156

10U_0603_6.3V6M
220 ohm +3VS R171 1 @ 2 0_0603_5% +VDDIO_33_PCIGP AB17 T14
VDDIO_33_PCIGP_1 VDDCR_11_1

22U_0603_6.3V6M

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K
1 1 AB18 T17 1 1 1 1 1
VDDIO_33_PCIGP_2 VDDCR_11_2

C146

C151

C152

C157
AE9 T20

PCI/GPIO I/O
AD10 VDDIO_33_PCIGP_3 VDDCR_11_3 U16
1 1 1 1 VDDIO_33_PCIGP_4 VDDCR_11_4
AG7 U18
2 2 AC13 VDDIO_33_PCIGP_5 VDDCR_11_5 V14 2 2 2 2 2
VDDIO_33_PCIGP_6 VDDCR_11_6

CORE S0
AB12 V17
2 2 2 2 AB13 VDDIO_33_PCIGP_7 VDDCR_11_7 V20
+FCH_VDDAN_33_DAC AB14 VDDIO_33_PCIGP_8 VDDCR_11_8 Y17
1 AB16 VDDIO_33_PCIGP_9 VDDCR_11_9 +1.1VS_CKVDD +1.1VS 1
VDDIO_33_PCIGP_10
47mA 340mA
R168 1 @ 2 0_0402_5% +VDDPL_33_MLDAC
+VDDPL_33_SYS
H24 H26 +1.1VS_CKVDD R172 1 @ 2 0_0603_5%
VDDPL_33_SYS VDDAN_11_CLK_1 J25
20mA VDDAN_11_CLK_2
+3VS

C159

.1U_0402_16V7K

C160

.1U_0402_16V7K

C161

1U_0402_6.3V6K

C162

1U_0402_6.3V6K

C163

22U_0603_6.3V6M
R173 1 @ 2 0_0402_5% +VDDPL_33_DAC V22 K24

.1U_0402_16V7K

.1U_0402_16V7K

CLKGEN I/O
+VDDPL_33_MLDAC VDDPL_33_DAC VDDAN_11_CLK_3
C153

C158
L3 12mA L22 1 1 1 1 1
1 2 R169 1 @ 2 0_0402_5% +VDDPL_33_ML U22 VDDAN_11_CLK_4 M22
1 1 VDDPL_33_ML VDDAN_11_CLK_5
MBK1608221YZF_2P 30mA N21
@ +FCH_VDDAN_33_DAC T22 VDDAN_11_CLK_6 N22
VDDAN_33_DAC VDDAN_11_CLK_7 P22 2 2 2 2 2
2 2
11mA VDDAN_11_CLK_8
+VDDPL_33_SSUSB_S L18
VDDPL_33_SSUSB_S
14mA
+VDDPL_33_USB_S D7 1088mA +1.1VS
VDDPL_33_USB_S AB24 +VDDAN_11_PCIE
11mA VDDAN_11_PCIE_1
+VDDPL_33_PCIE AH29 Y21 +VDDAN_11_PCIE 0_0805_5% 1 @ 2 R175
VDDPL_33_PCIE VDDAN_11_PCIE_2 AE25
12mA VDDAN_11_PCIE_3

PCI EXPRESS

C165

.1U_0402_16V7K

C166

1U_0402_6.3V6K

C167

22U_0603_6.3V6M
+VDDPL_33_SATA AG28 AD24
VDDPL_33_SATA VDDAN_11_PCIE_4 AB23
VDDAN_11_PCIE_5 1 1 1
LDO_CAP: Internally generated 1.8V @ AA22
1 2 M31 VDDAN_11_PCIE_6 AF26
supply for the RGB outputs C164 2.2U_0603_6.3V6K LDO_CAP VDDAN_11_PCIE_7 AG27
+1.1VS L4 VDDAN_11_PCIE_8 2 2 2
7mA
1 2 R176 1 @ 2 0_0402_5% +VDDPL_11_DAC V21
MBK1608221YZF_2P VDDPL_11_DAC +1.1VS
1337mA
220 ohm/2A +VDDAN_11_ML AA21 +AVDD_SATA
R177 1 @ 2 0_0603_5% VDDAN_11_SATA_1 Y20 0_0805_5% 1 @ 2 R178
226mA VDDAN_11_SATA_4
+3VS +FCH_VDDAN_33_DAC Y22 AB21
VDDAN_11_ML_1 VDDAN_11_SATA_2

C168

4.7U_0402_6.3V6M
C169

.1U_0402_16V7K
C170

.1U_0402_16V7K

C171

.1U_0402_16V7K

C172

1U_0402_6.3V6K

C173

1U_0402_6.3V6K

C174

22U_0603_6.3V6M
L5 30mil V23 AB22

SERIAL ATA
MAIN LINK
1 2 V24 VDDAN_11_ML_2 VDDAN_11_SATA_3 AC22
1 1 1 VDDAN_11_ML_3 VDDAN_11_SATA_5 1 1 1 1
FBMA-L11-201209-221LMA30T_0805 V25 AC21
VDDAN_11_ML_4 VDDAN_11_SATA_6
C175

2.2U_0603_6.3V6K

C176

0.1U_0402_16V4Z

220 ohm AA20

VDDAN_11_SATA_7 AA18
1 1 2 2 2 VDDAN_11_SATA_8 2 2 2 2
2 AB20 2
VDDAN_11_SATA_9 AC19
AB10 VDDAN_11_SATA_10 +3V_FCH
2 2 VDDIO_33_GBE_S
59mA
AB11 N18 +VDDIO_33_S R179 1 @ 2 0_0402_5%
AA11 VDDCR_11_GBE_S_1 VDDIO_33_S_1 L19

GBE LAN
VDDCR_11_GBE_S_2 VDDIO_33_S_2

C177

1U_0402_6.3V6K

C178

1U_0402_6.3V6K

C179

2.2U_0402_6.3V6M
M18
R180 1 @ 2 0_0402_5% AA9 VDDIO_33_S_3 V12
VDDIO_GBE_S_1 VDDIO_33_S_4 1 1 1

3.3V_S5 I/O
AA10 V13
+3V VDDIO_GBE_S_2 VDDIO_33_S_5 Y12
L6 VDDIO_33_S_6 Y13
470mA VDDIO_33_S_7 2 2 2
1 2 +VDDAN_33_USB G7 W11
VDDAN_33_USB_S_1 VDDIO_33_S_8
10U_0603_6.3V6M

10U_0603_6.3V6M
FBMA-L11-201209-221LMA30T_0805 H8
+3V VDDAN_33_USB_S_2 +3V
C180

C181

C182

1U_0402_6.3V6K

C183

1U_0402_6.3V6K

C184

.1U_0402_16V7K
220 ohm/2A J8 +VDDXL_3.3V
L7 K8 VDDAN_33_USB_S_3 L8
1 1 1 1 1 VDDAN_33_USB_S_4 5mA Tie to +3.3V_S5 rail if USB3 Wake
1 2 +VDDPL_33_SSUSB_S K9 G24 +VDDXL_3.3V 1 2
MBK1608221YZF_2P M9 VDDAN_33_USB_S_5 VDDXL_33_S MBK1608221YZF_2P is supported; otherwise, tie to
VDDAN_33_USB_S_6
C185

2.2U_0402_6.3V6M

C186

.1U_0402_16V7K

C187

2.2U_0402_6.3V6M
M10 220 ohm +3.3V_S0 rail.
2 2 2 2 2 N9 VDDAN_33_USB_S_7
220 ohm 1 1 VDDAN_33_USB_S_8 1 Hudson-2 designs: Tie to +3.3V_S0
N10
M12 VDDAN_33_USB_S_9 rail.
N12 VDDAN_33_USB_S_10
2 2 M11 VDDAN_33_USB_S_11 2
+1.1V VDDAN_33_USB_S_12
L10 140mA +1.1VALW
1 2 +VDDAN_11_USB_S U12 187mA

USB
MBK1608221YZF_2P U13 VDDAN_11_USB_S_1 N20 +VDDCR_1.1V R181 1 @ 2 0_0603_5%
VDDAN_11_USB_S_2 VDDCR_11_S_1
C188

2.2U_0402_6.3V6M

C189

.1U_0402_16V7K

C190

.1U_0402_16V7K

220 ohm M20

+3V VDDCR_11_S_2

C191

1U_0402_6.3V6K

C192

1U_0402_6.3V6K
1 1 1
L11 1 1
1 2 +VDDPL_33_USB_S
MBK1608221YZF_2P @
2 2 2
C193

2.2U_0402_6.3V6M

C194

.1U_0402_16V7K

3 3
220 ohm 2 2
1 1
+1.1V VDDPL_11_SYS_S should be
L12 42mA +1.1V
2 2 1 2 +VDDCR_11V_USB T12
tied to +1.1V_S5 rail if USB 3.0 Wake is
70mA L13
MBK1608221YZF_2P T13 VDDCR_11_USB_S_1 J24 +VDDPL_11_SYS_S 1 2 supported; otherwise, it can be tied to
VDDCR_11_USB_S_2 VDDPL_11_SYS_S
C195

10U_0603_6.3V6M

C196

.1U_0402_16V7K

C197

.1U_0402_16V7K

220 ohm MBK1608221YZF_2P +1.1V_S0 rail.

.1U_0402_16V7K
C198

2.2U_0402_6.3V6M

C199
1 1 1 220 ohm
1 1
+3VS
L14 2 2 2
1 2 +VDDPL_33_PCIE 2 2
MBK1608221YZF_2P
220 ohm +3V_FCH
+FCH_VDD_11_SSUSB_S
C200

2.2U_0402_6.3V6M

282mA 12mA
1 P16 M8 +VDDAN_33_HWM R182 1 @ 2 0_0402_5%
R183 1 @ 2 0_0603_5% +VDDAN_11_SSUSB M14 VDDAN_11_SSUSB_S_1 VDDAN_33_HWM_S
40mils VDDAN_11_SSUSB_S_2 AMD reply:

C204

2.2U_0402_6.3V6M

C205

.1U_0402_16V7K
N14
VDDAN_11_SSUSB_S_3 VDDAN_33_HWM_S: Please connect
C201

1U_0402_6.3V6K

C202

.1U_0402_16V7K

C203

.1U_0402_16V7K

P13 1 1
2 P14 VDDAN_11_SSUSB_S_4 it to +3.3V_S5 directly if HWM is not used.
1 1 1 VDDAN_11_SSUSB_S_5
USB SS

2 2
2 2 2
424mA
N16 VDDIO_AZ_S
+3VS N17 VDDCR_11_SSUSB_S_1 +3VS
P17 VDDCR_11_SSUSB_S_2 Wake on Ring supported: Tie to +3.3/
L15 26mA
1 2 +VDDPL_33_SATA M17 VDDCR_11_SSUSB_S_3 AA4 +VDDIO_AZ R184 1 @ 2 0_0402_5% 1.5V_S5 rail, and treat like a 3.3/1.1V_S5 rail.
MBK1608221YZF_2P VDDCR_11_SSUSB_S_4 VDDIO_AZ_S Wake on Ring not supported: Tie to +3.3/
C207

2.2U_0402_6.3V6M

220 ohm POWER C206 1 2 2.2U_0402_6.3V6M 1.5V_S0 rail, and treat like a 3.3/1.1V S0 rail.
4
1 4
2 L16 1 R185 1 @ 2 0_0603_5% +VDDCR_11_SSUSB
+1.1V 218-0844000 A0 BOLTON-M3
C208

10U_0603_6.3V6M

C209

1U_0402_6.3V6K

C210

.1U_0402_16V7K

C211

.1U_0402_16V7K

FBMA-L11-201209-221LMA30T_0805
2
42 ohm/4A 1 1 1 1

2 2 2 2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/11/22 Deciphered Date 2015/11/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
FCH PWR Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-8127P
Tuesday, March 12, 2013 Sheet 15 of 51
A B C D E
 5 4 3 2 1

DEBUG STRAPS
U2E

HUDSON-2
STRAP PINS FCH HAS 15K INTERNAL PU FOR PCI_AD[27:23]
A3 T25
A33 VSS VSS T27
B7 VSS VSS U6
VSS VSS PCI_CLK1 PCI_CLK3 PCI_CLK4 CLK_PCI_EC LPC_CLK1 EC_PWM2 RTC_CLK PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23
B13 U14
D9 VSS VSS U17
D D13 VSS VSS U20 D
VSS VSS PULL ALLOW USE NON_FUSION EC CLKGEN LPC ROM S5 PLUS USE PCI DISABLE USE FC USE DEFAULT DISABLE PCI
E5 U21 PULL
E12 VSS VSS U30 HIGH PCIE GEN2 DEBUG CLOCK MODE ENABLED ENABLED MODE PLL ILA PLL PCIE STRAPS MEM BOOT
E16 VSS VSS U32 STRAPS DISABLED HIGH AUTORUN
E29 VSS VSS V11 DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT
F7 VSS VSS V16
F9 VSS VSS V18
F11 VSS VSS W4
VSS VSS PULL FORCE IGNORE FUSION EC CLKGEN SPI ROM S5 PLUS PULL BYPASS ENABLE BYPASS USE EEPROM ENABLE PCI
F13 W6
F16 VSS VSS W25 LOW PCIE GEN1 DEBUG CLOCK DISABLED DISABLE MODE LOW PCI PLL ILA FC PLL PCIE STRAPS MEM BOOT
F17 VSS VSS W28 STRAP MODE ENABLED AUTORUN
F19 VSS VSS Y14 DEFAULT DEFAULT DEFAULT DEFAULT
F23 VSS VSS Y16
F25 VSS VSS Y18
F29 VSS VSS AA6
G6 VSS VSS AA12
G16 VSS VSS AA13 +3VS +3VS +3VS +3V_FCH +3V_FCH +3V_FCH +3V_FCH
G32 VSS VSS AA14
VSS VSS

R186 10K_0402_5%

R187 10K_0402_5%

R188 10K_0402_5%

R189 10K_0402_5%

R190 10K_0402_5%

R191 10K_0402_5%

R192 10K_0402_5%
H12 AA16
H15 VSS VSS AA17
VSS VSS

1
H29 AA25
GROUND

J6 VSS VSS AA28

J9 VSS VSS AA30 @ @ @ @
VSS VSS [12] PCI_AD27
J10 AA32
C VSS VSS C
J13 AB25
[12] PCI_AD26

2
J28 VSS VSS AC6
J32 VSS VSS AC18
K7 VSS VSS AC28 [12] PCI_AD25
VSS VSS [12] PCI_CLK1
K16 AD27
K27 VSS VSS AE6 [12] PCI_AD24
VSS VSS [12] PCI_CLK3
K28 AE15
L6 VSS VSS AE21 [12] PCI_AD23
L12 VSS VSS AE28 [12] PCI_CLK4
L13 VSS VSS AF8
VSS VSS [12,31] CLK_PCI_EC

R193 2.2K_0402_5%

R194 2.2K_0402_5%

R195 2.2K_0402_5%

R196 2.2K_0402_5%

R197 2.2K_0402_5%
L15 AF12
VSS VSS

1
L16 AF16
L21 VSS VSS AF33 [12] LPC_CLK1
M13 VSS VSS AG30 @ @ @ @ @
VSS VSS [14] EC_PWM2
M16 AG32
M21 VSS VSS AH5
[12,31] RTC_CLK

2
M25 VSS VSS AH11
VSS VSS R198 10K_0402_5%

R199 10K_0402_5%

R200 10K_0402_5%

R201 10K_0402_5%

R202 10K_0402_5%

R203 2.2K_0402_5%

R204 2.2K_0402_5%
N6 AH18
N11 VSS VSS AH19
VSS VSS
1

1
N13 AH21
N23 VSS VSS AH23
N24 VSS VSS AH25 @ @ @
P12 VSS VSS AH27
P18 VSS VSS AJ18
B B
2

2
P20 VSS VSS AJ28
P21 VSS VSS AJ29
P31 VSS VSS AK21
P33 VSS VSS AK25
R4 VSS VSS AL18
R11 VSS VSS AM21
R25 VSS VSS AM25
R28 VSS VSS AN1
T11 VSS VSS AN18
T16 VSS VSS AN28
T18 VSS VSS AN33
VSS VSS
N8 T21
VSSAN_HWM VSSPL_DAC L28
K25 VSSAN_DAC K33
VSSXL VSSANQ_DAC N28
H25 VSSIO_DAC
VSSPL_SYS R6
EFUSE

218-0844000 A0 BOLTON-M3
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/22 Deciphered Date 2015/11/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
FCH-VSS/Strap Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-8127P
Tuesday, March 12, 2013 Sheet 16 of 51
5 4 3 2 1
 A B C D E

SDV/FVT, NO.3
PCIE_CTX_GRX_P[7..0] U1401A PCIE_CRX_GTX_P[7..0]
[5] PCIE_CTX_GRX_P[7..0] PCIE_CRX_GTX_P[7..0] [5]

[5] PCIE_CTX_GRX_N[7..0]
PCIE_CTX_GRX_N[7..0] PART 1 0F 9 PCIE_CRX_GTX_N[7..0]
PCIE_CRX_GTX_N[7..0] [5] LVDS Interface
U1401D
1 1
PCIE_CTX_GRX_P0 AA38 Y33 PCIE_CRX_C_GTX_P0 .1U_0402_16V7K 2 1 C1401 DIS@ PCIE_CRX_GTX_P0 PART 7 0F 9
PCIE_CTX_GRX_N0 Y37 PCIE_RX0P PCIE_TX0P Y32 PCIE_CRX_C_GTX_N0 2 1 C1402 DIS@ PCIE_CRX_GTX_N0
.1U_0402_16V7K
PCIE_RX0N PCIE_TX0N
AK27
RSVD/VARY_BL AJ27
PCIE_CTX_GRX_P1 Y35 W33 PCIE_CRX_C_GTX_P1 .1U_0402_16V7K 2 1 C1404 DIS@ PCIE_CRX_GTX_P1 RSVD/DIGON
PCIE_CTX_GRX_N1 W36 PCIE_RX1P PCIE_TX1P W32 PCIE_CRX_C_GTX_N1 2 1 C1405 DIS@ PCIE_CRX_GTX_N1 LVDS CONTROL
.1U_0402_16V7K
PCIE_RX1N PCIE_TX1N

PCIE_CTX_GRX_P2 W38 U33 PCIE_CRX_C_GTX_P2 .1U_0402_16V7K 2 1 C1406 DIS@ PCIE_CRX_GTX_P2 AK35

PCIE_CTX_GRX_N2 V37 PCIE_RX2P PCIE_TX2P U32 PCIE_CRX_C_GTX_N2 2 1 C1407 DIS@ PCIE_CRX_GTX_N2 TXCBP_DPB3P
.1U_0402_16V7K AL36
PCIE_RX2N PCIE_TX2N TXCBM_DPB3N
AJ38
PCIE_CTX_GRX_P3 V35 U30 PCIE_CRX_C_GTX_P3 .1U_0402_16V7K 2 1 C1408 DIS@ PCIE_CRX_GTX_P3 TX3P_DPB2P AK37
PCIE_CTX_GRX_N3 U36 PCIE_RX3P PCIE_TX3P U29 PCIE_CRX_C_GTX_N3 2 1 C1403 DIS@ PCIE_CRX_GTX_N3 TX3M_DPB2N
.1U_0402_16V7K
PCIE_RX3N PCIE_TX3N
AH35
TX4P_DPB1P AJ36
PCIE_CTX_GRX_P4 U38 T33 PCIE_CRX_C_GTX_P4 .1U_0402_16V7K 2 1 C1409 DIS@ PCIE_CRX_GTX_P4 TX4M_DPB1N
PCIE_RX4P PCIE_TX4P
PCIE_CTX_GRX_N4 T37 T32 PCIE_CRX_C_GTX_N4 .1U_0402_16V7K 2 1 C1410 DIS@ PCIE_CRX_GTX_N4 AG38
PCIE_RX4N PCIE_TX4N TX5P_DPB0P AH37
TX5M_DPB0N
PCIE_CTX_GRX_P5 T35 T30 PCIE_CRX_C_GTX_P5 .1U_0402_16V7K 2 1 C1411 DIS@ PCIE_CRX_GTX_P5 AF35
PCIE_CTX_GRX_N5 R36 PCIE_RX5P PCIE_TX5P T29 PCIE_CRX_C_GTX_N5 .1U_0402_16V7K 2 1 C1412 DIS@ PCIE_CRX_GTX_N5 NC#AF35 AG36
SUN NC
PCIE_RX5N PCIE_TX5N NC#AG36

LVTMDP
PCIE_CTX_GRX_P6 R38 P33 PCIE_CRX_C_GTX_P6 .1U_0402_16V7K 2 1 C1413 DIS@ PCIE_CRX_GTX_P6
PCIE_CTX_GRX_N6 P37 PCIE_RX6P PCIE_TX6P P32 PCIE_CRX_C_GTX_N6 2 1 C1414 DIS@ PCIE_CRX_GTX_N6
.1U_0402_16V7K
PCIE_RX6N PCIE_TX6N
AP34
TXCAP_DPA3P AR34
PCIE_CTX_GRX_P7 P35 P30 PCIE_CRX_C_GTX_P7 .1U_0402_16V7K 2 1 C1415 DIS@ PCIE_CRX_GTX_P7 TXCAM_DPA3N
PCIE_RX7P PCIE_TX7P
PCIE_CTX_GRX_N7 N36 P29 PCIE_CRX_C_GTX_N7 .1U_0402_16V7K 2 1 C1416 DIS@ PCIE_CRX_GTX_N7 AW37
PCIE_RX7N PCIE_TX7N TX0P_DPA2P AU35
2 SDV/FVT, NO.1 SDV/FVT, NO.2 TX0M_DPA2N 2
N38 N33 AR37
M37 NC NC N32 TX1P_DPA1P AU39
NC NC TX1M_DPA1N
PCI EXPRESS INTERFACE AP35
M35 N30 TX2P_DPA0P AR35
L36 NC NC N29 TX2M_DPA0N
NC NC
AN36
NC AP37
L38 L33 NC
K37 NC NC L32
NC NC

K35 L30 DIS@ S IC 216-0841000 A0 SUN PRO M2 FCBGA 962P A39

J36 NC NC L29
NC NC

J38 K33
H37 NC NC K32
NC NC

H35 J33
G36 NC NC J32
NC NC

G38 K30
F37 NC NC K29
NC NC

F35 H33
E37 NC NC H32
NC NC
3 3
CLOCK +3VGS

CLK_PCIE_VGA AB35
[12] CLK_PCIE_VGA AA36 PCIE_REFCLKP
CLK_PCIE_VGA#
[12] CLK_PCIE_VGA# PCIE_REFCLKN

5
U1400
2

P
CALIBRATION [12,14] PXS_RST# B 4 GPU_RST#
Y30 R1403 1 DIS@ 2 1.69K_0402_1% 1 Y
PCIE_CALR_TX +0.95VGS [12,33,35] APU_PCIE_RST# A

G
DIS@
2 DIS@ 1 AH16 Y29 R1405 1 DIS@ 2 1K_0402_1%
TEST_PG PCIE_CALR_RX +0.95VGS

3
R1404 1K_0402_5% MC74VHC1G08DFT2G SC70 5P

GPU_RST# AA30
PERSTB
1

DIS@ DIS@ S IC 216-0841000 A0 SUN PRO M2 FCBGA 962P A39

R2486
100K_0402_5%
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/22 Deciphered Date 2015/11/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ATI_Sun Pro_M2_PCIE/LVDS
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8127P
Date: Tuesday, March 12, 2013 Sheet 17 of 51
A B C D E
 A B C D E

U1401B CONFIGURATION STRAPS RECOMMENDED SETTINGS

PART 2 0F 9 ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE 0= DO NOT INSTALL RESISTOR
1 = INSTALL 10K RESISTOR
SDV/FVT, NO.11 MUTI GFX GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET X = DESIGN DEPENDANT
T1401
T1402
GENLK_CLK
GENLK_VSYNC
AD29
AC29
GENLK_CLK
GENLK_VSYNC
NC
AU24
AV23 STRAPS Resistor Divider Lookup Lable
NA = NOT APPLICABLE
NC
AT25 STRAPS MLPS DESCRIPTION OF DEFAULT SETTINGS Default Setting
AJ21 NC AR24
R_pu (ohm) R_pd (ohm)
AK21
SWAPLOCKA DPA NC
R1430 R1436 Bitd [3:1] Transmitter Power Savings Enable
SWAPLOCKB
AU26 +3VGS TX_PWRS_ENB PS_1[4] 0:50% Tx output swing X
NC
AV25 NC 4.75k 000 1:Full Tx output swing
NC
AR8 AT27 GPU_GPIO5 R1425 2 @ 1 100K_0402_5% PCIE Transmitter De-emphasis Enable
AU8
NC NC
AR26
8.45k 2k 001 TX_DEEMPH_EN PS_1[5] 0:Tx de-emphasis disabled X
NC NC
AP8 1:Tx de-emphasis enabled
AW8
DBG_CNTL0
AR30 THM_ALERT# R1426 2 @ 1 2.2K_0402_5%
4.53k 2k 010
1 NC NC 1
AR3 AT29 PCIE Gen3 Enable
AR1
NC NC 6.98k 4.99k 011 BIF_GEN3_EN_A PS_1[1] (NOTE:RESERVED for Thames/Seymour and should 1
NC
AU1 DBG_DATA0 AV31 4.53k 4.99k 100 be strapped to 0)
AU3 NC AU30
DBG_DATA1 DPB NC
AW3 DBG_DATA2 3.24k 5.62k 101 0:GEN3 not support at power-on
AP6 AR32 1:GEN3 supported at power-on
DBG_DATA3 NC
AW5 AT31
AU5
DBG_DATA4 NC 3.4k 10k 110 VGA control
DBG_DATA5 +3VGS
AR6 AT33 BIF_VGA DIS PS_2[4] 0:VGA controller capacity enabled 0
AW6
DBG_DATA6 NC
AU32
4.75k NC 111 1:VGA controller capacity disabled (for multi-GPU)
DBG_DATA7 NC
AU6 GPIO24_TRSTB R1418 1 @ 2 10K_0402_5%
AT7
DBG_DATA8
AU14 GPIO25_TDI R1419 1 @ 2 10K_0402_5%
0402 1% resistors are equired Serial ROM type or Memory Aperture Size Select
DBG_DATA9 NC
AV7 DBG_DATA10 AV13 GPIO27_TMS R1420 1 @ 2 10K_0402_5% ROMIDCFG[2:0] PS_0[3..1] If PS_2[3]=0, defines memory aperture size XXX
AN7 NC
DBG_DATA11 If PS_2[3]=1, defines ROM type
AV9 DBG_DATA12 AT15 GPIO26_TCK R1421 1 @ 2 10K_0402_5% Capacitor Divider Lookup Lable 100 - 512Kbit M25P05A (ST)
NC
AT9 AR14 101 - 1Mbit M25P10A (ST)
DBG_DATA13 NC
AR10
AW10
DBG_DATA14 DPC AU16
Cap (nF) 101 - 2Mbit M25P20 (ST)
AU10
DBG_DATA15 NC AV15 C1439 Bitd [5:4] Compal PN 101 - 4Mbit M25P40 (ST)
DBG_DATA16 NC 101 - 8Mbit M25P80 (ST)
AP10 DBG_DATA17 100 - 512Kbit Pm25LV010 (Chingis)
AV11 AT17
AT11
DBG_DATA18 NC AR16
680nF 00 SE00000YJ80 101 - 1Mbit Pm25LV010 (Chingis)
DBG_DATA19 NC
AR12 DBG_DATA20 82nF 01 SE076823K80
AW12 AU20 Enable external BIOS ROM device
DBG_DATA21 NC
AU12 DBG_DATA22 AT19 10nF 10 SE074103KN0 BIOS_ROM_EN PS_2[3] 0:Disabled X
NC
AP12 1:Enabled
DBG_DATA23
AT21
NC
AR20
NC 11 00 - No audio function
NC
AUD[1] NA 01 - Audio for DP only XX
VGA_SMB_CK2 AJ23 DPD AU22 10 - Audio for DP and HDMI if dongle is detected
SMBCLK SMBus NC
VGA_SMB_DA2 AH23 AV21 AUD[0] NA 11 - Audio for both DP and HDMI
SMBDATA NC
AT23 HDMI must only be enabled on systems that are
NC AR22 legally entitled. It isthe responsibility of the system
NC
AK26 SCL designer to ensure that the system is entitled to
AJ26 I2C support this feature.
SDA
2 AD39 2
R AD37
GENERAL PURPOSE I/O CEC_DIS PS_0[4] Reserved for future ASIC 0
AH20 AVSSN
SDV/FVT, NO.6 AH18
GPIO_0
AE36
AVDD MarsCRB Design NOTE:ALLOW FOR PULLUP PADS FOR THE
GPIO_1 G
AN16
GPIO_2 AVSSN
AD35 120ohm 1 1 RESERVED STRAPS BUT DO NOT INSTALL
D1401 RESISTOR
RB751V_SOD323 @
B
AF37 0.1u 1 1 IF THESE GPIOS ARE USEED, THEY MUST KEEP
1 2 GPU_GPIO5 AH17 AE38 LOW AND NOT CONFLICT DURING RESET
[31,44] VGA_AC_DET
AJ17
GPIO_5_AC_BATT
GPIO_6_TACH
AVSSN 1u 1 1
AK17 DAC1 AC36
AJ13
GPIO_7_BLON HSYNC AC38
10u 1 1 RESERVED PS_1[3] Reserved 0
GPIO_8_ROMSO VSYNC
AH15 RESERVED PS_1[2] Reserved 0
GPIO_9_ROMSI
AJ16 GPIO_10_ROMSCK
AK16 AB34 R1422 1 MARS@ 2 499_0402_1% +1.8VGS RESERVED NA Reserved 0
GPIO_11 RSET
AL16 MARS@
GPIO_12
AM16 GPIO_13 AD34 +AVDD (1.8V@70mA AVDD) L1401 1 2 BLM15BD121SN1D_2P~D RESERVED NA Reserved (for Thames/Whistler/Seymour only) 0
AM14 AVDD AE34
GPIO_14_HPD2 AVSSQ
GPU_VID1 AM13

C1432

C1433

C1434
GPIO_15_PWRCNTL_0

.1U_0402_16V7K

1U_0402_6.3V6K

10U_0603_6.3V6M
[44] GPU_VID1 (1.8V@117mA VDD1DI)
GPU_VID5 AK14 AC33 +VDD1DI 1 1 1 STRAPS TO INDICATE THE NUMBER OF AUDIO
[44] GPU_VID5 GPIO_16 VDD1DI
THM_ALERT# AG30 AC34 AUD_PORT_CONN_PINSTRAP[2] PS_3[5] CAPABLE DISPLAY OUTPUTS XXX
GPIO_17_THERMAL_INT VSS1DI
AN14 GPIO_18_HPD3 111 = 0 usable endpoints
R1423 1 @ 2 10K_0402_5% AM17
GPIO_19_CTF AUD_PORT_CONN_PINSTRAP[1] PS_3[4] 110 = 1 usable endpoints
GPU_VID2 AL13 V13 2 2 2

MARS@

MARS@

MARS@
[44] GPU_VID2 GPIO_20_PWRCNTL_1 NC 101 = 2 usable endpoints
AJ14 U13 AUD_PORT_CONN_PINSTRAP[0] PS_0[5] 100 = 3 usable endpoints
GPIO_21 NC
AK13 AF33 011 = 4 usable endpoints
GPIO_22_ROMCSB NC
PEG_CLKREQ# AN13 CLKREQB AF32 010 = 5 usable endpoints
[14] PEG_CLKREQ# NC AA29
NC 001 = 6 usable endpoints
AG21 +1.8VGS 000 = all endpoints are usable
NC
GPU_VID3 AG32 AC32
[44] GPU_VID3 GPIO_29 NC
GPU_VID4 AG33 2 1
[44] GPU_VID4 GPIO_30
AC31 L1402 MARS@
AJ19 NC_SVI2 AD30 BLM15BD121SN1D_2P~D

C1435

C1436

C1437
GENERICA
.1U_0402_16V7K

1U_0402_6.3V6K

10U_0603_6.3V6M
NC_SVI2
AK19 GENERICB AD32 1 1 1
NC_SVI2
AJ20
GENERICC
AK20
GENERICD
AJ24 GENERICE_HPD4
AH26 2 2 2
MARS@

MARS@

MARS@
GENERICF_HPD5
AH24 GENERICG_HPD6
3 3
+1.8VGS
PS_0
AM34 PS_0 MLPS Strap
2

AC30
CEC_1
R1424 0.60 V level, Please Bits[5:4] Bits[3:1] Capacitor R_pu R_pd
499_0402_1% AK24 AD31 PS_1
VDD1DI MarsCRB Design
VREFG Divider ans HPD1 MLPS PS_1
DIS@ cap close to ASIC
120ohm 1 1
PS_0[5:1] 11 001 NC 8.45K 2K
1

0.1u 1 1
+VREFG_GPU AH13 AG31 PS_2
DBG_VREFG PS_2 1u 1 1 PS_1[5:1] 11 000 NC NC 4.75K
1

DIS@
R1429
1 DIS@
C1438
10u 1 1
BACO
249_0402_1% .1U_0402_16V7K PX_EN AL21 AD33 PS_3 PS_2[5:1] 00 000 680 nF NC 4.75K
PX_EN PS_3
T1408
2 Mapping to VRAM type please refer to page 04
2

PS_3[5:1] 11 XXX NC X X
DEBUG DDC/AUX
DDC1CLK
AM26
AN26 +3VGS
Internal VGA Thermal Sensor +1.8VGS
DDC1DATA
1 DIS@ 2 AD28
TESTEN
R1434 1K_0402_5% AM27
AUX1P

1
AL27
AUX1N +3VGS
GPIO_28_FDO MLPS R1430 R1431 R1432 R1433
1

GPIO24_TRSTB AM23 JTAG_TRSTB AM19 DIS@ DIS@ X76@ @ @ DIS@

DDC2CLK
H Disable GPIO25_TDI AN23 AL19 R1427 R1428 8.45K_0402_1% 8.45K_0402_1% 8.45K_0402_1% 8.45K_0402_1%
JTAG_TDI DDC2DATA
GPIO26_TCK AK23 10K_0402_5% 10K_0402_5%
JTAG_TCK

2
L Enable GPIO27_TMS AL24 JTAG_TMS AN20 PS_0
AUX2P
5

GPIO28_TDO AM24 AM20 PS_1

JTAG_TDO AUX2N
2

T1400 PS_2
AL30 VGA_SMB_CK2 4 3 PS_3
NC AM30 EC_SMB_CK2 [25,31,32,7]
NC
2

1
DIS@ Q1400B @ 1 DIS@ 1 DIS@ 1 @ 1
THERMAL AL29 2N7002KDWH_SOT363-6 C1439 C1440 C1441 C1442 R1436 R1438 R1439 R1440
NC
AF29 DPLUS AM29 VGA_SMB_DA2 1 6 X76@ DIS@ DIS@ DIS@
NC EC_SMB_DA2 [25,31,32,7]

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K
AG29 4.75K_0402_1% 4.75K_0402_1% 4.75K_0402_1% 2K_0402_1%
DMINUS 2 2 2 2
AN21 DIS@ Q1400A
NC

2
4 AM21 2N7002KDWH_SOT363-6 4
1 DIS@ 2 AK32 NC
GPIO_28_FDO
R1435 10K_0402_5% AK30
NC
AL31 AK29
+1.8VGS TS_A NC
DIS@
L1404 (1.8V@13mA TSVDD) DDCVGACLK
AJ30 Place CLOSE VGA CHIP
1 2 +TSVDD AJ32 AJ31 SDV/FVT, NO.14
TSVDD DDCVGADATA
BLM15BD121SN1D_2P~D AJ33
C1447

C1448

C1449

TSVSS
1U_0402_6.3V6K

0.1U_0402_16V4Z

1 1 1
10U_0603_6.3V6M

DIS@ S IC 216-0841000 A0 SUN PRO M2 FCBGA 962P A39

TSVDD MarsCRB Design Security Classification Compal Secret Data Compal Electronics, Inc.
2 2 2
120ohm 1 1 Issued Date 2012/11/22 Deciphered Date 2015/11/22 Title
DIS@

DIS@

DIS@

0.1u 1 1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ATI_Sun Pro_M2_Main_MSIC
Size Document Number Rev
1u 1 1 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C 1.0
10u 1 1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8127P
Date: Tuesday, March 12, 2013 Sheet 18 of 51
A B C D E
 A B C D E

U1401C

PART 9 0F 9

SDV/FVT, NO.9
+1.8VGS
MPLL_PVDD MarsCRB Design
220ohm 1 1 L1405 DIS@ (MPLL_PVDD:1.8V@130mA )
1 2 AV33 XTALIN
0.1u 1 1 MBK1608221YZF_2P
XTALIN

10U_0603_6.3V6M

1U_0402_6.3V6K

.1U_0402_16V7K
C1450

C1451

C1452
1 1
1u 1 1 1 1 1
10u 1 1 XTALOUT R1437 DIS@ 1M_0402_5% XTALIN

DIS@
2 2 2

DIS@

DIS@

DIS@
AU34 XTALOUT Y1400
XTALOUT
1 3
1 3
+MPLL_PVDD H7 DIS@ GND GND DIS@
MPLL_PVDD
H8 C1445 C1446
SPLL_PVDD MarsCRB Design +1.8VGS MPLL_PVDD
20P_0402_50V8 2 4 20P_0402_50V8
120ohm 1 1 DIS@
XO_IN
AW34
L1406 (SPLL_PVDD:1.8V@75mA ) 27MHZ 16PF 5YEA27000163IF50Q5
0.1u 1 1 2 1 +SPLL_PVDD AM10 SPLL_PVDD

PLLS/XTAL
BLM15BD121SN1D_2P~D
1u 1 1

10U_0603_6.3V6M
C1453

C1454

C1455
1U_0402_6.3V6K

.1U_0402_16V7K
10u 1 1 1 1 1
+SPLL_VDDC AN9 AW35
SPLL_VDDC XO_IN2

2 2 2

DIS@

DIS@

DIS@
AN10 SPLL_PVSS

SPLL_VDDC MarsCRB Design

120ohm 1 1 +0.95VGS DIS@
CLKTESTA
AK10 GPUTESTA
L1407 (SPLL_VDDC:0.95V@100mA ) T1406 AF30 NC_XTAL_PVDD AL10 GPUTESTB
0.1u 1 1 2 1 T1407 AF31 NC_XTAL_PVSS
CLKTESTB
BLM15BD121SN1D_2P~D
1u 1 1

1
10U_0603_6.3V6M

1U_0402_6.3V6K

.1U_0402_16V7K
C1456

C1457

C1458
@ @

2
10u 1 1 1 1 1 SDV/FVT, NO.5 C1443
0.1U_0402_16V7K
C1444
0.1U_0402_16V7K 2

2
1
1
2 2 2

DIS@

DIS@

DIS@
DIS@ S IC 216-0841000 A0 SUN PRO M2 FCBGA 962P A39
@ @
R1441 R1442
51.1_0402_1% 51.1_0402_1%

2
2
+3VALW
SDV/FVT, NO.7
1

@
R1443 +1.5VS TO +1.5VGS
100K_0402_5%
2

+1.5V +1.5VGS
PXS_PWREN# J2 @
2 1
1

2MM
@ DIS@
OUT

Q1409 U1404
DDTC124EKA-7-F_SC59-3 AO4430L_SO8
3 8 1 3
DIS@ 1 7 2 1 DIS@ 1 DIS@

1
PXS_PWREN 2 C1467 6 3 C1468 C1469
[12,14,43,44] PXS_PWREN IN 10U_0603_6.3V6M 5 10U_0603_6.3V6M 1U_0603_10V6K R1448 @
470_0603_5%
2 2 2
GND

4
+3.3VS TO +3.3VGS

1 2
@
+VSB Q1411
3

D 2N7002K_SOT23-3
short Jumper J2 DIS@ 2
R1449 G
+3VS +3VGS +3VALW 330K_0402_5% S

3
J1 @ R1450

1
2 1 10U_0603_6.3V6M 1U_0603_10V6K 1 2

2
DIS@ 20K_0402_5% 1
1

6
2MM 1 1 R1451 R1452 DIS@
C1464 C1465 R1444 100K_0402_5% DIS@ DIS@ 0_0402_5% C1470 @
DIS@ DIS@ 470_0603_5% Q1412A @ .1U_0603_25V7K PXS_PWREN2#1 R1453 2 0_0402_5%

2
@ PXS_PWREN2# 2 2N7002KDWH_SOT363-6 2

1
3 1 2 2
1 2

+5VALW

1
3
@
SDV/FVT, NO.15 Q1407 DIS@ D Q1408 DIS@
DIS@ DIS@ AP2301GN-HF_SOT23-3 2 Q1412B
2

R1445 R1446 G PXS_PWREN 5 2N7002KDWH_SOT363-6

1 2 1 2 S 2N7002K_SOT23-3

1
3

4
470K_0402_1% 10K_0402_5%
DIS@ R1454
1

1 DIS@ 100K_0402_5%
4 D C1466 PXS_PWREN# 1 @ 2 0_0402_5% 4

2
PXS_PWREN 2 DIS@ .1U_0603_25V7K R1447
G Q1410
S 2
2N7002K_SOT23-3
3

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/22 Deciphered Date 2015/11/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ATI_Sun Pro_M2_BACO POWER
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8127P
Date: Tuesday, March 12, 2013 Sheet 19 of 51
A B C D E
 A B C D E

U1401G
PART 6 0F 9 DP_VDDR MarsCRB Design
AB39 A3
0.1u 1 1 U1401F
+0.95VGS
E39 GND GND A37 1u 1 1 PART 8 0F 9
F34 GND GND AA16
F39 GND GND AA18 10u 1 1 DP_VDDR DP_VDDC (DP_VDDC:0.95V@280mA/link )
G33 GND GND AA2 AP31 DP_VDDC 0_0402_5%1 @ 2 R1455
G34 GND GND AA21 DP_VDDC AP32
H31 GND GND AA23 DP_VDDC AN33
GND GND DP_VDDC
SDV/FVT, NO.8

@
1U_0402_6.3V6K

.1U_0402_16V7K
H34 AA26 AP33
H39 GND GND AA28 AN24 DP_VDDC AL33
GND GND NC DP_VDDC 1 1
J31 AA6 AP24 AM33
J34 GND GND AB12 AP25 NC DP_VDDC AK33
GND GND NC DP_VDDC

C1485

C1486
1 K31 AB15 AMD: AP26 AK34 1
K34 GND GND AB17 AU28 NC DP_VDDC AN31 2 2
GND GND no display from GPU, NC DP_VDDC
K39 AB20 AV29
GND GND can uninstall the capacitors NC
L31 AB22
L34 GND GND AB24
M34 GND GND AB27 AP20 AP13
GND GND NC NC
M39 AC11 AP21 AT13
N31 GND GND AC13 AP22 NC NC AP14
N34 GND GND AC16 AP23 NC NC AP15
P31 GND GND AC18 AU18 NC NC DP_VDDC MarsCRB Design
GND GND NC
P34
P39 GND GND
AC2
AC21
+1.8VGS AV19
NC DP GND
0.1u 1 1
R34 GND
GND
GND
GND
AC23 (DP_VDDR:1.8V@237mA/link ) DP_VSSR
AN27 1u 1 1
T31 AC26 R1456 1 @ 2 0_0402_5% DP_VDDR AH34 AP27
T34 GND GND AC28 AJ34 DP_VDDR DP_VSSR AP28 10u 1 1
T39 GND GND AC6 AF34 DP_VDDR DP_VSSR AW24
GND GND
SDV/FVT, NO.8 DP_VDDR DP_VSSR

@
.1U_0402_16V7K

1U_0402_6.3V6K
U31 AD15 AG34 AW26
U34 GND GND AD17 AM37 DP_VDDR DP_VSSR AN29
GND GND 1 1 DP_VDDR DP_VSSR
V34 AD20 AL38 AP29
V39 GND GND AD22 AM32 DP_VDDR DP_VSSR AP30
GND GND DP_VDDR DP_VSSR

C1471

C1476
W31 AD24 AW30
W34 GND GND AD27 2 2 DP_VSSR AW32
Y34 GND GND AD9 DP_VSSR AN17
Y39 GND GND AE2 DP_VSSR AP16
GND GND AE6 DP_VSSR AP17
GND AF10 DP_VSSR AW14
GND AF16 DP_VSSR AW16
GND AF18 DP_VSSR AN19
GND AF21 DP_VSSR AP18
GND GND DP_VSSR
AG17 AP19
F15 GND AG2 DP_VSSR AW20
F17 GND GND AG20 CALIBRATION DP_VSSR AW22
GND GND
SDV/FVT, NO.10 DP_VSSR
2 F19 AN34 2
F21 GND AG6 DP_VSSR AP39
F23 GND GND AG9 AW28 DP_VSSR AR39
F25 GND GND AH21 NC DP_VSSR AU37
F27 GND GND AJ10 DP_VSSR AF39
F29 GND GND AJ11 DP_VSSR AH39
F31 GND GND AJ2 AW18 DP_VSSR AK39
F33 GND GND AJ28 NC DP_VSSR AL34
F7 GND GND AJ6 DP_VSSR AV27
F9 GND GND AK11 DP_VSSR AR28
G2 GND GND AK31 DP_VSSR
R1459 2 DIS@ 1 150_0402_1% AM39 AV17
G6 GND GND AK7 DP_CALR DP_VSSR AR18
H9 GND GND AL11 DP_VSSR AN38
J2 GND GND AL14 DP_VSSR AM35
J27 GND GND AL17 DP_VSSR AN32
J6 GND GND AL2 DP_VSSR
J8 GND GND AL20
K14 GND GND
K7 GND AL23
L11 GND AL26
L17 GND GND AL32
L2 GND GND AL6 DIS@ S IC 216-0841000 A0 SUN PRO M2 FCBGA 962P A39
L22 GND GND AL8
L24 GND GND AM11
L6 GND GND AM31
M17 GND GND AM9
M22 GND GND AN11
M24 GND GND AN2
N16 GND GND AN30
N18 GND GND AN6
N2 GND GND AN8
N21 GND GND AP11
3 N23 GND GND AP7 3
N26 GND GND AP9
N6 GND GND AR5
R15 GND GND B11
R17 GND GND B13
R2 GND GND B15
R20 GND GND B17
R22 GND GND B19
R24 GND GND B21
R27 GND GND B23
R6 GND GND B25
T11 GND GND B27
T13 GND GND B29
T16 GND GND B31
T18 GND GND B33
T21 GND GND B7
T23 GND GND B9
T26 GND GND C1
U15 GND GND C39
U17 GND GND E35
U2 GND GND E5
U20 GND GND F11
U22 GND GND F13
U24 GND GND
U27 GND GND
U6 GND
V11 GND AG22
V16 GND NC
V18 GND
V21 GND
V23 GND
V26 GND
4 W2 GND 4
W6 GND
Y15 GND
Y17 GND
Y20 GND
Y22 GND A39 MECH#1
Y24 GND VSS_MECH AW1 MECH#2 T1403 PAD
Y27 GND VSS_MECH AW39 MECH#3 T1404 PAD
GND VSS_MECH T1405 PAD Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/11/22 Deciphered Date 2015/11/22 Title

DIS@ S IC 216-0841000 A0 SUN PRO M2 FCBGA 962P A39

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ATI_Sun Pro_M2_PWR_GND
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8127P
Date: Tuesday, March 12, 2013 Sheet 20 of 51
A B C D E
 A B C D E

For GDDR5, MVDDQ = 1.5V

(VDDR1:1.5V@3A,GDDR5:1125MHz ) (PCIE_VDDR:1.8V@100mA ) +1.8VGS
+1.5VGS U1401E DIS@ L1408
PART 5 0F 9 +PCIE_VDDR 2 1
PCIE_VDDR MarsCRB Design
MBK1608121YZF_0603 0.1u 0 2

C1489

C1490

C1491

C1492

C1493

C1494
MEM I/O

10U_0603_6.3V6M
.1U_0402_16V7K

.1U_0402_16V7K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
AC7
VDDR1 NC
AA31 1 1 1 1 1 1 1u 2 3
AD11 AA32
AF7
VDDR1 NC AA33 10u 1 1

C1495

C1496

C1503

C1497

C1498

C1504

C1499

C1505

C1500

C1506

C1507

C1501

C1508

C1509

C1510

C1502
1 VDDR1

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
NC

220U_B2_2.5VM_R35
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 AG10 VDDR1 AA34
+ NC 2 2 2 2 2 2
AJ7 W30

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
VDDR1 NC
@ AK8 Y31
VDDR1 NC
AL9 VDDR1 V28
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 G11 NC_BIF_VDDC W29

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
VDDR1 NC_BIF_VDDC +0.95VGS
G14 AB37
1 VDDR1 PCIE_PVDD PCIE_VDDC MarsCRB Design 1

PCIE
G17 (PCIE_VDDC:0.95V@2.5A_GEN3.0 )
VDDR1
G20
G23
VDDR1 PCIE_VDDC
G30
G31
+PCIE_VDDC 1u 7 5
VDDR1 PCIE_VDDC
G26 H29 10u 2 1

C1511

C1512

C1513

C1514

C1515

C1516
VDDR1

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M
PCIE_VDDC
G29 VDDR1 H30 1 1 1 1 1 1
PCIE_VDDC
H10 J29
VDDR1 MarsCRB Design J7
VDDR1 PCIE_VDDC J30
VDDR1 PCIE_VDDC
0.01u 5 0 J9 VDDR1 PCIE_VDDC
L28
2 2 2 2 2 2

@
K11 M28

DIS@

DIS@

DIS@

DIS@

DIS@
VDDR1 PCIE_VDDC
0.1u 5 5 K13 VDDR1 PCIE_VDDC
N28
K8 R28
1u 0 5 L12
VDDR1
VDDR1
PCIE_VDDC T28
PCIE_VDDC
2.2u 5 0 L16 VDDR1 U28
L21 PCIE_VDDC +0.95VGS
VDDR1
10u 3 5 L23 VDDR1 (BIF_VDDC:0.95V@1.4A)
L26 N27 +0.95VGS
220u 0 1 VDDR1 BACO BIF_VDDC
L7 T27
VDDR1 BIF_VDDC
M11

C1517

C1518
VDDR1

1U_0402_6.3V6K

1U_0402_6.3V6K
N11 1 1
VDDR1
P7 VDDR1 AA15
CORE VDDC
R11 AA17
VDDR1 VDDC
U11 AA20
+1.8VGS +VDDC_CT VDDR1 VDDC 2 2
U7 AA22

DIS@

DIS@
VDD_CT MarsCRB Design Y11
VDDR1 VDDC AA24
VDDR1 VDDC
120ohm 1 1 1
DIS@ L1409
2
(VDD_CT:1.8V@13mA ) Y7 VDDR1 VDDC
AA27
AB16
0.1u 1 1 VDDC AB18
BLM15BD121SN1D_2P~D
VDDC
AB21

C1532

C1533

C1534

C1535

C1536
1u 1 3

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

.1U_0402_16V7K
VDDC AB23 +VGA_CORE
1 1 1 1 1 VDDC
10u 1 1 LEVEL AB26
VDDC
TRANSLATION AB28
AF26 VDDC AC17
2 2 2 2 2 VDD_CT VDDC
AF27 AC20

DIS@

DIS@

DIS@

DIS@

DIS@

C1523

C1524

C1525

C1526

C1519

C1527

C1528

C1520

C1529

C1530

C1521

C1522

C1531
VDD_CT

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
AG26 VDDC AC22
VDD_CT VDDC 1 1 1 1 1 1 1 1 1 1 1 1 1
AG27 VDD_CT AC24
VDDC
AC27
+3VGS VDDC AD18
VDDC 2 2 2 2 2 2 2 2 2 2 2 2 2
AD21

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
2
VDDR3 MarsCRB Design (VDDR3:3.3V@25mA) +VDDR3 AF23
I/O VDDC AD23
2
VDDR3 VDDC
120ohm 1 0 AF24 VDDR3
AG23
VDDC
AD26
AF17
C1537

C1538

C1539

C1540
10U_0603_6.3V6M

VDDR3
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
0.1u 1 0 AG24 VDDC AF20
1 1 1 1 VDDR3 VDDC
AF22
1u 2 3 DVP
VDDC AG16
VDDC +VGA_CORE
10u 0 1 AD12 VDDR4 AG18
2 2 2 2 VDDC
AF11
DIS@

DIS@

DIS@

DIS@

VDDR4
AF12 AH22
VDDR4 VDDC
AF13 VDDR4 AH27
VDDC AH28

C1541

C1542

C1543

C1544

C1545

C1546

C1547

C1548

C1549

C1550

C1551

C1552
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
VDDC
M26 1 1 1 1 1 1 1 1 1 1 1 1
+1.8VGS VDDC
AF15 N24
VDDR4 VDDC
AG11 R18
VDDR4 VDDC
L1410 MARS@ ( VDDR4:1.8V@300mA) AG13 VDDR4 R21
VDDR4 MarsCRB Design 1 2 +VDDR4 AG15 VDDC R23 2 2 2 2 2 2 2 2 2 2 2 2

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
VDDR4 VDDC
220ohm 1 1 MBK1608221YZF_2P
VDDC
R26
T17
C1553

C1554
1U_0402_6.3V6K

.1U_0402_16V7K

0.1u 1 1 VDDC T20

1 1 VDDC
T22
1u 1 1 VDDC T24
VDDC
10u 1 0 U16
2 2 VDDC +VGA_CORE
U18
MARS@

MARS@

VDDC U21
VDDC
U23
VDDC U26
VDDC
V17

C1555

C1556
10U_0603_6.3V6M

22U_0603_6.3V6M
VDDC
V20 1 1
VDDC V22
for Sun Pro Ball name AD12,AF11,AF12,AF13,AF15,AG11,AG13,AG15 is NC VDDC
V24
VDDC V27
VDDC 2 2
Y16

DIS@

DIS@
VDDC
Y18
VDDC Y21
VDDC
Y23
VDDC Y26
VDDC +VGA_CORE
Y28
3 VDDC 3
(VDDCI:0.9~1.15V@8.8A)
AA13
VDDCI
AB13
VDDCI AC12

C1557

C1558

C1559

C1560

C1561

C1562

C1563

C1564

C1565

C1566

C1567

C1568
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

22U_0603_6.3V6M
VDDCI
AC15 1 1 1 1 1 1 1 1 1 1 1 1
VDDCI
AD13
VDDCI AD16
VDDCI
M15
VDDCI M16 2 2 2 2 2 2 2 2 2 2 2 2

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
VDDCI
M18
Route as differential pair VOLTAGE VDDCI
M23
CORE I/O

SENESE VDDCI
ISOLATED

N13
VDDCI
AF28 FB_VDDC N15
[44] VCCSENSE_VGA VDDCI N17
VDDCI
N20
VDDCI
AG28 N22
FB_VDDCI VDDCI R12
VDDCI
R13
AH29 VDDCI R16
[44] VSSSENSE_VGA FB_GND VDDCI
T12
VDDCI
T15
VDDCI V15
VDDCI
Y13
VDDCI

DIS@ S IC 216-0841000 A0 SUN PRO M2 FCBGA 962P A39

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/22 Deciphered Date 2015/11/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ATI_Sun Pro_M2_Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8127P
Date: Tuesday, March 12, 2013 Sheet 21 of 51
A B C D E
 A B C D E

U1401H SDV/FVT, NO.4

U1401I
PART 3 0F 9
PART 4 0F 9
GDDR5/DDR3
C37 G24
DQA0_0 MAA0_0/MAA_0 GDDR5/DDR3
C35 DQA0_1 MAA0_1/MAA_1 J23 MDA0 C5 MAB0_0/MAB_0 P8 MAA0
A35 H24 C3 DQB0_0 T9
DQA0_2 MAA0_2/MAA_2 MDA1 MAB0_1/MAB_1 MAA1
DQB0_1
E34 DQA0_3 MAA0_3/MAA_3 J24 MDA2 E3 MAB0_2/MAB_2 P9 MAA2
DQB0_2
G32 H26 MDA3 E1 N7 MAA3
DQA0_4 MAA0_4/MAA_4 DQB0_3 MAB0_3/MAB_3
D33 J26 MDA4 F1 N8 MAA4
DQA0_5 MAA0_5/MAA_5 DQB0_4 MAB0_4/MAB_4
F32 DQA0_6 MAA0_6/MAA_6 H21 MDA5 F3 MAB0_5/MAB_5 N9 MAA5
E32 G21 F5 DQB0_5 U9
MDA6 MAA6

MEMORY INTERFACE A
DQA0_7 MAA0_7/MAA_7 DQB0_6 MAB0_6/MAB_6
D31 DQA0_8 MAA1_0/MAA_8 H19 MDA7 G4 MAB0_7/MAB_7 U8 MAA7
DQB0_7
F30 H20 MDA8 H5 Y9 MAA8
DQA0_9 MAA1_1/MAA_9 DQB0_8 MAB1_0/MAB_8
C30 L13 MDA9 H6 W9 MAA9
DQA0_10 MAA1_2/MAA_10 DQB0_9 MAB1_1/MAB_9
A30 DQA0_11 MAA1_3/MAA_11 G16 MDA10 J4 MAB1_2/MAB_10 AC8 MAA10
F28 J16 K6 DQB0_10 AC9
DQA0_12 MAA1_4/MAA_12 MDA11 MAB1_3/MAB_11 MAA11
DQB0_11
C28 DQA0_13 MAA1_5/MAA_BA2 H16 MDA12 K5 MAB1_4/MAB_12 AA7 MAA12
1 DQB0_12 1
A28 J17 MDA13 L4 AA8 A_BA2
DQA0_14 MAA1_6/MAA_BA0 MDA[0..63] DQB0_13 MAB1_5/BA2
E28 H17 MDA14 M6 Y8 A_BA0
DQA0_15 MAA1_7/MAA_BA1 MDA[0..63] [23] DQB0_14 MAB1_6/BA0
D27 DQA0_16 MDA15 M1 MAB1_7/BA1 AA9 A_BA1
MAA[0..14] DQB0_15

MEMORY INTERFACE B
F26 A32 MDA16 M3
DQA0_17 WCKA0_0/DQMA_0 MAA[0..14] [23] DQB0_16
C26 DQA0_18 WCKA0B_0/DQMA_1 C32 MDA17 M5 H3 DQMA#0
A_BA[0..2] DQB0_17 WCKB0_0/DQMB_0
A26 D23 MDA18 N4 H1 DQMA#1
DQA0_19 WCKA0_1/DQMA_2 A_BA[0..2] [23] DQB0_18 WCKB0B_0/DQMB_1
F24 E22 MDA19 P6 T3 DQMA#2
DQA0_20 WCKA0B_1/DQMA_3 DQB0_19 WCKB0_1/DQMB_2
C24 C14 DQMA#[0..7] MDA20 P5 T5 DQMA#3
DQA0_21 WCKA1_0/DQMA_4 DQMA#[0..7] [23] DQB0_20 WCKB0B_1/DQMB_3
A24 A14 MDA21 R4 AE4 DQMA#4
DQA0_22 WCKA1B_0/DQMA_5 DQB0_21 WCKB1_0/DQMB_4
E24 E10 QSA[0..7] MDA22 T6 AF5 DQMA#5
DQA0_23 WCKA1_1/DQMA_6 QSA[0..7] [23] DQB0_22 WCKB1B_0/DQMB_5
C22 D9 MDA23 T1 AK6 DQMA#6
DQA0_24 WCKA1B_1/DQMA_7 QSA#[0..7] DQB0_23 WCKB1_1/DQMB_6
A22 MDA24 U4 AK5 DQMA#7
DQA0_25 QSA#[0..7] [23] DQB0_24 WCKB1B_1/DQMB_7
F22 DQA0_26 C34 MDA25 V6
D21 EDCA0_0/QSA_0 D29 V1 DQB0_25 F6
DQA0_27 MDA26 QSA0
EDCA0_1/QSA_1 DQB0_26 EDCB0_0/QSB_0
A20 DQA0_28 D25 MDA27 V3 K3 QSA1
EDCA0_2/QSA_2 DQB0_27 EDCB0_1/QSB_1
F20 E20 MDA28 Y6 P3 QSA2
DQA0_29 EDCA0_3/QSA_3 DQB0_28 EDCB0_2/QSB_2
D19 E16 MDA29 Y1 V5 QSA3
DQA0_30 EDCA1_0/QSA_4 DQB0_29 EDCB0_3/QSB_3
E18 DQA0_31 E12 MDA30 Y3 AB5 QSA4
C18 EDCA1_1/QSA_5 J10 Y5 DQB0_30 EDCB1_0/QSB_4 AH1
DQA1_0 MDA31 QSA5
EDCA1_2/QSA_6 DQB0_31 EDCB1_1/QSB_5
A18 DQA1_1 D7 MDA32 AA4 AJ9 QSA6
EDCA1_3/QSA_7 DQB1_0 EDCB1_2/QSB_6
F18 MDA33 AB6 AM5 QSA7
DQA1_2 DQB1_1 EDCB1_3/QSB_7
D17 A34 MDA34 AB1
DQA1_3 DDBIA0_0/QSA_0B DQB1_2
A16 DQA1_4 E30 MDA35 AB3 G7 QSA#0
F16 DDBIA0_1/QSA_1B E26 AD6 DQB1_3 DDBIB0_0/QSB_0B K1
DQA1_5 MDA36 QSA#1
DDBIA0_2/QSA_2B DQB1_4 DDBIB0_1/QSB_1B
D15 DQA1_6 C20 MDA37 AD1 P1 QSA#2
DDBIA0_3/QSA_3B DQB1_5 DDBIB0_2/QSB_2B
E14 C16 MDA38 AD3 W4 QSA#3
DQA1_7 DDBIA1_0/QSA_4B DQB1_6 DDBIB0_3/QSB_3B
F14 C12 MDA39 AD5 AC4 QSA#4
DQA1_8 DDBIA1_1/QSA_5B DQB1_7 DDBIB1_0/QSB_4B
D13 DQA1_9 J11 MDA40 AF1 AH3 QSA#5
F12 DDBIA1_2/QSA_6B F8 AF3 DQB1_8 DDBIB1_1/QSB_5B AJ8
DQA1_10 MDA41 QSA#6
DDBIA1_3/QSA_7B DQB1_9 DDBIB1_2/QSB_6B
A12 DQA1_11 MDA42 AF6 AM3 QSA#7
DQB1_10 DDBIB1_3/QSB_7B
D11 J21 MDA43 AG4
DQA1_12 ADBIA0/ODTA0 DQB1_11
F10 G19 MDA44 AH5 T7 ODTA0
DQA1_13 ADBIA1/ODTA1 DQB1_12 ADBIB0/ODTB0 ODTA0 [23]
A10 DQA1_14 MDA45 AH6 W7 ODTA1
C10 H27 AJ4 DQB1_13 ADBIB1/ODTB1 ODTA1 [23]
DQA1_15 CLKA0 MDA46
DQB1_14
G13 DQA1_16 CLKA0B G27 MDA47 AK3 L9 CLKA0
DQB1_15 CLKB0 CLKA0 [23]
H13 MDA48 AF8 L8 CLKA0#
DQA1_17 DQB1_16 CLKB0B CLKA0# [23]
J13 J14 MDA49 AF9
DQA1_18 CLKA1 DQB1_17
2 H11 DQA1_19 CLKA1B H14 MDA50 AG8 AD8 CLKA1 2
G10 AG7 DQB1_18 CLKB1 AD7 CLKA1# CLKA1 [23]
DQA1_20 MDA51
DQB1_19 CLKB1B CLKA1# [23]
G8 DQA1_21 K23 MDA52 AK9
RASA0B DQB1_20
K9 K19 MDA53 AL7 T10 RASA0#
DQA1_22 RASA1B DQB1_21 RASB0B RASA0# [23]
K10 MDA54 AM8 Y10 RASA1#
DQA1_23 DQB1_22 RASB1B RASA1# [23]
G9 DQA1_24 K20 MDA55 AM7
A8 CASA0B K17 AK1 DQB1_23 W10 CASA0#
DQA1_25 MDA56
CASA1B DQB1_24 CASB0B CASA0# [23]
C8 DQA1_26 MDA57 AL4 AA10 CASA1#
DQB1_25 CASB1B CASA1# [23]
E8 CSA0B_0 K24 MDA58 AM6
DQA1_27 DQB1_26
A6 CSA0B_1 K27 MDA59 AM1 P10 CSA0#_0
DQA1_28 DQB1_27 CSB0B_0 CSA0#_0 [23]
C6 DQA1_29 MDA60 AN4 L10
E6 M13 AP3 DQB1_28 CSB0B_1
DQA1_30 CSA1B_0 MDA61
DQB1_29
A5 DQA1_31 CSA1B_1 K16 MDA62 AP1 AD10 CSA1#_0
DQB1_30 CSB1B_0 CSA1#_0 [23]
MDA63 AP5 AC10
L18 K21 DQB1_31 CSB1B_1
MVREFDA CKEA0
L20 MVREFSA CKEA1 J20 U10 CKEA0
CKEB0 CKEA0 [23]
SDV/FVT, NO.11 +VDD_MEM15_REFDA Y12 AA11 CKEA1
MVREFDB CKEB1 CKEA1 [23]
L27 NC WEA0B K26 +VDD_MEM15_REFSA AA12
MVREFSB
N12 WEA1B L15 N10 WEA0#
NC WEB0B WEA0# [23]
AG12 AB11 WEA1#
NC WEB1B WEA1# [23]
H23
MAA0_8/MAA_13
R1470 1 DIS@ 2 120_0402_1% M27 MEM_CALRP0 MAA1_8/MAA_14 J19 MAB0_8/MAB_13 T8 MAA13
SDV/FVT, NO.11 M21 W8 MAA14
MAA0_9/MAA_15 MAB1_8/MAB_14
M12 M20 U12
NC MAA1_9/RSVD MAB0_9/MAB_15
AH12 NC MAB1_9/RSVD V12

DRAM_RST AH11 DRAM_RST#_R

DIS@ S IC 216-0841000 A0 SUN PRO M2 FCBGA 962P A39 DIS@ S IC 216-0841000 A0 SUN PRO M2 FCBGA 962P A39

3 3

+1.5VGS

1
+1.5VGS +1.5VGS
R1472
4.7K_0402_5%
1

@
R1473 R1474
2

40.2_0402_1% 40.2_0402_1%
DIS@ DIS@
DIS@
2

1 R1475 2 1 R1476 2 DRAM_RST#_R

+VDD_MEM15_REFDA +VDD_MEM15_REFSA [23] DRAM_RST# 51.1_0402_1% 10_0402_5%
DIS@
1 1
1

DIS@ DIS@ DIS@ DIS@ 1

R1477 C1571 R1478 C1572 DIS@ DIS@
100_0402_1% 1U_0402_6.3V6K 100_0402_1% 1U_0402_6.3V6K C1573 R1479
2 2 120P_0402_50V8 4.99K_0402_1%
2
2

DRAM_RST# is a daisy-chain net that connects to all VRAM

This basic topology should be used for DRAM_RST for DDR3/GDDR5.These
Capacitors and Resistor values are an example only. The Series R and
|| Cap values will depend on the DRAM load and will have to be
4 4
calculated for different Memory ,DRAM Load and board to pass Reset
Signal Spec.
Place all these components very close to GPU (Within
25mm) and keep all component close to each Other (within
5mm) except Rser2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/22 Deciphered Date 2015/11/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ATI_Sun Pro_M2_MEM IF
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8127P
Date: Tuesday, March 12, 2013 Sheet 22 of 51
A B C D E
 5 4 3 2 1

The Seymour M2 only support channel B (64 bit),

this page unmount all parts
U1405 U1406 U1407 U1408

VREFC_A1 M8 E3 MDA19 VREFC_A2 M8 E3 MDA27 VREFC_A3 M8 E3 MDA35 VREFC_A4 M8 E3 MDA53

VREFD_Q1 H1 VREFCA DQL0 F7 MDA20 VREFD_Q2 H1 VREFCA DQL0 F7 MDA31 VREFD_Q3 H1 VREFCA DQL0 F7 MDA37 VREFD_Q4 H1 VREFCA DQL0 F7 MDA50
VREFDQ DQL1 F2 MDA21 VREFDQ DQL1 F2 MDA25 VREFDQ DQL1 F2 MDA32 VREFDQ DQL1 F2 MDA52
MAA0 N3 DQL2 F8 MDA16 MAA0 N3 DQL2 F8 MDA29 MAA0 N3 DQL2 F8 MDA39 MAA0 N3 DQL2 F8 MDA51
MAA1 P7 A0 DQL3 H3 MDA23 MAA1 P7 A0 DQL3 H3 MDA26 MAA1 P7 A0 DQL3 H3 MDA34 MAA1 P7 A0 DQL3 H3 MDA55
MAA2 P3 A1 DQL4 H8 MDA17 MAA2 P3 A1 DQL4 H8 MDA30 MAA2 P3 A1 DQL4 H8 MDA36 MAA2 P3 A1 DQL4 H8 MDA49
MAA3 N2 A2 DQL5 G2 MDA22 MAA3 N2 A2 DQL5 G2 MDA24 MAA3 N2 A2 DQL5 G2 MDA33 MAA3 N2 A2 DQL5 G2 MDA54
MAA4 P8 A3 DQL6 H7 MDA18 MAA4 P8 A3 DQL6 H7 MDA28 MAA4 P8 A3 DQL6 H7 MDA38 MAA4 P8 A3 DQL6 H7 MDA48
MAA5 P2 A4 DQL7 MAA5 P2 A4 DQL7 MAA5 P2 A4 DQL7 MAA5 P2 A4 DQL7
MAA6 R8 A5 MAA6 R8 A5 MAA6 R8 A5 MAA6 R8 A5
D MDA[0..63] MAA7 R2 A6 D7 MDA0 MAA7 R2 A6 D7 MDA15 MAA7 R2 A6 D7 MDA45 MAA7 R2 A6 D7 MDA56 D
[22] MDA[0..63] MAA8 T8 A7 DQU0 C3 MDA4 MAA8 T8 A7 DQU0 C3 MDA11 MAA8 T8 A7 DQU0 C3 MDA41 MAA8 T8 A7 DQU0 C3 MDA59
MAA9 R3 A8 DQU1 C8 MDA1 MAA9 R3 A8 DQU1 C8 MDA12 MAA9 R3 A8 DQU1 C8 MDA47 MAA9 R3 A8 DQU1 C8 MDA63
MAA10 L7 A9 DQU2 C2 MDA7 MAA10 L7 A9 DQU2 C2 MDA10 MAA10 L7 A9 DQU2 C2 MDA40 MAA10 L7 A9 DQU2 C2 MDA61
MAA11 R7 A10/AP DQU3 A7 MDA3 MAA11 R7 A10/AP DQU3 A7 MDA13 MAA11 R7 A10/AP DQU3 A7 MDA44 MAA11 R7 A10/AP DQU3 A7 MDA57
MAA12 N7 A11 DQU4 A2 MDA6 MAA12 N7 A11 DQU4 A2 MDA9 MAA12 N7 A11 DQU4 A2 MDA42 MAA12 N7 A11 DQU4 A2 MDA62
MAA[14..0] MAA13 T3 A12 DQU5 B8 MDA2 MAA13 T3 A12 DQU5 B8 MDA14 MAA13 T3 A12 DQU5 B8 MDA46 MAA13 T3 A12 DQU5 B8 MDA58
[22] MAA[14..0] A13 DQU6 A13 DQU6 A13 DQU6 A13 DQU6
MAA14 T7 A3 MDA5 MAA14 T7 A3 MDA8 MAA14 T7 A3 MDA43 MAA14 T7 A3 MDA60
M7 A14 DQU7 M7 A14 DQU7 M7 A14 DQU7 M7 A14 DQU7
A15/BA3 +1.5VGS A15/BA3 +1.5VGS A15/BA3 +1.5VGS A15/BA3 +1.5VGS

M2 B2 A_BA0 M2 B2 A_BA0 M2 B2 A_BA0 M2 B2

[22] A_BA0 BA0 VDD BA0 VDD BA0 VDD BA0 VDD
N8 D9 A_BA1 N8 D9 A_BA1 N8 D9 A_BA1 N8 D9
DQMA#[7..0] [22] A_BA1 M3 BA1 VDD G7 M3 BA1 VDD G7 M3 BA1 VDD G7 M3 BA1 VDD G7
A_BA2 A_BA2 A_BA2
[22] DQMA#[7..0] [22] A_BA2 BA2 VDD BA2 VDD BA2 VDD BA2 VDD
K2 K2 K2 K2
VDD K8 VDD K8 VDD K8 VDD K8
VDD N1 VDD N1 VDD N1 VDD N1
J7 VDD N9 CLKA0 J7 VDD N9 J7 VDD N9 CLKA1 J7 VDD N9
[22] CLKA0 K7 CK VDD R1 K7 CK VDD R1 [22] CLKA1 K7 CK VDD R1 K7 CK VDD R1
CLKA0# CLKA1#
QSA[7..0] [22] CLKA0# CK VDD CK VDD [22] CLKA1# CK VDD CK VDD
K9 R9 CKEA0 K9 R9 K9 R9 CKEA1 K9 R9
[22] QSA[7..0] [22] CKEA0 CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS [22] CKEA1 CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS

K1 A1 ODTA0 K1 A1 K1 A1 ODTA1 K1 A1
[22] ODTA0 L2 ODT/ODT0 VDDQ A8 L2 ODT/ODT0 VDDQ A8 [22] ODTA1 L2 ODT/ODT0 VDDQ A8 L2 ODT/ODT0 VDDQ A8
CSA0#_0 CSA1#_0
[22] CSA0#_0 CS/CS0 VDDQ CS/CS0 VDDQ [22] CSA1#_0 CS/CS0 VDDQ CS/CS0 VDDQ
J3 C1 RASA0# J3 C1 J3 C1 RASA1# J3 C1
[22] RASA0# RAS VDDQ RAS VDDQ [22] RASA1# RAS VDDQ RAS VDDQ
K3 C9 CASA0# K3 C9 K3 C9 CASA1# K3 C9
QSA#[7..0] [22] CASA0# L3 CAS VDDQ D2 L3 CAS VDDQ D2 [22] CASA1# L3 CAS VDDQ D2 L3 CAS VDDQ D2
WEA0# WEA1#
[22] QSA#[7..0] [22] WEA0# WE VDDQ WE VDDQ [22] WEA1# WE VDDQ WE VDDQ
E9 E9 E9 E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
QSA2 F3 VDDQ H2 QSA3 F3 VDDQ H2 QSA4 F3 VDDQ H2 QSA6 F3 VDDQ H2
QSA0 C7 DQSL VDDQ H9 QSA1 C7 DQSL VDDQ H9 QSA5 C7 DQSL VDDQ H9 QSA7 C7 DQSL VDDQ H9
DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ

DQMA#2 E7 A9 DQMA#3 E7 A9 DQMA#4 E7 A9 DQMA#6 E7 A9

DQMA#0 D3 DML VSS B3 DQMA#1 D3 DML VSS B3 DQMA#5 D3 DML VSS B3 DQMA#7 D3 DML VSS B3
DMU VSS E1 DMU VSS E1 DMU VSS E1 DMU VSS E1
VSS G8 VSS G8 VSS G8 VSS G8
QSA#2 G3 VSS J2 QSA#3 G3 VSS J2 QSA#4 G3 VSS J2 QSA#6 G3 VSS J2
C C
QSA#0 B7 DQSL VSS J8 QSA#1 B7 DQSL VSS J8 QSA#5 B7 DQSL VSS J8 QSA#7 B7 DQSL VSS J8
DQSU VSS M1 DQSU VSS M1 DQSU VSS M1 DQSU VSS M1
VSS M9 VSS M9 VSS M9 VSS M9
VSS P1 VSS P1 VSS P1 VSS P1
T2 VSS P9 DRAM_RST# T2 VSS P9 DRAM_RST# T2 VSS P9 DRAM_RST# T2 VSS P9
[22] DRAM_RST# RESET VSS T1 RESET VSS T1 RESET VSS T1 RESET VSS T1
L8 VSS T9 L8 VSS T9 L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1

1
DIS@ J1 B1 DIS@ J1 B1 DIS@ J1 B1 DIS@ J1 B1
R1480 L1 NC/ODT1 VSSQ B9 R1481 L1 NC/ODT1 VSSQ B9 R1482 L1 NC/ODT1 VSSQ B9 R1483 L1 NC/ODT1 VSSQ B9
J9 NC/CS1 VSSQ D1 J9 NC/CS1 VSSQ D1 J9 NC/CS1 VSSQ D1 J9 NC/CS1 VSSQ D1
243_0402_1% NC/CE1 VSSQ 243_0402_1% NC/CE1 VSSQ 243_0402_1% NC/CE1 VSSQ 243_0402_1% NC/CE1 VSSQ
L9 D8 L9 D8 L9 D8 L9 D8
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
2

2
VSSQ E8 VSSQ E8 VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9 VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9 VSSQ G9 VSSQ G9
VSSQ VSSQ VSSQ VSSQ
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
CLKA0 1 DIS@ 2 X76@ X76@ X76@ X76@
R1484 40.2_0402_1%

CLKA0# 1 DIS@ 2
R1485 40.2_0402_1%
1

C1574
0.01U_0402_16V7K +1.5VGS +1.5VGS
DIS@ +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS
2

1
DIS@
DIS@ R1487 R1488 R1489 R1490 R1491 R1492 R1493
R1486 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
B B
4.99K_0402_1% DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
2

2
CLKA1 1 DIS@ 2
R1494 40.2_0402_1% VREFD_Q1 VREFC_A1 VREFC_A2 VREFD_Q2 VREFC_A3 VREFD_Q3 VREFC_A4 VREFD_Q4
1

1
.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K
DIS@ DIS@
C1576

C1577

C1578

C1579

C1580

C1581

C1582
1

1
.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K
CLKA1# 1 DIS@ 2 R1496 R1497 R1498 R1499 R1500 R1501 R1502 R1503

C1583
R1495 40.2_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
1

C1575 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
2

2
0.01U_0402_16V7K DIS@ DIS@ DIS@
2

2
DIS@
2

+1.5VGS
+1.5VGS
+1.5VGS +1.5VGS
C1584

C1585

C1586

C1587

C1588

C1589

C1590

C1591

C1592

C1593

C1594

C1595

C1596
.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

C1597

C1598

C1599

C1600

C1601

C1602

C1603

C1604

C1605

C1606

C1607

C1608

C1609

C1610

C1611

C1612

C1613

C1614

C1615

C1616

C1617

C1618

C1619

C1620
1 1 1 1 1 1 1 1 1 1 1 1 1
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2
DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/22 Deciphered Date 2015/11/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
ATI_Sun
Document Number
Pro_M2_VRAM_A Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-8127P
Tuesday, March 12, 2013 Sheet 23 of 51
5 4 3 2 1
 5 4 3 2 1

The Mars Pro M2 only support channel B (64 bit)

SDV/FVT, NO.4

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/22 Deciphered Date 2015/11/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
ATI_Sun
Document Number
Pro_M2_VRAM_B Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-8127P
Tuesday, March 12, 2013 Sheet 24 of 51
5 4 3 2 1
 5 4 3 2 1

+3VS +3VS_PS EEROM

Part number: SA00004EU10
30mil 30mil +SWR_VDD
R2101 1 @ 2 0_0603_5%

R2169 2 1 10K_0402_5%
+3VS_PS
Close to Pin3 U2101 U2100
19 8 1 A0
TXEC+ LVDS_ACLK [26] VCC A0
+DP_V33 2
L2101 1 +DP_V33 40mil 3 20 0_0402_5% WP 7 2 A1
DP_V33 TXEC- LVDS_ACLK# [26] WP A1
FBMA-L11-201209-221LMA30T_0805 MIIC_SCL R2102 1 2 MIIC_SCL_R 6 3 A2
SCL A2
10U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z 60mil 13 21 MIIC_SDA R2103 1 2 MIIC_SDA_R 5 4

SWR_VDD TXE2+ LVDS_A2 [26] SDA GND

Power
D 2
L2102 1 +SWR_VDD 18 22 0_0402_5% D
1 1 1

LVDS
PVCC TXE2- LVDS_A2# [26]
FBMA-L11-201209-221LMA30T_0805 CAT24C64WI-GT3_SO8
C2102

C2103

C2101
+SWR_V12 1
L2100 @ 2 +SWR_LX 60mil 12 23
SWR_LX TXE1+ LVDS_A1 [26]
2 2 2
4.7UH_PG031B-4R7MS_1.1A_20% 60mil 11 SWR_VCCK TXE1-
24
LVDS_A1# [26]
27
7 VCCK 25
DP_V12 TXE0+ LVDS_A0 [26]
26
TXE0- LVDS_A0# [26]
+3VS_PS

RTD2132S

2
2
[7] DP0_AUXP_C AUX_P

DP-IN
1 14 R2104

GPIO
[7] DP0_AUXN_C AUX_N GPIO(PWM OUT) TL_INVT_PWM [26]
Close to L27 Close to Pin18 15 4.7K_0402_5%
5 GPIO(Panel_VCC) 16 TL_ENVDD [26]
[7] DP0_TXP0_C 6 LANE0P GPIO(PWM IN) 17 APU_INVT_PWM [9]
+SWR_VDD TL_BKOFF#_R
[7] DP0_TXN0_C

1
LANE0N GPIO(BL_EN) MIIC_SCL
10U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
22U_0603_6.3V6M
C2106

1 1 1 1 1 Reserved for EC programming ROM CSCL 9 LVDS 29

CIICSCL1 MIICSCL1 EDID_CLK [26]

2
CSDA 10 28 @
Need EC confirm CIICSDA1 EDID MIICDA1 EDID_DATA [26]
C2104

C2105

C2107

C2108

Other
R2105
4.7K_0402_5%
2 2 2 2 2 R2171 1 2 1K_0402_1% LVDS_HPD_C 32 31 MIIC_SCL
[7] LVDS_HPD HPD ROM MIICSCL0 30 MIIC_SDA

1
8 MIICSDA0
DP_REXT

1
4 33
DP_GND GND

2
Close to Pin13 R2106
100K_0402_5% R2107 RTD2132S-GR_QFN32_5X5 2132S-Ver E: External ROM, pin31 PU +3VS
12K_0402_1%
Internal RAM support, pin31 PD to GND

1
Close to L29 +1.2VS EEROM EEROM EEROM EEROM
C C
+SWR_V12L2103 1 2 0_0805_5%
Change to 12Kohm 1% (DG ref.)
22U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

20101114
1 1 1 1
A0 R2167 2 1 10K_0402_5%
C2109

C2110

C2111

C2100

A1 R2168 2 1 10K_0402_5%
2 2 2 2
WP R2170 2 1 10K_0402_5%

Close to
Pin27
Close to Pin7
+3VS_PS

EDID_DATA R2108 1 2 4.7K_0402_5%

EDID_CLK R2109 1 2 4.7K_0402_5%

MIIC_SDA R2110 1 2 4.7K_0402_5%

Vendor advise reserve it
CSCL R2158 1 2 4.7K_0402_5%

CSDA R2159 1 2 4.7K_0402_5%

R2100 1 @ 2 0_0402_5%
ENBKL [31]

B B
TL_BKOFF#_R R2160 1 @ 2 0_0402_5%
TL_BKOFF# [26]
C2112 TL_INVT_PWM R2163 1 2 100K_0402_5%
+3VS_PS .1U_0402_16V7K
1 2 TL_ENVDD R2164 1 2 100K_0402_5%

5
TL_BKOFF#_R R2165 1 2 100K_0402_5%
2

P
B 4
1 Y
[26,31] BKOFF# A

G
U2104

3
MC74VHC1G08DFT2G_SC70-5
Vendor Suggest 2011.08.15
SIT, NO.7

+3VS_PS
SIT, NO.7 +3VS

R2177 2 @ 1 10K_0402_5%
2

@Q2107A
@ Q2107A R2178 2 @ 1 10K_0402_5%

CSDA 1 6 EC_SMB_DA2
EC_SMB_DA2 [18,31,32,7]
DMN66D0LDW-7_SOT363-6 CSDA @
TL_DATA [31]
5
@ Q2107B R2117 0_0402_5%

CSCL 4 3 EC_SMB_CK2 CSCL @

A EC_SMB_CK2 [18,31,32,7] TL_CLK [31] A
R2116 0_0402_5%
DMN66D0LDW-7_SOT363-6

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/22 Deciphered Date 2015/11/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL LVDS Translator - RTD2132SRev
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-8127P
Tuesday, March 12, 2013 Sheet 25 of 51
5 4 3 2 1
 1 2 3 4 5

LCD POWER CIRCUIT

LCD/LED PANEL Conn.

+LCDVDD +5VALW +3VS

W=60mils

1
R2111 R2112
150_0603_1% 100K_0402_5% 1
C2114 +LEDVDD
A
4.7U_0805_10V4Z
Place closed to JLVDS1 B+
A

2
2 +3VS 0_0805_5% 1 @ 2 R2113

3
D Q2100
2 1 2
R2114 2
G 220K_0402_1% AP2301GN-HF_SOT23-3
1 1 1
S 2N7002K_SOT23-3 Q2101 C2115 C2116 C2117 @
1
C2118 +LCDVDD +LCDVDD_CONN 0.1U_0402_16V4Z 4.7U_0805_25V6-K 680P_0402_50V7K
W=60mils
3

1
0.1U_0402_16V4Z

1
D Q2102 1 2 2 2 2
TL_ENVDD 2 2 FBMA-L11-201209-221LMA30T_0805
[25] TL_ENVDD
G L2104

C2120

0.1U_0402_16V4Z

C2119

4.7U_0805_25V6-K
S 2N7002K_SOT23-3 (20 MIL) JLCD1
1

1 1 40
3

@ R2115 39 40
100K_0402_5% 38 39
37 38
2 2 R2122 1 @ 2 0_0402_5% 36 37
2

DISPOFF# 35 36
INVPWM 34 35
33 34
32 33
31 32
+3VS_CMOS 31
DMIC_CLK 30
[29] DMIC_CLK 30
DMIC_1_2 29
[29] DMIC_1_2 29
+3VS 28 SIT, NO.4
Logo_LED# 27 28
LOGO RED LIGHT [31,35] Logo_LED# 27
+3VALW R2166 1 2 1.6K_0402_1% 26
USB20_N6 25 26
[14] USB20_N6 25
USB20_P6 24
[14] USB20_P6 24
23
[25] LVDS_ACLK 23
22
[25] LVDS_ACLK# 22
21
B
20 21 B
[25] LVDS_A2 20
19
[25] LVDS_A2# 19
18
+3VS [25] LVDS_A1 18
17
[25] LVDS_A1# 17
16
[25] LVDS_A0 16
15
[25] LVDS_A0# 15
14
14
1

13
@ R2118 12 13
4.7K_0402_5% 11 12
10 11
@ D2101 9 10
2

2 1 8 9
7 8 46
RB751V-40_SOD323-2 6 7 G6 45
EDID_DATA 5 6 G5 44
[25] EDID_DATA 5 G4
EDID_CLK 4 43
[25] EDID_CLK 4 G3
R2161 1 @ 2 0_0402_5% R2119 1 2 0_0402_5% DISPOFF# +3VS 3 42
[25,31] BKOFF# 3 G2
+LCDVDD_CONN 2 41
R2162 1 @ 2 0_0402_5% 1 2 G1
[25] TL_BKOFF# 1
1

STARC_107K40-000001-G2
@ R2120 R2121 CONN@
10K_0402_5% 10K_0402_5% +3VS
2

R2123 1 @ 2 10K_0402_5% INVPWM DISPOFF#

2
C2121 1 2 220P_0402_50V7K INVPWM
@ D2100
C2124 1 2 220P_0402_50V7K DISPOFF# PJSOT24C 3P C/A SOT-23

C2122 1 @ 2 10P_0402_50V8J EDID_CLK

PN:SCA00001G00

1
C C2123 1 @ 2 10P_0402_50V8J EDID_DATA C

+3VS C2145 1 2 22P_0402_50V8J DMIC_CLK

C2144 1 2 22P_0402_50V8J DMIC_1_2 CMOS Camera Conn

1

R2175
4.7K_0402_5% CMOS@
@ Q2103 (20 MIL)
@ D2110 (20 MIL)
2

2 1 3 1 CMOS SUSPEND 2.4mA

+3VS +3VS_CMOS
RB751V-40_SOD323-2
+3VALW AP2301GN-HF_SOT23-3
CMOS@ 1 1 CMOS@

2
R2173 1 2 0_0402_5% INVPWM C2125 C2126
[25] TL_INVT_PWM 0.1U_0402_16V4Z 10U_0603_6.3V6M
1 2 2
C2127
1

@ @ 0.1U_0402_16V4Z
R2174 R2172 CMOS@
10K_0402_5% 10K_0402_5% CMOS@ 2 4.7V
R2125 1 2
[31] CMOS_ON#
150K_0402_5%
2

1
C2128
0.1U_0402_16V4Z
CMOS@
2
D D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/22 Deciphered Date 2015/11/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS CONN/CAMERA
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-8127P
Tuesday, March 12, 2013 Sheet 26 of 51
1 2 3 4 5
 5 4 3 2 1

R2126 1 @ 2 0_0402_5% HDMI_CLK+_CONN

[7] HDMI_CLKP
R2127 1 @ 2 0_0402_5% HDMI_CLK-_CONN
[7] HDMI_CLKN
R2128 1 @ 2 0_0402_5% HDMI_TX0+_CONN
[7] HDMI_TX0P
R2129 1 @ 2 0_0402_5% HDMI_TX0-_CONN
[7] HDMI_TX0N
R2130 1 @ 2 0_0402_5% HDMI_TX1+_CONN
[7] HDMI_TX1P
R2131 1 @ 2 0_0402_5% HDMI_TX1-_CONN
[7] HDMI_TX1N
R2132 1 @ 2 0_0402_5% HDMI_TX2+_CONN
[7] HDMI_TX2P
R2133 1 @ 2 0_0402_5% HDMI_TX2-_CONN
[7] HDMI_TX2N

D D

+3VS

HDMI_CLK+_CONN 1 2
R2134 604_0402_1%
HDMI_CLK-_CONN 1 2
L2105 R2135 604_0402_1%
HDMI_CLKP 1 2 HDMI_CLK+_CONN HDMI_TX0+_CONN 1 2
1 2 R2136 604_0402_1%

2
HDMI_TX0-_CONN 1 2
HDMI_CLKN 4 3 HDMI_CLK-_CONN R2137 604_0402_1%
4 3 HDMI_TX1+_CONN 1 2 1 6 HDMICLK_R
[7] HDMI_CLK
WCM-2012HS-900T_4P R2138 604_0402_1%
HDMI_TX1-_CONN 1 2 2N7002KDWH_SOT363-6
L2106 R2139 604_0402_1% Q2104A
HDMI_TX0P 1 2 HDMI_TX0+_CONN HDMI_TX2+_CONN 1 2
1 2 R2140 604_0402_1%
HDMI_TX2-_CONN 1 2

5
HDMI_TX0N 4 3 HDMI_TX0-_CONN R2141 604_0402_1%
4 3

1
WCM-2012HS-900T_4P 4 3 HDMIDAT_R
[7] HDMI_DATA
D Q2105
L2107 2 2N7002KDWH_SOT363-6
+5VS
HDMI_TX1P 1 2 HDMI_TX1+_CONN G Q2104B
1 2

1
S 2N7002K_SOT23-3
@

3
C HDMI_TX1N 4 3 HDMI_TX1-_CONN R2143 0_0402_5% C
4 3 100K_0402_5% 1 @ 2
WCM-2012HS-900T_4P R2142

2
L2108 1 @ 2 0_0402_5%
HDMI_TX2P 1 2 HDMI_TX2+_CONN R2144
1 2
NEAR CONNECTOR
HDMI_TX2N 4 3 HDMI_TX2-_CONN
4 3
WCM-2012HS-900T_4P

@ R2145

0_0805_5%
ESD Request +5VS_HDMI_F 1
3

D2105 2
+5VS
HDMI_CLK-_CONN 1 1 10 9 HDMI_CLK-_CONN

2
RB491D-YS_SOT23-3
HDMI_CLK+_CONN 2 2 9 8 HDMI_CLK+_CONN D2104
F2100
HDMI_TX1-_CONN 4 4 7 7 HDMI_TX1-_CONN 1.1A_6V_SMD1812P110TF

1
HDMI_TX1+_CONN 5 5 6 6 HDMI_TX1+_CONN +5VS_HDMI

3 3 1 C2129
0.1U_0402_16V4Z

2
8
B B
R2146 R2147 2
YSCLAMP0524P_SLP2510P8-10-9 2K_0402_5% 2K_0402_5%
+3VS

1
D2102

1
HDMI_TX0-_CONN 1 1 10 9 HDMI_TX0-_CONN C R2148 JHDMI1
Q2106 2 1 2 HDMI_HPD HDMI_HPD 19
2 2 HP_DET
HDMI_TX0+_CONN 9 8 HDMI_TX0+_CONN MMBT3904_NL_SOT23-3 B 150K_0402_5% 18
+5V
E 17
3

DDC/CEC_GND

2
HDMI_TX2-_CONN 4 4 7 7 HDMI_TX2-_CONN HDMIDAT_R 16
[7] HDMI_DET SDA
@ HDMICLK_R 15
SCL
1

HDMI_TX2+_CONN 5 5 6 6 HDMI_TX2+_CONN R2149 14

200K_0402_5% 13 Reserved
3 3 R2150 HDMI_CLK-_CONN 12 CEC 20

1
100K_0402_5% 11 CK- GND 21
8 HDMI_CLK+_CONN 10 CK_shield GND 22
2

HDMI_TX0-_CONN 9 CK+ GND 23

8 D0- GND
YSCLAMP0524P_SLP2510P8-10-9 HDMI_TX0+_CONN 7 D0_shield
HDMI_TX1-_CONN 6 D0+
5 D1-
HDMI_TX1+_CONN 4 D1_shield
HDMI_TX2-_CONN 3 D1+
D2103 2 D2-
1 1 D2_shield
HDMI_HPD 10 9 HDMI_HPD HDMI_TX2+_CONN 1
D2+
HDMICLK_R 2 2 9 8 HDMICLK_R SUYIN_100042GR019M23DZL
CONN@
HDMIDAT_R 4 4 7 7 HDMIDAT_R
A A
+5VS_HDMI 5 5 6 6 +5VS_HDMI

3 3

YSCLAMP0524P_SLP2510P8-10-9 Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/22 Deciphered Date 2015/11/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL HDMI Connector
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-8127P
Tuesday, March 12, 2013 Sheet 27 of 51
5 4 3 2 1
 A B C D E

FCM1608CF-121T03_2P
1 DAC_RED 1 2 RED 1
[13] DAC_RED
L2109
FCM1608CF-121T03_2P
DAC_GRN 1 2 GREEN
[13] DAC_GRN
L2110

[13] DAC_BLU
DAC_BLU
FCM1608CF-121T03_2P
1
L2111
2 BLUE ESD Request
1

1
1 1 1 1 1 1 D2107
BLUE 6 3 RED
R2151 R2152 R2153 C2130 C2131 C2132 C2133 C2134 C2135 I/O4 I/O2
150_0402_1% 150_0402_1% 150_0402_1% 10P_0402_50V8J 10P_0402_50V8J +R_CRT_VCC
2 2 2 2 2 2
2

2
5 2
10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J10P_0402_50V8J VDD GND
CLOSE TO CONN
4 1 GREEN
I/O3 I/O1
AZC099-04S.R7G_SOT23-6

+CRT_VCC D2108
R2154
CRT_DDC_DATA 6 3 JVGA_HS
1 2 I/O4 I/O2
+R_CRT_VCC
1
C2136 1K_0402_5% 5 2
VDD GND
0.1U_0402_16V4Z
2 2 2
5

U2102
CRT_DDC_CLK 4 1 JVGA_VS
OE#
P

2 4 CRT_HSYNC_1 1 2 JVGA_HS I/O3 I/O1

[13] CRT_HSYNC A Y L2112 AZC099-04S.R7G_SOT23-6
G

FCM1608CF-121T03_2P
74AHCT1G125GW _SOT353-5 1
3

@
C2137
10P_0402_50V8J
+CRT_VCC 2
R2155
1 2
1
C2138 1K_0402_5%
0.1U_0402_16V4Z
2
CRT Connector
5

U2103
OE#
P

2 4 CRT_VSYNC_1 1 2 JVGA_VS
[13] CRT_VSYNC A Y L2113
G

FCM1608CF-121T03_2P 1
74AHCT1G125GW _SOT353-5 @
3

C2139 +5VS +R_CRT_VCC +CRT_VCC

10P_0402_50V8J D2106
2 2 F2101
1 1 2
3 1
3 3
+R_CRT_VCC RB491D-YS_SOT23-3 1.1A_6V_SMD1812P110TF C2140
W=40mils 2
0.1U_0402_16V4Z
1

R2156 R2157
4.7K_0402_5% 4.7K_0402_5%
JCRT1
2

6
R2179 1 2 0_0402_5% 11
RED 1
R2180 1 2 0_0402_5% 7
[13] CRT_DDC_DATA CRT_DDC_DATA CRT_DDC_DATA 12
R2181 1 2 0_0402_5% GREEN 2
8
R2182 1 2 0_0402_5% JVGA_HS 13
BLUE 3
9
JVGA_VS 14 16
4 17
[13] CRT_DDC_CLK CRT_DDC_CLK 10
CRT_DDC_CLK 15
1 1 5
@ @ 1
C2141 C2142 C2143 C-H_13-12201558CP
100P_0402_50V8J 68P_0402_50V8J CONN@
2 2 100P_0402_50V8J
4 2 4

AMD check list update

20101110
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/11/22 Deciphered Date 2015/11/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
CRT Connector Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-8127P
Tuesday, March 12, 2013 Sheet 28 of 51
A B C D E
 1 2 3 4 5

CX20671
High Definition Audio Codec SoC
+3VS
EMI
FILT_1.65_R C1135 1 2 1U_0402_6.3V6K
With Integrated Class-D Stereo C1102 @1
@ 2 0.1U_0402_16V4Z
C1136 1 2 0.1U_0402_16V4Z
Amplifier. C1103 @1
@ 2 0.1U_0402_16V4Z
An integrated 5 V to 3.3 V Low-dropout Near Pin 29
Layout Note:Path from +5VS to Pin12, C1104 @1
@ 2 0.1U_0402_16V4Z

1
voltage regulator (LDO). Pin15 must be very low C1121 @ C1119
0.1U_0402_16V4Z 4.7U_0603_6.3V6K
resistance (<0.01 ohms) +LDO_OUT_3.3V C1133 1 2 4.7U_0603_6.3V6K
An integrated 3.3 V to 1.8V Low-dropout

2
R1102 1 @ 2 0_0402_5%
voltage regulator (LDO). D1102
To support Wake-on-Jack or Wake-on-Ring, the CODEC Near Pin 2 C1134 1 2 0.1U_0402_16V4Z
R1104 1 @ 2 0_0402_5%
VAUX_3.3 & VDD_IO pins must be powerd by a rail that
2 1 is not removed unless AC power is removed. Near Pin 27
A PC Beep RB751V-40_SOD323-2
*DSH page42 has more detail. R1105 1 @ 2 0_0402_5% A

1
C1111 1 @ 2 0.1U_0402_16V4Z C1116 @ C1114 +5VS
EC Beep [31] BEEP#
0.1U_0402_16V4Z 1U_0402_6.3V6K
GND

2
GND GNDA

1
Near Pin 7 C1113 @ C1112
C1141 1 @ 2 0.1U_0402_16V4Z R1120 1 2 33_0402_5% PC_BEEP_C 1 2 PC_BEEP
ICH Beep [14] FCH_SPKR 0.1U_0402_16V4Z 4.7U_0603_6.3V6K

2
0.1U_0402_16V4Z FILT_1.8_R Near Pin 28
D1101 C1142
2 1

1
RB751V-40_SOD323-2 C1132 C1130 +3VS
0.1U_0402_16V4Z 4.7U_0603_6.3V6K

2
1

1
R1121 Near Pin 3
10K_0402_5% C1124 @ C1129
4.7U_0603_6.3V6K 0.1U_0402_16V4Z

2
2
Sense resistors must be
Near Pin 26 connected same power
10K only needed if supply to VAUX_3.3

18

29

27
28
26
that is used for

3
7
2
is removed during system re-start. U1101
VAUX_3.3

AVDD_5V
AVDD_HP
FILT_1.8
VDD_IO
VAUX_3.3
DVDD_3.3

FILT_1.65

AVDD_3.3
Near Pin 17
12
R1112 1 @ 2 4.7K_0402_5% LPWR_5.0 15 +CLASSD_5V 1
R1137 2 0_0805_5%
Combo Jack detect (normal close) +3VS
[14] HDA_RST_AUDIO#
HDA_RST#_AUDIO 9
RESET#
RPWR_5.0
CLASS-D_REF
17 C1107 1 2 0.1U_0402_16V4Z
+5VS

MIC_JD HDA_BITCLK_AUDIO 5 R1113 1 2 5.11K_0402_1% +3VS Port B

[14] HDA_BITCLK_AUDIO BIT_CLK
HDA_SYNC_AUDIO 8 36 SENSE_A R1114 1 2 20K_0402_1% MIC_JD Port A
R1115 1 2 33_0402_5% 6 SYNC SENSE_A R1116 1 2 39.2K_0402_1% PLUG_IN
[14] HDA_SDIN0 SDATA_IN
Q1103 HDA_SDOUT_AUDIO 4 External MIC
[14] HDA_SDOUT_AUDIO SDATA_OUT
1

B D LBSS138LT1G_SOT-23-3 35 PORTC_R C1108 1 2 2.2U_0603_6.3V6K R1133 1 2 100_0402_1% EXT_MIC B

PORTB_R EXT_MIC [35]
2 R1130 1 2 33K_0402_5% EXT_MIC 34 PORTC_L
PORTB_L 33
G 1 EAPD active low 10 B_BIAS +MICBIASB
S C1146 PC_BEEP
0=power down ex AMP
3

1U_0402_6.3V6K PC_BEEP +MICBIASB

1=power up ex AMP 32
PLUG_IN 2 C_BIAS 31 EXT_MIC R1132 1 2 2K_0402_5% R1128 1 2 4.7K_0402_5%
[35] PLUG_IN PORTC_R 30
R1111 1 2 0_0402_5% CX_GPIO0 38 PORTC_L
[31] EAPD GPIO0/EAPD#
R1131 1 @ 2 0_0402_5% 37
[31] EC_MUTE# GPIO1/SPK_MUTE#
CX_GPIO0 R1129 1 @ 2 33K_0402_5% 23 HP_OUTR_R R1117 1 2 39_0402_5% HP_OUTR Headphone
PORTA_R HP_OUTR [35]
1 22 HP_OUTL_R R1118 1 2 39_0402_5% HP_OUTL
PORTA_L HP_OUTL [35]
C1147
1U_0402_6.3V6K R1138 1 2 DMIC_CLK_R 40
[26] DMIC_CLK DMIC_CLK
@ Internal DMIC FBMA-10-100505-301T_2P 1 24
2 R1139 1 2 0_0402_5% DMIC_1_2_R DMIC_1/2 NC 25
[26] DMIC_1_2 NC Changed from 5.1ohm to 15ohm
39
SPK_L2+ 11 NC for "zi zi"noise.
SPK_L1- 13 LEFT+
LEFT- 21 AVEE C1122 1 2 0.1U_0402_16V4Z
AVEE 19 FLY_P
+5VS Internal SPEAKER FLY_P Near Pin 21
SPK_R2+ 16 20 FLY_N C1110 1 2 1U_0603_10V4Z C1125 1 2 4.7U_0603_6.3V6K
SPK_R1- 14 RIGHT+ FLY_N
@ RIGHT-
Rdc < 0.05 ohms

GND
2
G

Q1104 Rated Current > 2A

BSS138_NL_SOT23-3
3 1 HDA_SYNC_AUDIO
potential leakage concern CX20671-21Z_QFN40_6X6
[14] HDA_SYNC_AUDIO

41
S

1 2
R1136 0_0402_5%

C C

Width 20 mil
Internal Speaker
Decoupling CAP JSPK1
SPK_R1- L1102 1 2 0_0603_5% SPK_R1-_CONN 1
SPK_R2+ L1103 1 2 0_0603_5% SPK_R2+_CONN 2 1
SPK_L1- L1104 1 2 0_0603_5% SPK_L1-_CONN 3 2
SPK_L2+ L1105 1 2 0_0603_5% SPK_L2+_CONN 4 3
SPK_RT_Detect# R1140 1 2 0_0402_5% SPK_RT_Detect#_R 5 4
[31] SPK_RT_Detect# 5
6
6
7
8 GND
@ @ @ @ GND

C1137

C1138

C1139

C1140
1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K
E-T_4070K-G06N-00L
+CLASSD_5V C1115 1 2 0.1U_0402_16V4Z 1 1 1 1 CONN@
Near Pin 12
C1117 1 2 10U_0603_6.3V6M

C1118 1 2 0.1U_0402_16V4Z
EMI 2 2 2 2
Near Pin 15
C1120 1 2 10U_0603_6.3V6M
@

Note.
D EMI QALEA 14" => JSPK1 => 4Pin
QALEB 15" => JSPK1 => 6Pin
D

HDA_RST#_AUDIO C1123 @1
@ 2 22P_0402_50V8J

HDA_SYNC_AUDIO C1126 @1
@ 2 22P_0402_50V8J

HDA_SDOUT_AUDIO C1128 @1
@ 2 22P_0402_50V8J

HDA_BITCLK_AUDIO R1123 1 @ 2 33_0402_5% HDA_BITCLK_AUDIO_R C1131 @1

@ 2 22P_0402_50V8J
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/11/22 Deciphered Date 2015/11/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD Audio Codec CX20671
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-8127P
Tuesday, March 12, 2013 Sheet 29 of 51
1 2 3 4 5
 A B C D E F G H

SATA HDD Conn.

JHDD1

1
SATA_FTX_DRX_P0 2 GND
[13] SATA_FTX_DRX_P0 A+
SATA_FTX_DRX_N0 3
[13] SATA_FTX_DRX_N0 A-
4
C2401 1 2 0.01U_0402_16V7K SATA_FRX_DTX_N0 5 GND
[13] SATA_FRX_C_DTX_N0 C2402 1 2 0.01U_0402_16V7K SATA_FRX_DTX_P0 6 B-
[13] SATA_FRX_C_DTX_P0 7 B+
+3VS GND
1 1
8 +5VS +5VS_HDD
9 V33
10 V33 @ J2401
11 V33 1 2
12 GND 1 2
[31] HDD_DETECT# 13 GND JUMP_43X79
+5VS_HDD 14 GND
15 V5
16 V5
17 V5
18 GND
19 Reserved 23
+5VS_HDD 20 GND GND 24
21 V12 GND
22 V12
@ @ V12

C2405

1000P_0402_50V7K

C2471

1U_0603_10V4Z

C2406

10U_0603_6.3V6M
1 1 1 SANTA_198202-1
CONN@

2 2 2

2 2
ODD Power Control
SATA ODD Conn. 1
@ J4
2
1 2
+5VS JUMP_43X79 +5VS_ODD

AP2301GN-HF_SOT23-3

3 1
JODD2 Q2411

1
SATA_FTX_DRX_P1 SATA_FTX_DRX_P1 1 1 1
[13] SATA_FTX_DRX_P1 1
SATA_FTX_DRX_N1 SATA_FTX_DRX_N1 2 R2438 C2486
[13] SATA_FTX_DRX_N1 2
3 10K_0402_5% 0.01U_0402_16V7K C2501

2
SATA_FRX_C_DTX_N1 C2408 1 2 0.01U_0402_16V7K SATA_FRX_DTX_N1 SATA_FRX_DTX_N1 4 3 10U_0805_10V4Z
[13] SATA_FRX_C_DTX_N1 SATA_FRX_C_DTX_P1 C2409 1 2 0.01U_0402_16V7K SATA_FRX_DTX_P1 SATA_FRX_DTX_P1 5 4 2 2

2
[13] SATA_FRX_C_DTX_P1 6 5
R2406 1 @ 2 0_0402_5% ODD_DETECT#_R 7 6
[14] ODD_DETECT# +5VS_ODD 8 7 R2440
R2401 1 @ 2 0_0402_5% ODD_DETECT#_R 9 8 1 2 C2413 1 2 0.01U_0402_16V7K
+5VS_ODD ODD_DA#_R 10 9
+5VS_ODD 10

1
11
R2437 1 @ 2 0_0402_5% ODD_DA#_R 12 GND 100K_0402_5%

OUT
[14] ODD_DA#_FCH GND
ACES_88514-104N
CONN@
Q2410
2 DDTC124EKA-7-F_SC59-3
[13] ODD_EN IN

Note.

GND
3 3
QALEA 14" => JODD1
QALEB 15" => JODD2

3
APS G-Sensor +3VS
1

R2402 3 1Q2402
100K_0402_5% AP2301GN-HF_SOT23-3

1
1 1
U2406 @ @ R2409
2

R2411 C2421 C2419 @ 0_0603_5%

2
2 12 VOUTX R2403 1 2 56K_0402_5% 150K_0402_5% 0.01U_0402_16V7K 0.1U_0402_16V4Z
[31] GS_SELFTEST ST Xout 10 GS_VOUTX [31] 2 2
VOUTY R2404 1 2 56K_0402_5%
GS_VOUTY [31]

2
Yout

2
+3VS +3VS_GS 8 R2410
Zout GS_ON# 1 2
[31] GS_ON# +3VS_GS
R2405 1 @ 2 0_0603_5% 14 150K_0402_5%
Vs
C2411

.1U_0402_16V7K

C2418

.1U_0402_16V7K

C2412

.1U_0402_16V7K

C2416

.1U_0402_16V7K

15
Vs
10U_0603_6.3V6M

C2417

C2410

.1U_0402_16V7K

1 1 1 1 1 1
1 1 1 C2487
NC 4 C2420 10U_0603_6.3V6M
3 NC 9 0.01U_0402_16V7K @
5 COM NC 11 2 2 2 2 2 2
2 2 6 COM NC 13
7 COM NC 16
4 COM NC 4
APS_GND
LIS34ALTR LGA 16P G-SENSOR
APS_GND @ J2402
1 2
Note.
Main Source => C2417 use 10U (SE000005T80) 2MM
2nd Source => C2417 use 10K (SD013100280) APS_GND
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/11/22 Deciphered Date 2015/11/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
HDD/ODD/G-Sensor Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-8127P
Tuesday, March 12, 2013 Sheet 30 of 51
A B C D E F G H
 1 2 3 4 5

+3VALW_EC +3VLP +EC_AVCC J2200

Logo_LED#
Vcc 3.3V +/- 5%
Logo_LED# [26,35]
+3VLP 1 2 +3VALW_EC
1 2 R2207 100K +/- 5%
L2200 1 @ 2 0_0603_5% @ JUMP_43X39 Board ID
+3VALW_EC +EC_AVCC R2209 VAD_BID min V AD_BID typ VAD_BID max
J2201

C2203

0.1U_0402_16V4Z

C2204

0.1U_0402_16V4Z

C2205

0.1U_0402_16V4Z

C2206

0.1U_0402_16V4Z

C2207

1000P_0402_50V7K

C2208

1000P_0402_50V7K
C2201
1 1
C2202 +3VALW 1 2 +3VALW_EC
0 0K +/- 5% 0 V 0 V 0 V SVT
1 1 1 1 1 1 1 2

1
0.1U_0402_16V4Z 1000P_0402_50V7K
@ JUMP_43X39 D Q2201
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V SDV2
2 2 2 2N7002K_SOT23-3
L2201 1 @ 2 0_0603_5% ECAGND 2 2 2 2 2 2 G
2 18K +/- 5% 0.436 V 0.503 V 0.538 V FVT
S 3 33K +/- 5% 0.712 V 0.819 V 0.875 V SIT

3
111
125
4 56K +/- 5% 1.036 V 1.185 V 1.264 V SDV

22
33
96

67
9
U2200
A A

EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC

EC_VDD/VCC

EC_VDD/AVCC
EC_VDD0
+3VALW

HDD_DETECT# R2232 1 2 100K_0402_5%

GATEA20 1 21
[14] GATEA20 GATEA20/GPIO00 GPIO0F
KB_RST# 2 23 BEEP# BM# R2230 1 @ 2 100K_0402_5%
[14] KB_RST# KBRST#/GPIO01 BEEP#/GPIO10 BEEP# [29]
SERIRQ 3 26 WLAN_WAKE#
[12] SERIRQ SERIRQ GPIO12 WLAN_WAKE# [33]
LPC_FRAME# 4 27 ACOFF EC_MUTE# R2202 1 2 100K_0402_5%
[12,33,35] LPC_FRAME# LPC_FRAME# ACOFF/GPIO13 ACOFF [39]
LPC_AD3 5
[12,33,35] LPC_AD3 LPC_AD3
LPC_AD2 7 PWM Output
[12,33,35] LPC_AD2 LPC_AD2
LPC_AD1 8 63 BATT_TEMP +3VALW_EC
[12,33,35] LPC_AD1 LPC_AD1 BATT_TEMP/GPIO38 BATT_TEMP [38]
LPC_AD0 10 LPC & MISC 64 GS_VOUTX
[12,33,35] LPC_AD0 LPC_AD0 GPIO39 GS_VOUTX [30]
C2209 @1 2 22P_0402_50V8J R2204 1 @ 2 10_0402_5% 65 ADP_I BEEP# R2205 1 @ 2 10K_0402_5%
ADP_I/GPIO3A ADP_I [38,39]
12 AD Input 66 GS_VOUTY
[12,16] CLK_PCI_EC CLK_PCI_EC GPIO3B GS_VOUTY [30]
13 75 BRDID LID_SW# R2206 1 2 100K_0402_5%
[12,31,35] PLT_RST# PCIRST#/GPIO05 GPIO42
R2203 1 2 330K_0402_5% EC_RST# 37 76 APU_IMON
+3VALW_EC EC_RST# IMON/GPIO43 APU_IMON [45]
EC_SCI# 20 +3VALW
[14] EC_SCI# EC_SCII#/GPIO0E
1 ADP_PROTECT 38
[38] ADP_PROTECT GPIO1D 68 AOU_CTL2
DAC_BRIG/GPIO3C AOU_CTL2 [35]

1
C2210 70 FCH_PWR_EN EAPD_R R2223 1 @ 2 0_0402_5%
EN_DFAN1/GPIO3D FCH_PWR_EN [36] EAPD [29]
0.1U_0402_16V4Z DA Output 71 AOU_CTL3 TL_CLK R2224 1 @ 2 0_0402_5% R2207
2 IREF/GPIO3E AOU_CTL3 [35]
KSI0 55 72 SPK_RT_Detect# 100K_0402_1%
KSI0/GPIO30 CHGVADJ/GPIO3F SPK_RT_Detect# [29]
KSI1 56
KSI2 57 KSI1/GPIO31 +5VALW

2
KSI3 58 KSI2/GPIO32 83 EC_MUTE# BRDID
KSI3/GPIO33 EC_MUTE#/GPIO4A EC_MUTE# [29]
KSI4 59 84 USB_ON# USB_ON# R2208 1 @ 2 10K_0402_5%
KSI4/GPIO34 USB_EN#/GPIO4B USB_ON# [34]

1
KSI5 60 85 TL_CLK
KSI5/GPIO35 CAP_INT#/GPIO4C TL_CLK [25]
KSI6 61 PS2 Interface 86 TL_DATA R2209
KSI6/GPIO36 EAPD/GPIO4D TL_DATA [25] +5VS
KSI7 62 87 TP_CLK 0_0402_5%
KSI7/GPIO37 TP_CLK/GPIO4E TP_CLK [33]
KSO0 39 88 TP_DATA
KSO[0..17] KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA [33]
KSO1 40 TP_CLK R2210 1 2 4.7K_0402_5%
[33] KSO[0..17]

2
KSO2 41 KSO1/GPIO21
KSI[0..7] KSO3 42 KSO2/GPIO22 97 VGATE TP_DATA R2211 1 2 4.7K_0402_5%
[33] KSI[0..7] KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 VGATE [14,45]
KSO4 43 98
KSO4/GPIO24 WOL_EN/GPXIOA01 VGA_AC_DET [18,44]
KSO5 44 99 APU_ALERT#_EC BATT_TEMP C2211 1 2 100P_0402_50V8J
B
KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 9012_PH1
APU_ALERT#_EC [7] B
+3VALW KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 9012_PH1 [38]
ACIN C2212 1 2 100P_0402_50V8J
KSO7/GPIO27 SPI Device Interface
KSO8 47
48 KSO8/GPIO28 119
KSO9
KSO9/GPIO29 SPIDI/GPIO5B
EAPD_R SDV/FVT, NO.13
KSO10 49 120
R2212 1 @ 2 47K_0402_5% KSO1 KSO11 50 KSO10/GPIO2A SPIDO/GPIO5C 126
KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58
KSO12 51 128 BM#
KSO12/GPIO2C SPICS#/GPIO5A BM# [40]
R2213 1 @ 2 47K_0402_5% KSO2 KSO13 52
53 KSO13/GPIO2D R2233 1 2 100K_0402_5%
KSO14
KSO14/GPIO2E
SDV/FVT, NO.13 ENBKL @
R2214 1 2 2.2K_0402_5% EC_SMB_CK1 KSO15 54 73 ENBKL +3VALW
KSO15/GPIO2F ENBKL/GPIO40 ENBKL [25]
KSO16 81 74 ADP_ID VR_ON R2234 1 @ 2 100K_0402_5%
KSO16/GPIO48 PECI_KB930/GPIO41 ADP_ID [37]
R2215 1 2 2.2K_0402_5% EC_SMB_DA1 KSO17 82 89
KSO17/GPIO49 FSTCHG/GPIO50

2
90 AOU_EN
BATT_CHG_LED#/GPIO52 AOU_EN [35]
91 AOAC_WLAN R2216
CAPS_LED#/GPIO53 AOAC_WLAN [33]
+3VS EC_SMB_CK1 77 GPIO 92 HDD_DETECT# 10K_0402_5%
[38,39] EC_SMB_CK1 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54 HDD_DETECT# [30]
EC_SMB_DA1 78 93 CP_RESET#
[38,39] EC_SMB_DA1 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 CP_RESET# [33]
EC_SMB_CK2 79 SM Bus 95 SYSON
[18,25,32,7] EC_SMB_CK2 SYSON [41,43]

1
R2236 1 @ 2 100K_0402_5% SPK_RT_Detect# EC_SMB_DA2 80 EC_SMB_CK2/GPIO46 SYSON/GPIO56 121 VR_ON
[18,25,32,7] EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 VR_ON [42,45]
127 VSB_ON
PM_SLP_S4#/GPIO59 VSB_ON [38]
R2235 1 @ 2 10K_0402_5% H_PROCHOT#_EC
R2219 1 @ 2 0_0402_5% EC_PME#
PM_SLP_S3# 6 100 EC_RSMRST# [35] LAN_WAKE#
[14] PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 EC_RSMRST# [14]
PM_SLP_S5# 14 101 EC_LID_OUT#
[14] PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 EC_LID_OUT# [14]
EC_SMI# 15 102 Turbo_V
[14] EC_SMI# EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 Turbo_V [38]
CMOS_ON# 16 103 H_PROCHOT#_EC
[26] CMOS_ON# GPIO0A H_PROCHOT#_EC/GPXIOA06 H_PROCHOT#_EC [38,7]
TP_RESET 17 104 MAINPWON_R
[33] TP_RESET GPIO0B VCOUT0_PH/GPXIOA07
GS_ON# 18 GPO 105 BKOFF# MAINPWON_R R2228 1 @ 2 0_0402_5%
[30] GS_ON# GPIO0C BKOFF#/GPXIOA08 BKOFF# [25,26] MAINPWON [38,40]
WL_OFF_EC# 19 GPIO 106 PBTN_OUT#
[33] WL_OFF_EC# GPIO0D PBTN_OUT#/GPXIOA09 PBTN_OUT# [14]
25 107
EC_TACH 28 EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 108 EC_PXCONTROL
[32] EC_TACH FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11 EC_PXCONTROL [14]
@ EC_PME# 29
D2200 EC_TX_P80_DATA 30 EC_PME#/GPIO15
[33,35] EC_TX_P80_DATA EC_TX/GPIO16
RB751V-40_SOD323-2 EC_RX_P80_CLK 31 110 ACIN
[33,35] EC_RX_P80_CLK EC_RX/GPIO17 AC_IN/GPXIOD01 ACIN [35,39]
2 1 FCH_PWROK 32 112 EC_ON
[14] FCH_POK PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON [35,40]
C EC_FAN_PWM 34 114 ON/OFF C
[32] EC_FAN_PWM SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 ON/OFF [35]
2 1 2 1 GS_SELFTEST 36 GPI 115 LID_SW#
+3VS [30] GS_SELFTEST NUM_LED#/GPIO1A LID_SW#/GPXIOD04 LID_SW# [35]
R2220 R2221 116 SUSP#
SUSP#/GPXIOD05 SUSP# [36,42,44]
+3VALW 10K_0402_5% 0_0402_5% 117
@ GPXIOD06 118
PECI_KB9012/GPXIOD07
AGND/AGND
XCLKI 122
R2217 1 2 2.2K_0402_5% EC_SMB_CK2 R2200 1 @ 2 0_0402_5% XCLKO 123 XCLKI/GPIO5D 124 +V18R
GND/GND
GND/GND
GND/GND
GND/GND

[12,16] RTC_CLK XCLKO/GPIO5E V18R

GND0

R2218 1 2 2.2K_0402_5% EC_SMB_DA2

2

C2220 1 @ 2 100P_0402_50V8J EC_SMB_CK2 KB9012QF-A4_LQFP128_14X14 1

11
24
35
94
113

69

R2225 C2215 C2216

C2219 1 @ 2 100P_0402_50V8J EC_SMB_DA2 100K_0402_5% 20P_0402_50V8 2.2U_0805_10V6K
2

ECAGND

+3VS 2
1

R2227 1 @ 2 2.2K_0402_5% EC_SMB_CK2 POP for susclk implemented

20100810
R2226 1 @ 2 2.2K_0402_5% EC_SMB_DA2 +3VS Security ROM

1
R2222
10K_0402_5% +3VS
@
XCLKI U2201

2
1 8 1
R2231 1 @ 2 10M_0402_5% XCLKO 2 NC VCC 7 ROM_WP C2200
PLT_RST# 3 NC WP 6 0.1U_0402_16V4Z
[12,31,35] PLT_RST# FCH_SCLK0 [10,11,14,33]
@ 4 PROT# SCL 5 FCH_SDATA0 [10,11,14,33]
Y2200 GND SDA 2
1 2 PCA24S08D_SO8
EEPROM SA00004MK00
D 32.768KHZ_12.5PF_CM31532768DZFT D

@ 1 1@
C2217 C2218
18P_0402_50V8J 18P_0402_50V8J
2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/22 Deciphered Date 2015/11/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
EC ENE-KB9012 Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-8127P
Tuesday, March 12, 2013 Sheet 31 of 51
1 2 3 4 5
 5 4 3 2 1

Fintek Thermal sensor

Close U2402
REMOTE1+
Placed near by APU_CORE +3VS REMOTE1+
Close to DDR
1 1

1
@ C

1
C2439 C2440 2 Q2406
2200P_0402_50V7K +3VS R2434 100P_0402_50V8J B MMST3904-7-F_SOT323-3
2 REMOTE1- 2 E
10K_0402_5%

3
@ REMOTE1-
D U2402 D

2
REMOTE2+ 1 10 EC_SMB_CK2 [18,25,31,7]
VCC SCL
@
1
REMOTE1+ 2 9 EC_SMB_DA2 [18,25,31,7]
Under VRAM
C2441 DP1 SDA REMOTE2+
2
2200P_0402_50V7K REMOTE1- 3 8 1
DN1 ALERT#

1
2 REMOTE2- C2443 @ C
0.1U_0402_16V4Z REMOTE2+ 4 7 C2442 2 Q2407 DIS@
1 DP2 THERM# 100P_0402_50V8J B MMST3904-7-F_SOT323-3
REMOTE2- 5 6 2 E

3
DN2 GND REMOTE2-

F75303M_MSOP10
REMOTE1,2+/-:
Address 1001_101xb
Trace width/space:10/10 mil
Trace length:<8"

C C

SIT, NO.6
BT Connector FAN1 Conn
+3VS

1
+5VS

R2467 @ R2468
10K_0402_5% 10K_0402_5%

2
+3VS +3VAUX_BT C2499 1 2 1U_0603_10V4Z
B Q30 B
AP2301GN-HF_SOT23-3

3 1
40mil JFAN1
C468

C469

1
2 1
[31] EC_TACH 2
1

3
[31] EC_FAN_PW M
2

@ 4 3
1 1 4
R500 5
SDV2, NO.78 470_0402_5% 6 G5
G6
2

2 2 ACES_50273-00401-001
0.1U_0402_16V4Z

10U_0805_10V4Z

CONN@
1

@
R475 D Q42
[13] BT_ON# 1 2 2
G
220K_0402_5% S 2N7002K_SOT23-3
3

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/22 Deciphered Date 2015/11/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
Thermal/FAN/BT Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-8127P
Tuesday, March 12, 2013 Sheet 32 of 51
5 4 3 2 1
 Mini Card Power Rating
WLAN Conn Power Primary Power (mA) Auxiliary Power (mA)
+3VS +3VS_WLAN +1.5VS
Peak Normal Normal
+3VS 1000 750
+3V 330 250 250 (wake enable)

1
@ J2403
AOAC function +VSB +3VALW +3VS_WLAN
+1.5VS 500 375 5 (Not wake enable)

1
JUMP_43X79

2
R2494 1 @ 2 0_0805_5%

1
2
JMINI1 R2493

D
WLAN_WAKE# 1 2 470K_0402_5% 6

S
[31] WLAN_WAKE# 1 2
3 4 @ 1 5 4
R2484 1 2 0_0402_5% 5 3 4 6 C2494 2
[13,33] WLBT_OFF#

2
WLAN_CLKREQ# 7 5 6 8 LPC_FRAME#_R 1U_0402_6.3V6K 1 Q2400
[14] WLAN_CLKREQ# 9 7 8 10 LPC_AD3_R R2495 1 @ 2 0_0402_5% @ SI3456DDV-T1-GE3_TSOP6

G
9 10 WL_OFF# [13] 2
CLK_PCIE_WLAN# 11 12 LPC_AD2_R RF_OFF# R2496 1 2 0_0402_5% @
[12] CLK_PCIE_WLAN# WL_OFF_EC# [31]

3
CLK_PCIE_WLAN 13 11 12 14 LPC_AD1_R R2491
[12] CLK_PCIE_WLAN 15 13 14 16 1 2
LPC_AD0_R WLAN_EN
15 16 0_0402_5%

1
PCI_RST#_R 17 18 @
17 18

1
CLK_PCI_DB 19 20 RF_OFF# D 1
21 19 20 22 APU_PCIE_RST# 2
21 22 APU_PCIE_RST# [12,17,35] [31] AOAC_WLAN
R2489 1 @ 2 0_0402_5% PCIE_CRX_C_DTX_N1 23 24 G R2492 C2493
[5] PCIE_CRX_DTX_N1 23 24
R2490 1 @ 2 0_0402_5% PCIE_CRX_C_DTX_P1 25 26 Q2403 S 1.5M_0402_5% .1U_0603_25V7K
[5] PCIE_CRX_DTX_P1 27 25 26 28 2
2N7002K_SOT23-3 @ @

2
29 27 28 30 FCH_SCLK0 @
29 30 FCH_SCLK0 [10,11,14,31]
PCIE_CTX_DRX_N1 31 32 FCH_SDATA0
[5] PCIE_CTX_DRX_N1 33 31 32 34 FCH_SDATA0 [10,11,14,31]
PCIE_CTX_DRX_P1
[5] PCIE_CTX_DRX_P1 33 34
35 36 USB20_N5
37 35 36 38 USB20_N5 [14]
USB20_P5
37 38 USB20_P5 [14]
39 40
41 39 40 42
+3VS_WLAN 41 42
43 44
45 43 44 46
R2432 47 45 46 48 Reserve for SW mini-pcie debug card. For AOAC assessment
EC_TX_P80_DATA 1 2 100_0402_1% 49 47 48 50
[31,35] EC_TX_P80_DATA
EC_RX_P80_CLK 1 2 100_0402_1% 51 49 50 52 Series resistors closed to KBC side. +3VS_WLAN path:
[31,35] EC_RX_P80_CLK 51 52
R2433
1K_0402_5% 1 2 R2461 53 54 LPC_FRAME#_R R2477 1 2 0_0402_5% LPC_FRAME# 1. +3VS (default)
[13,33] WLBT_OFF# GND1 GND2 LPC_FRAME# [12,31,35]
LPC_AD3_R R2478 1 2 0_0402_5% LPC_AD3
LPC_AD3 [12,31,35]
2. +3VALW
LPC_AD2_R R2474 1 2 0_0402_5% LPC_AD2 3. +3VALW + Switch
LPC_AD2 [12,31,35]
For EC to detect LPC_AD1_R R2475 1 2 0_0402_5% LPC_AD1
LPC_AD1 [12,31,35]
1 BELLW_80003-7021 LPC_AD0_R R2476 1 2 0_0402_5% LPC_AD0
debug card R2441 CONN@ PCI_RST#_R R2479 1 2 0_0402_5% APU_PCIE_RST#
LPC_AD0 [12,31,35]
insert. 100K_0402_5% CLK_PCI_DB
CLK_PCI_DB [12,35]
2

INT_KBD Conn. Track Point Conn

+5VS
Click pad 10PIN
LEFT C2490 1 2 @ 100P_0402_50V8J +5VS
1
MIDDLE C2491 1 2 @ 100P_0402_50V8J JKB1
KSI1 1 C2470 JCP1
RIGHT C2492 1 2 @ 100P_0402_50V8J KSI7 2 1 0.1U_0402_16V4Z R2483 1
KSI[0..7] KSI6 3 2 2 1 2 FCH_SCLK1_R 2 1
KSI[0..7] [31] 4 3 [14] FCH_SCLK1 3 2
KSO9 0_0402_5% TP_DETECT
KSO[0..17] KSO16 C2483 1 2 @ 100P_0402_50V8J KSI4 5 4 TP_DATA2 4 3
KSO[0..17] [31] 6 5 5 4
KSI5 R2485 TP_CLK2
KSO17 C2482 1 2 @ 100P_0402_50V8J KSO0 7 6 1 2 FCH_SDATA1_R 6 5
7 [14] FCH_SDATA1 6
KSI2 8 JTP1 0_0402_5% 7
KSO2 C2445 1 2 @ 100P_0402_50V8J KSO1 C2446 1 2 @ 100P_0402_50V8J KSI3 9 8 TP_DATA2 1 CP_RESET# 8 7
9 1 [31] CP_RESET# 8
KSO5 10 TP_RESET 2 TP_CLK 9 11
10 [31] TP_RESET 2 [31] TP_CLK 9 GND
KSO15 C2448 1 2 @ 100P_0402_50V8J KSO7 C2447 1 2 @ 100P_0402_50V8J KSO1 11 MIDDLE 3 TP_DATA 10 12
11 3 [31] TP_DATA 10 GND
KSI0 12 RIGHT 4
KSO6 C2449 1 2 @ 100P_0402_50V8J KSI2 C2450 1 2 @ 100P_0402_50V8J KSO2 13 12 LEFT 5 4
13 5 1 1
KSO4 14 TP_CLK2 6 ACES_51522-01001-001
KSO8 C2451 1 2 @ 100P_0402_50V8J KSO5 C2452 1 2 @ 100P_0402_50V8J KSO7 15 14 7 6 @ C2489 @ C2488 CONN@
KSO8 16 15 8 7 100P_0402_50V8J 100P_0402_50V8J
KSO13 C2453 1 2 @ 100P_0402_50V8J KSI3 C2454 1 2 @ 100P_0402_50V8J KSO6 17 16 9 8 2 2
KSO3 18 17 10 9
KSO12 C2455 1 2 @ 100P_0402_50V8J KSO14 C2456 1 2 @ 100P_0402_50V8J KSO12 19 18 11 10
KSO13 20 19 12 GND
KSO11 C2457 1 2 @ 100P_0402_50V8J KSI7 C2458 1 2 @ 100P_0402_50V8J KSO14 21 20 GND
KSO11 22 21 ACES_50524-0100N-001
KSO10 C2459 1 2 @ 100P_0402_50V8J KSI6 C2460 1 2 @ 100P_0402_50V8J KSO10 23 22 CONN@
KSO15 24 23
KSO3 C2461 1 2 @ 100P_0402_50V8J KSI5 C2462 1 2 @ 100P_0402_50V8J 25 24
LEFT 26 25 +5VS
KSO4 C2463 1 2 @ 100P_0402_50V8J KSI4 C2464 1 2 @ 100P_0402_50V8J MIDDLE 27 26
RIGHT 28 27
KSI0 C2465 1 2 @ 100P_0402_50V8J KSO9 C2466 1 2 @ 100P_0402_50V8J KSO16 29 28
KSO17 30 29 R2473 1 @ 2 4.7K_0402_5% TP_CLK2
KSO0 C2467 1 2 @ 100P_0402_50V8J KSI1 C2468 1 2 @ 100P_0402_50V8J
31
32
30

GND1
ESD Request R2464 1 @ 2 4.7K_0402_5% TP_DATA2 SIT, NO.2
GND2 R2470 1 2 4.7K_0402_5% TP_RESET
CONN PIN define need double check JAE_FL4S030HA3R3000A-DT
CONN@ R2472 1 @ 2 0_0402_5% TP_DETECT

R2471 1 2 100K_0402_1% CP_RESET#

TP_CLK2 TP_CLK

TP_DATA2 TP_DATA
3

2
@ @ +3VS
D2403 D2402
PJDLC05_SOT23-3 PJDLC05_SOT23-3
Screw Holes R2497 1 2 2.2K_0402_5% FCH_SCLK1_R

R2498 1 2 2.2K_0402_5% FCH_SDATA1_R

H2 H3 H4 H5 H6 H7 H9 H8 H12 H13 H15 H16 H14 H18
H_4P0 H_4P0 H_4P0 H_4P0 H_2P3 H_2P3 H_2P3 H_2P3 H_2P3 H_2P3 H_2P3 H_2P3 H_2P3 H_2P3
1

1
@ @ @ @ @ @ @ @ @ @ @ @ @ @
1

FVT, NO.33
H22 H10 H19 H23 H20 H17 H24 H25 H11 H21
H_3P3 H_2P3 H_5P2X5P7N H_5P2X5P7N H_2P1N H_3P5X4P5N H_3P5X4P5N H_4P0N H_4P0N H_4P0N

@ @ @ @ @ @ @ @ @ @ ZZZ3
1

FD1 FD2 FD3 FD4

Security Classification Compal Secret Data Compal Electronics, Inc.
LA-8127_PCB Issued Date 2012/11/22 Deciphered Date 2015/11/22 Title
1 1 1 1
DA8000XR010 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
TP/KBD/Screw
Document Number
Hole/Debug Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-8127P
Tuesday, March 12, 2013 Sheet 33 of 51
 5 4 3 2 1

USB3.0 Conn *3 LP1

For EMI request
L2400 +USB3_VCCA
USB30_FTX_DRX_P0 1 2USB30_FTX_DRX_P0_L
W=80mils
1 2 +USB3_VCCA
D2405
JUSB3
USB30_FTX_DRX_N0 4 3USB30_FTX_DRX_N0_L USB30_P10_L 3 6 USB30_FTX_DRX_P0_L 9
4 3 I/O2 I/O4 1 SSTX+

150U_B2_6.3VM_R35M
WCM-2012HS-900T_4P D2404 USB30_FTX_DRX_N0_L 8 VBUS

C2473

C2474
470P_0402_50V7K
USB30_FTX_DRX_N0 1@ R2443 2 USB30_FTX_DRX_N0_L USB30_FRX_DTX_N0_L 9 1USB30_FRX_DTX_N0_L USB30_P10_L 3 SSTX-
[14] USB30_FTX_DRX_N0 1 D+
0_0402_5% L2401 2 5 +5VALW 1 7
D
USB30_FTX_DRX_P0 1@ R2442 2 USB30_FTX_DRX_P0_L USB30_FRX_DTX_P0 1 2USB30_FRX_DTX_P0_L USB30_FRX_DTX_P0_L 8 2USB30_FRX_DTX_P0_L GND VDD + USB30_N10_L 2 GND 10 D
[14] USB30_FTX_DRX_P0 1 2 6 D- GND 11
0_0402_5% USB30_FRX_DTX_P0_L
USB30_FRX_DTX_N0 1@ R2444 2 USB30_FRX_DTX_N0_L USB30_FTX_DRX_N0_L 7 4USB30_FTX_DRX_N0_L 4 SSRX+ GND 12
[14] USB30_FRX_DTX_N0 4 3USB30_FRX_DTX_N0_L 1 4 2 2 5 GND GND 13
0_0402_5% USB30_FRX_DTX_N0 USB30_N10_L USB30_FRX_DTX_N0_L
USB30_FRX_DTX_P0 1@ R2445 2 USB30_FRX_DTX_P0_L 4 3 USB30_FTX_DRX_P0_L 6 5USB30_FTX_DRX_P0_L I/O1 I/O3 SSRX- GND
[14] USB30_FRX_DTX_P0
0_0402_5% WCM-2012HS-900T_4P ACON_TARA4-9K1311
USB30_P10 1@ R2446 2 USB30_P10_L AZC099-04S.R7G_SOT23-6 CONN@
[14] USB30_P10
0_0402_5% L2402
USB30_N10 1@ R2447 2 USB30_N10_L USB30_P10 1 2 USB30_P10_L 3
[14] USB30_N10 1 2
0_0402_5%
TVWDF1004AD0_DFN9
USB30_N10 4 3 USB30_N10_L
4 3
WCM-2012-670T_4P

+5VALW +USB3_VCCA

U2404 W=80mils
C2475 1 8
0.1U_0402_16V4Z 2 GND VOUT 7
1 2 3 VIN VOUT 6
USB_ON# 4 VIN VOUT 5 R2487 1 @ 2 0_0402_5%
EN FLG USB_OC0# [14]
G547I2P81U_MSOP8 2
Low Active
@ C2476
[31] USB_ON# 0.1U_0402_16V4Z
1
For EMI request
L2403
USB30_FTX_DRX_N1 1 2USB30_FTX_DRX_N1_L
1 2
D2406

C
USB30_FTX_DRX_P1 4
4 3
3USB30_FTX_DRX_P1_L USB30_FRX_DTX_N1_L 9 1USB30_FRX_DTX_N1_L LP2 C
USB30_FTX_DRX_N1 1@ R2448 2 USB30_FTX_DRX_N1_L WCM-2012HS-900T_4P USB30_FRX_DTX_P1_L 8 2USB30_FRX_DTX_P1_L
[14] USB30_FTX_DRX_N1 +USB3_VCCA
0_0402_5% W=80mils
USB30_FTX_DRX_P1 1@ R2449 2 USB30_FTX_DRX_P1_L L2404 USB30_FTX_DRX_N1_L 7 4USB30_FTX_DRX_N1_L
[14] USB30_FTX_DRX_P1 1 2USB30_FRX_DTX_N1_L
0_0402_5% USB30_FRX_DTX_N1
USB30_FRX_DTX_N1 1@ R2450 2 USB30_FRX_DTX_N1_L 1 2 USB30_FTX_DRX_P1_L 6 5USB30_FTX_DRX_P1_L JUSB2
[14] USB30_FRX_DTX_N1 D2407 9
0_0402_5% USB30_FTX_DRX_P1_L
USB30_FRX_DTX_P1 1@ R2452 2 USB30_FRX_DTX_P1_L USB30_FRX_DTX_P1 4 3USB30_FRX_DTX_P1_L USB30_P11_L 3 6 1 SSTX+
[14] USB30_FRX_DTX_P1 4 3 I/O2 I/O4 VBUS
0_0402_5% USB30_FTX_DRX_N1_L 8
USB30_P11 1@ R2451 2 USB30_P11_L WCM-2012HS-900T_4P 3 USB30_P11_L 3 SSTX-
[14] USB30_P11 D+
0_0402_5% 7
USB30_N11 1@ R2453 2 USB30_N11_L L2405 TVWDF1004AD0_DFN9 2 5 USB30_N11_L 2 GND 10
[14] USB30_N11 GND VDD +5VALW D- GND
0_0402_5% USB30_P11 1 2 USB30_P11_L USB30_FRX_DTX_P1_L 6 11
1 2 4 SSRX+ GND 12
USB30_FRX_DTX_N1_L 5 GND GND 13
USB30_N11 4 3 USB30_N11_L 1 4 USB30_N11_L SSRX- GND
4 3 I/O1 I/O3 ACON_TARA4-9K1311
WCM-2012-670T_4P CONN@
AZC099-04S.R7G_SOT23-6

+USB3_VCCB
+5VALW +USB3_VCCB

150U_B2_6.3VM_R35M
U2405 W=80mils

C2478

C2479
470P_0402_50V7K
C2477 1 8 1
0.1U_0402_16V4Z 2 GND VOUT 7
VIN VOUT 1
For EMI request 1 2 3 6 +
USB_ON# 4 VIN VOUT 5 R2488 1 @ 2 0_0402_5%
EN FLG USB_OC1# [14]
L2406
USB30_FTX_DRX_N2 1 2 USB30_FTX_DRX_N2_L G547I2P81U_MSOP8 2 2
1 2 2
USB30_FTX_DRX_N2 1@ R2454 2 USB30_FTX_DRX_N2_L Low Active
B [14] USB30_FTX_DRX_N2 B
0_0402_5% @ C2480
USB30_FTX_DRX_P2 1@ R2455 2 USB30_FTX_DRX_P2_L USB30_FTX_DRX_P2 4 3 USB30_FTX_DRX_P2_L 0.1U_0402_16V4Z
[14] USB30_FTX_DRX_P2 4 3 1
0_0402_5%
USB30_FRX_DTX_N2 1@ R2457 2 USB30_FRX_DTX_N2_L WCM-2012HS-900T_4P
[14] USB30_FRX_DTX_N2
0_0402_5%
USB30_FRX_DTX_P2 1@ R2456 2 USB30_FRX_DTX_P2_L L2407 D2408
[14] USB30_FRX_DTX_P2 1 2 9 1USB30_FRX_DTX_N2_L
0_0402_5% USB30_FRX_DTX_N2 USB30_FRX_DTX_N2_L USB30_FRX_DTX_N2_L
USB30_P12 1@ R2458 2 USB30_P12_L 1 2
[14] USB30_P12 8 2USB30_FRX_DTX_P2_L
0_0402_5% USB30_FRX_DTX_P2_L
USB30_N12 1@ R2459 2 USB30_N12_L USB30_FRX_DTX_P2 4 3 USB30_FRX_DTX_P2_L
[14] USB30_N12
0_0402_5% 4
WCM-2012HS-900T_4P
3 USB30_FTX_DRX_N2_L 7 4USB30_FTX_DRX_N2_L LP3
USB30_FTX_DRX_P2_L 6 5USB30_FTX_DRX_P2_L
L2408 +USB3_VCCB
USB30_P12 1 2 USB30_P12_L
W=80mils
1 2
3 JUSB1
USB30_N12 4 3 USB30_N12_L USB30_FTX_DRX_P2_L 9
4 3 TVWDF1004AD0_DFN9 1 SSTX+
D2409 VBUS
WCM-2012-670T_4P USB30_FTX_DRX_N2_L 8
USB30_P12_L 3 6 USB30_P12_L 3 SSTX-
I/O2 I/O4 7 D+
USB30_N12_L 2 GND 10
USB30_FRX_DTX_P2_L 6 D- GND 11
2 5 4 SSRX+ GND 12
GND VDD +5VALW GND GND
USB30_FRX_DTX_N2_L 5 13
SSRX- GND
ACON_TARA4-9K1311
1 4 USB30_N12_L CONN@
I/O1 I/O3

AZC099-04S.R7G_SOT23-6

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/22 Deciphered Date 2015/11/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
USB 3.0 Conn Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-8127P
Tuesday, March 12, 2013 Sheet 34 of 51
5 4 3 2 1
 5 4 3 2 1

ON/OFF switch
USB2.0/Audio Jack SB CONN
+3VLP
Power Button Board Conn

2
+3VLP +3VALW

R2460

2
100K_0402_5% JAUD1
1
+5VALW

1
R2481 R2482 2 1
0_0402_5% 0_0402_5% 3 2
@ 4 3
D D

1
5 4
JPWR1 6 5
[29] HP_OUTL 6
1 7
1 [29] HP_OUTR 7
ON/OFFBTN# 2 8
3 2 5 9 8
3 G1 [29] EXT_MIC 9
LID_SW# 4 6 10
[31] LID_SW# 4 G2 [29] PLUG_IN 10
D2410 11
J2405 2 ON/OFF ACES_50504-0040N-001 12 11
ON/OFF [31] [14] USB20_N0 12
1 2 ON/OFFBTN# 1 CONN@ 13
[14] USB20_P0 13
3 51_ON# 14
51_ON# 14
SHORT PADS 15
[14] USB_OC3# 15
BAV70W_SOT323-3 16
[31] AOU_EN 16
17
18 17
[31] AOU_CTL2 18
SIT, NO.1 19
[31] AOU_CTL3 19
20
21 20
GND1

1
22
D Q2408 GND2
EC_ON 2 2N7002K_SOT23-3
ESD Request ACES_88194-2041
[31,40] EC_ON
G @ ON/OFFBTN# LID_SW# CONN@
S
2

2
3

R2463
100K_0402_5%
@
1

1
D2416
PJSOT24CH_SOT23-3

C C

Lan Conn
[5] PCIE_CRX_DTX_N0 PCIE_CRX_DTX_N0 1
JRJ45 Finger Printer
PCIE_CRX_DTX_P0 2 1
[5] PCIE_CRX_DTX_P0 2
3
PCIE_CTX_DRX_N0 4 3
[5] PCIE_CTX_DRX_N0 4
PCIE_CTX_DRX_P0 5
[5] PCIE_CTX_DRX_P0 5
6
CLK_PCIE_LAN# 7 6
[12] CLK_PCIE_LAN# 7
CLK_PCIE_LAN 8
[12] CLK_PCIE_LAN 8
[14] LAN_CLKREQ# LAN_CLKREQ# 9
APU_PCIE_RST# 10 9
[12,17,33,35] APU_PCIE_RST# 10
LAN_WAKE# 11
[31] LAN_WAKE# 11
FCH_PCIE_WAKE# 12
[14] FCH_PCIE_WAKE# 12
CLK_LAN_25M 13
[12] CLK_LAN_25M 13
ACIN 14 JFPB1
[31,39] ACIN 14
+3VS
15 +3VS +3VS_FP 1
16 15 USB20_N7 2 1
16 1 [14] USB20_N7 2
+3VALW
17 C2481 USB20_P7 3 5
17 [14] USB20_P7 3 G1 6
+RTCBATT
18 0.1U_0402_16V4Z 4
19 18 FP_GND 4 G2
20 GND 2 ACES_50504-0040N-001
GND CONN@

3
ESD Request ACES_50506-01841-P01 @
CONN@ D2413

3
AZC199-02SPR7G_SOT23-3

1
CLK_LAN_25M R2480 1 2 33_0402_5%

For ESD 1
B 2 B

C2500
22P_0402_50V8J
1

Card Reader Debug Conn.

+3VS +3VS +3VALW
JCARD1
1 JDB3
2 1 1
PCIE_CRX_DTX_P3 3 2 2 1
[5] PCIE_CRX_DTX_P3 3 2
[5] PCIE_CRX_DTX_N3 PCIE_CRX_DTX_N3 4 3
5 4 4 3
5 [12,31,33] LPC_FRAME# 4
CLK_PCIE_CARD 6 5
[12] CLK_PCIE_CARD 6 [12,31,33] LPC_AD3 5
CLK_PCIE_CARD# 7 6
[12] CLK_PCIE_CARD# 7 [12,31,33] LPC_AD2 6
8 7
8 [12,31,33] LPC_AD1 7
PCIE_CTX_DRX_P3 9 8
[5] PCIE_CTX_DRX_P3 9 [12,31,33] LPC_AD0 8
PCIE_CTX_DRX_N3 10 PLT_RST# 9
[5] PCIE_CTX_DRX_N3 10 [12,31] PLT_RST# 9
CARD_CLKREQ# 11 10
[14] CARD_CLKREQ# 11 [12,33] CLK_PCI_DB 10
APU_PCIE_RST# 12 [31,33] EC_TX_P80_DATA 11 13
[12,17,33,35] APU_PCIE_RST# 12 11 GND
+3VALW
13 [31,33] EC_RX_P80_CLK
12 14
14 13 12 GND
[26,31] Logo_LED# 14 15
GND 16 CLK_PCI_DB ACES_85201-1205N
GND CONN@
ACES_50224-0140N-001
CONN@
C2502
12P_0402_50V8J
@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/22 Deciphered Date 2015/11/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
Sub Board Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-8127P
Tuesday, March 12, 2013 Sheet 35 of 51
5 4 3 2 1
 A B C D E

+3VALW TO +3VS +5VALW TO +5VS +1.5V to +1.5VS

SIT, NO.8 SIT, NO.8 +1.5V Q2301 +1.5VS

+3VALW +3VS +5VALW U2301 +5VS 3 1

U2302 1 1 1

1
8 1 @
1 8 1 1 1 7 2 1 C2301 AP2301GN-HF_SOT23-3 C2302 C2303

1
7 2 6 3 10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0603_10V6K R2301

2
C2307 6 3 C2308 C2304 5 C2305 2 2 2 470_0603_5%
10U_0603_6.3V6M5 10U_0603_6.3V6M R2303 10U_0603_6.3V6M 10U_0603_6.3V6M R2302 @

2
2 2 470_0603_5% 2 AP4800BGM-HF_SO-8 2 470_0603_5%

4
+VSB

1 2

1 2

1
AP4800BGM-HF_SO-8 +VSB +5VALW
D
1

1 1
D D 2 SUSP

1
2 SUSP 2 SUSP G@
R2304 G G S Q2303
470K_0402_5% S R2305 S 100K_0402_5% 2N7002K_SOT23-3

3
Q2302 150K_0402_5% Q2300 R2306
2

3
2N7002K_SOT23-3 2N7002K_SOT23-3

2
3VS_GATE 2 R2308 1 3VS_GATE_R 5VS_GATE 2 R2307 15VS_GATE_R 1.5VS_GATE 1 21.5VS_GATE_R

1
1 10K_0402_5% 1 R2309 1
1

1
10K_0402_5% D 150K_0402_5%
D C2311 SUSP 2 C2310 D C2300
SUSP 2 .1U_0603_25V7K G Q2304 .1U_0603_25V7K SUSP# 2 Q2306 .1U_0603_25V7K
G Q2305 2 S 2N7002K_SOT23-3 2 G 2N7002K_SOT23-3 2
S 2N7002K_SOT23-3 S

3
3

3
+1.1VALW to +1.1VS +3VALW TO +3V SIT, NO.5 +1.1VALW to +1.1V SIT, NO.5

+1.1VALW +1.1VS
U2300

1 8 1 1 1 @
1

7 2 @ +1.1VALW Q2317 +1.1V

C2313 6 3 C2314 C2315 +3VALW Q2318 +3V

S
10U_0603_6.3V6M5 10U_0603_6.3V6M 1U_0603_10V6K R2311 3 1

D
2 2
2 2 2

S
470_0603_5% 3 1

D
1 1 1
AP4800BGM-HF_SO-8 @ 1 1 @ @
4

@ @ C2317 C2320 C2318

G
2
+VSB C2309 C2321 10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0603_10V6K

G
2
1

10U_0603_6.3V6M 10U_0603_6.3V6M 2 SI2305CDS-T1-GE3_SOT23-3 2 2

@ D 2 SI2305CDS-T1-GE3_SOT23-3 2
Q2307 2SUSP +5VALW @
1

2N7002K_SOT23-3 G +5VALW
R2315 S

1
220K_0402_5%
3

1
R2323 @
1 2

1.1VS_GATE 2 R2316 1 1.1VS_GATE_R 100K_0402_5% R2322

1 150K_0402_5%

2
D 47K_0402_5% @
SUSP 2 C2316 3V_FCH_GATE 2 R2310 13V_FCH_GATE_R @

2
G Q2310 1U_0603_25V6K 1 1.1V_FCH_GATE 2 R2317 11.1V_FCH_GATE_R
S 2N7002K_SOT23-3 2 0_0402_5% @ 1
1

1
C2312 0_0402_5% @
3

D @ .1U_0603_25V7K D @ C2319
FCH_PWR_EN_R 2 Q2313 2 FCH_PWR_EN_R 2 Q2316 1U_0603_10V6K
G 2N7002K_SOT23-3 G 2N7002K_SOT23-3 2
S S
3

3
+3VALW +3V +1.1VALW +1.1V

J2303 @ J2302 @
1 2 1 2
1 2 1 2
JUMP_43X79 JUMP_43X79

+RTCBATT +5VALW
3 3

+3VALW TO +3V_FCH

1
+0.75VS @
R2312 R2313
100K_0402_5% 100K_0402_5%
1

2 Short J2301 for PCH VCCSUS3.3

2
SUSP
[43] SUSP
R2319
470_0603_5%

1
@ +3VALW +3V_FCH
1 2

OUT
@ Q2308
D Q2312 DDTC124EKA-7-F_SC59-3 J2301 @
2 SUSP 1 2
G 1 2
S 2N7002K_SOT23-3 2 JUMP_43X79
[31,42,44] SUSP# IN
3

GND
3

R2325 2 @ 1 0_0402_5% FCH_PWR_EN_R

[31] FCH_PWR_EN

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/22 Deciphered Date 2015/11/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
DC
Document Number
V TO VS INTERFACE Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-8127P
Tuesday, March 12, 2013 Sheet 36 of 51
A B C D E
 5 4 3 2 1

ADP_ID
PR101
10K_0402_1% AC Adapter 135W 90W 65W

680P_0603_50VK
1 2
+3VALW ADP_ID [31] R(K ohm) 0 open 10

0.1U_0402_16V7K
A/D ADP_ID(V) 0 3.3 1.65

1
PC102

PC103
Detection voltage <0.33 >2.64 1.32~1.98

2
PR102
D
JDCIN1
1 1
270_0402_1%
2
VIN D
1 2 APDIN
2 3 1 2 APDIN1 1 2
3 4
4 5 PF101 PL101
5 7A_24VDC_429007.WRML SMB3025500YA_2P

1000P_0402_50V7K

1000P_0402_50V7K
100P_0402_50V8J

100P_0402_50V8J
ACES_50312-00541-001

1
@

2
PC101

PC104

PC105

PC106
VIN

2
PD104
LL4148_LL34-2

PD105

1
LL4148_LL34-2 51ON-1
BATT+ 2 1

1
C @ C
PR123 PR124
68_1206_5% 68_1206_5%
@
PR125

2
200_0603_5%
CHGRTCP 1 2
@ @

+3VLP

2
@

1
PR133
+CHGRTC 0_0603_5% PU102 PR131
200_0603_5%
PR132 BIT3021A-ST9 SOT89 3P
PD106
1
B 1K_0603_5% B

2
1 2 1 2 3 2 CHGRTCIN
+RTCBATT VOUT VIN

RB751V-40_SOD323-2
1

1
GND PC117
PC116 1U_0805_25V6K
10U_0603_6.3V6M 1
2

2
@ @
@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/04/18 Deciphered Date 2015/07/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR DCIN / Vin Detector /Pre-charge
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 12, 2013 Sheet 37 of 51
5 4 3 2 1
 5 4 3 2 1

VMB2 VMB
PF201 PL201
JBATT1 12A_65V_451012MRL SMB3025500YA_2P
1 1 2 1 2
1 2 BATT+
2 3 EC_SMCA
3 4 EC_SMDA
4 5
5

1
D 6 D
6

1
7 PC201 PC202
7

100_0402_1%

100_0402_1%
8 1000P_0402_50V7K 0.01U_0402_25V7K

2
GND 9
GND PR201

PR202
SUYIN_200082GR007M211ZR
PH1 under CPU botten side : For KB930 --> Keep PU201 circuit
2

2
@ CPU thermal protection at 93 +-3 degree C (Vth = 1.25V)
Recovery at 56 +-3 degree C For KB9012 (Red square) --> Remove PU201 circuit, but keep PR206
PH201
EC_SMB_CK1 [31,39]

EC_SMB_DA1 [31,39] [31,39] ADP_I

2.1K_0402_1%
2
1 2
+3VALW

PR225
PR203
6.49K_0402_1%
<BOM Structure> VL

1
1 2 +3VLP
BATT_TEMP [31] A/D +3VLP +3VALW

2N7002W-T/R7_SOT323-3
PR204

12.7K_0402_1%
10K_0402_5%

1
<BOM Structure>

2
47K_0402_1%
1

1
D

PQ205

PR206

2
47K_0402_1%
PR231
PC203 PR224 2 PR205 @

PR234
0.1U_0603_25V7K 4.42K_0402_1% G 21.5K_0402_1%

2
C C
S

2
[31] ADP_PROTECT PR211 @

1
1

1
PU201 0_0402_5%
1
VCC TMSNS1
8 1 2 9012_PH1 [31]

2
2 7 @
GND RHYST1 PR207
+3VS 3 6 10K_0402_1%
OT1 TMSNS2

27.4K_0402_1%
4 5

1
OT2 RHYST2

2
100K_0402_1%

100K_0402_1%_TSM0B104F4251RZ
PR227

PR208
G718TM1U_SOT23-8

PH201
[45,7] H_PROCHOT#
PR232

2
PQ206 0_0402_5%

1
D 1 2
2ADP_OCP_1 MAINPWON [31,40]

2
G
S SSM3K7002FU_SC70-3 PR209
+3VLP

1
3
10K_0402_1%
PR228
PR226

100K_0402_1%
[31,7] H_PROCHOT#_EC 0_0402_5% 0_0402_5%

PR229
1
1 2 @

2
@ @

1
1
PR230
0_0402_5%

2
B
[31] Turbo_V B

PQ202
TP0610K-T1-E3_SOT23-3

3 1
B+ +VSBP

100K_0402_1%

0.22U_0603_25V7K
1

1
PR214

PC204
PC205
0.1U_0603_25V7K

2
2

2
PR215
VL 22K_0402_1%
1 2
2

PR213
100K_0402_1%
@
PR212
1

1K_0402_5% D PJ201
1 2 2 PQ201 @ JUMP_43X39
[40,41] SPOK 1 2
G 2N7002W-T/R7_SOT323-3 +VSBP 1 2 +VSB
1U_0402_6.3V6K

S
3
1

PC206

PR233
0_0402_5%
1 2
[31] VSB_ON
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/04/18 Deciphered Date 2015/07/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-BATTERY CONN/OTP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 12, 2013 Sheet 38 of 51
5 4 3 2 1
 5 4 3 2 1

P3
B+ PQ302
AO4407A_SO8
P2 Need EC write ChargeOption() bit[8]=1 1 8
2 7
PQ301 PQ304 3 6
AO4407A_SO8 AO4423_SO8 5
8 1 1 8 PR302
VIN 7 2 2 7 0.01_1206_1% B+
SH00000AA00

4
6 3 3 6 BATT+
5 5 1 2 1 4

PL302 2 3 VIN

100U_25V_M
1UH_PCMB061H-1R0MS_7A_20% 1 PR305
200K_0402_1%

10U_0805_25V6K

@ 10U_0805_25V6K

2200P_0402_50V7K
+

PC323
PQ305 1 2

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
D D
1 2
47K_0402_5%
1

2
200K_0402_1%
0.1U_0603_25V7K

PC308
1
2 V1
PR301

PC303

PC304

PC305

PC306

PC307
DTA144EUA_SC70-3 PC302

2
PC301

PR306

47K_0402_1%
5600P_0402_25V7K

1
@
2

2
2

PR307
2
ACN

1DISCHG_G-1
1

2
PQ307 PR308
LTC015EUBFS8TL_UMT3F
1

ACP 220K_0402_1%
V1
1

1
P2-1

0.1U_0603_25V7K
2

PC309 PC310
2
1 2 2 1
3

0.1U_0603_25V7K
6

VIN LTC015EUBFS8TL_UMT3F

0.039U_0603_25V7K
3
1

PC312 PQ308
150K_0402_1%

1
D
PR309

PC311
PQ310A
2 2N7002KDW -2N_SOT363-6 0.1U_0603_25V7K P2 2 PACIN_2
G

2
2 1 S
1

3
ACPRN

432K_0603_1%
1

5
6
7
8
PR314
P2-2

PQ312
PACIN_2

10_1206_5%

AO4466L_SO8
2
C C
2N7002KDW-2N_SOT363-6

PR318
PQ311
2
3
PQ310B

2N7002W -T/R7_SOT323-3

ACOK

CMPIN

CMPOUT

ACP

ACN
PR317 [31,38] ADP_I 4
47K_0402_1% PR319 21

1
PACIN 1 2 5 1 2 6 TP
ACDET PC314
PL301
64.9K_0603_1% PC313 20 BQ24727VCC-1 1 2 10UH_+-20%_PCMB104T-100MS_6A PR320
4

3
2
1
1 2 1 2 7 VCC 0.01_1206_1%
PQ313 PR333 PC324 IOUT
LTC015EUBFS8TL_UMT3F

1U_0603_25V6
1

0_0402_5% 100p_0603_50V8 19 LX_CHG 1 2CHG 1 4

0.1U_0603_25V7K 1 2 8 PU301 PHASE
[31,38] EC_SMB_DA1 SDA 2 3
PR334 BQ24737RGRR_VQFN20_3P5X3P5 @
PR321 0_0402_5% 18 DH_CHG
HIDRV

1
1 2 2 1 2 9
SA000051W00

4.7_1206_5%
[31] ACOFF [31,38] EC_SMB_CK1 SCL

5
6
7
8

PR323
10K_0402_5% PR324

PQ314
PR322 2.2_0603_5%

AO4466L_SO8
1 2 10 17 BST_CHG 1 2 2 1 SRP SRN

10U_0805_25V6K

10U_0805_25V6K
ILIM BTST
1

+3VALW 316K_0402_1%

124727_SN
3

2
PD303 RB751V-40_SOD323-2 PC315

LODRV

1
16 2 1 4

PC316

PC317
PR325 0.047U_0603_25V7M

GND
SRN

SRP
REGN

BM
100K_0402_1%
BQ24727VDD
2

2
11 @

1 12

1 13

14

15

680P_0603_50V7K
6.8_0603_5%

3
2
1

PC319
10_0603_5%
PC318

2
PR326

PR327
1U_0603_25V6

2
2

2
PC320 DL_CHG
B 0.1U_0603_25V7K B
2 1

CHGVADJ=(Vcell-4)/0.10627
1

Vcell CHGVADJ

1
PC321 @
4V 0V 0.1U_0603_25V7K PC322
2

2 0.1U_0603_25V7K
4.2V 1.882V BQ24727VDD
4.35V 3.2935V
PR337
10K_0402_1%

1
1 2
ACIN [31,35]
CC=0.25A~3A PR338
PR336 10K_0402_1%
IREF=1.016*Icharge 47K_0402_1%
PACIN

2
IREF=0.254V~3.048V

1
VCHLIM need over 95mV

1
D PR339
ACPRN 2
G PQ319 12K_0402_1%

2
S

3
2N7002W -T/R7_SOT323-3

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/04/18 Deciphered Date 2015/07/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 12, 2013 Sheet 39 of 51

5 4 3 2 1
 5 4 3 2 1

Note:
Use TPS51125 IC can remove RTC refernece LDO
Use TPS51427 IC must keep RTC refernece LDO

2VREF_8205 PJ402
+3VALW P 2 1 +3VALW
2 1
@ JUMP_43X118

1U_0603_10V6K
D D

1
PJ403

PC402
+5VALW P 2 1 +5VALW

2
2 1
@ JUMP_43X118

PR401 PR402
13K_0402_1% 30K_0402_1%
1 2 1 2

Typ: 175mA PR403 PR404

RT8205_B+ 20K_0402_1% 20K_0402_1% RT8205_B+
+3VLP 1 2 1 2
PJ401

B+ 2 1
0.1U_0603_25V7K

2 1

ENTRIP2

ENTRIP1
@ JUMP_43X118 PR405 PR406
PC401

2200P_0402_50V7K

2200P_0402_50V7K
0.1U_0603_25V7K

0.1U_0603_25V7K
4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
1

130K_0402_1% 66.5K_0402_1%
1 2 1 2
PC421

PC409
1

1
PC403

PC404

PC405

PC406

PC407

PC408
4.7U_0805_10V6K
2

8
7
6
5

5
6
7
8
PU401
2

2
ENTRIP2

FB2

TONSEL

FB1

ENTRIP1
REF
1
C PQ401 C

TPC8037-H_SO8
PC410
25

PQ402
AO4466L_SO8 P PAD

2
4 4
7 24
VO2 VO1 SPOK [38,41]
PR407 8 23 PR408 PC412
2.2_0603_5% VREG3 PGOOD 2.2_0603_5% 0.1U_0603_25V7K
1
2
3

3
2
1
1 2 1 2 BST_3V 9 22 BST_5V 1 2 1 2
BOOT2 BOOT1
PL401 PC411 UG_3V 10
VFB=2.0V 21 UG_5V PL402
4.7UH +-20% PCMC063T-4R7MN 5.5A 0.1U_0603_25V7K UGATE2 UGATE1 4.7UH_20%_VMPI1004AR-4R7M-Z01_10A
1 2 LX_3V 11 20 LX_5V 1 2 +5VALWP
+3VALWP PHASE2 PHASE1
1

8
7
6
5

1
LG_3V 12 19 LG_5V
4.7_1206_5%

4.7_1206_5%
LGATE2 LGATE1

5
6
7
8
PQ403
PR409

PR410
SKIPSEL
AO4712L_SO8

VREG5

PQ404
PR417

GND

VIN
@ 499K_0402_1% RT8205LZQW (2) W QFN24_4X4

NC
EN
1 1
2

2
4 1 2
+ PC413 VS 4 + PC414
1U_0603_10V6K

1U_0603_10V6K
13

14

15

16

17

18
1

1
150U_B2_6.3VM_R45M PR411 150U_B2_6.3VM_R45M
PC423

PC422
680P_0603_50V7K

TPC8A03-H_SO8
499K_0402_1%

680P_0603_50V7K
2 1 2 2
PC415

PC416
2

1
2
3

2
B+

3
2
1
1
100K_0402_1%

1U_0603_10V6K
VL

1
PC417

1
PR412

PC418
Typ: 175mA

4.7U_0805_10V6K
B B

2
ENTRIP1 ENTRIP2
2

2
RT8205_B+
6

1
PQ405B
PQ405A 2N7002KDW -2N_SOT363-6

0.1U_0603_25V7K
2N7002KDW -2N_SOT363-6 2 5 2VREF_8205 +3.3VALWP OCP(min)=5.81A

2
PC419
+5VALWP OCP(min)=8.44A
1

PR413
100K_0402_1%
[31,35] EC_ON PR418 2 1
VL
2 1

2.2K_0402_5%

[31,38] MAINPWON PR414

0_0402_5% PQ406
LTC015EUBFS8TL_UMT3F
1

2 1

+3VLP
2

1 2 2
PR420 VS
100K_0402_1% PR415
40.2K_0402_1%

A A
1

@ 100K_0402_1%
4.7U_0603_10V6K
1

PR419
PR416

PC420

[31] BM# @
1

D
1

0_0402_5%
2N7002KW 1N SOT323-3

2 1 2
PQ407

G
2

S
Security Classification Compal Secret Data Compal Electronics, Inc.
3
1

PC424
0.1U_0603_10V7K

@ @ 2011/04/18 2015/07/08 Title

@ Issued Date Deciphered Date
3VALWP/5VALWP
2

@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 12, 2013 Sheet 40 of 51
5 4 3 2 1
 5 4 3 2 1

@ PJ501
+1.1VALWP_B+ 2 1
2 1 B+
JUMP_43X118

2200P_0402_50V7K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
0.1U_0402_25V6
1

1
PC503
PC502

PC504

PC505
D D

2
5
6
7
8
PR502 PQ501
PC506 4
2.2_0603_5% TPC8037-H 1N SO8
1 2 1 2

PU501 0.1U_0603_25V7K PJ502

1 10 BST_+1.1VALWP 2 1
+1.1VALWP +1.1VALW

3
2
1
PGOOD VBST 2 1
PR501
1 2 TRIP_+1.1VALWP 2 9 UG_+1.1VALWP PL501 @ JUMP_43X118
TRIP DRVH 1UH +-20%_VMPI0703AR-1R0M-Z01_11A
34K_0402_1%
PR503 EN_+1.1VALWP 3 8 SW_+1.1VALWP 1 2
0_0402_5% EN SW +1.1VALWP
1 2 FB_+1.1VALWP 4 7 +1.1VALWP_5V
[38,40] SPOK VFB V5IN +5VALW
0.1U_0402_16V7K
2
47K_0402_1%

RF_+1.1VALWP 5 6 LG_+1.1VALWP
RF DRVL
1

5
6
7
8

1
@
PR504

PC501

@ 1 +1.1VALWP

1U_0603_10V6K
11

220U_D2_4VY_R15M
TP Iocp=5.85A

1
PC508

PC519
PC507 PR505 +
2

@ TPS51212DSCR_SON10_3X3 1U_0603_6.3V6M 4.7_1206_5%

1

2
PQ502

2
PR506 4 TPC8A03_SO8 2
470K_0402_1%

1
@ PC509
2

680P_0603_50V7K

3
2
1

2
C PR507 C

5.76K_0402_1%
2 1
2

PR508
10K_0402_1%

@ PJ503
1

+1.5VP_B+ 2 1
2 1 B+
JUMP_43X118

2200P_0402_50V7K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
0.1U_0402_25V6
1

1
PC511
PC510

PC512

PC513
2

2
5
6
7
8
PR509 PQ503
PC514 4
2.2_0603_5% TPC8037-H 1N SO8
1 2 1 2

PU502 0.1U_0603_25V7K
1 10 BST_+1.5VP

3
2
1
PGOOD VBST
PR510
B 1 2 TRIP_+1.5VP 2 9 UG_+1.5VP PL502 B
TRIP DRVH 1.0UH_PCMC104T-1R0MN_20A_20%
140K_0402_1%
PR511 EN_+1.5VP 3 8 SW_+1.5VP 1 2
[31,43] SYSON
0_0402_5% EN SW
+1.5VP
1 2 FB_+1.5VP 4 7 +1.5VP_5V
VFB V5IN +5VALW
0.1U_0402_16V7K
2
47K_0402_1%

RF_+1.5VP 5 6 LG_+1.5VP
RF DRVL
1

5
6
7
8

1
PR512

@ 1
1

1U_0603_10V6K
PC515

220U_6.3V_M
11
TP

1
PC517

PC520
PC516 PR513 +
@ 2

TPS51212DSCR_SON10_3X3 1U_0603_6.3V6M 4.7_1206_5%

1

PQ504

2
@ PR514 4 TPC8A03_SO8 2
470K_0402_1%

1
@ PC518
2

680P_0603_50V7K
3
2
1

2
PR515

11.5K_0402_1%
2 1
PJ504 +1.5V
+1.5VP 2 1
2 1
2

PR516 @ JUMP_43X118
10K_0402_1%
1

A A
+1.5VP
Iocp=15.6A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/04/18 Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.1VALWP/+1.5VP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 12, 2013 Sheet 41 of 51
5 4 3 2 1
 5 4 3 2 1

@ PJ601
+1.2VSP_B+ 2 1
2 1 B+
JUMP_43X118

2200P_0402_50V7K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
0.1U_0402_25V6
1

1
PC603
PC602

PC604

PC605
2

2
5
6
7
8
D D

PR602 PQ601
PC606
2.2_0603_5% 4 TPC8037-H 1N SO8
1 2 1 2

[31,45] VR_ON PU601 0.1U_0603_25V7K

PR610 0_0402_5%
2 1 1 10 BST_+1.2VSP

3
2
1
PGOOD VBST
@ PR601
1 2 TRIP_+1.2VSP 2 9 UG_+1.2VSP PL601
TRIP DRVH 1UH +-20%_VMPI0703AR-1R0M-Z01_11A
75K_0402_1%
PR603 EN_+1.2VSP 3 8 SW _+1.2VSP 1 2
[31,36,44] SUSP#
243K_0402_1% EN SW
+1.2VSP
1 2 FB_+1.2VSP 4 7 +1.2VSP_5V
VFB V5IN
+5VALW
2

RF_+1.2VSP 5 6 LG_+1.2VSP
47K_0402_1%

1U_0402_16V7K

RF DRVL
1

5
6
7
8

1
PR604

1
11
PC601

1U_0603_10V6K
220U_D2_4VY_R15M
TP

1
PC607 PR605 +

PC608

PC612
2

TPS51212DSCR_SON10_3X3 1U_0603_6.3V6M 4.7_1206_5%

1

2
PQ602

2
@ PR606 4 TPC8A03_SO8 2
470K_0402_1%

1
PC609
2

680P_0603_50V7K

3
2
1

2
C PR607 C

7.15K_0402_1%
2 1
PJ602 +1.2VS
+1.2VSP 2 1
2 1
2

@ JUMP_43X118
PR608
10K_0402_1%
1

+1.2VSP
Iocp=13A

B B

PU602
APL5508-25DC-TRL_SOT89-3
PJ603
+3VS PJ604
1 2 2 3 +2.5VSP
1 2 IN OUT +2.5VSP 2 1 +2.5VS
@ JUMP_43X39 2 1

1
GND @ JUMP_43X39

4.7U_0805_6.3V6K
1

1
PR609

PC611
1 (0.38A,20mils ,Via NO.=1)
PC610 10K_1206_5%
1U_0603_10V6K
2

2
@

2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/04/18 Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.2VSP/+2.5VSP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 12, 2013 Sheet 42 of 51
5 4 3 2 1
 5 4 3 2 1

+1.5V

D D

2
PJ701

2
JUMP_43X79
@

1
1
PU701
1
VIN VCNTL
6 +3VALW
PC702 2 5
GND NC PJ702

1
4.7U_0805_6.3V6K

1
3 7 PC703 2 1
VREF NC +0.75VSP 2 1 +0.75VS
PR702

2
@ PR701
@PR701 1K_0402_1% 4 8 1U_0603_10V6K
0_0402_5% VOUT NC JUMP_43X79
1 2 9 @
[31,41] SYSON

2
PQ701 TP
2N7002KW 1N SOT323-3 APL5336KAI-TRL_SOP8P8

0.1U_0402_16V7K
PR703
+0.75VSP
1

1
D

PC705

PC706
0_0402_5%

1K_0402_1%

10U_0603_6.3V6M

10U_0603_6.3V6M
PC704
1 2 2
[36] SUSP

1
G

2
1

3 S PR704
@ PC701

2
1U_0402_6.3V6K
2

C C

PU702 PL701
4

PJ703 1UH_PH041H-1R0MS_3.8A_20% PJ704

2 1 10 2 LX_1.8V 1
<BOM Structure> 2 +1.8VSP 2 1 +1.8VGS
+5VALW
PG

2 1 PVIN LX +1.8VSP 2 1

68P_0402_50V8J
@ JUMP_43X118 9 3 @ JUMP_43X118
PVIN LX
1

1
680P_0603_50V7K 4.7_1206_5%

B B
1

1
PC708
PC707 8
SVIN
PR705

22U_0805_6.3VAM PR706
6 30K_0402_1%
2

FB 2

22U_0805_6.3VAM

22U_0805_6.3VAM
5
1 2

EN

1
NC

NC
TP

PC710

PC711
FB=0.6Volt
PC709
11

2
1 2 EN_1.8V
2

PR707
0.1U_0402_10V7-K

12,14,19,44] PXS_PWREN 200K_0402_1%

2

SY8033BDBC_DFN10_3X3
2

PR708
PC712

1M_0402_5%
FB_1.8V
1
1

PR709
14.7K_0402_1%
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/04/18 Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+0.75VP/+1.8VP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 12, 2013 Sheet 43 of 51
5 4 3 2 1
 A B C D E

PR874
PD801
S SCH DIO RB751V40 SC76 82K_0402_1%
2 1 1 2
PJ805
PR866
130K_0402_1% 2 1
1 2 EN_0.95V +VGA_PCIEP 2 1 +0.95VGS
[12,14,19,43,44] PXS_PWREN
GPIO21 GPIO29 GPIO30 GPIO20 GPIO15 JUMP_43X79

2
@

1
PR867 PR868 PC876 @
VID5 VID4 VID3 VID2 VID1 VDDC
PC868 100K_0402_1% 0_0402_5% 0.22U_0603_10V7K
0 1 1 1 1 1.125V 0.1U_0402_10V7K 1 2 1 2

1
1 0 0 0 0 1.100V

16

15

14

13
1 0 0 0 1 1.075V
PL803
+3VALW

VIN

EN

PWRGD

BOOT
PJ801
1 0 0 1 0 1.050V 1UH_PCMB063T-1R0MS_12A_20%
2 1 1 12 LX_0.95V 1 2
2 1 VIN PH +VGA_PCIEP
1 0 0 1 1 1.025V

10U_0805_6.3V6M
0.1U_0402_10V7K

10U_0805_6.3V6M

22U_0805_6.3VAM

22U_0805_6.3VAM

22U_0805_6.3VAM

22U_0805_6.3VAM
JUMP_43X79

1
2 11

4.7_0402_1%
1
1 0 1 0 0 1.000V 1

1
@ VIN PH

PC869

PC870

PC871
PU802

PR871

PC877

PC878

PC879

PC880
22P_0402_50V8J
19.1K_0402_1%
1 0 1 0 1 0.975V

2
3 TPS54618RTER_QFN16_3X3 10

2
GND PH

1
PR872
1 0 1 1 0 0.950V

PC875
@

SNUB_0.95V
1 0 1 1 1 0.925V 4 9

VSENSE

2
GND SS/TR

RT/CLK
@

COMP

1
AGND

2200P_0402_50V7K
17

680P_0402_50V7K
1 1 0 0 0 0.900V Default PWRPD

1
+3VALW +3VGS

PC873
1 1 0 0 1 0.875V 0.8V

PC874
PR813 PR814

2
1 1 0 1 0 0.850V 1 2 1 2
@

2
1 1 0 1 1 0.825V 10K_0402_5% 10K_0402_5%

2
PR873

1
100K_0402_1%

182K_0402_1%
1 1 1 0 0 0.800V @
PQ802A
@
PQ802B PR869

PR870
1 1 1 0 1 0.775V 2 2N7002KDWH_SOT363-6 5 2N7002KDWH_SOT363-6 18K_0402_1%

1
3300P_0402_50V7K
1 1
1

2
PC872
PR863 @ @

2
0_0402_5%
1 2
PR861
91K_0402_1%

[18]

[18]

[18]

[18]

[18]
GPU_VID5

GPU_VID4

GPU_VID3

GPU_VID2

GPU_VID1

GPU_VID0
1 2
[12,14,19,43,44] PXS_PWREN
PR862 @
0_0402_5%
1 2
[31,36,42] SUSP#
1 2
+3VGS
PC801 .1U_0402_16V7K

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%
PR865
1 2 DPRSLPVR_VGA-1

2
1

1
10K_0402_1%
+3VGS PR820 PR821 PR822 PR823 PR824 PR825 PR826
2 2
0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5%

PR801

PR802

PR803

PR804

PR805

PR806

PR807

PR808

PR809

PR810

PR811

PR812
1

1
1.91K_0402_1%
1

2
PJ802

GPU_VID5

GPU_VID4

GPU_VID3

GPU_VID2

GPU_VID1

GPU_VID0

GPU_VID5

GPU_VID4

GPU_VID3

GPU_VID2

GPU_VID1

GPU_VID0
2 1
PR831

+VGA_COREP 2 1 +VGA_CORE
PR832
@ JUMP_43X118
2

1 2 PR833 @ @ @ @ @ @
100K_0402_5%
VRON_VGA

1 2 PJ803
GPU_VID6

[14] VGA_PWRGD 0_0402_5% +3VGS

2 1
2 1
@ JUMP_43X118
PSI#_VGA

PR834
147K_0402_1%
2 1

PR835
40
39
38
37
36
35
34
33
32
31

+3VGS @ 100K_0402_5% PU801

1 2
CLK_EN#

VID6
VID5
VID4
VID3
VID2
VID1
VID0
DPRSLPVR
VR_ON
RBIAS_VGA

1 2 30
[18,31] VGA_AC_DET BOOT2 29
PR836 @ 1 UGATE2 28
0_0402_5% 2 PGOOD PHASE2 27
PR837 470K_0402_5%_TSM0B474J4702RE 3 PSI# VSSP2 26
1 2 1 2 4 RBIAS LGATE2 25
5 VR_TT# VCCP 24
NTC PWM3 +5VS
4.02K_0402_1% PH801 VW_VGA 6 23
COMP_VGA 7 VW LGATE1 22
FB_VGA 8 COMP VSSP1 21
@ @ FB PHASE1
9
UGATE1

ISEN3
1

10 PC815
BOOT1
ISUM+
ISEN1

ISEN2
ISUM-
VSEN

IMON

1U_0603_10V6K
1000P_0402_50V7K
8.06K_0402_1%

VDD
RTN

VIN

41
249K_0402_1%

2
2

AGND
PR838 @

PC816
PR839

ISL62883CHRTZ-T_TQFN40_5X5
11
12
13
14
15
16
17
18
19
20

PR840
2

499_0402_1% PC817
ISUM-_VGA

1 2FB1_VGA1 2
VDD_VGA
1

RTN_VGA

3 3

390P_0402_50V7K
PC865 PR842 PR841 @ 0_0402_5%
33P_0402_50V8J 1.3K_0402_1% 1 2
+5VS
1 2 1 2 VSEN_VGA
PR843 0_0402_5%
7.87K_0402_1%
.047U_0402_16V7K

+VGA_B+
2

PR827 VIN_VGA 1 2
PR829
1

1 2
PC866

PR845

+5VS
1 2FB2_VGA1 2 PR846 1 2
0_0402_5% 1_0402_5% VGA_IMVP_IMON
2

PC867 PR844 1 2 1 2 +VGA_B+

PL802
1

0_0402_5%
1

150P_0402_50V8J 169K_0402_1% PR828 +5VS

1

1 2
PC826

PC827
1U_0603_10V6K

0.22U_0603_25V7K

0_0402_5% B+
PR847
FBMA-L11-453215800LMA90T_2P

@2200P_0402_50V7K
56K_0402_1%
2

BOOT1_VGA

68P_0402_50V8J

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
2

TPCA8065-H_SOP-ADV8-5

1
PC828
PQ804

PC844

PC829

PC830

PC831
PR864

2
VSUM+_VGA UGATE1_VGA 1 2 4
PR848
@ @
1 2 0_0603_5%
82.5_0402_5%

+VGA_COREP
PR849 @

PR850 PC832
1

2.2_0603_5% 0.22U_0603_10V7K

3
2
1
0_0402_5%
1

2 1 BOOT1_1_VGA 1 2
2.61K_0402_1%~N
PR851

PL801
0.36UH_PCMC104T-R36MN1R17_30A_20%
PR858
2

1 2 PHASE1_VGA 1 4
[21] VCCSENSE_VGA +VGA_COREP
2
2200P_0603_25V7K

0.22U_0603_25V7K
VSUM_VGA_N001
1

2 3
NTC_VGA

0_0402_5%
5

PC833
TPCA8057-H 1N PPAK56-8
1

1
PC834

PC835

3.65K_0402_1%
2

1
PR854

1_0402_1%
330P_0402_50V7K

4.7_1206_5%
PR853 @
PQ805

PR856

330U_D2_2V_Y

330U_D2_2V_Y

330U_D2_2V_Y

330U_D2_2V_Y
1 1 1 1
2

2
0.01U_0402_25V7K
PC840 @

4 + + + +

PC881

PC882

PC836

PC837
LGATE1_VGA
330P_0402_50V7K

SNUB1_VGA

2
1

1
PC839 @

11K_0402_1%

2
1

PR857

PC838 PH802
PR875 2 2 2 2
1000P_0402_50V7K 10K_0402_1%_TSM0A103F34D1RZ
4 1 2 4
[21] VSSSENSE_VGA
2

3
2
1
2

0_0402_5% VSUM+_VGA VSUM-_VGA

1

PR860
PR859
866_0402_1%
680P_0603_50V7K

1 2 1 2
PC841

VSUM-_VGA
2

0_0402_5% Layout Note:

@
Place near Phase1 Choke
1

PC842
.1U_0402_16V7K
Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2012/07/03 Deciphered Date 2013/07/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_COREP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 12, 2013 Sheet 44 of 51
A B C D E
 5 4 3 2 1

PC902 PR902
330P_0402_50V7K 2K_0402_1%
2 1 2 1
[7] APU_VDDNB_SEN PC903
PR903 PR904 @ PR905
3.4K_0402_1% 137K_0402_1%390P_0402_50V7K 32.4K_0402_1%
2 1 2 1 2 1 2 1
CPU_B+ PL902
PR906 PR907 PC904 PR908 PC905 FBMA-L18-453215-900LMA90T_1812
10_0402_5% 0_0402_5% 1000P_0402_50V7K 301_0402_1% 100P_0402_50V8J 2 1 B+
D D
2 1 2 1 2 1
<BOM Structure> 2 1 2 1
+APU_CORE_NB

10U_0805_25V6K

10U_0805_25V6K

2200P_0402_50V7K
0.01U_0402_25V7K
1 1

5
PC910

100U_25V_M

68U_25V_M
TPCA8065-H_SOP-ADV8-5

1
VSUMP_NB 1000P_0402_50V7K +

PC908

PC909

PC911

PC906
+

PC949
1
PC907
2.61K_0402_1%
10K_0402_5%_ERTJ0ER103J
1

2 1

PQ901

2
2 2
PR909

2
@ UGATE_NB1 4

0.1U_0402_25V6
0.047U_0402_16V7-K
2

11K_0402_1%

2
PR911
12
PH902

PC912

PC913

PL901
1

3
2
1
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
1

PR912
590_0402_1% PHASE_NB1 1 4
+APU_CORE_NB
2

VSUMN_NB 2 1 FCCM_NB

1
PR915 PC916 2 3

5
1

1
@ PR914 @ PC915 2.2_0603_5%
0.22U_0603_25V7K

PR913
0_0603_5%
PC914 100_0402_1% 220P_0402_50V7K BOOT_NB1 1 2 2 1 <BOM
PR916
Structure> PR919
0.1U_0603_50V7K 2 1 2 1 LGATE_NB1 4.7_1206_5% 3.65K_0402_1%
2

PR969 VSUMP_NB 2 1

TPCA8057-H_PPAK56-8-5
2
2 1 PHASE_NB1

1 2
10K_0402_1% LGATE_NB1 4 4 PR922
UGATE_NB1 @ <BOM
PC917
Structure> 1_0402_1%

PQ907
After rev1.1 must change to 133k PQ902 VSUMN_NB 2
680P_0603_50V7K 1
TPCA8057-H_PPAK56-8-5

2
3
2
1
48

47

46

45

44

43

42

41

40

39

38

37

3
2
1
2

PU901
<BOM Structure>
2

PR920 +APU_CORE_NB

ISEN1_NB

ISUMP_NB

ISUMN_NB

VSEN_NB

FB_NB

COMP_NB

PGOOD_NB

FCCM_NB

PWM2_NB

LGATEX

PHASEX

UGATEX
133K_0402_1% PC919 PR923
1000P_0402_25V6K 10_0402_5% CPU_B+ Iocp=39A
1

+5VS
2 1 1 36 BOOT_NB1
1

PR921 27.4K_0402_1% ISEN2_NB BOOTX PR924

2 1 2 35 2 1
NTC_NB VIN
PH901 3 34 BOOT2 0_0603_5%
IMON_NB BOOT2

1
470K_0402_5%_TSM0B474J4702RE PR901 0_0402_5%
C 2 1 2 1 SVC 4 33 UGATE2 PC920 PR972 C
[38,7] H_PROCHOT# [7] APU_SVC SVC UGATE2 CPU_B+
PR925 0_0402_5% 0.22U_0603_25V7K 0_0603_5%

2
2 1 5 32 PHASE2 2 1
VR_HOT_L PHASE2 +5VALW
1

PR927 0_0402_5%
PR926 2 1 SVD 6 31 LGATE2 PR973

10U_0805_25V6K

10U_0805_25V6K

2200P_0402_50V7K
0.01U_0402_25V7K
[7] APU_SVD SVD LGATE2
10.5K_0402_1% PR929 0_0402_5% ISL6277HRTZ-T_TQFN48_6X6 0_0603_5%
+1.5VS 2 1 VDDIO 7 30 2 1
PR930 0_0402_5% VDDIO VDDP PR931 +5VS
2

1
2 1 SVT 8 29 2 1

PC921

PC923

PC922

PC924
[7] APU_SVT SVT VDD

5
PR933 0_0402_5% 1_0603_5%

1U_0603_16V6K

TPCA8065-H_SOP-ADV8-5
2 1 ENABLE 9 28
[31,42] VR_ON

2
ENABLE PWM_Y

1
After rev1.1 must change to 133k PR932 0_0402_5%

1U_0603_16V6K
2 1PWROK 10 27

PQ903
PR934 LGATE1

PC926
[12,7] APU_PWRGD PWROK LGATE1
133K_0402_1%

PC925
2

2
1 2 11 26 PHASE1 UGATE1 4
IMON PHASE1
PC927 PR968 0_0402_5% 12 25 UGATE1
NTC UGATE1

PGOOD
1000P_0402_25V6K 2 1 PL903

BOOT1
ISUMN
ISUMP

[14] FCH_PWRGD COMP

2

ISEN3

ISEN2

ISEN1

VSEN

1 2 @ +3VS 0.36UH_VMPI1004AR-R36M-Z03_30A_20%
RTN

3
2
1
FB2

+5VS
FB

TP
PR971 PHASE1 1 4
PR936 27.4K_0402_1% 0_0402_5% PR938 +APU_CORE
13

14

15

16

17

18

19

20

21

22

23

24

49

1
2 1 0_0402_5% PR941 PC928 ISEN1 2 PR937 1 2 3 1 2 ISEN2
1

5
2 1 ISEN3 2.2_0603_5% 0.22U_0603_25V7K 10K_0402_1%

1
PH903 PR939 BOOT1 1 2 2 1 <BOM
PR943
Structure> PR940
470K_0402_5%_TSM0B474J4702RE 2 1 ISEN2 BOOT1 100K_0402_5% 4.7_1206_5% PR944 10K_0402_1%
2 1 PR942 3.65K_0402_1%

2
10_0402_5% ISEN1 VSUM+ 2 1
1

LGATE1 4
0.22U_0402_10V6K

0.22U_0402_10V6K

1 2
1

[31] APU_IMON PR970 VGATE [14,31] <BOM

PC931
Structure>
1

PR945 10K_0402_1% PQ904 680P_0603_50V7K PR946

10.5K_0402_1% PC932 TPCA8057-H_PPAK56-8-5 1_0402_1%
@ 10P_0402_25V8K VSUM- 2 1
2

3
2
1

2
2 1
PC929

PC930

<BOM Structure>
2

VSUM-
CPU_B+

VSUM+
B B
PC933 PR948 PC934 PR949 +APU_CORE
2.61K_0402_1%

10U_0805_25V6K

10U_0805_25V6K

2200P_0402_50V7K
0.01U_0402_25V7K
1

1000P_0402_50V7K301_0402_1% 100P_0402_50V8J 32.4K_0402_1%

10K_0402_5%_ERTJ0ER103J

Iocp=60A

5
2 1 2 1 2 1 2@ 1
PR947

<BOM Structure>
330P_0402_50V7K
0.082U_0402_16V7K

0.22U_0402_10V6K

TPCA8065-H_SOP-ADV8-5
2

1
PC938

PC939

PC940

PC941
2

PQ905
PR951 PR952 PC942
11K_0402_1%
12

2.94K_0402_1% 137K_0402_1% 390P_0402_50V7K

PR950

PC935

PC936

PC937
PH904

2
2 1 2 1 2 1 UGATE2 4
1

<BOM Structure> <BOM Structure>

1

PR955
604_0402_1% PR954 PC943
2

VSUM- 2 1 2K_0402_1% 680P_0402_50V7K PL904

3
2
1
2 1 2 1 0.36UH_VMPI1004AR-R36M-Z03_30A_20%
PC944
1

PR957 820P_0402_50V7K PHASE2 1 4

PC946 100_0402_1% PR956 +APU_CORE
0.1U_0603_50V7K 2 1 2 1 10_0402_5% PR960 PC945 ISEN2 2 PR958 1 2 3 1 2 ISEN1
2

1
2 1 +APU_CORE 2.2_0603_5%
0.22U_0603_25V7K 10K_0402_1%
@ @ PR962 BOOT2 1 2 2 1 <BOM
PR961
Structure> PR959
0_0402_5% 4.7_1206_5% PR963 10K_0402_1%
2 1 APU_VDD_SEN_H [7] 3.65K_0402_1%
VSUM+ 2 1

1 2
LGATE2 4
PR964 <BOM
PC947
Structure>
0_0402_5% PQ906 680P_0603_50V7K PR965
2 1 TPCA8057-H_PPAK56-8-5 1_0402_1%
0.01U_0402_25V7K

2
PR966 APU_VDD_SEN_L [7] VSUM- 2 1

3
2
1
10_0402_5%
<BOM Structure>
2

2 1
PC948
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/04/18 Deciphered Date 2015/07/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_COREP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 12, 2013 Sheet 45 of 51
5 4 3 2 1
 A
B
C
D

@
PC1012 PC1001
22U_0603_6.3V6K 22U_0603_6.3V6K

2
1
2
1

+
+
2 1 2 1
PC1026 PC1022
330U_D2_2VM_R7M 330U_D2_2VM_R9M

5
5

+APU_CORE
+APU_CORE

PC1017 PC1013 PC1002

22U_0603_6.3V6K 22U_0603_6.3V6K 22U_0603_6.3V6K
2 1 2 1 2 1

2
1
+
PC1023
330U_D2_2VM_R9M

@
PC1018 PC1014 PC1003
22U_0603_6.3V6K 22U_0603_6.3V6K 22U_0603_6.3V6K
2 1 2 1 2 1

2
1
+
PC1024
330U_D2_2VM_R9M
@

PC1019 PC1015 PC1004

22U_0603_6.3V6K 22U_0603_6.3V6K 22U_0603_6.3V6K
2 1 2 1 2 1

2
1
+
PC1025
330U_D2_2VM_R9M

4
4

PC1016 PC1005
22U_0603_6.3V6K 22U_0603_6.3V6K
2 1 2 1
+CPU_CORE

Issued Date
Security Classification
PC1006

3
3

22U_0603_6.3V6K
PC1027 2 1
2
1
+

22U_0603_6.3V6K
2 1 PC1020 PC1007
330U_D2_2VM_R7M 22U_0603_6.3V6K
2 1

PC1028 PC1008
2
1
+

2011/04/18
10U_0603_6.3V6K 22U_0603_6.3V6K
+1.2VS

2 1 PC1021 2 1
330U_D2_2VM_R7M
PC1029 PC1009
+APU_CORE_NB

10U_0603_6.3V6K 22U_0603_6.3V6K
@

2 1 2 1
+1.2VS

PC1030 PC1010
10U_0603_6.3V6K 10U_0603_6.3V6K
2 1 2 1

PC1031 PC1011
10U_0603_6.3V6K 22U_0603_6.3V6K
2 1 2 1

PC1032
10U_0603_6.3V6K
Compal Secret Data
Deciphered Date
2 1

PC1033
+CPU_CORE_NB

10U_0603_6.3V6K
2 1

2
2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A3
Size
Title

Date:
Document Number

Tuesday, March 12, 2013

1
1

Sheet
46
of
Compal Electronics, Inc.

51
PROCESSOR DECOUPLING
Rev
1.0
A
B
C
D
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 1

for PWR
Item Reason for change PG# Modify List Date Phase

1 Base on EE's request for fine tune power sequence. P44 Change PR866 from 2.49k to 130k. 2013.1.11 From 0.1 to 0.2

D D
2 For fine tune OCP set up point of VGA core. P44 Change PR860 from 604ohm to 866ohm. 2013.1.11 From 0.1 to 0.2

3 Base on EE's request for fine tune power sequence. P44 Change PR861 from 47k to 91k. 2013.1.11 From 0.1 to 0.2

Remove PR110, PC108, PR114, PC109, PR109, PC107,PU101, PR111, PD101, PR138, PR116, PR112, PD105,
4 Base on must meet EUP spec, change power design. P37 PR125, PR128, PC114, PR129, PQ101, PD104, PR123, PR124, PC115, PR131, PC117, PR103, PR104, PR105, 2013.1.11 From 0.2 to 0.3
PD102, PQ102, PR106, PR107, PQ103, PQ104, PR108, PR118, PR121, PC113, PR127, PQ106, PQ105, PR120,
PR115, PC110, PC112, PR126, PR119, PR122, PD103.

5 Base on must meet EUP spec, change power design. P39 RemovePQ315, PR328, PR329, PQ316, PD304, PD301, PD302, PQ303, PR303, PR304, PQ306, PQ309. 2013.1.11 From 0.2 to 0.3

6 Base on must meet EUP spec, change power design. P39 Add PR336, PR338, PR337, PR339, PQ319. 2013.1.11 From 0.2 to 0.3

Remove PR417, PC420, PQ407, PR420, PC424.

Base on must meet EUP spec, change power design. P40 2013.1.11 From 0.2 to 0.3
7 Add PR411.
Change PR418 from 47K to 2.2K.

8
C C
9

10
11

12

13

14
15

16
B B

17

18

19

20

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/04/18 Deciphered Date 2015/07/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (PWR)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C38-G series Chief River Schematic1.0
Date: Tuesday, March 12, 2013 Sheet 47 of 51
5 4 3 2 1
 5 4 3 2 1

Phase Date No. BOM Sch Layout Description

SDV/FVT 2012/11/22 No.1 V V V Page 5, Delete for Sun Pro M2

C17,C18,C19,C20,C21,C22,C23,C24,C25,C26,C27,C28,C29,C30,C31,C32
Delete PCIE_CRX_GTX_P8~15 PCIE_CTX_C_GRX_P8~15 PCIE_CTX_GRX_P8~15
PCIE_CRX_GTX_N8~15 PCIE_CTX_C_GRX_N8~15 PCIE_CTX_GRX_N8~15

SDV/FVT 2012/11/22 No.2 V V V Page 17, Delete for Sun Pro M2

C1400,C1417,C1418,C1419,C1420,C1421,C1422,C1423,C1424,C1425,C1426,C1427,C1428,C1429,C1430,C1431
Delet PCIE_CRX_C_GTX_P8~15
PCIE_CRX_C_GTX_N8~15
D D
SDV/FVT 2012/11/22 No.3 V V V Page 17 ,U1401 change Part Number from SA000047H50 to SA00006BA30 for Sun Pro M2
SDV/FVT 2012/11/22 No.4 V V V Page 24, Delete for Sun Pro M2 no Channel B
C1621,C1622,C1623,C1624,C1625,C1626,C1627,C1628,C1629,C1630,C1631,C1632,C1633,C1634,C1635,R1462,R1463
C1636,C1637,C1638,C1639,C1640,C1641,C1642,C1643,C1644,C1645,C1646,C1647,C1648,C1649,C1650,R1464,R1465
C1651,C1652,C1653,C1654,C1655,C1656,C1657,C1658,C1659,C1660,C1661,C1662,C1663,C1664,C1665,C1569
C1666,C1667,R1504,R1504,R1505,R1505,R1506,R1507,R1508,R1509,R1510,R1510,R1511,R1511,R1512,C1570
R1513,R1514,R1515,R1516,R1517,R1518,R1519,R1520,R1521,R1522,R1523,R1524,R1525,R1526,R1527,U1409,U1410,U1411,U1412

SDV/FVT 2012/11/22 No.5 V V Page 19, Reserved T1406,T1407 for Sun Pro M2
SDV/FVT 2012/11/22 No.6 V V V Page 18, Reserved D1401 for Sun Pro M2 PX5.5
SDV/FVT 2012/11/22 No.7 V V V Page 19, Delete PX4.0 and PX5.0 schematic
C1459,C1460,C1461,C1462,C1463,D1400,Q1401,Q1402,Q1403A,Q1403B,Q1404,Q1405,Q1406,R1401,R1438,R1439,,R1440,
R1442,R1460,R1461,U1402,U1403
SDV/FVT 2012/11/22 No.8 V V V Page 20, Delete DGPU Display Power not need reserved
C1472,C1473,C1474,C1475,C1477,C1478,C1479,C1480,C1481,C1482,C1483,C1484,C1487,C1488
SDV/FVT 2012/11/22 No.9 V V V Page 20, L1405 change Part Number from SM010009U00 to SM01000AX00 for Sun Pro M2 Spec Suggetion 120 to 220 ohm
SDV/FVT 2012/11/22 No.10 V V V Page 20, Delete R1457,R1458 ,Because the Sun Pro M2 AW28,AW18 are NC.
SDV/FVT 2012/11/22 No.11 V V V Page 20, Delete Thames&Seymour reserved
R1407,R1408,R1409,R1410,R1411,R1412,R1413,R1414,R1415,R1416,R1417,R1466,R1467,R1468,R1469,R1471
SDV/FVT 2013/1/10 No.12 X V V Page 12 U2 change Part Number from SA000066K10 to SA000066K60
SDV/FVT 2013/1/10 No.13 V V Page 31, for Power Eulot 6 modfiy
C C
Delete net FSTCHG,BATT_LEN#
SDV/FVT 2013/1/11 No.14 X V V Page 18, for fine tune VGA Power saving
Stuff C1441
SDV/FVT 2013/1/11 No.15 X V V Page 19, for fine tune VGA Power Sequence
R1445 change value from 20K to 470K
R1446 change value from 20K to 10K

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/22 Deciphered Date 2015/11/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EE modify list
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8126P
Date: Tuesday, March 12, 2013 Sheet 48 of 51
5 4 3 2 1
 5 4 3 2 1

Phase Date No. BOM Sch Layout Description

SIT 2013/1/10 No.1 V V V Page 35, for Power Eulot 6 modfiy

Un-Stuff @ Q2408,R2463
SIT 2013/1/10 No.2 V V V Page 33, for Touch Pad Module requirment
Stuff R2470
SIT 2013/2/1 No.3 V V V Page 07, for APU_SID and APU_SIC voltage smothly
Stuff C69
SIT 2013/2/1 No.4 V V V Page 26, for Logo LED brightness change Resistor Valve from 4.99K to 1.6K
D SIT 2013/2/20 No.5 V V Page 36, for delete Discharge circuit ,remove R2324,Q2314,R2321,Q2309 D

SIT 2013/3/05 No.6 V V Page 33, for Factory issue ,remove JBT1
SIT 2013/3/12 No.7 V V V Page 25, for cost down ,not need reserved for EC ,non-stuff Q2107,R2177,R2178
SIT 2013/3/12 No.8 V V V Page 36, for customer request , Stuff R2302,R2303,Q2300,Q2302

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/22 Deciphered Date 2015/11/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EE modify list
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8126P
Date: Tuesday, March 12, 2013 Sheet 49 of 51
5 4 3 2 1
 5 4 3 2 1

Phase Date No. BOM Sch Layout Description

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/22 Deciphered Date 2015/11/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EE modify list
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8126P
Date: Tuesday, March 12, 2013 Sheet 50 of 51
5 4 3 2 1
 5 4 3 2 1

Phase Date No. BOM Sch Layout Description

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/22 Deciphered Date 2015/11/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
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AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8126P
Date: Tuesday, March 12, 2013 Sheet 51 of 51
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