VLSI

DEVICE MODELLING
ENP 302
ASSIGNMENT-02

Submitted by:
Domatoti Vinay Kumar
BT18ECE082

Submitted to:
Sumedh Ramteke (Course Instructor)
Dr. Ganesh C Patil (Course Co-ordinator)
Q1)
Problem Statement : Simulate the clipper circuit which clips the voltage above +3V and
Below -3V using NGSPICE.

Circuit Diagram:

Code:

*Dual diode clipper +3V & 3V

V1 n1 0 sin(0 5 1k)

R1 n1 n2 1

.model Diode D

D1 n2 n3 Diode

V2 n3 0 2.3

D2 n4 n2 Diode

V3 0 n4 2.3

.control

Tran 0.01ms 5ms

Set Xbrushwidth =3

Plot V(n2) V(n1)

.endc

.end
Output:

Conclusion:

● For an ideal diode, the clipping occurs at the level of the clipping voltage, V2
and V3.But, due to the 0.7V forward drop of the silicon diodes, clipping occurs
at an additional 0.7V.
● Hence, we apply 2 DC voltage sources of 2.3 V each. When D1 conducts, D1
clips at 2.3+0.7 =3V. And, when D2 conducts D2 clips at -0.7-2.3V= -3V.
Q2)
Problem Statement : SImulate the Voltage Tripler Circuit using NGSPICE?

Circuit Diagram:

Code:
*tripler
v1 n1 0 sin(0 4 0.7k)
c1 n1 n2 1nF
c2 0 n3 1nF
C3 n2 n4 1nF

D1 n2 0 Diode
D2 n3 n2 Diode
D3 n4 n3 Diode
.model Diode D
.tran 1u 40m
.control
Run
Set Xbrushwidth = 2
plot v(n1) v(n1,n4)
.endc
.end
Output:

Observations & Conclusion:

● It can observed from the graph the tripled voltage value(shown by red), but due to
the diode voltages it comes out to be approximately greater than 11 but not 12
exactly, which is the desired voltage.
Q3)
Problem Statement : Simulate the Clamper Circuit which Clamps the Voltage above the
-9V with peak to peak voltage 20V using NGSPICE.

Circuit Diagram:

Code:

Series positive clamper

V1 n1 0 SIN(0 10 1kHz)

D1 n3 n2 D

V2 0 n3 0.4

R1 n2 0 1k

C1 n1 n2 100uF

.model D D

.CONTROL

TRAN 0.01ms 10ms

Set Xbrushwidth=2

PLOT V(n1)

PLOT V(n2)

.ENDC

.END
Output:

Input waveform and output waveform are represented by green and red graphs respectively.

Observation &Conclusion:
● It can be observed from the above graph, the voltage graph above -9V is clamped
with peak to peak 20V.
Q4a)
Problem Statement : Simulate the Boolean Functions Given below using NGSPICE.
(a) A+BC
Circuit Diagram:

Code:
* A + BC
.model vinaybjt npn is=1e-15
Vdc dc 0 9

Vb n1 0 PULSE(0 2 1us 1us 1us 5ms 10ms)

Vc n2 0 PULSE(0 2 1us 1us 1us 10ms 20ms)
Va n3 0 PULSE(0 2 1us 1us 1us 15ms 30ms)

Rb n1 b1 1k
Rc n2 b2 1k
Ra n3 b3 1k

Q1 dc b1 c1 vinaybjt
Q2 c1 b2 out1 vinaybjt
R1 out1 0 1k
Q3 dc out1 out vinaybjt
Q4 dc b3 out vinaybjt
R2 out 0 1000K

.tran 1ms 100ms

.control
run
Set Xbrushwidth=2
plot v(n1) v(n2)+4 v(n3)+8 v(out)+14
.endc
.end

Output:

Green -B, Red - C, Blue- A, Yellow - A+BC

Q4b)
Problem Statement : Simulate the Boolean Functions Given below using NGSPICE.
(b) A+B+C

Circuit Diagram:

Code:
4b)

A+B+C

V1 n1 0 PULSE(0 3 1us 1us 1us 5ms 10ms)

V2 n2 0 PULSE(0 3 1us 1us 1us 10ms 20ms)

V3 n3 0 PULSE(0 3 1us 1us 1us 15ms 30ms)

D1 n1 n4 diode

D2 n2 n4 diode

D3 n3 n4 diode

R1 0 n4 1k

.model diode D

.tran 10us 100ms

.control

run

Set Xbrushwidth=2

plot V(n1) V(n2)+5 V(n3)+10 V(n4)+15

.endc

.end
Output:

Green -A, Red - B, Blue- C, Yellow - A+B+C

Observations & conclusion:

● The Boolean expression A+B+C can be observed in the graph(Yellow), and it

matches exactly with the Truth Table.
● Whereas, due to some errors made, The Boolean Expression A+BC pulse does’nt
exactly match with the truth table.