NAME: - Tushar Vithoba Bhadrike

ROLL NO: - 03

UID: - 121CP3292A

COMPUTER BRANCH
SUBJECT: - Digital Logic & Computer Organization and Architecture

Experiment no 2

❖ Aim
To implement Booth’s algorithm.

❖ Objective:
i. To design Booth's multiplier with a controller and a datapath. This
will also help in the learning of control unit design as a finite state
machine
ii. To understand the advantages of Booth's multiplier
iii. It can handle signed integers in 2's complement notion
iv. It decreases the number of addition and subtraction
v. It requires less hardware than combinational multiplier
vi. It is faster than straightforward sequential multiplier

❖ Theory

Booth's Multipliers:
Booth's multiplication algorithm is an algorithm which multiplies 2 signed integers in 2's
complement. The algorithm is depicted in the following figure with a brief description. This
approach uses fewer additions and subtractions than more straightforward algorithms.
The multiplicand and multiplier are placed in the m and Q registers respectively. A 1-bit
register is placed logically to the right of the LSB (least significant bit) Q0 of Q register. This
is denoted by Q-1. A and Q-1 are initially set to 0. Control logic checks the two bits Q0 and
Q-1. If the two bits are same (00 or 11) then all of the bits of A, Q, Q-1 are shifted 1 bit to the
right. If they are not the same and if the combination is 10 then the multiplicand is subtracted
from A and if the combination is 01 then the multiplicand is added with A. In both the cases
results are stored in A, and after the addition or subtraction operation, A, Q, Q-1 are right
shifted. The shifting is the arithmetic right shift operation where the left most bit namely, An-
1is not only shifted into An-2 but also remains in An-1. This is to preserve the sign of the
number in A and Q. The result of the multiplication will appear in the A and Q

Design Issues:
Booth's algorithm can be implemented in many ways. This experiment is designed using a
controller and a Datapath. The operations on the data in the Datapath is controlled by the
control signal received from the controller. The Datapath contains registers to hold multiplier,
multiplicand, intermediate results, data processing units like ALU, adder/subtractor etc.,
counter and other combinational units. Following is the schematic diagram of the Booth's
multiplier which multiplies two 4-bit numbers in 2's complement of this experiment. Here the
adder/subtractor unit is used as data processing unit. M, Q, A are 4-bit and Q-1 is a 1-bit
register. M holds the multiplicand, Q holds the multiplier, A holds the results of
adder/subtractor unit. The counter is a down counter which counts the number of operations
needed for the multiplication. The data flow in the data path is controlled by the five control
signals generated from the controller. these signals are load (to load data in registers), add (to
initiate addition operation), sub (to initiate subtraction operation), shift (to initiate arithmetic
right shift operation), dc (this is to decrement counter). The controller generates the control
signals according to the input received from the Datapath. Here the inputs are the least
significant Q0 bit of Q register, Q-1 bit and count bit from the down counter.
 ❖ Procedure

Booth's Multipliers:
Procedure to perform the experiment on the given working module which multiplies two 4-
bit numbers
Start the simulator as directed.This simulator supports 5-valued logic.
To perform the experiment on the given modules, we need the datapath specified for booth's
multiplication, a controller with a specified state chart, a clock input, bit switch (to give input,
which will toggle its value with a double click), bit displays (for seeing output), wires.
Instantiating the controller: A control unit can be seen as a finite state machine, so its
behavior can be represented in a state table. The controller of the simulator accepts the Moore
type state chart and must contain an end state. State names will automatically be generated in
the form of S<sub<n< sub="">. In the left pane of the simulator, click on the ASM chart
button in the controller subsection. Give the required informations in the appeared form as
follows:
Number of states: 7
Number of inputs: 3
Number of outputs: 5
The controller will generate 5 output control signals. After entering these information’s, the
second form will appear where you can set the names of the inputs and outputs. Here inputs
are the Q0, Q-1, count. Outputs control signals are load, add, sub, shift, dc. The order of
given input/outputs are maintained while creating terminals of the controller. for example, the
first output signal will appear in the left most output terminal (lower terminals), second
output will appear in the second left most bit and so on. In case of input terminals, the left
most bit is for clock input, so the first input appears in the second terminal, and then the order
is maintained. Then the third form will appear where you actually specify the state chart i.e.
state, outputs of that state and transition conditions . The fields of the chart will be generated
dynamically according to previously given information on states, inputs and outputs.After
entering the following state chart, click on the controller component in the palette of the
simulator then click on the position of the design editor where you want to put the component
(no drag and drop, simple click will serve the purpose).

</sub<n<>
Instantiate the Booth's multiplier datapath from the sequential ckt drawer in the palette (by
clicking as mentioned previously).
The pin configuration of the component is shown whenever the mouse is hovered on any
canned component of the palette or pressing the show pin configuration button on the toolbar
will show it constantly in the left pane. Pin numbering starts from 1 and from the bottom left
corner(indicating with the circle) and increases anticlockwise.
Pin configuration of the datapath module:
M : Multiplicand (4 bit), Q : Multiplier (4 bit)
Initialization : Inl:1, preset:1, set M, Q, start clock
Starting multiplication: Inl:0, preset:0, start clock
Result: FQ0 to FA3, at end state (here it is S6). These are the content of A(4bit) and Q(4bit)
register, total 8 bit (FQ0 is LSB, FA3 is MSB)
I/P:
Clk:32, Inl:31, preset:30
Control pins: load:29, add:28, sub:27, shift:26, dc:25
Multiplicand: M3 : 24, M2 : 23, M1 : 22, M0 : 21
Multiplier: Q3 : 20, Q2 : 19, Q1 : 18, Q0 : 17
O/P: FQ-1 is output of Q-1 bit register, similarly FQ0 to FQ3 are for Q register and FA0 to
FA3 are for A register.
Datapath to controller input: Count, clkToController, FQ-1, FQ0
Count : 16, clkToController : 15, FQ-1 : 14, FQ0 : 13
FQ1 : 12, FQ2 : 11, FQ3 : 10
FA0 : 9, FA1 : 8, FA2 : 7, FA3 : 6
To connect any two components select the Connection menu of Palette, and then click on the
Source terminal and click on the target terminal. According to the following diagram connect
all the components. Connect the controller outputs to the specified control input terminals of
the datapath, specified datapath outputs to the inputs of the controller, the clock input, Bit
switches with the inputs and Bit displays component with the outputs (from Display and
Input drawer of the pallet,if it is not seen scroll down in the drawer). After the connection is
over click the selection tool in the pallete.
At first initialize the multiplier by giving the specified inputs specified earlier, this will load
the multiplier and multiplicand, then start the multiplication operation by giving the specified
inputs specified earlier. At the end state (S6), the multiplication result will be seen through
ports FQ0 to FA3 (FQ0 is LSB, FA3 is MSB). The current state of the controller is shown in
the left pane as it transits from one state to another. The controller can be reset by clicking
the reset controller button in the top toolbar, to start with a new input.
Circuit diagram of 4 bit Booth's Multiplier:

The combinational logic between the control signals of the controller and the control pins of
the registers are to satisfy different operational conditions of individual components. In this
design, the controller controls only the multiplication process, the initialization has been
seperated, so a multiplexer is used to the clock port of the controller to deactivate ot during
initialization. Except M, A, Q, Q-1 registers one more 4-bit register has been used which
works as temporary storage. With the preset, the down counter is set to all one which is then
decremented. The controller state chart is designed in such a way that at each state it activates
only one control signal. The controller of this circuit behaves according to the state chart
shown in the procedure section of this experiment. A and Q will hold the final multiplication
result.
Components:
To build the 4 bit Booth's multiplier, we need:
Controller
Registers, Adder/subtractor unit, multiplexer, down counter, logic gates to construct the
Datapath
Inputs
Outputs
Wires to connect

❖ Program:
class GFG
{

// function to perform adding in the accumulator

static void add(int ac[], int x[], int qrn)
{
int i, c = 0;

for (i = 0; i < qrn; i++)

{

// updating accumulator with A = A + BR

ac[i] = ac[i] + x[i] + c;

if (ac[i] > 1)
{
ac[i] = ac[i] % 2;
c = 1;
}
else
{
c = 0;
}
}
}

// function to find the number's complement

static void complement (int a [], int n)
{
int i;
int[] x = new int[8];
x[0] = 1;

for (i = 0; i < n; i++)

{
a[i] = (a[i] + 1) % 2;
}
add(a, x, n);
}

// function ro perform right shift

static void rightShift(int ac[], int qr[],
int qn, int qrn)
{
int temp, i;
temp = ac[0];
qn = qr[0];

System.out.print("\t\trightShift\t");

for (i = 0; i < qrn - 1; i++)

{
ac[i] = ac[i + 1];
qr[i] = qr[i + 1];
}
qr[qrn - 1] = temp;
}

// function to display operations

static void display(int ac[], int qr[], int qrn)
{
int i;

// accumulator content
for (i = qrn - 1; i >= 0; i--)
{
System.out.print(ac[i]);
}
System.out.print("\t");

// multiplier content
for (i = qrn - 1; i >= 0; i--)
{
System.out.print(qr[i]);
}
}

// Function to implement booth's algo

static void boothAlgorithm(int br[], int qr[], int mt[],
int qrn, int sc)
{

int qn = 0;
int[] ac = new int[10];
int temp = 0;
System.out.print("qn\tq[n+1]\t\tBR\t\tAC\tQR\t\tsc\n");
System.out.print("\t\t\tinitial\t\t");
display(ac, qr, qrn);
System.out.print("\t\t" + sc + "\n");

while (sc != 0)
{
System.out.print(qr[0] + "\t" + qn);

// SECOND CONDITION
if ((qn + qr[0]) == 1)
{
if (temp == 0)
{

// subtract BR from accumulator

add(ac, mt, qrn);
System.out.print("\t\tA = A - BR\t");

for (int i = qrn - 1; i >= 0; i--)

{
System.out.print(ac[i]);
}
temp = 1;
}

// THIRD CONDITION
else if (temp == 1)
{
// add BR to accumulator
add(ac, br, qrn);
System.out.print("\t\tA = A + BR\t");

for (int i = qrn - 1; i >= 0; i--)

 {
System.out.print(ac[i]);
}
temp = 0;
}
System.out.print("\n\t");
rightShift(ac, qr, qn, qrn);
}

// FIRST CONDITION
else if (qn - qr[0] == 0)
{
rightShift(ac, qr, qn, qrn);
}

display(ac, qr, qrn);

System.out.print("\t");

// decrement counter
sc--;
System.out.print("\t" + sc + "\n");
}
}

static void reverse(int a[])

{
int i, k, n = a.length;
int t;
for (i = 0; i < n / 2; i++)
{
t = a[i];
 a[i] = a[n - i - 1];
a[n - i - 1] = t;
}
}

// Driver code
public static void main(String[] args)
{
int[] mt = new int[10];
int sc;
int brn, qrn;

// Number of multiplicand bit

brn = 4;

// multiplicand
int br[] = {0, 1, 1, 0};

// copy multiplier to temp array mt[]

for (int i = brn - 1; i >= 0; i--)
{
mt[i] = br[i];
}

reverse(br);

complement(mt, brn);

// No. of multiplier bit

qrn = 4;

// sequence counter
 sc = qrn;

// multiplier
int qr[] = {1, 0, 1, 0};
reverse(qr);

boothAlgorithm(br, qr, mt, qrn, sc);

System.out.print("\n"
+ "Result = ");

for (int i = qrn - 1; i >= 0; i--)

{
System.out.print(qr[i]);
}
}
}

Output:
Conclusion: Hence we have implemented, simulated, analyzed 4 bit Booth’s Multiplier.

Industrial Application: 4 bit Booth’s Multiplier is used in many high performance

systems such as calculators, digital signal processing applications, filters, microprocessors, etc.
Performance of any system is generally determined by the performance of the multiplier used
in it because the multiplier is generally the slowest element in any system.

QUESTIONNAIRE

Que 1. Which of the following gives best performance with Booth's algorithm?

1. 0000 1111

2. 1111 0000

3. 1111 1111

4. 1010 1010

Que 2. Booth's algorithm is faster due to less number of addition and subtraction and
can handle signed numbers.

1. True

2. False

Que 3. Booth's algorithm increases space in case of fixed point signed multiplication

1. True

2. False

Que 4. 2's complement of 7 is?

1. 11100

2. 11001

3. 10111

4. 10100

Que 5. Sign extension is a step in

1. Arithmetic left shift

2. Signed 16 bit integer addition

 3. Floating point multiplication

4. None of these

Que 6. In which notation, 0 has two representations?

1. Sign magnitude

2. 1's complement

3. 2's complement

4. None of these

Que 7. What is the difference between combinational multiplier and Booth's multiplier?

In booth multiplier number of gates is reduced and hence area of booth multiplier is less than
combinational multiplier. However Combinational Multiplier gives optimum number of
components required. Hence for less delay requirement Booth's multiplier is suggested.
Que 8. Why Booth's multiplier is faster than other approaches like shift and add
multiplier?

Booth used desk calculators that were faster at shifting than adding and created the
algorithm to increase their speed. Booth’s algorithm is of interest in the study of computer
architecture.

Que 9. How Booth's multiplier handles the signed integer while others cannot?

Booth algorithm gives a procedure for multiplying binary integers in signed 2’s
complement representation in efficient way, i.e., a smaller number of additions/subtractions
required. It operates on the fact that strings of 0’s in the multiplier require no addition but
just shifting and a string of 1’s in the multiplier from bit weight 2^k to weight 2^m can be
treated as 2^ (k+1) to 2^m.

Que 10. Prove that the multiplication of two m-bit numbers in base R gives a product of
no more than 2m digits
It can be simply concluded using examples:

11*11(since 11 is the maximum 2-bit number) =1001(4 bit)

111*111=110001(6 bit)

1111*1111=11100001(8 bit)

11111*11111=1111000001(10 bit)
and so, from above we can see your answer is 2*m
❖ References
1. Computer Architecture and Organization - John P. Hayes
2. Computer Organization and Architecture - William Stallings
3. Digital Logic and Computer Design - M. Morris Mano. Pearson Education - Prentice
Hall.
4. Digital Principles Foundation of Circuit Design and Application - Arun Kumar Singh.
New Age Publishers.
5. The Art of Electronics - Paul Horowitz and Winfield Hill (1989). Cambridge
University Press
6. Modern Dictionary of Electronics - Rudolf F. Graf (1999). Newness

The End