Professional Documents
Culture Documents
سرویس منوال
سرویس منوال
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD
REV ECN DESCRIPTION OF REVISION
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
8 0006400877 ENGINEERING RELEASED 2016-06-14
QQ :
<CSA_PAGE5> <SYNC_DATE5> <CSA_PAGE50> <SYNC_DATE50>
5 SYSTEM:BOARDID <SYNC_MASTER5> 50 spare <SYNC_MASTER50>
<CSA_PAGE6> <SYNC_DATE6> <CSA_PAGE51> <SYNC_DATE51>
6 spare <SYNC_MASTER6> 51 spare <SYNC_MASTER51>
<CSA_PAGE7> <SYNC_DATE7> <CSA_PAGE52> <SYNC_DATE52>
7 SOC:JTAG,USB,XTAL <SYNC_MASTER7> 52 MLB UNIQUE <SYNC_MASTER52>
196627811,
<CSA_PAGE8> <SYNC_DATE8> <CSA_PAGE53> <SYNC_DATE53>
8 SOC:PCIE <SYNC_MASTER8> 53 CELL,WIFI,NFC <SYNC_MASTER53>
<CSA_PAGE9> <SYNC_DATE9> <CSA_PAGE54> <SYNC_DATE54>
9 SOC:MIPI AND ISP <SYNC_MASTER9> 54 WIFI_MLB SCHEMATIC <SYNC_MASTER54>
<CSA_PAGE10> <SYNC_DATE10> <CSA_PAGE55> <SYNC_DATE55>
10 SOC:LPDP <SYNC_MASTER10> 55 PERENNIAL <SYNC_MASTER55>
11
12
<CSA_PAGE11>
<CSA_PAGE12>
SOC:SERIAL
SOC:GPIO & UART
<SYNC_MASTER11>
<SYNC_MASTER12>
笔记本台板
<SYNC_DATE11>
<SYNC_DATE12>
56
57
<CSA_PAGE56>
<CSA_PAGE57>
WIFI FRONT-END [77]
page1
<SYNC_MASTER56>
<SYNC_MASTER57>
<SYNC_DATE56>
<SYNC_DATE57>
C
14
<CSA_PAGE14>
SOC:POWER (1/3) <SYNC_MASTER14>
手机工控电
<SYNC_DATE14>
59
<CSA_PAGE59>
page1 [1] <SYNC_MASTER59>
<SYNC_DATE59>
m
<CSA_PAGE15> <SYNC_DATE15> <CSA_PAGE60> <SYNC_DATE60>
15 SOC:POWER (2/3) <SYNC_MASTER15> 60 UAT MATCH AND TUNER CONNECTOR [2] <SYNC_MASTER60>
<CSA_PAGE16> <SYNC_DATE16> <CSA_PAGE61> <SYNC_DATE61>
16 SOC:POWER (3/3) <SYNC_MASTER16> 61 BOM LIST <SYNC_MASTER61>
o
17
<CSA_PAGE17>
NAND <SYNC_MASTER17>
脑主板维修资料和学
<SYNC_DATE17>
62
<CSA_PAGE62>
page1 <SYNC_MASTER62>
<SYNC_DATE62>
.c
<CSA_PAGE18> <SYNC_DATE18> <CSA_PAGE63> <SYNC_DATE63>
18 SYSTEM POWER:PMU (1/3) <SYNC_MASTER18> 63 BOM_OMIT_TABLE <SYNC_MASTER63>
<CSA_PAGE19> <SYNC_DATE19> <CSA_PAGE64> <SYNC_DATE64>
19 SYSTEM POWER:PMU (2/3) <SYNC_MASTER19> 64 PMU: CONTROL AND CLOCKS <SYNC_MASTER64>
习录像分享群。
x
<CSA_PAGE20> <SYNC_DATE20> <CSA_PAGE65> <SYNC_DATE65>
20 SYSTEM POWER:PMU (3/3) <SYNC_MASTER20> 65 PMU: SWITCHERS AND LDOS <SYNC_MASTER65>
<SYNC_DATE21> <SYNC_DATE66>
fi
<CSA_PAGE21> <CSA_PAGE66>
21 SYSTEM POWER:CHARGER <SYNC_MASTER21> 66 BASEBAND: POWER2 <SYNC_MASTER66>
<CSA_PAGE22> <SYNC_DATE22> <CSA_PAGE67> <SYNC_DATE67>
22 SYSTEM POWER:BATTERY CONN <SYNC_MASTER22> 67 BASEBAND: CONTROL <SYNC_MASTER67>
a
<CSA_PAGE23> <SYNC_DATE23> <CSA_PAGE68> <SYNC_DATE68>
23 SYSTEM POWER:BOOST <SYNC_MASTER23> 68 BASEBAND GPIOS <SYNC_MASTER68>
<CSA_PAGE24> <SYNC_DATE24> <CSA_PAGE69> <SYNC_DATE69>
in
24 SENSORS <SYNC_MASTER24> 69 TRANSCEIVER0/1: POWER <SYNC_MASTER69>
<CSA_PAGE25> <SYNC_DATE25> <CSA_PAGE70> <SYNC_DATE70>
25 B2B FILTERS: UTAH <SYNC_MASTER25> 70 TRANSCEIVER0/1: TX PORTS <SYNC_MASTER70>
<CSA_PAGE26> <SYNC_DATE26> <CSA_PAGE71> <SYNC_DATE71>
26 CAMERA:STROBE DRIVER <SYNC_MASTER26> 71 TRANSCEIVER0/1: PRX PORTS <SYNC_MASTER71>
h
<CSA_PAGE27> <SYNC_DATE27> <CSA_PAGE72> <SYNC_DATE72>
27 Accessory: Buck Circuit <SYNC_MASTER27> 72 RECEIVE MATCHING <SYNC_MASTER72>
.c
<CSA_PAGE28> <SYNC_DATE28> <CSA_PAGE73> <SYNC_DATE73>
28 TRINITY: FF SPECIFIC <SYNC_MASTER28> 73 LOWER ANTENNA & COUPLERS <SYNC_MASTER73>
<CSA_PAGE29> <SYNC_DATE29> <CSA_PAGE74> <SYNC_DATE74>
29 B2B:FOREHEAD <SYNC_MASTER29> 74 DIVERSITY RECEIVE ASM'S <SYNC_MASTER74>
w
<CSA_PAGE30> <SYNC_DATE30> <CSA_PAGE75> <SYNC_DATE75>
30 spare <SYNC_MASTER30> 75 DIVERSITY RECEIVE LNA'S <SYNC_MASTER75>
<CSA_PAGE31> <SYNC_DATE31> <CSA_PAGE76> <SYNC_DATE76>
31 AUDIO:CALTRA CODEC (1/2) <SYNC_MASTER31> 76 UPPER ANTENNA FEEDS <SYNC_MASTER76>
w
B 32
<CSA_PAGE32>
AUDIO:CALTRA CODEC (2/2) <SYNC_MASTER32>
<SYNC_DATE32>
77
<CSA_PAGE77>
PMU: ET MODULATOR <SYNC_MASTER77>
<SYNC_DATE77>
B
<CSA_PAGE33> <SYNC_DATE33> <CSA_PAGE78> <SYNC_DATE78>
33
34
<CSA_PAGE34>
<CSA_PAGE35>
AUDIO:SPEAKER AMP 2
AUDIO:SPEAKER AMP 1
<SYNC_MASTER33>
<SYNC_MASTER34> w <SYNC_DATE34>
<SYNC_DATE35>
78
79
<CSA_PAGE79>
<CSA_PAGE80>
TEST POINTS & BOOT CONFIG
TDD TRANSMIT
<SYNC_MASTER78>
<SYNC_MASTER79>
<SYNC_DATE79>
<SYNC_DATE80>
35 ARC:DRIVER <SYNC_MASTER35> 80 FDD TRANSMIT <SYNC_MASTER80>
<CSA_PAGE36> <SYNC_DATE36> <CSA_PAGE81> <SYNC_DATE81>
36 ARC:MAGGIE <SYNC_MASTER36> 81 ICEFALL, SIM, DEBUG_CONN <SYNC_MASTER81>
<CSA_PAGE37> <SYNC_DATE37> <CSA_PAGE82> <SYNC_DATE82>
37 DISPLAY & MESA:POWER <SYNC_MASTER37> <SYNC_MASTER82>
<CSA_PAGE38> <SYNC_DATE38> <CSA_PAGE83> <SYNC_DATE83>
38 B2B:ORB & MESA <SYNC_MASTER38> <SYNC_MASTER83>
<CSA_PAGE39> <SYNC_DATE39> <CSA_PAGE84> <SYNC_DATE84>
39 B2B FILTERS: DISPLAY & TOUCH <SYNC_MASTER39> <SYNC_MASTER84>
<CSA_PAGE40> <SYNC_DATE40> <CSA_PAGE85> <SYNC_DATE85>
40 TRISTAR 2 <SYNC_MASTER40> <SYNC_MASTER85>
<CSA_PAGE41> <SYNC_DATE41> <CSA_PAGE86> <SYNC_DATE86>
41 B2B:DOCK FLEX <SYNC_MASTER41> <SYNC_MASTER86>
<CSA_PAGE42> <SYNC_DATE42> <CSA_PAGE87> <SYNC_DATE87>
42 spare <SYNC_MASTER42> <SYNC_MASTER87>
<CSA_PAGE43> <SYNC_DATE43> <CSA_PAGE88> <SYNC_DATE88>
43 spare <SYNC_MASTER43> <SYNC_MASTER88>
<CSA_PAGE44> <SYNC_DATE44> <CSA_PAGE89> <SYNC_DATE89>
44 B2B FILTERS: RIGHT BUTTON FLEX <SYNC_MASTER44> <SYNC_MASTER89>
<CSA_PAGE45> <SYNC_DATE45> <CSA_PAGE90> <SYNC_DATE90>
45 B2B: SMALL FF SPECIFIC <SYNC_MASTER45> <SYNC_MASTER90>
TABLE OF CONTENTS
A TABLE OF CONTENTS
SCH 051-00419 SYNC_MASTER=Sync
PAGE TITLE
SYNC_DATE=05/17/2016
A
spare
Schematic & PCB Callouts System Block Diagram: BRD 820-00188 DRAWING NUMBER
051-00419
SIZE
D
Apple Inc.
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
TABLE_5_HEAD
TABLE_5_ITEM
<rdar://problem/16684269> MCO 056-01342 R
REVISION
8.0.0
051-00419 1 SCH,MLB,D10 SCH CRITICAL ? NOTICE OF PROPRIETARY PROPERTY: BRANCH
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
PART NUMBER PART NUMBER
TABLE_5_ITEM
TABLE_5_ITEM
376S00106 376S00047 ALTERNATE Q2101 DIODES INC. ACT DIODE 371S00087 371S00064 ALTERNATE D2700 DIODE,SHOTTKY,30V,200MA,0201
TABLE_5_ITEM
152S00558 152S00557 ALTERNATE L2700 IND,MLD,0.47UH,2.5A,80Mohm,1608
CAP,X5R,10UF,20%,6.3V,0.65MM,HRZTL,0402 C1748,C1713,C1716,C1721,C1733
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: 353S01007 353S01039 ALTERNATE U2710 IC,LOAD SWITCH,WLCSP4
PART NUMBER
TABLE_5_ITEM
D
TABLE_ALT_ITEM
TABLE_5_ITEM
TABLE_ALT_HEAD
Power Inductor Alternates
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
PART NUMBER PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
TABLE_ALT_ITEM
PART NUMBER
TABLE_ALT_ITEM
152S00118 152S00075 ALTERNATE ALL IND,PWR,SHLD,1.2 UH,3.0A,0.080 OHM,2016
TABLE_ALT_ITEM
152S00077 152S00397 ALTERNATE ALL IND,PWR,SHLD,1.0 UH,2.25A,0.150 OHM,2016 updated 11/12
335S00195 335S00182 ALTERNATE U1701 SS,1Ynm,TLC,128GB TABLE_ALT_ITEM
TABLE_ALT_ITEM
152S00121 152S00081 ALTERNATE ALL IND,PWR,SHLD,0.47 UH,3.8A,0.048 OHM,2012
TABLE_ALT_ITEM
152S00123 152S1936 ALTERNATE ALL IND,PWR,SHLD,15 UH,0.72A,0.900 OHM,3225
TABLE_ALT_ITEM
152S00402 152S00366 ALTERNATE ALL IND,MULT,1UH,1.2A,0.320 OHM,0603 updated 11/12
335S00148 335S00183 ALTERNATE U1701 SD,3Dv2,TLC,256GB TABLE_ALT_ITEM
TABLE_ALT_ITEM
152S00297 152S1843 ALTERNATE ALL CYNTEC 2012 1UH reverted 11/13
335S00190 335S00183 ALTERNATE U1701 SS,3Dv3,TLC,256GB TABLE_ALT_ITEM
QQ :
CYNTEC 2012 1UH
152S00398 152S00204 ALTERNATE ALL IND,PWR,0.22UH,20%,6.7a,23MOHM,2012 For Chestnut inductor; so it doesn't interfere with PMU inducotr Buck 7 alts
TABLE_ALT_ITEM
196627811,
152S00117 152S00074 ALTERNATE L1806,L1810,L1814,L1816,L1817 IND,PWR,SHLD,1.0 UH,3.0A,0.060 OHM,2016
m
TABLE_ALT_HEAD
o
118S0764 118S0717 ALTERNATE ALL RES, 3.92K, 0.1%, 0201
手机工控电
TABLE_ALT_ITEM
.c
TABLE_ALT_ITEM
脑主板维修资料和学
x
TABLE_ALT_ITEM
fi
TABLE_ALT_ITEM
TABLE_ALT_ITEM
习录像分享群。
CAP,X5R,0.22UF,6.3V,01005,TDK
a
Magnesium Alternates 138S00024 138S0986 ALTERNATE ALL CAP,CER,3-TERM,7.5UF,20%,4V,0402,TAIYO/TDK
TABLE_ALT_ITEM
in
TABLE_ALT_HEAD TABLE_ALT_ITEM
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: 138S0706 138S0739 ALTERNATE ALL CAP,CER,1UF,20%,10V,X5R,0201,MURATA
PART NUMBER
TABLE_ALT_ITEM
TABLE_ALT_ITEM
h
132S0436 132S0400 ALTERNATE ALL CAP,CER,X5R,0.22UF,20%,6.3V,20%
Carbon Alternates
.c
TABLE_ALT_HEAD
w
338S00087 338S00226 ALTERNATE U2401,U2404 Updated version of Carbon
w
B TABLE_ALT_HEAD
B
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
155S00067
w
PART NUMBER
TABLE_ALT_ITEM
UT LDO Alternates
TABLE_ALT_ITEM
TABLE_ALT_HEAD
353S00889 353S00015 ALTERNATE U2501 ST, LDO REG, 2.925V, CSP 0.65x0.65
I2C5 Alternate
A
TABLE_ALT_HEAD
spare
DRAWING NUMBER SIZE
D
TABLE_5_ITEM
138S00049 138S00032 ALTERNATE (C2507,C2531) CAP,CER,X5R,2,2UF,20%6.3V,20%, KYOCERA #25634778: Exclude Kyocera as 2.2UF alt at only C2507/C2531 REFDES (other refdes no impact)
TABLE_ALT_ITEM
m
TABLE_5_HEAD
o
TABLE_5_ITEM
#24629229
117S0156 2 RES,MF,1K OHM, 5%, 1/32W, 01005 R4808,R4809 CRITICAL UTAH_C
.c
x
fi
a
in
h
.c
w
w
B B
w
A SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
spare
DRAWING NUMBER SIZE
A FD0404
28 27 26 25 23 21 19 18 10 9
52 46 41 40 39 37 35 34 33 31
TP-P55 VDD_MAIN Note: Fiducial used as test point
FID
1 C0401 1 C0402 1 C0403 1 C0404 1 C0405 1 C0406 ROOM=TEST
FD0408 0P5SQ-SMP3SQ-NSP
220PF 220PF 100PF 56PF 18PF 4PF 1
5%
10V
5%
10V
5%
16V
5%
25V
2%
16V
+/-0.1PF
16V
FID ROOM=ASSEMBLY
2 C0G-CERM 2 C0G-CERM 2 NP0-C0G 2 NP0-C0G-CERM 2 CERM 2 NP0-C0G 0P5SM1P0SQ-NSP
01005 01005 01005 01005 01005 01005 1 FD0403
FID
ROOM=TEST 0P5SQ-SMP3SQ-NSP
1
4 CHASSIS_GND_BS402 FD0400 ROOM=ASSEMBLY
FID
1 C0407 1 C0408 1 C0409 1 C0410 1 C0411 1 C0412 TP0419
1 TP0424
1 0P5SQ-SMP3SQ-NSP FD0402
A A 1 FID
5%
220PF 220PF
5%
100PF
5% 5%
56PF
2%
18PF 4PF
+/-0.1PF
TP-P55
ROOM=TEST
TP-P55
ROOM=TEST
GND TP 0P5SQ-SMP3SQ-NSP
10V
2 C0G-CERM
10V
2 C0G-CERM
16V
2 NP0-C0G
25V
2 NP0-C0G-CERM
16V
2 CERM
16V
2 NP0-C0G ROOM=TEST 1
DFU
ROOM=ASSEMBLY
01005 01005 01005 01005 01005 01005
PMU_TO_AP_FORCE_DFU TP0414
1
4 CHASSIS_GND_BS403
20 12 A
TP-P55
ROOM=TEST FORCE DFU
1 C0417 1 C0418 1 C0419 1 C0420 1 C0421 1 C0422
C
220PF 220PF 100PF 56PF 18PF 4PF E75 TP0402 C
m
5% 5% 5% 5% 2% +/-0.1PF
2 10V 2 10V 2 16V 2 25V 2 16V 2 16V 90_TRISTAR_DP1_CONN_P 1
C0G-CERM C0G-CERM NP0-C0G NP0-C0G-CERM CERM NP0-C0G 41 40 A
01005 01005 01005 01005 01005 01005 TP-P55
ROOM=TEST FD0407
o
FID
0P5SM1P0SQ-NSP
TP0403 1
Front Shields 90_TRISTAR_DP1_CONN_N 1
.c
41 40 A
Back Shields TP-P55
ROOM=TEST
ROOM=TEST
TP0404
x
1 1 90_TRISTAR_DP2_CONN_P 1
41 40
A
SH0400 SH0401 TP-P55
fi
SM SM ROOM=TEST
90_TRISTAR_DP2_CONN_N TP0405
1
SHLD-EMI-UPPER-BK-D10 SHLD-EMI-UPPER-FRT-D10 41 40 A
a
TP-P55
ROOM=TEST
TP0406
in
PP_TRISTAR_ACC1 1
41 40 A
TP-P55
ROOM=TEST ACCESSORY ID AND POWER
h
1
SH0402
1
SH0403 PP_TRISTAR_ACC2 TP0407
1
41 40 A
SM SM TP-P55
.c
ROOM=TEST
w
TP-P55
ROOM=TEST IN THE FACTORY FIXTURE.
ZT0404
w
B 2.70R1.80-NSP
TRISTAR_CON_DETECT_L TP0412
1 B
1 41 40 A FOR DIAGS
TP-P55
w AMUX
ROOM=TEST
PMU_AMUX_AY TP0413
1
20 A ANALOG MUX A OUTPUT
TP-P55
ROOM=TEST
1
R0413 #25244799
200K 100k to 200k
1%
1/32W
PMU_AMUX_BY TP0423
1
MF
2 01005
20 A ROOM=PMU ANALOG MUX B OUTPUT
TP-P55
ROOM=TEST
MOJAVE
BS0405 MESA_TO_BOOST_EN TP0400
1
STDOFF-2.56OD1.4ID.99H-SM
38 37 A
TP-P55
1 ROOM=TEST
PP_LCM_BL_CAT1_CONN TP0409
1 LCM BACKLIGHT SINK1 spare
CLIP-MLB-COAX-RETENTION-D10 45 39 A
TP-P55 DRAWING NUMBER SIZE
CL0401 1 ROOM=TEST
051-00419 D
Apple Inc.
TP0410
SM-SP
REVISION
PP_LCM_BL_CAT2_CONN 1
45 39 A LCM BACKLIGHT SINK2 R
8.0.0
TP-P55
ROOM=TEST NOTICE OF PROPRIETARY PROPERTY: BRANCH
TOP SIDE
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
PP_LCM_BL_ANODE_CONN 1 LCM BACKLIGHT SOURCE
45 39 A I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 6 OF 53
TP-P55 II NOT TO REPRODUCE OR COPY IT
ROOM=TEST SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 6 OF 81
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
BOOTSTRAPPING:BOARD REV
BOARD ID
BOOT CONFIG
NOSTUFFROOM=SOC
12 BOARD_REV3 R0509 1 2 1.00K PP1V8 7 8 9 11 12 13 16 17 18 25 29
39 46 47 48 52
01005 MF 5% 1/32W
NOSTUFFROOM=SOC
12 BOARD_REV2 R0505 1 2 1.00K
01005 MF 1/32W
5% BOARD_REV[3:0]
FLOAT=LOW, PULLUP=HIGH
12 BOARD_REV1 R0508 1ROOM=SOC 2 1.00K
01005 MF 1/32W 1111 Pre-Proto w/D520 (non enclosure)
5%
NOSTUFFROOM=SOC 1110 PROTO1
m
xxxx SPARE
1000 CARRIER
xxxx SPARE
o
BOARD_ID4=No connect SELECTED --> 0010 DVT
xxxx SPARE
.c
0000 PVT
11 PP1V8 MAKE_BASE=TRUE
NOSTUFFROOM=SOC
R0503
x
BOARD_ID2 1 2 1.00K BOARD_ID[4:0]
11
0=EUREKA, 1=KAROO 01005 MF 1/32W FLOAT=LOW, PULLUP=HIGH
5%
fi
NOSTUFF ROOM=SOC SELECTED --> 01000 D10 MLB
11 BOARD_ID1 R0501 1 2 1.00K 01001 D10 DEV
01005 MF 1/32W 01010 D11 MLB
a
5%
0=FORM FACTOR A, 1=FORM FACTOR B 01011 D11 DEV
01100 D101 MLB
in
BOARD_ID0=No connect 01101 D101 DEV
01110 D111 MLB
01111 D111 DEV
h
0=MLB, 1=DEV
.c
0=FORM FACTOR A, 1=FORM FACTOR B
12 PP1V8 MAKE_BASE=TRUE
0=EUREKA, 1=KAROO
w
BOOT_CONFIG1=No connect
w
BOOT_CONFIG0=No connect
B B
BOOT_CONFIG[2:0]
w FLOAT=LOW, PULLUP=HIGH
000
001
SPI0
SPI0 TEST MODE
010 NVME0_X2
011 NVME0 X2 TEST
SELECTED --> 100 NVME0 X1
101 NVME0 X1 TEST
110 SLOW SPI0 TEST
111 FAST SPI0 TEST
A SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
spare
DRAWING NUMBER SIZE
D D
C C
m
o
.c
x
fi
a
in
h
.c
w
w
B B
w
A SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
spare
DRAWING NUMBER SIZE
PP1V8 5 7 8 9 11 12 13 16 17 18 25 29
39 46 47 48 52
1 C0700
0.1UF
20%
2 6.3V
X5R-CERM
01005
ROOM=SOC
D D
FL0700 VDD11_XTAL:1.06-1.17V @TBD mA MAX
240-OHM-25%-0.20A-0.9DCR
PP1V1_XTAL 1 2 PP1V1 15 18
1 C0704 01005
ROOM=SOC 1 C0705
0.1UF
20%
2.2UF
20%
2 6.3V 2 6.3V
X5R-CERM X5R-CERM
01005 0201-1
ROOM=SOC ROOM=SOC
25 18 17 16 13 12 11 9 8 7 5
52 48 47 46 39 29
PP1V8 1 C0701 3.14-3.46V @20mA MAX
0.1UF
20%
6.3V
2 X5R-CERM
01005
ROOM=SOC
CKPLUS_WAIVE=PWRTERM2GND
PP0V9_SOC_FIXED 8 9 10 15 18
VDD11_XTAL CG50
VDD33_USB CG26
VDD_FIXED_USB CC25
VDD18_USB CE25
VDD12_UH1_HSIC0 CL20
VDD18_AMUX AJ60
C C
m
o
U0700
.c
CAYMAN-2GB-20NM-DDR-M
CSP
SYM 1 OF 16
x
CM22 UH1_HSIC0_DATA ANALOGMUX_OUT N64 AP_TO_PMU_AMUX_OUT
NC 20
fi
CM20 UH1_HSIC0_STB
NC
a
Dev ONLY
USB_DP CM26 90_USB_AP_DATA_P
in
40
CL31 JTAG_SEL USB_DM CL26 90_USB_AP_DATA_N 40
CL29 JTAG_TRST*
NC
h
CG37 JTAG_TDO
NC
NC
CJ35 JTAG_TDI USB_VBUS CH26 USB_VBUS_DETECT 21
.c
40 SWD_DOCK_BI_AP_SWDIO CK33 JTAG_TMS
40 SWD_DOCK_TO_AP_SWCLK CH37 JTAG_TCK USB_ID CJ26NC
CM14 COLD_RESET*
w
20 13 PMU_TO_SYSTEM_COLD_RESET_L
BJ3 CFSB USB_REXT CK26 AP_USB_REXT
40 37 20 13 PMU_TO_AOP_TRISTAR_ACTIVE_READY
PP0701 1
R0700
w
B P2MM-NSM
SM
PP
1
20 AP_TO_PMU_TEST_CLKOUT BJ2 TST_CLKOUT
1%
200 B
1/32W
17 AP_TO_NAND_RESET_L BL65 S3E_RESET*
w MF
2 01005
ROOM=SOC
BL3 TESTMODE
A SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
spare
DRAWING NUMBER SIZE
PP0V9_SOC_FIXED 7
D
9 10 15 18
BW55
CC49
CC53
CC62
CC47
VDD12_PCIE CE58
CE49
CA55
CA60
CE55
CE60
MF ROOM=SOC ROOM=SOC ROOM=SOC
1 0.1UF
1
C0805
2.2UF
C0801
0.1UF 2
20%
6.3V
01005
ROOM=SOC
20% 20% X5R-CERM
6.3V 6.3V 01005
VDD_FIXED_PCIE_REFBUF
VDD12_PCIE_REFBUF
VDD_FIXED_PCIE_CLK
VDD_FIXED_PCIE_ANA
2 X5R-CERM 2 X5R-CERM ROOM=SOC
0201-1 01005
ROOM=SOC ROOM=SOC
PP1V8 5 7 9 11 12 13 16 17 18 25 29
39 46 47 48 52
1
R0805 U0700
CAYMAN-2GB-20NM-DDR-M
100K CSP
5%
1/32W
MF
2 01005 SYM 2 OF 16
ROOM=SOC BC64
17 PCIE_NAND_BI_AP_CLKREQ_L PCIE_CLKREQ0* PCIE_CLKREQ3* BE66 PCIE_WLAN_BI_AP_CLKREQ_L 52
PCIE LINK 3
#24557655:replace with 20% caps. SI no negative impact
C C
m
C0807 20%1 2 GND_VOID=TRUE
6.3V
0.22UF
ROOM=SOC X5R 01005
17 90_PCIE_NAND_TO_AP_RXD_P 90_PCIE_NAND_TO_AP_RXD_C_P CM46 PCIE_RX0_P PCIE_RX3_P CM61 90_AP_PCIE3_RXD_C_P 52
o
1 2 GND_VOID=TRUE
17 90_PCIE_NAND_TO_AP_RXD_N C0808 20% 6.3V
0.22UF 90_PCIE_NAND_TO_AP_RXD_C_N CL46 PCIE_RX0_N PCIE_RX3_N CL61 90_AP_PCIE3_RXD_C_N 52
PCIE LINK 0
ROOM=SOC
X5R 01005
.c
D10 NAND is now Gen3 (was Gen2). Caps intentionally 0.22uF
1 2 GND_VOID=TRUE
C0809
ROOM=SOC 20% 6.3V
0.22UF
X5R 01005
x
17 90_PCIE_AP_TO_NAND_TXD_P 90_PCIE_AP_TO_NAND_TXD_C_P CK44 PCIE_TX0_P PCIE_TX3_P CK63 90_AP_PCIE3_TXD_C_P 52
1 2 GND_VOID=TRUE
17 90_PCIE_AP_TO_NAND_TXD_N C0810 0.22UF 90_PCIE_AP_TO_NAND_TXD_C_N CJ44 PCIE_TX0_N PCIE_TX3_N CJ63 90_AP_PCIE3_TXD_C_N 52
fi
ROOM=SOC 20% 6.3V
X5R 01005 BJ65
17 PCIE_AP_TO_NAND_RESET_L PCIE_PERST0* PCIE_PERST3* BJ66 PCIE_AP_TO_WLAN_RESET_L
52
1
R0802
1
R0806
a
LINK0 LINK3 100K
100K 5%
5%
in
1/32W
1/32W MF
MF 2 01005
2 01005 ROOM=SOC
ROOM=SOC BG66
NC PCIE_CLKREQ1* PCIE_CLKREQ2* BE65 PCIE_BB_BI_AP_CLKREQ_L 52
h
CL54 PCIE_REF_CLK1_P PCIE_REF_CLK2_P CK59 90_PCIE_AP_TO_BB_REFCLK_P
NC 52
CM54 PCIE_REF_CLK1_N PCIE_REF_CLK2_N CJ59 90_PCIE_AP_TO_BB_REFCLK_N
NC 52
.c
PCIE LINK 2
WLAN RX PP's are now managed on Page 52
w
CK52 PCIE_RX1_P PCIE_RX2_P CK56 90_AP_PCIE2_RXD_C_P
NC 52
PCIE LINK 1
w
NC 52
B B
LINK 1 USED ON AP_DEV ONLY
w
CM50 PCIE_TX1_P PCIE_TX2_P CM57 90_AP_PCIE2_TXD_C_P
NC 52
CL50 PCIE_TX1_N PCIE_TX2_N CL57 90_AP_PCIE2_TXD_C_N
NC 52
A SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
spare
DRAWING NUMBER SIZE
G13
G17
G10
G15
G19
G21
2 X5R-CERM 2 X5R-CERM 2 2
G6
X5R-CERM X5R-CERM
01005 0201-1 0201-1 01005
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC
VDD_FIXED_MIPI
VDD18_MIPI
U0700
CAYMAN-2GB-20NM-DDR-M
CSP
NC
C24 MIPI0C_DPDATA2 ISP_I2C2_SCL U65 I2C_ISP_NH_SCL 48
NC
B24 MIPI0C_DNDATA2 ISP_I2C2_SDA U66 I2C_ISP_NH_SDA 48
C C
m
A26 MIPI0C_DPDATA3 ISP_I2C3_SCL W64 NC
NC
NC
B26 MIPI0C_DNDATA3 ISP_I2C3_SDA W66 NC
Dev ONLY R0906
1
33.2 2 AP_TO_UT_CLK 25
o
B22 NOSTUFF
90_MIPI_NH_TO_AP_CLK_P MIPI0C_DPCLK
45
.c
01005
ROOM=SOC 5%
MIPI0C_REXT E24 MIPI0C_REXT SENSOR_INT AA64NC Spare 2
35V
NP0-C0G
01005
R0900 1
x
4.02K
1%
1/32W 90_MIPI_AP_TO_LCM_DATA0_P B4 MIPID_DPDATA0 SENSOR0_CLK B50 AP_TO_UT_CLK_R
R0907
39
fi
MF
01005 2 39 90_MIPI_AP_TO_LCM_DATA0_N A4 MIPID_DNDATA0 SENSOR1_CLK A48 NC_AP_TO_NV_CLK_R D11/111 ONLY
ROOM=SOC 33.2
SENSOR2_CLK C48 AP_TO_NH_CLK_R 1 2 AP_TO_NH_CLK 29
B5 NOSTUFF
90_MIPI_AP_TO_LCM_DATA1_P MIPID_DPDATA1 1%
C0907
a
39
1/32W 1
90_MIPI_AP_TO_LCM_DATA1_N C5 MIPID_DNDATA1 MF
39
01005 100PF
5%
in
ROOM=SOC 35V
C9 A50 2 NP0-C0G
NC_MIPI_AP_TO_LCM_DATA2_P MIPID_DPDATA2 SENSOR0_RST AP_TO_UT_SHUTDOWN_L 25 01005
NC_MIPI_AP_TO_LCM_DATA2_N B9 MIPID_DNDATA2 SENSOR1_RST E50 NC_AP_TO_NV_SHUTDOWN_L D11/111 ONLY
D11/111 ONLY SENSOR2_RST AA65 AP_TO_NH_SHUTDOWN_L 29
h
Radar 20511449
NC_MIPI_AP_TO_LCM_DATA3_P A11 MIPID_DPDATA3 SENSOR3_RST AE64 TP_SENSOR3_RST 1 PP SM PP0902
P2MM-NSM <--- Needed for Cayman debug; this pin cannot be input
NC_MIPI_AP_TO_LCM_DATA3_N B11 MIPID_DNDATA3 SENSOR4_RST AC65 ROOM=SOC
NC
.c
B7 SENSOR0_ISTRB E52
w
39 90_MIPI_AP_TO_LCM_CLK_P MIPID_DPCLK NC_SENSOR0_ISTRB
39 90_MIPI_AP_TO_LCM_CLK_N A7 MIPID_DNCLK SENSOR1_ISTRB D50 NC
w
B 26
36
AP_TO_STROBE_DRIVER_HWEN
SPI_AP_TO_MAGGIE_CS_L
BN4
BR2
DISP_TOUCH_BSYNC0
DISP_TOUCH_BSYNC1
SENSOR0_XSHUTDOWN C50 NC
SENSOR1_XSHUTDOWN B48 AP_TO_MUON_BL_STROBE_EN 37
B
NC
BR4 DISP_TOUCH_EB w MIPI1C_REXT E16
A 53
28 27 26 25 23 21 19 18 10 4
52 46 41 40 39 37 35 34 33 31
PP_VDD_MAIN SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
1 C0904
220PF
1 C0905
220PF
1 C0908
220PF
1 C0909
220PF
1 C0910
220PF
spare
DRAWING NUMBER SIZE
5% 5% 5% 5% 5%
2 10V
C0G-CERM 2 10V
C0G-CERM
10V
2 C0G-CERM 2 10V
C0G-CERM 2 10V
C0G-CERM Apple Inc. 051-00419 D
01005 01005 01005 01005 01005 REVISION
ROOM=SOC
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC
R
8.0.0
AC return path for LCM MIPI which is referenced to GND and VDD_MAIN NOTICE OF PROPRIETARY PROPERTY: BRANCH
Radar 21203307 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
6 OF 53
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 6 OF 81
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
VDD12_PLL_LPDP:1.14-1.26V @3mA MAX
PP1V2_SOC VDD12_LPDP:1.14-1.26V @60mA MAX
1 C1013 1 C1001 1 C1004 1 C1005 1 C1002 CKPLUS_WAIVE=PWRTERM2GND
CKPLUS_WAIVE=PWRTERM2GND
CKPLUS_WAIVE=PWRTERM2GND
2.2UF 2.2UF 0.1UF 0.01UF 15PF
20% 20% 20% 10% 5%
6.3V 6.3V 6.3V 6.3V 16V
2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R 2 NP0-C0G-CERM
G25
G28
G30
G55
G58
G60
G62
VDD12_PLL_LPDP G23
0201-1 0201-1 01005 01005 01005
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC
Desense for Wifi frequencies
VDD12_LPDP_TX
VDD12_LPDP_RX
U0700
CAYMAN-2GB-20NM-DDR-M
CSP
25 90_LPDP_UT_TO_AP_D0_P A54 LPDPRX_RX_D0_P LPDP_TX0P B27 NC
90_LPDP_UT_TO_AP_D0_N SYM 4 OF 16 Dev ONLY
25
B54 LPDPRX_RX_D0_N LPDP_TX0N C27 NC
25
90_LPDP_UT_TO_AP_D1_P B56 LPDPRX_RX_D1_P LPDP_TX1P A29 NC
25 90_LPDP_UT_TO_AP_D1_N C56 LPDPRX_RX_D1_N LPDP_TX1N B29 NC
C C
m
LPDP Lanes swapped between D10 and D11
o
46 NC_90_LPDP_NV_TO_AP_D2_P A61 LPDPRX_RX_D2_P LPDP_TX2P B31 NC
46
NC_90_LPDP_NV_TO_AP_D2_N B61 LPDPRX_RX_D2_N LPDP_TX2N C31 NC
.c
D11/111 ONLY
x
46
NC_90_LPDP_NV_TO_AP_D3_P B63 LPDPRX_RX_D3_P LPDP_TX3P A33 NC
46 NC_90_LPDP_NV_TO_AP_D3_N C63 LPDPRX_RX_D3_N LPDP_TX3N B33
fi
a
A64 LPDPRX_RX_D4_P
GND ON MLB; other on Dev B64 LPDPRX_RX_D4_N
in
h
25 LPDP_UT_BI_AP_AUX D54 LPDPRX_AUX_D0_P LPDP_AUX_P D33 NC
NC
E56 LPDPRX_AUX_D1_P LPDP_AUX_N E33 NC
.c
D11/111 ONLY 46 NC_AP_LPDP_AUX2 D61 LPDPRX_AUX_D2_P
NC
E63 LPDPRX_AUX_D3_P LPDP_CAL_DRV_OUT E35 NC
NC
D64 LPDPRX_AUX_D4_P LPDP_CAL_VSS_EXT E31 NC
w
B59 LPDPRX_BYP_CLK_P EDP_HPD BN3 NC
Reserved for PanelID[1:0] on ap_dev board
GND ON MLB; other on Dev C59 LPDPRX_BYP_CLK_N DP_WAKEUP AP2 NC
w
Reserved for PanelID[1:0] on ap_dev board
B B
18 15 9 8 7 PP0V9_SOC_FIXED w
A57 LPDPRX_RCAL_P
R1001 1
300
1%
1/32W
MF
01005-1 2
ROOM=SOC B57 LPDPRX_RCAL_N
AP_LPDPRX_RCAL_NEG
C1006 1
D57 LPDPRX_EXT_C
100PF NC
5%
16V
NP0-C0G 2
01005
ROOM=SOC
#24401637:Unconnect LPDPRX_EXT_C
A 53
28 27 26 25 23 21 19 18 9 4
52 46 41 40 39 37 35 34 33 31
PP_VDD_MAIN
SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
1 C1010 1 C1011 spare
33PF 33PF
5% 5% DRAWING NUMBER SIZE
2 16V 2 16V
NP0-C0G-CERM
01005
NP0-C0G-CERM
01005 Apple Inc. 051-00419 D
ROOM=SOC ROOM=SOC REVISION
AC return path for LCM LPDP which is referenced to GND and VDD_MAIN
R
8.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
D D
R1103
33.2 BV65
32 I2S_AP_TO_CODEC_MCLK 1 2 I2S_AP_TO_CODEC_MCLK_R I2S0_MCK I2C0_SCL CK7 I2C0_AP_SCL 47
1%
1/32W
32 I2S_AP_TO_CODEC_MSP_BCLK BY66 I2S0_BCLK U0700 I2C0_SDA CG12 I2C0_AP_SDA 47
I2C2_SCL U3 I2C2_AP_SCL 47
I2S1/2/3 MCLK NC #24559456 D48 I2S1_MCK I2C2_SDA U4 I2C2_AP_SDA
NC 47
BU66 I2S2_MCK
NC
I2S_MAGGIE_TO_AP_L26_CODEC_BCLK BR66 I2S2_BCLK
36 35 34 33 32
m
53
o
53 I2S_AP_TO_BB_DOUT I2S3_DOUT
I2C5_SCL CH16 I2C5_SCL 11 47
.c
11 47
x
39 46 47 48 52
5 BOARD_ID1 BY4 SPI0_MOSI GPIO_43 CH22NC
BY3 SPI0_SCLK 1 1
BOARD_ID0 NC R1113 R1114
fi
5 PP1V8 CB4 SPI0_SSIN 10K 10K
5% 5%
1/32W 1/32W
MF MF
01005 01005
a
N2 2 ROOM=SOC 2 ROOM=SOC
SPI_CODEC_MAGGIE_TO_AP_MISO SPI1_MISO
R1116 36 32
in
36 32 20
0.00 N4 PMU_MISO AH66 SPI_PMU_TO_PMGR_MISO
36 32 SPI_AP_TO_CODEC_MAGGIE_SCLK 1 2 SPI_AP_TO_CODEC_MAGGIE_SCLK_R SPI1_SCLK 20
Route as daisy-chain. No T's allowed.
0% 32 SPI_AP_TO_CODEC_CS_L R3 SPI1_SSIN PMU_MOSI AK64 SPI_PMGR_TO_PMU_MOSI 20
1/32W
MF
DWI_CLK AK65 DWI_PMGR_TO_BACKLIGHT_CLK
h
01005 37
DWI_DO AM64
ROOM=SOC
C44 DWI_PMGR_TO_BACKLIGHT_DATA 37
SPI_TOUCH_TO_AP_MISO SPI2_MISO
R1101 39
.c
39 SPI_AP_TO_TOUCH_MOSI B44 SPI2_MOSI
0.00 SPI_AP_TO_TOUCH_SCLK_R A44 DROOP AE3 PMU_TO_AP_PRE_UVLO_L
39 SPI_AP_TO_TOUCH_SCLK 1 2 SPI2_SCLK 20
w
MF
01005
ROOM=SOC SOCHOT AG4 AP_TO_PMU_SOCHOT_L 20
w
38
B 38
38
SPI_AP_TO_MESA_MOSI
SPI_AP_TO_MESA_SCLK
A42
E44
SPI3_MOSI
SPI3_SCLK
CLK32K_OUT AM66 AP_TO_CUMULUS_CLK32K 39
B
0.00
38 MESA_TO_AP_INT
w C42 SPI3_SSIN NAND_SYS_CLK BN66 AP_TO_NAND_SYS_CLK_R
R1118
1
0%
1/32W
MF
01005
2 AP_TO_NAND_SYS_CLK 17
ROOM=SOC
I2C5
See Radar#25316444 for Details
25 18 17 16 13 12 11 9 8 7 5
52 48 47 46 39 29
PP1V8
1
C1101
A1
1.0UF
20% VCC
6.3V
2 X5R I2S_AP_TO_CODEC_MCLK I2S_AP_TO_CODEC_MCLK_R
I2S_AP_TO_CODEC_MSP_BCLK
I2C0_AP_SCL
I2C0_AP_SDA
0201-1
ROOM=SOC U1101 I2S_AP_TO_CODEC_MSP_LRCLK
I2S_CODEC_TO_AP_MSP_DIN I2C1_AP_SCL
I2S_AP_TO_CODEC_MSP_DOUT I2C1_AP_SDA
B1 A2 I2C5_SDA
A SCL WLCSP SDA
I2C5_SCL
11 47
I2S_AP_TO_BT_LRCLK
11 47 To Cayman
I2S_BT_TO_AP_DIN
I2S_AP_TO_BT_LRCLK
I2C2_AP_SCL
I2C2_AP_SDA
SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
I2S_AP_TO_BT_LRCLK I2C3_AP_SCL
I2S_BT_TO_AP_DIN I2C3_AP_SDA
PAGE TITLE
VSS
ROOM=SOC
I2S_AP_TO_BT_DOUT
I2S_MAGGIE_TO_AP_L26_CODEC_BCLK spare
B2
CRITICAL I2S_MAGGIE_TO_AP_L26_CODEC_BCLK
I2S_MAGGIE_TO_AP_DIN DRAWING NUMBER SIZE
I2S_MAGGIE_TO_AP_L26_CODEC_BCLK
I2S_MAGGIE_TO_AP_L26_CODEC_LRCLK
I2S_AP_TO_MAGGIE_DOUT
I2S_MAGGIE_TO_AP_DIN Apple Inc. 051-00419 D
I2S_AP_TO_MAGGIE_DOUT REVISION
I2S_BB_TO_AP_BCLK
I2S_BB_TO_AP_BCLK
I2S_BB_TO_AP_BCLK
R
8.0.0
I2S_BB_TO_AP_BCLK
I2S_BB_TO_AP_LRCLK I2C5_SCL NOTICE OF PROPRIETARY PROPERTY: BRANCH
I2S_BB_TO_AP_DIN I2C5_SCL
I2C5_SDA
I2S_AP_TO_BB_DOUT I2C5_SDA
I2C5_SCL THE INFORMATION CONTAINED HEREIN IS THE
I2C5_SCL
I2C5_SDA PROPRIETARY PROPERTY OF APPLE INC.
BOARD_ID2 I2C5_SDA THE POSESSOR AGREES TO THE FOLLOWING: PAGE
BOARD_ID2
BOARD_ID2
BOARD_ID2
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
6 OF 53
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 6 OF 81
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
BB64 GPIO_0
NC
27 AP_TO_ACC_BUCK_VSEL BC65 GPIO_1 U0700
36 AP_TO_MAGGIE_CRESETB_L BB66 GPIO_2 CAYMAN-2GB-20NM-DDR-M
#24557547:Delete R1204 44 20 BUTTON_VOL_UP_L AY65 GPIO_3 CSP
DEV ONLY AY66 GPIO_4
NC
53 AP_TO_BB_RESET_L AV65 GPIO_5 SYM 5 OF 16 TMR32_PWM0 AG2 NC
36 MAGGIE_TO_AP_CDONE AV67 GPIO_6 TMR32_PWM1 AH4 PROX_BI_AP_AOP_INT_PWM_L 13 29
RESERVERD FOR SSHB ID ON DEV BOARD AT67 GPIO_7 TMR32_PWM2 AH3 NC_BB_TO_AP_RESET_ACT_L D101/D111 ONLY
D101/D111 ONLY NC_AP_TO_BB_IPC_GPIO2 AT66 GPIO_8
AT64 UART0_RXD CL5
C NC_AP_TO_GNSS_WAKE GPIO_9 UART_AP_DEBUG_RXD
C
m
D101/D111 ONLY 40
o
53 BB_TO_AP_RESET_DETECT_L GPIO_12 UART1_CTS* UART_BT_TO_AP_CTS_L 53
29 25 18 17 16 13 11 9 8 7 5 PP1V8 33 AP_TO_SPKAMP2_RESET_L
AE4 GPIO_13 UART1_RTS* D39 UART_AP_TO_BT_RTS_L 53
52 48 47 46 39
NOSTUFF AC3 C39
.c
29 ALS_TO_AP_INT_L GPIO_14 UART1_RXD UART_BT_TO_AP_RXD
1
R1210
53
x
39
01005
2 ROOM=SOC BOOT_CONFIG0 BC3 GPIO_18 UART2_RTS* AK3 NC_AP_UART2_RTS_L
NC D101/D111 ONLY; for GNSS
PMU_TO_AP_THROTTLE_CPU_L BC4 GPIO_19 UART2_RXD AK4 NC_AP_UART2_RXD
fi
20
a
D10/D11 ONLY 53 AP_TO_ICEFALL_FW_DWLD_REQ BE3 GPIO_22 UART3_CTS* AA4 UART_NFC_TO_AP_CTS_L 53
in
36 AP_BI_HOMER_BOOTLOADER_ALIVE CJ11 GPIO_24 UART3_RXD W4 UART_NFC_TO_AP_RXD 53
h
Dev only GPIO_27 UART4_CTS* 53
.c
BOARD_ID4 NC 53
w
53 21
w
BOARD_REV2 E41 GPIO_35
B B
5
39
53
53
AP_TO_TOUCH_MAMBA_RESET_L
AP_TO_BB_MESA_ON
AP_TO_BB_COREDUMP
w AT2
AV3
AY2
GPIO_38
GPIO_39
GPIO_40
UART6_TXD CG14
UART7_RXD AP3
UART_AP_TO_ACCESSORY_TXD
UART_HOMER_TO_AP_RXD
40
40
36
#25120460:REQUEST_DFU Assignment
A SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
spare
DRAWING NUMBER SIZE
SOC - AOP
D D
PP1V8
5 7 8 9 11 12 16 17 18 25 29 39
46 47 48 52
NOSTUFF
1
R1304
1.00K
5%
U0700 1/32W
MF
01005
CAYMAN-2GB-20NM-DDR-M 2
CSP ROOM=SOC
CM16 SYM 7 OF 16
20 AOP_TO_PMU_SLEEP1_REQUEST AOP_DDR_REQ CFSB_AOP CH35 PMU_TO_SYSTEM_COLD_RESET_L 7 20
C C
m
SPI_AOP_TO_PHOSPHORUS_CS_L CK20 AOP_FUNC_6
AOP_SWD_TCK_OUT CL14
24
CJ31 SWD_AP_TO_MANY_SWCLK 17 36 53
53 39 23 20 LCM_TO_MANY_BSYNC AOP_FUNC_7
TRISTAR_TO_AOP_INT CK27 AOP_FUNC_8
40
CL16
o
CK24 AOP_SWD_TMS0 HOMER_TO_AOP_WAKE_INT 36
36 AOP_TO_MAGGIE_EN AOP_FUNC_9 CG35
CK29 AOP_FUNC_10
AOP_SWD_TMS1 SWD_AOP_BI_BB_SWDIO 53 BB_SWDIO has pullup in Radio_MLB pages
24 PHOSPHORUS_TO_AOP_INT_L BU4
.c
SPI_AOP_TO_BOT_ACCEL_GYRO_CS_L CK22 AOP_FUNC_11
SWD_TMS2 SWD_AP_BI_NAND_SWDIO 17
24
SWD_TMS3 BV3 SWD_AP_BI_HOMER_SWDIO
24 BOT_ACCEL_GYRO_TO_AOP_DATARDY CM12 AOP_FUNC_12
36
x
48 AOP_TO_MESA_I2C_ISO_EN CG33 AOP_FUNC_14
Internal pullup in AOP. Radar 21210869 20 PMU_TO_AOP_IRQ_L CJ33 AOP_FUNC_15
fi
48 I2C_AOP_SCL CM11 AOP_I2C0_SCL
I2C_AOP_SDA CJ24 AOP_I2C0_SDA
a
48
in
24
h
1/32W CK14
MF 53 UART_BB_TO_AOP_RXD AOP_UART0_RXD
01005 CJ20
ROOM=SOC 53 UART_AOP_TO_BB_TXD AOP_UART0_TXD
.c
R1306 36 MAGGIE_TO_AOP_INT CJ22 AOP_UART1_RXD
49.9 2 36 UART_AOP_TO_MAGGIE_TXD CL11 AOP_UART1_TXD
#25756894:South Carbon R2 24 SPI_AOP_TO_IMU_SCLK_R2 1
CG29
w
1% 39 UART_TOUCH_TO_AOP_RXD AOP_UART2_RXD
1/32W CH29
MF 39 UART_AOP_TO_TOUCH_TXD AOP_UART2_TXD
01005
ROOM=SOC
w
B R1303 32
32
I2S_CODEC_XSP_TO_AOP_BCLK
I2S_CODEC_XSP_TO_AOP_DIN
CL35
CJ39
AOP_I2S_BCLK
AOP_I2S_DIN
B
33.2
36 35 34 33 I2S_AOP_TO_MAGGIE_L26_MCLK 1
1%
1/32W
MF
01005
2
32
32
w
I2S_AOP_TO_MAGGIE_L26_MCLK_R
I2S_CODEC_XSP_TO_AOP_LRCLK
I2S_AOP_TO_CODEC_XSP_DOUT
CM35
CK37
CG39
AOP_I2S_MCK
AOP_I2S_LRCK
AOP_I2S_DOUT
DOCK_ATTENTION CG41
DOCK_CONNECT CL37
AOP_TO_SPKAMP1_ARC_RESET_L 34
MESA_TO_AOP_FDINT 38
35
ROOM=SOC
DOCK_CONNECT can be GPIO, but input only. Radar 21680759
A SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
spare
DRAWING NUMBER SIZE
m
BD21 L15
AN32 BP32
BD8 L19 ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC AN36 BP36
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC
BF10 L23 C1410 C1415 C1420 C1425 C1429 C1456 C1457 AN40 BP40
o
C1406 C1413 C1419 C1424 C1460 C1461 BF23 L28 1UF
20%
1UF
20%
1UF
20%
0.47UF
20%
0.47UF
20%
0.47UF
20%
0.47UF
20% AN45 BP45
0.47UF 0.47UF 0.47UF 0.47UF 7.5UF 7.5UF BH13 VDD_GPU L32 4V 4V 4V 6.3V 6.3V 6.3V 6.3V AN49 BP49
.c
20% 20% 20% 20% 20% 20% BH17 L36 CERM CERM CERM CERM CERM CERM CERM
6.3V 6.3V 6.3V 6.3V 4V 4V 0402 0402 0402 0402 0402 0402 0402 AN53 BP53
CERM CERM CERM CERM CERM CERM BH21 L40 1 3 1 3 1 3 1 3 1 3 1 3 1 3
0402 0402 0402 0402 0402 0402 AN58 BP58
1 3 1 3 1 3 1 3 1 3 1 3 BK10 L45
2 4 2 4 2 4 2 4 2 4 2 4 2 4 AR25 BT13
x
BK15 L49
2 4 2 4 2 4 2 4 2 4 2 4 AR30 BT17
AJ10 L53
AR34 BT21
fi
P13
AR38 BT25
T15
AR43 BT30
OMIT T36
a
AR47 BT34
T40
XW1402 T53
AR51 BT38
in
SHORT-20L-0.05MM-SM AR55 BT43
18 BUCK0_PP_CPU_FB 2 1 V13
1.06V @1.0A MAX AW30 BT47
ROOM=SOC
NO_XNET_CONNECTION V25
0.80V @TBDA MAX AW34 BT51
V34
AW38 BT55
h
V38
AW43 VDD_SOC BW10
PP_CPU_SRAM_VAR AF8 V51 VDD_SOC
18 AW47 CA13
.c
AN15 V55
ROOM=SOC ROOM=SOC AW51 CA17
ROOM=SOC AR8 Y28
C1407 C1435 C1433 C1458 AW55 CA21
|-
1 AU19
--
AW60 CA25
|||
7.5UF 7.5UF 7.5UF 10UF VDD_CPU_SRAM
|||
AW8
|-
20% 20% 20% 20% BD25
-|
2 6.3V CA30
||=
4V 4V 4V BA15
=
CERM CER CERM CERM-X5R BD30 CA34
0402 0402 0402 0402-9 BA19
1 3 BD34
w
1 3 1 3
ROOM=SOC CA38
B 2 4 2 4
BH8
BD38 CA43 B
2 4 BD43 CA47
AF43
w BD47
BD51
BD55
CE13
CE17
CE45
AF47
BD6 J13
AF51
BD60 J21
P17 VDD_CPU_SENSE BK23 AP_VDD_CPU_SENSE 20 BF28 J34
P21
P25 VSS_CPU_SENSE BK21 TP_AP_VSS_CPU_SENSE 1 SM PP1403 1
SM
PP PP1408
P2MM-NSM
BF32 P55
PP
P2MM-NSM BF36 T10
P30 ROOM=SOC
ROOM=SOC
BF45 T60
P34 VDD_GPU_SENSE AJ45 AP_VDD_GPU_SENSE 20 BF49 V30
P38
1.03V @1.44A MAX P43 VDD_SOC_SENSE AL47 TP_VDD_SOC_SENSE 1 PP1410 1
SM
PP PP1409
P2MM-NSM
BF53 Y10
0.92V @1.50A MAX VDD_GPU_SRAM PP SM
P2MM-NSM BF58 Y36
0.80V @TBD A MAX P47 ROOM=SOC
ROOM=SOC
BK28 Y60
PP_GPU_SRAM_VAR
P51 VSS_SENSE AJ47 TP_VSS_SENSE 1
PP SM PP1411
P2MM-NSM BK32 BF40
18
Y15 ROOM=SOC BK36 J60
Y19
ROOM=SOC ROOM=SOC BK40 AW25
Y23
C1439 C1437 1 C1459 Y40
7.5UF 7.5UF 10UF
20% 20% 20% Y45
4V 4V 2 6.3V
CER CERM CERM-X5R Y49
0402 0402 0402-9
1 3 ROOM=SOC Y53
1 3
2 4
2 4
A SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
spare
DRAWING NUMBER SIZE
=| ||| |-
2 4 2 4 2 4 AF30 BM30 1.06 - 1.17V @4mA MAX 100OHM-25%-0.12A
-- -| --
- - ||-
VDDIO11_PLL_DDR0 CE8 PP1V1_DDR_PLL 1 2 PP1V1
- | ||||| |||||-
AF34 BM34 7 15 18
||| |||| -
BW60
- - |- ||
AF38 BM38 VDDIO11_PLL_DDR1 01005
||- |- | |==
C1508 C1509 C1523 C1510 ROOM=SOC
- | - ||
J8
||
VDDIO11_PLL_DDR2 1 1 1 1
- | |-
AF62 BM43
- - ||-
P58
- - ||-
AJ58 BM47 BE67 VDDIO11_PLL_DDR3 0.22UF 0.22UF 0.22UF 0.22UF
|-
20% 20% 20% 20%
AL25 BM51 BH60 2 6.3V 2 6.3V 2 6.3V 2 6.3V
1 C1501 AL30 BP10 BJ67
X5R
01005-1
ROOM=SOC
X5R
01005-1
ROOM=SOC
X5R
01005-1
ROOM=SOC
X5R
01005-1
ROOM=SOC
10UF AL34 BP60 BK62
20%
2 6.3V AL38 BW15 BL67
CERM-X5R
0402-9 AL43 BW19 BM60 VDDIO11_DDR1
ROOM=SOC
C C
m
AL51 BW23 BP62 (CURRENT INCLUDED IN VDD2)
AL55 BW28 BT60 VDDIO11_RET_DDR0 CG3 PP1V1_SDRAM 15 18 19
AL60 BW32 BW62 VDDIO11_RET_DDR1 CD65
o
AR60 BW36 CD67 VDDIO11_RET_DDR2 H4
AU28 BW40 CH67 VDDIO11_RET_DDR3 H64
.c
AU32 BW45
AU36 BW49
AU40 BW53
x
AU45 BW58 DDR0_SYS_ALIVE CF4 SYSTEM_ALIVE
VDD_FIXED VDD_FIXED 17 20 21
AU49 BW8 DDR1_SYS_ALIVE CB64
fi
AU53 CC10 DDR2_SYS_ALIVE H3
AB8
AU58 CC15 DDR3_SYS_ALIVE H65
AC1
AU6 CC19
a
AE1
BA28 CC23
AH1
BA32 CC28
in
E1
BA36 CC32 AM3
K1 VDDIO11_DDR2
BA40 CC45 AM65
L6
BA45 G32 BB3
P8
h
BA49 G36 BB65
T6
BA53 J17 BR1
V8
.c
BA58 J23 BR67
Y6
BH25 J55 BV1
BH30 J62 BV67
BH34 L10
w
BY1
BH38 L58 BY67
BH43 L60 C2 1.06 - 1.17V @1.74A MAX
w
PP1V1_SDRAM
B BH47 T32 C66
B
15 18 19
A SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
spare
DRAWING NUMBER SIZE
=| ||| |-
-- -| --
CAYMAN-2GB-20NM-DDR-M CAYMAN-2GB-20NM-DDR-M CAYMAN-2GB-20NM-DDR-M CAYMAN-2GB-20NM-DDR-M
A2 AL32 B35 BM15 CA23 CH54 D24 L47 1
C1615 1
C1605 1
C1608 1
C1612 BB1
- - ||-
CAYMAN-2GB-20NM-DDR-M
- | ||||| |||||-
CSP CSP CSP CSP 2.2UF 2.2UF 2.2UF 2.2UF
||| |||| -
A20 AL36 B41 BM19 CA28 CH56 D26 L51 BB67 CSP
- - |- ||
20% 20% 20% 20%
||- |- | |==
A24 AL40 B46 BM23 CA32 CH59 D27 L55 6.3V 6.3V 6.3V 6.3V C3 VDD1
- | - ||
||
SYM 16 OF 16 2 2 2 2
- | |-
D
SYM 13 OF 16 SYM 14 OF 16 SYM 15 OF 16 X5R-CERM X5R-CERM X5R-CERM X5R-CERM
- - ||-
SYM 12 OF 16
D CA36
A27 AL45 B52 BM28 CH61 D29 L62 0201-1 0201-1 0201-1 0201-1 C65
- - ||-
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC
|-
A31 AL53 B65 BM32 CA40 CH63 D3 L8 CK3
A35 AL58 B67 BM36 CA45 CH64 D31 M1 CK65
A5 AL62 BA13 BM40 CA49 CH65 D35 M2
A52 AN13 BA17 BM45 CA53 CH66 D4 M3
A56 AN17 BA21 BM49 CA58 CH7 D41 M4 CKPLUS_WAIVE=PWRTERM2GND
1.62-1.98V @43mA MAX CKPLUS_WAIVE=PWRTERM2GND
A59 AN21 BA30 BM53 CA6 CH9 D46 M64 PP1V8 AJ62 VDD18_EFUSE1 CG7
=| ||| |-
-- -| --
29 25 18 17 13 12 11 9 8 7 5
52 48 47 46 39
A63 AN25 BA34 BM58 CA62 CJ1 D5 M65
- - ||-
AN62 VDD18_EFUSE2 G34
- | ||||| |||||-
1
C1602 C1607 C1610 C1614
||| |||| -
A66 AN30 BA38 BM6 CB1 CJ3 D52 M66 1 1 1 AU62
- - |- ||
VDDIO18_GRP1
||- |- | |==
A9 AN34 BA43 BM62 CB3 CJ4 D56 M67 10UF 2.2UF 2.2UF 2.2UF BA62
- | - ||
||
20%
- | |-
20% 20% 20%
- - ||-
AA1 AN38 BA47 BN1 CB66 CJ41 D59 P10 6.3V 6.3V 6.3V 6.3V BF62
- - ||-
2 CERM-X5R 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM
|-
AA67 AN43 BA51 BN67 CB67 CJ42 D63 P15 0402-9 0201-1 0201-1 0201-1
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC
AB10 AN47 BA55 BP13 CC13 CJ46 D65 P19 G40
AB15 AN51 BA60 BP17 CC17 CJ5 D67 P23 G45
AB19 AN55 BA8 BP21 CC21 CJ50 D7 P28 G49 VDDIO18_GRP2
AB23 AN60 BC1 BP25 CC30 CJ54 D9 P32 G53
AB28 AN8 BC2 BP30 CC34 CJ57 E12 P36
=| ||| |-
-- -| --
AB32 BP34 CC38 CJ61 E14
- - ||-
AP1 BC66 P40 AD6
- | ||||| |||||-
||| |||| -
AB36 AP4 BC67 BP38 CC43 CJ64 E18 P45 AJ6
- - |- ||
||- |- | |==
AB40 AP64 BD10 BP43 CL22 CJ65 E2 P49 AN6
- | - ||
||
- | |-
VDDIO18_GRP3
- - ||-
AB45 AP67 BD23 BP47 T30 CJ67 E20 P53 BA6
- - ||-
|-
AB49 AR10 BD28 BP51 CC8 CK4 E22 P6 BF6
AB53 AR15 BD32 BP55 CD2 CK41 E26 P62
AB58 AR19 BD36 BP8 CD4 CK42 E27 R2 CE19
AB6 AR28 BD40 BR3 CD64 CK46 E29 R4 CE23 VDDIO18_GRP4
AB62 AR32 BD45 BR65 CD66 CK5 E3 R64
AC2 AR36 BD49 BT10 CE10 CK50 E37 R66 1.62-1.98V @10mA MAX CE28
C
=|
PP1V8_SDRAM
C
m
- - ||- | - - -
47 41 40 37 36 32 21 20 18 16
53 52 48
AC4 CE15 E4
- - ||-
AR40 BD53 BT15 CK54 T13 CE32
- | ||||| |||||-
C1603 C1601
||| |||| -
AC64 AR45 BD58 BT19 CE47 CK57 E5 T25 1 1 CE34
- - |- ||
|
||- |- | |==
AC66 AR49 BD62 BT23 CE53 CK61 E54 T34 2.2UF 0.1UF CE36 VDDIO18_GRP10
- | - ||
o
||
- | |-
20% 20%
- - ||-
AD13 AR53 BF21 BT28 CE6 CK64 E57 T38 6.3V 6.3V CE43
- - ||-
VSS VSS VSS VSS VSS VSS VSS VSS 2 X5R-CERM 2 X5R-CERM
|-
AD17 AR58 BF25 BT32 CE62 CL1 E59 T51 0201-1 01005 CE38
.c
ROOM=SOC ROOM=SOC
AD21 AR6 BF30 BT36 CF1 CL12 E61 T55
AD25 AR62 BF34 BT40 CF2 CL18 E64 U1 1.62-1.98V @2mA MAX AR23 VDD18_TSADC0
AD30 AT1 BF43 BT45 CF64 CL24 E65 U67 BK19 VDD18_TSADC1
x
AD34 AT3 BF47 BT49 CF65 CL27 E66 V10 AF21 VDD18_TSADC2
AD43 AT65 BF51 BT53 CF66 CL3 E7 V15 J36
=|
VDD18_TSADC3
fi
- - ||- | - - -
CF67
- - ||-
AD47 AU13 BF55 BT58 CL33 E9 V28 CE21
|
VDD18_TSADC4
- | ||||| |||||-
||| |||| -
AD51 AU17 BF8 BT6 CG1 CL39 F1 V32 BF60
- - |- ||
|
VDD18_TSADC5
||- |- | |==
a
AD55 AU21 BG1 BT62 CG11 CL4 F2 V36
- | - ||
||
- | |-
- - ||-
AD60 AU25 BG3 BU1 CG2 CL41 F3 V40 1.62-1.98V @1mA MAX CG9
- - ||-
VDD18_FMON
|-
in
AD8 AU30 BG65 BU67 CG24 CL44 F4 V53
AF10 AU34 BG67 BV2 CG27 CL48 F64 V58 1.62-1.98V @1mA MAX CC40 VDD18_LPOSC
AF15 AU38 BH10 BV4 CG4 CL52 F65 V6
AF19 AU43 BH15 BV64 CG42 CL56 F66 V62 TBD-TBDV @30mA MAX AU23
PP1V2_REF
h
19 VDD12_CPU_UVD
AF23 AU47 BH19 BV66 CG44 CL59 F67 W3 T28 VDD12_GPU_UVD
AF28 AU51 BH23 BW13 CG46 CL63 G38 W65 1 C1611 Y38
=|
VDD12_SOC_UVD
.c
- - ||- | - - -
CG48 2.2UF
- - ||-
AF32 AU55 BH28 BW17 CL65 G43 Y13
|
20%
- | ||||| |||||-
||| |||| -
AF36 AU60 BH32 BW21 CG5 CL67 G47 Y17 2 6.3V BA25
- - |- ||
|
X5R-CERM VDD12_PLL_CPU
||- |- | |==
AF40 AU8 BH36 BW25 CG52 CL7 G51 Y21 0201-1
- | - ||
||
- | |-
ROOM=SOC
w
- - ||-
AF45 AV1 BH40 BW30 CG54 CM18 G8 Y25 Y32
- - ||-
R1602
|-
AF49 AV2 BH45 BW34 CG56 CM2 H1 Y30 VDD12_PLL_CPU:1.14-1.26V @13mA MAX AD36
AF53 CG59 H2 0.00
w
AV4 BH49 BW38 CM24 Y43 PP1V2_SOC 1 2 PP1V2_PLL_CPU AD38 VDD12_PLL_SOC
B B
19 10 8
AF58 AV64 BH53 BW43 CG61 CM27 H66 Y47 0% Y34
AF6 AV66 BH58 BW47 CG64 CM39 H67 Y51 1/32W
MF 1 C1606
AG1
AG3
AW10
AW15
BH6
BH62
BW51
CE51
CG65
CG66
CM4
CM41
w J10
J15
Y55
BF38
01005
ROOM=SOC 0.1UF
20%
=|
2 6.3V
-
- - - ||| - - |
01005
||| ||||| ||- -
R1601
- | |-
- - ||-
0.00
=
ROOM=SOC
- - ||-
- | ||||| |||||-
||| |||| -
||- |- | |==
- | |-
- - ||-
SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
spare
DRAWING NUMBER SIZE
315mA MAX
R1703
24.9
25 18 17 16 13 12 11 9 8 7 5
52 48 47 46 39 29
PP1V8 1 2 PP1V8_NAND_AVDD
1%
1/32W
MF
01005
ROOM=NAND
1
C1726
2.2UF
1
C1710
0.1UF
20% 20%
6.3V 6.3V
2 X5R-CERM 2 X5R-CERM
0201-1 01005
ROOM=NAND ROOM=NAND
17 NAND_AGND
PROBE POINTS
D D
1
C1701
15UF
1
C1707
15UF
1
C1729
15UF
1
C1730
15UF 17 8 90_PCIE_AP_TO_NAND_REFCLK_P 1
SM
PP1701
PP
20% 20% 20% 20% P2MM-NSM
6.3V 6.3V 6.3V 6.3V ROOM=NAND
2 X5R
0402-1
ROOM=NAND
2 X5R
0402-1
ROOM=NAND
2 X5R
0402-1
ROOM=NAND
2 X5R
0402-1
ROOM=NAND
17 8 90_PCIE_AP_TO_NAND_REFCLK_N 1
SM
PP PP1702
P2MM-NSM
ROOM=NAND
1
C1708 1
C1711 1
C1717 1
C1723 1
C1712
100PF
220PF 22PF
5%
68PF
5%
39PF
5% 5%
5% 16V
2 10V 2 16V 2 16V 2 16V 2
C0G-CERM CERM NP0-C0G NP0-C0G NP0-C0G
01005 01005 01005 01005 01005
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND
19 PP0V9_NAND
1007mA MAX
1
C1704 1
C1702 1
C1705 1 C1722 1 C1727
15UF 15UF 15UF 15UF 15UF
20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
C C
m
0402-1 0402-1 0402-1 0402-1 0402-1 #24543147:10uF for 32GB
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND
#26326159:10uF for C1719 1230mA MAX (1us peak power)
PP3V0_NAND
o
OMIT OMIT OMIT OMIT OMIT
.c
1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 20% 20% 20% 20% 20% 20%
20% 20% 20% 20% 20% 20% 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 X5R 2 X5R 2 X5R 2 CERM-X5R 2 X5R 2 X5R
2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 0402-1 0402-1 0402-1 0402-9 0402-1 0402-1
X5R X5R X5R X5R X5R X5R
0201-1 0201-1 0201-1 0201-1 0201-1 0201-1 ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND
x
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND
fi
1 C1703 1 C1706 1 C1709 1 C1714 1 C1720 1 C1728
1 C1749 1 C1750 1 C1751 1 C1752 1 C1753 1 C1754
1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF
220PF 22PF 100PF 220PF 100PF 68PF 20% 20% 20% 20% 20% 20%
a
5%
10V
5%
16V 5% 5% 5% 5% 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V 2 6.3V
2 C0G-CERM 2 CERM 2 16V 2 10V
C0G-CERM 2 16V 2 16V
NP0-C0G 0201-1 0201-1 0201-1 0201-1
X5R
0201-1
X5R
0201-1
01005 01005 NP0-C0G 01005 NP0-C0G 01005
in
01005 01005 ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND
h
25 18 17 16 13 12 11 9 8 7 5
52 48 47 46 39 29
PP1V8 220PF 22PF 68PF 39PF 100PF 220PF 100PF
5% 5% 5% 5% 5% 5% 5%
2 10V 2 16V 16V 16V 16V 10V 2 16V
.c
1
C1724
0.01UF
C0G-CERM
01005
CERM
01005
2 NP0-C0G
01005
2 NP0-C0G
01005
2 NP0-C0G
01005
2 C0G-CERM
01005
NP0-C0G
01005
10% ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND
6.3V
2 X5R
01005
NAND_VREF
OG10
OD10
w
OB10
OA10
OF10
OG0
OD0
OB0
OA0
OF0
M4
R3
R7
R5
C3
E5
A3
A7
A5
K4
K6
F2
ROOM=NAND
J1
J9
J5
J7
C1725
PCI_AVDD_CLK1
w
PCI_AVDD_CLK2
PCI_AVDD_H
PCI_VDD1
PCI_VDD2
AVDD1
VREF
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VCC
VCC
VCC
VCC
VCC
VCC
1
B 0.01UF
10%
B
2 6.3V
X5R
01005
ROOM=NAND w U1701
THGBX6T1T82LFXF
VLGA
AP_TO_NAND_SYS_CLK D2 CLK_IN EXT_D0 G3 PMU_TO_NAND_LOW_BATT_BOOT_L
VER-1
11 20
EXT_D1 J3 AP_TO_NAND_FW_STRAP
90_PCIE_AP_TO_NAND_REFCLK_P H8 PCIE_REFCLK_P
12
17 8
EXT_D2 H2
90_PCIE_AP_TO_NAND_REFCLK_N H6 PCIE_REFCLK_M ROOM=NAND NC
17 8
EXT_D3 E3
NC
PCIE_NAND_BI_AP_CLKREQ_L G9 PCIE_CLKREQ*
BOMOPTION=OMIT_TABLE
EXT_D4 E7
8
CRITICAL NC
EXT_D5 F6
PCIE_NAND_RESREF M6 PCI_RESREF NC
EXT_D6 C7
NC
1 90_PCIE_AP_TO_NAND_TXD_P M8 PCIE_RX0_P EXT_D7 B8 SYSTEM_ALIVE
R1704
3.01K
8
90_PCIE_AP_TO_NAND_TXD_N K8 PCIE_RX0_M
15 20 21
1%
8
EXT_NCE G1 PCIE_AP_TO_NAND_RESET_L 8
1/32W N5
MF NC PCIE_RX1_P F4 ROOM=NAND 0.00 R1702
01005 N3 EXT_NRE SWD_AP_BI_NAND_SWDIO_R 1 2 SWD_AP_BI_NAND_SWDIO 13
2 ROOM=NAND NC PCIE_RX1_M 1/32W 0% 01005 MF
C5 ROOM=NAND 0.00 R1707
P8 EXT_NWE SWD_AP_NAND_SWCLK_R 1 2 SWD_AP_TO_MANY_SWCLK 13 36 53
8 90_PCIE_NAND_TO_AP_RXD_P PCIE_TX0_P 1/32W 0% 01005 MF
90_PCIE_NAND_TO_AP_RXD_N N7 PCIE_TX0_M EXT_RNB G5
8 NC
M2 PCIE_TX1_P EXT_CLE H4
NC NC
K2 PCIE_TX1_M
NC EXT_ALE D4
7 AP_TO_NAND_RESET_L F8 RESET*
A NC
D8 TRST*
SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
NAND_ZQ D6 ZQ PAGE TITLE
spare
VSSA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
1
R1701
34.8
DRAWING NUMBER
051-00419
SIZE
D
B2
B4
B6
OE10
G7
L3
L5
L7
P2
P4
P6
OC0
OC10
0.5% OE0 Apple Inc.
1/32W REVISION
MF
01005
2 ROOM=NAND
17 NAND_AGND
R
8.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
BAT/USB
53
PP_VDD_MAIN
13.4A MAX
28 27 26 25 23 21 19 10 9 4
1 2 ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU
H14 VDD_MAIN_W A6 BUCK0_LX1
BUCK0
52 46 41 40 39 37 35 34 33 31
BUCK INPUT
0201-1 0201-1 0201-1 0201-1 0201-1 C13
ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU B18 BUCK1_LX0 1 2 PP_GPU_VAR 14
D13 PIQA20161T-SM
C18 NO_XNET_CONNECTION=1 CRITICAL
BUCK1_LX0
H1 D18
ROOM=PMU 1 C1813 1 C1820 1 C1827 1 C1833 1 C1839 1 C1865 0.67V - 0.92V
13.4A MAX
H2 VDD_BUCK2 A18 15UF 15UF 15UF 15UF 15UF 15UF
20% 20% 20% 20% 20% 20%
C1877 C1849 C1856 0.22UH-20%-6.7A-0.023OHM
BUCK1
1 1 1 H3 2
6.3V 6.3V
2 X5R
6.3V
2 X5R
6.3V
2 X5R
6.3V
2 X5R
6.3V
2 X5R
X5R
2.2UF 2.2UF
20%
2.2UF
20% A16 BUCK1_LX1 1 2 0402-1 0402-1 0402-1 0402-1 0402-1 0402-1
20% T2 ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU
6.3V 6.3V
2 6.3V
X5R-CERM 2 X5R-CERM 2 X5R-CERM VDD_BUCK3 B16 NO_XNET_CONNECTION=1 PINA20121T-SM CRITICAL
0201-1 0201-1 0201-1 T3 BUCK1_LX1 ROOM=PMU
C16
ROOM=PMU ROOM=PMU ROOM=PMU
M1 D16
M2 VDD_BUCK4 L1812 1 C1814 1 C1821 1 C1828 1 C1834 1 C1866 1 C1873
0.22UH-20%-6.7A-0.023OHM
C M3
C
m
15UF 15UF 15UF 15UF 15UF 220PF
A14 BUCK1_LX2 2 1 20% 20% 20% 20% 20% 5%
B1 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 10V
C0G-CERM
B14 PINA20121T-SM CRITICAL
VDD_BUCK5 BUCK1_LX2 0402-1 0402-1 0402-1 0402-1 0402-1 01005
C1 NO_XNET_CONNECTION=1 ROOM=PMU
o
C14 ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU
D1
D14
L1813
.c
K18
VDD_BUCK6 0.22UH-20%-6.7A-0.023OHM
K19
A12 BUCK1_LX3 1 2
U6 PINA20121T-SM
VDD_BUCK7 B12 CRITICAL
x
NO_XNET_CONNECTION=1
V6 BUCK1_LX3 ROOM=PMU
C12
F18
fi
D12
VDD_BUCK8
F19
BUCK1_FB F12BUCK1_PP_GPU_FB 14
L18
L1814
a
VDD_BUCK9
L19 1.0UH-20%-3.6A-0.060OHM
D10/D101:#24681501,TY ONLY, D11/D11: Both Vendor
in
BUCK2_LX0 1 2 PP_SOC_VAR 14
L1803 G1
4.7A MAX
CRITICAL
BUCK2
BUCK2_LX0 G2 PIQA20161T-SM CRITICAL
1.0UH-3.6A-0.06OHM ROOM=PMU 0.67V/0.80V
15 10 9 8 7 PP0V9_SOC_FIXED 2 1 BUCK5_LX0 B2
G3
L1815
1 C1822 1 C1829 1 C1835 1 C1841 1 C1864 1 C1871
h
MEKK2016T-SM C2 0.47UH-20%-3.8A-0.048OHM 15UF 15UF 15UF 15UF 15UF 220PF
BUCK5_LX0 20% 20% 20% 20% 20% 5%
C1867 C1840 C1801 C1803 C1807
BUCK5
.c
220PF 15UF 15UF 15UF 15UF J1 0402-1 0402-1 0402-1 0402-1 0402-1 01005
5% 20% 20% 20% 20% A2 PIQA20121T-SM
OMIT BUCK2_LX1 J2 NO_XNET_CONNECTION=1 CRITICAL ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU
2 10V 2 6.3V 2 6.3V 2 6.3V 2 6.3V
C0G-CERM
01005
X5R
0402-1
ROOM=PMU
X5R
0402-1
ROOM=PMU
X5R
0402-1
ROOM=PMU
X5R
0402-1
ROOM=PMU
XW1802
SHORT-20L-0.05MM-SM
J3
ROOM=PMU
ROOM=PMU
w
2 1 BUCK5_FB F5 BUCK5_FB
BUCK2_FB J5 BUCK2_PP_SOC_FB 14
CRITICAL L1804
ROOM=SOC NO_XNET_CONNECTION=1
L1816 ROOM=PMU
1.0UH-20%-3.6A-0.060OHM
w
1UH-20%-2.1A-0.12OHM
BUCK3
1.7A MAX
w
BUCK6
BUCK6_LX0 NO_XNET_CONNECTION=1 1 1 1
1.5A MAX
4.7A MAX
1.5A MAX
BUCK4
BUCK7
1 1 1 ROOM=PMU NO_XNET_CONNECTION=1 1 1 1 1 1
ROOM=PMU
220PF 15UF 15UF OMIT N3 15UF 15UF 15UF 15UF 220PF
5%
2 10V
20%
2 6.3V
20%
2 6.3V
XW1803 L1818 2
20%
6.3V 2
20%
6.3V
20%
2 6.3V 2
20%
6.3V 2
5%
10V
C0G-CERM X5R X5R SHORT-20L-0.05MM-SM 0.47UH-20%-3.8A-0.048OHM X5R X5R X5R X5R C0G-CERM
01005 0402-1 0402-1 2 1 0402-1 0402-1 0402-1 0402-1 01005
BUCK7_FB R8 BUCK7_FB 2 1
ROOM=PMU ROOM=PMU ROOM=PMU L1 BUCK4_LX1 ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU
ROOM=SOC NO_XNET_CONNECTION=1
PIQA20121T-SM
CRITICAL L1801 BUCK4_LX1 L2
L3
NO_XNET_CONNECTION=1 ROOM=PMU
OMIT
CRITICAL
1UH-20%-2.1A-0.12OHM XW1805
SHORT-20L-0.05MM-SM
14 PP_GPU_SRAM_VAR 2 1 BUCK8_LX0 G18
BUCK4_FB K5 BUCK4_FB 1 2
PIQA20121T-SM G19 BUCK8_LX0
0.80V - 0.92V 1 C1869 1 C1806 1 C1810 ROOM=PMU NO_XNET_CONNECTION=1 ROOM=SOC
1.5A MAX
BUCK8
A CRITICAL L1802
1.0UH-20%-1.5A-0.161OHM T1 PP1V8 5 7 8 9 11 12 13 16 17 25 29 39 A
BUCK3_SW1
SYNC_MASTER=Sync SYNC_DATE=05/17/2016
46 47 48 52
PAGE TITLE
1 2 U1
25 PP2V8_UT_AF_VAR BUCK9_LX0
0603
M18
BUCK9_LX0 spare
SWITCH OUTPUTS
M19
0.75A MAX
53 52
27 26 25 23 21 19 18 10 9 4
46 41 40 39 37 35 34 33 31 28
PP_VDD_MAIN ADELYN LDO SPECS
1 1 1 1
OMIT
1
C1901
15UF
C1910
10UF
C1914
10UF
C1911
10UF
C1907
10UF
XW1901
SHORT-20L-0.05MM-SM
20%
6.3V
20%
6.3V
20%
6.3V
20%
6.3V
20%
6.3V
LDO# ADJ.RANGE, LOW ADJ.RANGE, HI ACCURACY MAX.CURRENT LDO# ADJ.RANGE, LOW ADJ.RANGE, HI ACCURACY MAX.CURRENT
18 VDD_MAIN_SNS 2 1 2 X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R
0402-1 0402-9 0402-9 0402-9 0402-9 LDO1 (Ca) 1.2-2.475V 2.4-3.675V +/-1.4% 50mA 1.2-2.475V 2.4-3.675V
ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU LDO11 (Cb) +/-30mV 250mA
NO_XNET_CONNECTION
OMIT LDO2 (Ca) 1.2-2.475V 2.4-3.675V +/-2.5% 50mA LDO12 (E) 1.8V +/-5% 10mA
XW1902
SHORT-20L-0.05MM-SM LDO3 (Ca) 1.2-2.475V 2.4-3.675V +/-2.5% 50mA LDO13 (Cb) 1.2-2.475V 2.4-3.675V +/-30mV 250mA
20 PMU_PRE_UVLO_DET 2 1
D
ROOM=PMU
LDO4 (D) 0.7-1.2V +/-2.5% 60mA LDO14 (Gb) 0.7-1.4V +/-3.0% 400mA
D LDO5 (F) 2.5-3.6V(tbc) +/-75mV 1000mA LDO15 (Ca) 1.2-2.475V 2.4-3.675V +/-2.5% 50mA
1.2-2.475V 2.4-3.675V 250mA
LDO6 (Cb) +/-2.5% (500/100mA in bypass)
LDO16 (Cb) 1.2-2.475V 2.4-3.675V +/-30mV 250mA
LDO7 (Cb) 1.2-2.475V 2.4-3.675V +/-30mV 250mA
LDO17 (Ca) 1.2-2.475V 2.4-3.675V +/-2.5% 50mA
53 52
27 26 25 23 21 19 18 10 9 4 PP_VDD_MAIN LDO8 (Cb) 1.2-2.475V 2.4-3.675V +/-30mV 250mA
46 41 40 39 37 35 34 33 31 28 LDO18 (Gb) 0.7-1.4V +/-3.0% 400mA
LDO9 (Cb) 1.2-2.475V 2.4-3.675V +/-25mV 250mA
LDO19 (Gb) 0.7-1.4V +/-3.0% 400mA
53 38 37 32 25 23 PP_VDD_BOOST LDO10 (Ga) 0.7-1.2V +/-4.5% 1150mA
LDO_RTC 2.5V +/-2.0% 10mA
1 C1915 1 C1912 BUF_1V2 1.2V +/-5.0% 10mA
15UF
20%
15UF
20%
6.3V
2 X5R
6.3V
2 X5R U1801
0402-1 0402-1
ROOM=PMU ROOM=PMU D2333A1
WLCSP
SYM 1 OF 4
VLDO1 T12 PP3V3_USB 7 LDO1
VLDO2 U11 PP1V8_VA 32 33 34 35 LDO2
R12
VLDO3 T10 PP3V0_ALS_APS_CONVOY 25 29 LDO3
VDD_LDO1
VLDO4 T16 PP0V8_AOP 15 LDO4
V11 VDD_LDO2_15
R10
VLDO5_0 U9 PP3V0_NAND 17 52 LDO5
VDD_LDO3_17
VLDO5_1 U10
18 15 PP1V1_SDRAM R16 VDD_LDO4
V9
VLDO6 T14 PP_ACC_VAR 27 40 46 LDO6
1 C1908 1 C1913 VDD_LDO5
LDO INPUT
2.2UF 2.2UF V10 VBYPASS R15
20% 20% R14 VDD_LDO6_BYP
6.3V 6.3V
2 X5R-CERM 2 X5R-CERM VLDO7 T17 PP3V0_TRISTAR_ANT_PROX 29 40 41 53 LDO7
C P19 VDD_LDO7_8
C
m
0201-1 0201-1 VLDO8 P18 PP2V9_NH_AVDD 29 LDO8
ROOM=PMU ROOM=PMU R19 VDD_LDO9
VLDO9 R18 PP1V8_HAWKING 44 LDO9
R9 VDD_LDO10
o
V13 VDD_LDO11_13 VLDO9_FB P17
18 PP1V25_BUCK V16 VDD_LDO14
VLDO10 T9 PP0V9_NAND 17 LDO10
.c
T19 VDD_LDO16
VLDO11 U13NC LDO11
V17 VDD_LDO18
VLDO12 P7 PP1V8_ALWAYS 20 21 LDO12
V18 VDD_LDO19
LDO
VLDO13 U14 PP3V0_MESA 38 LDO13
U19 VDD_LDO19
x
VLDO14 U16 PP1V2_SOC 8 10 16 LDO14
VLDO15 U12 PP1V8_MESA 38 48 LDO15
R1901 MF NOSTUFF
fi
G15 VPP_OTP VLDO16 T18NC #24989262 1/20W LDO16
PP_LDO17
1%
2
0.00 1 0201
VLDO17 T11 LDO17
U1801
D2333A1 VLDO18 U17 PP1V2_UT_DVDD LDO18
in
A1 G17
A11 G4
NC J6 TP_DET VBUF_1V2 P8 PP1V2_REF 16 VBUF_1V2
A15 H17
h
H8 H18
A19 H19
P13 H4 1 C1918 1 C1933 1 C1923 1 C1926 1 C1935 1 C1930 1 C1932
.c
VPUMP R5 2.2UF 1.0UF 2.2UF 2.2UF 1.0UF 2.2UF 0.22UF
A3 J17 20% 20% 20% 20% 20% 20% 20%
P14 J4 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V
X5R-CERM X5R X5R-CERM X5R-CERM X5R X5R-CERM X5R
A7 J8 0201-1 0201-1 0201-1 0201-1 0201-1 0201-1 01005-1
w
ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU
B11 K1
B15 K17
C1916
w
B19 K2 1
C1921 C1922 C1925 C1927 C1904 1 C1919
B B3 K3
PMU_VPUMP 2.2UF
20%
1
2.2UF
1
2.2UF
1
1.0UF
1
2.2UF
1
2.2UF 2.2UF B
B7 K4 1 C1902 2 6.3V 20% 20% 20% 20% 20% 20%
6.3V
C11
C15
C19
K8
L17
L4
2
47NF
20%
6.3V
X5R-CERM
01005
w X5R-CERM
0201-1
ROOM=PMU
2 6.3V
X5R-CERM
0201-1
ROOM=PMU
2 6.3V
X5R-CERM
0201-1
ROOM=PMU
2 6.3V
X5R
0201-1
ROOM=PMU
2 6.3V
X5R-CERM
0201-1
ROOM=PMU
2 6.3V
X5R-CERM
0201-1
ROOM=PMU
2 X5R-CERM
0201-1
ROOM=PMU
ROOM=PMU
C3 L8 #24989262:OTP-AO LDO17 default off,50mA Iout_max
C7 M17
D11 M4 VPUMP: 10nF min. @4.6V
D15 N17
D19 N18
D3 N19
D7 N4
VSS VSS
E1 P1
E10 P2
E11 P3 53 52
27 26 25 23 21 19 18 10 9 4
46 41 40 39 37 35 34 33 31 28
PP_VDD_MAIN
E12 P4
E13 P15 1 C1905 1 C1909
E14 R17 33PF 220PF
5% 5%
E15 R4 2 16V
NP0-C0G-CERM 2 10V
C0G-CERM
E16 T5 01005 01005
ROOM=PMU ROOM=PMU
E17 T15
E18 T4
E19 T6
E2 T7
E3 T8
PMU_VSS_RTC
A E4
E5
U15
T13
20
A
U15 = PMU XTAL GND
SYNC_MASTER=Sync SYNC_DATE=05/17/2016
E6 U8 PAGE TITLE
E7 V1 spare
E8 V12 DRAWING NUMBER SIZE
E9 V19
Apple Inc. 051-00419 D
F1 V8 REVISION
F17
R
8.0.0
F2 NOTICE OF PROPRIETARY PROPERTY: BRANCH
P2MM-NSM
ROOM=SOC
1
R2008
100K
1 PP SM PP2003
P2MM-NSM
5%
1/32W
MF
47 41 40 37 36 32 21 20 18 16 PP1V8_SDRAM PP1V8_ALWAYS 19 20 21 ROOM=PMU 01005
53 52 48 2 ROOM=PMU
BUTTON_RINGER_A
D
44 20
D 1
R2006
100K
1
R2005
100K
1
R2012
10K
U1801
D2333A1
PP1V8_ALWAYS 19 20 21
5% 5% 5% WLCSP NOSTUFF
1/32W
MF
01005
1/32W
MF
01005
1/32W
MF
01005 7 AP_TO_PMU_WDOG_RESET P9 RESET_IN1
SYM 3 OF 4
IREF K6 PMU_IREF
1
R2007
220K
2 ROOM=PMU 2 ROOM=PMU 2 ROOM=PMU 5%
40 TRISTAR_TO_PMU_HOST_RESET P10 RESET_IN2 1/32W
RESETS
NO_XNET_CONNECTION MF
AP_TO_PMU_SOCHOT_L PMU_VREF
REFS
11 P11 RESET_IN3 VREF J7 01005
2 ROOM=PMU
PMU_TO_SYSTEM_COLD_RESET_L M5 RESET* 1 1 BUTTON_POWER_KEY_L
13 7
SHDN
C2006
0.22UF
R2011
200K
44 20
COMPARATOR
SYSTEM_ALIVE VDROOP1* G7 PMU_TO_AP_THROTTLE_GPU_L 11 44 20 BUTTON_VOL_DOWN_L
21 17 15 H5 SYS_ALIVE
53 39 23 13 LCM_TO_MANY_BSYNC HIGH=FORCE PWM MODE L13 FORCE_SYNC
NC L10 CRASH* VDROOP0_DET F6 AP_VDD_CPU_SENSE 14
PMGR
ROOM=PMU
11 SPI_PMGR_TO_PMU_MOSI N5 MOSI
IBAT L7 NC
C SPI_PMU_TO_PMGR_MISO P5 MISO
C
m
11
VBAT M7 NC
ADC
BRICK_ID H7 TRISTAR_TO_PMU_USB_BRICK_ID 20 40
7 AP_TO_PMU_AMUX_OUT J14 AMUX_A0
PMU_ADC_IN
ADC_IN K7
o
20 PMU_ADC_IN J15 AMUX_A1
20
NC J16 AMUX_A2
FOREHEAD NTC
.c
44 12 BUTTON_VOL_UP_L K16 AMUX_A3 BUTTON1 M12 BUTTON_VOL_DOWN_L 20 44
BUTTONS
39 37 20 44
AMUX
TRISTAR_TO_PMU_USB_BRICK_ID J13 AMUX_A6 BUTTON4 N11 NC Reserved for MENU key on dev board
C2007 1 R2001
x
40 20
fi
5% 4
16V 2 01005 BUTTONO2 J11 PMU_TO_AP_BUF_POWER_KEY_L 12 Button for two-finger reset: 20711463 and 21196187
NP0-C0G
01005 2 ROOM=PMU 53 BBPMU_TO_PMU_AMUX1 L14 AMUX_B0 BUTTONO3 K11 PMU_TO_AP_BUF_RINGER_A 12
ROOM=PMU
BBPMU_TO_PMU_AMUX2 L15 AMUX_B1
a
53
NC L16 AMUX_B2
GPIO1 F16 TIGRIS_TO_PMU_INT_L 21
ACC_BUCK_TO_PMU_AMUX M16 AMUX_B3
TBD
R2000
in
27
GPIO2 F15 BB_TO_PMU_PCIE_HOST_WAKE_L 53
PMUGPIO_TO_WLAN_CLK32K M15 AMUX_B4 1.00K
1 C2013 53 20
CHESTNUT_TO_PMU_ADCMUX M14 AMUX_B5
GPIO3 G14 PMU_TO_BBPMU_RESET_R_L 1 2 PMU_TO_BBPMU_RESET_L 53
h
2 X5R GPIO5 F13 53 MF
01005 53 BBPMU_TO_PMU_AMUX3 N15 AMUX_B7 01005
1 GPIO6 G13 PMU_TO_NAND_LOW_BATT_BOOT_L 17 ROOM=PMU
ROOM=PMU 4 PMU_AMUX_BY N14 AMUX_BY
GPIO7 NC_PMU_TO_GNSS_EN
.c
PLACE_NEAR=U1801:2mm G12
1
C2008
100PF
R2002 FOREHEAD_NTC R6 TDEV1
GPIO8 H12 PMUGPIO_TO_WLAN_CLK32K 20 53
GPIO
NTC
01005 ROOM=PMU RADIO_PA_NTC P6 TDEV3
ROOM=PMU 2 SHORT-20L-0.05MM-SM GPIO11 F9 PMU_TO_WLAN_REG_ON 53
ROOM=SOC 1 2 AP_NTC L5 TDEV4
GPIO12 G9 BT_TO_PMU_HOST_WAKE 53
OMIT L6 TDEV5
w
NC GPIO13 F8 PMU_TO_CODEC_DIGLDO_PULLDN
B PMU_TCAL
B
32
G16 TCAL
XW2003
SHORT-20L-0.05MM-SM
GPIO14 G8 PMU_TO_ACC_BUCK_SW_EN 27
R2009
XTAL
53
OMIT PMU_XTAL2 V15 XTAL2 0.00
RADIO PA NTC XW2004 GPIO17 J9 PMU_TO_AP_FORCE_DFU_R 1 2 PMU_TO_AP_FORCE_DFU 4 12
100PF
5% 10KOHM-1%
XW2005
SHORT-20L-0.05MM-SM
0.22UF
20%
37 47 RS
CRITICAL
1 1
C2011
100PF
R2010
3.92K
Y2001
32.768KHZ-20PPM-12.5PF
AP NTC 5%
16V
0.1%
1/20W 1 2
2 NP0-C0G MF
01005 0201
1 2 ROOM=PMU 1 1
ROOM=PMU
C2003
22PF
1.60X1.00-SM
ROOM=PMU C2004
22PF
C2010 1 R2004 5%
16V
CERM 2
5%
16V
2 CERM
100PF 01005 01005
5% 10KOHM-1% AP_NTC_RETURN ROOM=PMU ROOM=PMU
16V 2 01005 19 PMU_VSS_RTC
NP0-C0G
2
01005
ROOM=PMU
ROOM=PMU
XW2001
SHORT-20L-0.05MM-SM
1 2
ROOM=PMU
A OMIT
A
NOTE:100PF CAPS ARE THE SAMPLING CAPS FOR PMU ADC SYNC_MASTER=Sync
PAGE TITLE
SYNC_DATE=05/17/2016
spare
DRAWING NUMBER SIZE
TIGRIS CHARGER
D D
TIGRIS_LDO
C TIGRIS_PMID
C
m
1 C2104 1 C2115
1 C2103 1 C2109 1 C2111 1 C2112 220PF 2.2UF
D2
C2
A2
B2
5% 20%
330PF 4.2UF 4.2UF 330PF
o
2 10V 2 6.3V
X5R-CERM
A2
A3
B1
B2
B3
10% 10% 10% 10% C0G-CERM
VDD_MAIN
VDD_MAIN
VDD_MAIN
VDD_MAIN
16V 16V 16V 16V 01005 0201-1
2 CER-X7R 2 X5R-CERM 2 X5R-CERM 2 CER-X7R S CRITICAL
ROOM=CHARGER ROOM=CHARGER
Q2101
.c
01005 0402-1 0402-1 01005
ROOM=CHARGER ROOM=CHARGER ROOM=CHARGER ROOM=CHARGER 28
TO TRINITY A1
CSD68827W
NO_XNET_CONNECTION G BGA
#25112685,Remove Snub ROOM=CHARGER
F5 G4 C2105
x
PMID U2101 LDO
0.047UF C2106 1 C2102 1
A5 SN2400AB0 G5 1 2 330PF 220PF D
PP5V0_USB VBUS BOOT TIGRIS_BOOT
fi
40 4 WCSP 10% 5%
B5 16V 10V 2
VBUS A4
C2101 C2110 2
C1
C2
C3
1 1 ROOM=CHARGER ROOM=CHARGER 10% CER-X7R C0G-CERM
D5 BUCK_SW 16V 01005 01005
4.2UF 330PF VBUS CRITICAL B4 X5R ROOM=CHARGER ROOM=CHARGER
C5 BUCK_SW
a
20 19 PP1V8_ALWAYS 10% 10% VBUS D4 0201
2 16V
X5R-CERM 2 16V
CER-X7R E5 BUCK_SW
0402-1 01005 VBUS C4
BUCK_SW TIGRIS_BUCK_LX
in
ROOM=CHARGER ROOM=CHARGER
1
R2101 47 I2C1_AP_SDA
G3
SDA A1
100K E4 BAT
5% 47 I2C1_AP_SCL SCL B1
1/32W BAT
MF E3 D1
SYSTEM_ALIVE
h
2 01005 20 17 15 SYS_ALIVE BAT
ROOM=CHARGER C1
F4 BAT PP_BATT_VCC
R2103
4 22
40 TRISTAR_TO_TIGRIS_VBUS_OFF VBUS_OVP_OFF
E1
.c
F4: 100 kOhm pullup to VLDO (regulated output voltage)
100 G2 BAT_SNS VBATT_SENSE
20 TIGRIS_TO_PMU_INT_L 1 2 TIGRIS_TO_PMU_INT_R_L INT
E2
22
1 C2108 1 C2117 1 C2118
5%
ROOM=CHARGER
F1 ACT_DIODE TIGRIS_ACTIVE_DIODE 330PF 2.2UF 2.2UF
#24558610: Change to 100ohm 1/32W TIGRIS_VBUS_DETECT VBUS_DET 10% 20% 20%
16V
MF G1 NOSTUFF 2 CER-X7R 2 6.3V 2 6.3V
w
01005 F3 HDQ_HOST SWI_AP_BI_TIGRIS X5R-CERM X5R-CERM
R2102 1
12 01005 0201-1 0201-1
TEST
PGND
PGND
PGND
PGND
F2
R2104 HDQ_GAUGE TIGRIS_TO_BATTERY_SWI_1V8
100K
ROOM=CHARGER ROOM=CHARGER ROOM=CHARGER
30.1K 2 5%
w
USB_VBUS_DETECT 1 1/32W
B B
7
A3
B3
D3
C3
1%
ROOM=CHARGER 48 47 41 40 37 36 32 20 18 16 PP1V8_SDRAM MF
01005
ROOM=CHARGER 2
53 52
1/32W
MF
01005
w 1
R2105 Q2102
40.2K RV3C002UN
1% DFN
1
1/32W
MF
G
2 01005
TIGRIS_TO_BATTERY_SWI 22
3
D
S
SYM_VER_1
A SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
spare
DRAWING NUMBER SIZE
D D
BATTERY CONNECTOR
THIS ONE ON MLB ---> 516S00172 (matches d10 mlb MCO rev 27)
C C
m
XW2201
o
SHORT-20L-0.05MM-SM
1 2 VBATT_SENSE 21
ROOM=BATTERY_B2B
.c
PLACE_NEAR=J2201:2mm
J2201
RCPT-BATT-SHORT
NO_XNET_CONNECTION=1
F-ST-SM
11
x
7 8
R2201
fi
1 5 PP_BATT_VCC 4 21
100
TIGRIS_TO_BATTERY_SWI 1 2 TIGRIS_BATTERY_SWI_CONN 3 2
21
5% 4 6
1 C2202 1 C2203 1 C2204
a
56PF 100PF 220PF
1/32W
MF
01005
1 C2201 5%
2 25V
5%
2 16V
5%
10V
2 C0G-CERM
56PF 9 10 NP0-C0G-CERM NP0-C0G
in
ROOM=BATTERY_B2B 5% 01005 01005 01005
2 25V
NP0-C0G-CERM 12 ROOM=BATTERY_B2B ROOM=BATTERY_B2B ROOM=BATTERY_B2B
01005 ROOM=BATTERY_B2B
ROOM=BATTERY_B2B
CRITICAL
ALLOW_APPLE_PREFIX
h
.c
w
w
B B
w
A SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
spare
DRAWING NUMBER SIZE
D D
BOOST
C C
m
o
.c
When VDD_MAIN < 3.4, boosts to 3.4
Otherwise tracks VDD_MAIN
PP_VDD_MAIN A3 B3
53
28 27 26 25 21 19 18 10 9 4 VIN VOUT PP_VDD_BOOST 19 25 32 37 38 53
52 46 41 40 39 37 35 34 33 31
A4 U2301 VOUT B4
L2301 ROOM=BOOST VIN
x
1
C2309
10UF
1 C2301 0.47UH-20%-4.2A-0.048OHM C3 SW
SN61280D 1 C2302 1 C2303 1 C2304 1 C2307 1 C2308 1 C2306
4.7UF DSBGA 15UF 15UF 15UF 15UF 15UF 220PF
fi
20% 1 2 C4
6.3V 20% SYS_BOOST_LX SW 20% 20% 20% 20% 20% 5%
2 CERM-X5R 2 6.3V
X5R-CERM1 PIUA20121T-SM ROOM=BOOST 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 10V
C0G-CERM
0402-9 402 A1 0402-1 0402-1 0402-1 0402-1 0402-1 01005
ROOM=BOOST 20 PMU_TO_BOOST_EN EN
a
ROOM=BOOST ROOM=BOOST ROOM=BOOST ROOM=BOOST ROOM=BOOST ROOM=BOOST ROOM=BOOST
I2C0_AP_SCL B2 SCL
R2301
47
1
in
511K 47 I2C0_AP_SDA C2 SDA
1%
1/32W B1
MF VSEL
2 01005
C1
h
BYP*
53 39 20 13 LCM_TO_MANY_BSYNC A2 GPIO
.c
HIGH=FORCE PWM MODE PGND
AGND
D2
D3
D4
D1
w
Control details from Radar 19634006
w
B B
w
A SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
spare
DRAWING NUMBER SIZE
1 C2418 1
BOMOPTION=CARBON_1
C2402 1
BOMOPTION=CARBON_1
C2415
1 C2401 1
2.2UF
0.1UF 20%
2.2UF 0.1UF 0.1UF
C4
20%
20% 20% 20% 2
6.3V 2 6.3V
X5R-CERM
6.3V 6.3V X5R-CERM
2 6.3V
X5R-CERM 2 X5R-CERM 2 X5R-CERM 01005 0201-1 VDD
0201-1 01005 01005 ROOM=MAGNESIUM
36 24 18
PP1V8_MAGGIE_IMU ROOM=CARBON ROOM=CARBON ROOM=CARBON
BOMOPTION: CARBON_1
ROOM=MAGNESIUM
U2402
HSCDTD601A-19A
#25765850:Update Carbon APN
16
1
LGA
C2 VPP SDO B4
BOMOPTION=CARBON_1
SPI_IMU_TO_AOP_MISO
R2401
BOMOPTION=CARBON_1
1
VDD VDDIO NC 13 24
ROOM=MAGNESIUM
114K INT PD
DRDY A1 COMPASS_TO_AOP_INT
5PF 13
+/-0.1PF CRITICAL
13 ACCEL_GYRO_TO_AOP_INT 7 INT DRDY 6 ACCEL_GYRO_TO_AOP_DATARDY 13 2
16V
NP0-C0G
01005
VSS
ROOM=CARBON ROOM=CARBON
PP2404
1
C1
BOMOPTION=CARBON_1 CRITICAL SMPP
1 C2403 P2MM-NSM
0.1UF 9 GND ROOM=MAGNESIUM
10 GND
11 GND
12 GND
13 GND
15 GND
10%
6.3V
2 X6S PP2401
1
C C
SM
m
PP
0201
ROOM=CARBON P2MM-NSM
ROOM=MAGNESIUM
PP2402
o
1 PP SM
#25782019:Add 0ohm P2MM-NSM
.c
ROOM=MAGNESIUM
R2404 PP2403
PP1V8_MAGGIE_IMU 1
0.00 2 24 PP1V8_MAGGIE_IMU_R 1 SMPP
36 24 18
P2MM-NSM
0%
C2448 C2442 C2445
x
1/32W 1 1 1 ROOM=MAGNESIUM
MF
01005 2.2UF 0.1UF 0.1UF #25740540:PP for South Carbon MOSI
20% 20% 20%
fi
ROOM=BOT_CARBON
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
0201-1 01005 01005
PP1V8_MAGGIE_IMU_R
ROOM=BOT_CARBON ROOM=BOT_CARBON ROOM=BOT_CARBON 1
PP SM PP2440
P2MM-NSM
a
24
ROOM=HOMER
16
in
1
R2441
100K
VDD VDDIO
5%
1/32W U2404
MF MPU-6900-21
2 01005
h
ROOM=SOC LGA
13
SPI_AOP_TO_BOT_ACCEL_GYRO_CS_L 5 CS SPC 2 SPI_AOP_TO_IMU_SCLK_R2 13
.c
8 FSYNC SDI 3 SPI_AOP_TO_IMU_MOSI 13 24
NOSTUFF
w
7 INT DRDY 6 BOT_ACCEL_GYRO_TO_AOP_DATARDY 13 2 16V
SHORT-20L-0.05MM-SM NP0-C0G
01005
1 2 BOT_ACCEL_GYRO_TO_XW_INT ROOM=BOT_CARBON
NC ROOM=BOT_CARBON
w
ROOM=BOT_CARBON CRITICAL
B 1 C2443
NO_XNET_CONNECTION=1
XW2404 to balance Via/Cu at INT pin
B
0.1UF
9 GND
10 GND
11 GND
12 GND
13 GND
15 GND
10%
6.3V
2 X6S
0201
ROOM=BOT_CARBON
w
PHOSPHORUS #24593845, #25691124
BOSCH (APN:338S00188): nostuff C2420/C2421/C2422/C2423 and R2403 PU
R2422
1
0.00 2
24 PP1V8_MAGGIE_IMU_FILT PP1V8_MAGGIE_IMU 18 24 36
NOSTUFF NOSTUFF NOSTUFF NOSTUFF
1 C2413 1 C2405 1 C2420 1 C2421 0%
1/32W
MF
1 C2422 1 C2423 1 C2414
0.1UF 0.1UF 4PF 20PF 01005 20PF 5.6PF 2.2UF
20% 20% +/-0.1PF 5% ROOM=PHOSPHORUS 5% +/-0.1PF 20%
2 6.3V 2 6.3V 2 16V 2 16V 2 16V 2 16V 2 6.3V
X5R-CERM X5R-CERM NP0-C0G NP0-C0G-CERM NP0-C0G-CERM NP0-C0G-CERM X5R-CERM
01005 01005 01005 01005 01005 01005 0201-1
ROOM=PHOSPHORUS ROOM=PHOSPHORUS ROOM=PHOSPHORUS ROOM=PHOSPHORUS ROOM=PHOSPHORUS ROOM=PHOSPHORUS ROOM=PHOSPHORUS
24
PP1V8_MAGGIE_IMU_FILT
8
NOSTUFF
BOSCH: Internal PU 1
R2403 VDD VDDIO
100K U2403
A 5%
1/32W
MF 24 13 SPI_AOP_TO_IMU_MOSI 3 SDI
BMP284AA
LGA SDO 5 SPI_IMU_TO_AOP_MISO 13 24
SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
01005 4 SCK PAGE TITLE
2 SPI_AOP_TO_IMU_SCLK_R1
13
ROOM=SOC 24 13
REVISION
R
8.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
U2501 FL2504 D
D LP5907UVX2.925-S
DSBGA VOLTAGE=2.925V
150OHM-25%-200MA-0.7DCR
53 38 37 32 23 19 PP_VDD_BOOST A1 VIN VOUT A2 PP2V9_UT_AVDD_CONN 45 46 9 AP_TO_UT_CLK 1 2 AP_TO_UT_CLK_CONN 45
NOSTUFF
1 C2527 B1 VEN
ROOM=RCAM_B2B
See Page46: D10x C2531/C2507 are 2.2UF 1 C2502 1 C2504 1 C2512
01005
ROOM=RCAM_B2B 1 C2513
2.2UF 0.22UF 220PF 100PF 56PF
20% GND 10% 5% 5% 5%
6.3V 2 10V 2 25V
2 6.3V 2 CER-X5R 2 16V
C0G-CERM NP0-C0G NP0-C0G-CERM
B2
X5R-CERM 01005
0201-1 01005 01005 01005
ROOM=RCAM_B2B ROOM=RCAM_B2B ROOM=RCAM_B2B ROOM=RCAM_B2B ROOM=RCAM_B2B
FL2500 FL2501
33-OHM-25%-1500MA 150OHM-25%-200MA-0.7DCR
1 2
18 PP2V8_UT_AF_VAR PP2V8_UT_AF_VAR_CONN 45 9 AP_TO_UT_SHUTDOWN_L 1 2 AP_TO_UT_SHUTDOWN_CONN_L 45
0201 1
ROOM=RCAM_B2B 1 C2505 1 C2501 01005
ROOM=RCAM_B2B C2514
220PF
2.2UF 220PF 5%
10V
20% 5%
2 6.3V 2 10V 2 C0G-CERM
X5R-CERM C0G-CERM 01005
0201-1 01005 ROOM=RCAM_B2B
ROOM=RCAM_B2B ROOM=RCAM_B2B
FL2502 FL2503
33-OHM-25%-1500MA 150OHM-25%-200MA-0.7DCR
29 19 PP3V0_ALS_APS_CONVOY 1 2 PP3V0_UT_SVDD_CONN 45 26 UT_AND_NV_TO_STROBE_DRIVER_STROBE 1 2 UT_AND_NV_TO_LED_DRIVER_STROBE_EN_CONN 45
0201
ROOM=RCAM_B2B
1
C2519 1
C2518 01005
ROOM=RCAM_B2B
1 C2515
2.2UF 220PF 220PF
20% 5% 5%
6.3V 10V 10V
2 X5R-CERM 2 C0G-CERM 2 C0G-CERM
C C
m
0201-1 01005 01005
ROOM=RCAM_B2B ROOM=RCAM_B2B ROOM=RCAM_B2B
o
FL2505
33-OHM-25%-1500MA
.c
19 PP1V2_UT_DVDD 1 2 PP1V2_UT_VDD_CONN 45
0201
ROOM=RCAM_B2B
1
C2506
2.2UF
1
C2508
2.2UF
1
C2510
2.2UF
1
C2503
220PF
1
C2521
15PF
x
20% 20% 20% 5% 5%
6.3V 6.3V 6.3V 10V 16V
2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 C0G-CERM 2 NP0-C0G-CERM
0201-1 0201-1 0201-1 01005 01005
fi
ROOM=RCAM_B2B ROOM=RCAM_B2B ROOM=RCAM_B2B ROOM=RCAM_B2B ROOM=RCAM_B2B
Desense for Wifi frequencies
a
FL2506 LPDP FILTERS
33-OHM-25%-1500MA
in
1 2
29 18 17 16 13 12 11 9 8 7 5 PP1V8 PP1V8_UT_CONN 45
52 48 47 46 39
0201 1
ROOM=RCAM_B2B
1 C2509 C2511
220PF
1.0UF PP_VDD_MAIN
h
53
5% 28 27 26 23 21 19 18 10 9 4
20% 10V 52 46 41 40 39 37 35 34 33 31
2 6.3V 2 C0G-CERM
X5R 01005
1 C2522 1 C2528 1 C2529
.c
0201-1 ROOM=RCAM_B2B
ROOM=RCAM_B2B
33PF 33PF 33PF
5% 5% 5%
2 16V 2 16V 2 16V
NP0-C0G-CERM NP0-C0G-CERM NP0-C0G-CERM
01005 01005 01005
w
ROOM=RCAM_B2B ROOM=RCAM_B2B ROOM=RCAM_B2B
w
B B
w
10 90_LPDP_UT_TO_AP_D0_P
MAKE_BASE=TRUE
90_LPDP_UT_TO_AP_D0_P C2523
ROOM=RCAM_B2B
1 2 0.1UF 90_LPDP_UT_TO_AP_D0_CONN_P 45
20% 6.3V
X5R-CERM 01005
10 90_LPDP_UT_TO_AP_D0_N
MAKE_BASE=TRUE
90_LPDP_UT_TO_AP_D0_N C2524
ROOM=RCAM_B2B
1 2 0.1UF 90_LPDP_UT_TO_AP_D0_CONN_N 45
20% 6.3V
X5R-CERM 01005
10 90_LPDP_UT_TO_AP_D1_P
MAKE_BASE=TRUE
90_LPDP_UT_TO_AP_D1_P C2525
ROOM=RCAM_B2B
1 2 0.1UF 90_LPDP_UT_TO_AP_D1_CONN_P 45
20% 6.3V
X5R-CERM 01005
10 90_LPDP_UT_TO_AP_D1_N
MAKE_BASE=TRUE
90_LPDP_UT_TO_AP_D1_N C2526 1 2 0.1UF 90_LPDP_UT_TO_AP_D1_CONN_N 45
A SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
spare
DRAWING NUMBER SIZE
D M2600
D
53 52
27 26 25 23 21 19 18 10 9 4
46 41 40 39 37 35 34 33 31 28
PP_VDD_MAIN NEO
SIP
C2609 1 C2610 1 C2613 1 SYM 1 OF 3
10UF
20%
10UF
20%
220PF B8 ROOM=STROBE
5% VDD D9
6.3V 6.3V 10V D2 LED1 PP_STROBE_DRIVER1_COOL_LED
CERM-X5R 2 CERM-X5R 2 C0G-CERM 2 VDD D10
44 45
0402-9 0402-9 01005 D3 CRITICAL LED1
ROOM=STROBE ROOM=STROBE ROOM=STROBE VDD
D6
C9 LED2 PP_STROBE_DRIVER1_WARM_LED 44 45
9 AP_TO_STROBE_DRIVER_HWEN HWEN1 D7
LED2
C8
25 UT_AND_NV_TO_STROBE_DRIVER_STROBE STB1
C10
NTC STROBE_MODULE_NTC 44
D8
53 37 BB_TO_STROBE_DRIVER_GSM_BURST_IND GSM1
B9
48 I2C_ISP_UT_SDA SDA1
B10
48 I2C_ISP_UT_SCL SCL1
C C
m
o
PP_VDD_MAIN
M2600
.c
53 52
27 26 25 23 21 19 18 10 9 4
46 41 40 39 37 35 34 33 31 28
NEO
C2611 1 C2612 1 C2614 1 SIP
SYM 2 OF 3
10UF 10UF
20%
220PF
20% 5% B18 VDD
x
6.3V 6.3V 10V
CERM-X5R 2 CERM-X5R 2 C0G-CERM 2 LED1 B11 PP_STROBE_DRIVER2_COOL_LED 44 45
0402-9 0402-9 01005 B19 VDD
LED1 B12
D13 VDD
fi
ROOM=STROBE2 ROOM=STROBE2 ROOM=STROBE
A2
GND
M2600 GND C14
LED2 B14 PP_STROBE_DRIVER2_WARM_LED 44 45 A3 NEO C15
C12 HWEN0 GND GND
LED2 B15 A4 SIP
a
GND SYM 3 OF 3 GND C16
C13 STB0 A5 C17
GND GND
NTC C11 A6
in
GND GND C18
B13 GSM0 A7 C19
GND GND
A8 C20
46 I2C_ISP_NV_SDA D12 SDA2 GND GND
A9 D1
h
GND GND
46 I2C_ISP_NV_SCL D11 SCL2 A10 D4
GND GND
A11 D5
GND
.c
GND
A12 D14
GND GND
A13 D15
GND GND
A14 D16
GND GND
w
A15 D17
GND GND
A16 D18
GND GND
A17
w
GND GND D19
B A18
A19
GND GND E1 B
GND GND E2
w A20
B2
B3
GND
GND
GND
GND
GND
GND
E3
E4
E5
B4 E6
53 52
27 26 25 23 21 19 18 10 9 4 PP_VDD_MAIN GND GND
46 41 40 39 37 35 34 33 31 28 B5 E7
GND GND
B6
1 C2617 1 C2618 B7
GND GND E8
220PF 220PF GND GND E9
5% 5% B16
2 10V 2 10V GND GND E10
C0G-CERM C0G-CERM B17
01005 01005 GND GND E11
ROOM=STROBE2 ROOM=STROBE2 B20 E12
GND GND
C1 E13
AC return path for plane edge termination, which occurs near the Strobe modules. GND GND
C2 E14
GND GND
C3 E15
GND GND
C4 E16
GND GND
C5 E17
GND GND
C6 E18
GND GND
GND1S
GND2S
C7
GND1
GND2
GND GND E19
A1
B1
E20
D20
A SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
spare
DRAWING NUMBER SIZE
ACCESSORY BUCK
#25761020:Add Bypass 0ohm
NOSTUFF
R2711
0.00
1 2
D 1%
1/20W
D
MF
0201
ROOM=ACC_BUCK
From PMU LDO6
Q2700
A2
PMCM4401VPE
U2700 WLCSP
FAN53612-1.5V-1.9V
CRITICAL
L2700 #25370332: For EMC
WLCSP 0.47UH-20%-2.52A-0.08OHM #25919133: C2707 on P46
A2
ACC_BUCK_EN B2 B1 ACC_BUCK_SW 1 2 VOLTAGE=1.9V PP_ACC_BUCK_VAR
S
B1 B2
PIGA1608-SM
12 AP_TO_ACC_BUCK_VSEL A1 C1 ACC_BUCK_FB ROOM=ACC_BUCK
27
A1 G
1
R2701
1 1 1
XW2700 ROOM=TRISTAR
1 C2710 10UF 220PF 0.1UF SHORT-20L-0.05MM-SM PP_ACC_VAR
C2
100K 20% 5% 20%
1 2
19 27 40 46
5% 0.22UF 6.3V
2 CERM-X5R 2
10V
2
6.3V 27 ACC_BUCK_FB
o
1/32W 10% C0G-CERM X5R-CERM
MF
2 01005
2 6.3V
CER-X5R
01005 1
0402-9
ROOM=ACC_BUCK
01005
ROOM=ACC_BUCK
01005
ROOM=ACC_BUCK
ROOM=ACC_BUCK
NO_XNET_CONNECTION=1
PLACE_NEAR=Q2700:2mm
Q2701 1 C2708
ROOM=ACC_BUCK
PMCM4401VPE 4UF
R2705
.c
ROOM=ACC_BUCK
20%
10K WLCSP 2 6.3V
5% #25172498 2 OMIT CER-X5R
1/32W
MF
01005 2
1
R2702 XW2707
0201
ROOM=TRISTAR
ROOM=ACC_BUCK 200K A2 SHORT-20L-0.05MM-SM
x
0.1% ROOM=TRISTAR
S
1/32W B1 B2 1 NO_XNET_CONNECTION=1
TF
2 01005 #25741319: Change to 4UF
fi
ROOM=ACC_BUCK
20
ACC_BUCK_TO_PMU_AMUX ACT_DIODE_TO_COMP_SENSE
A1 G
ROOM=TRISTAR
PMU_AMUX_B3 FOR NOW 1
R2704
a
ACT_DIODE_TO_COMP_OUT
200K
0.1%
in
1/32W
TF
2 01005
ROOM=ACC_BUCK
ACT_DIODE_TO_COMP_POS
h
46 40 27 19 PP_ACC_VAR
.c
C2706 1
0.22UF
5
10%
6.3V 2
CER-X5R VCC
U2701
w
01005
ROOM=ACC_BUCK
SCY992200A
4 IN+ UDFN
w
B ACT_DIODE_TO_COMP_NEG 3 IN-
VOUT 6
B
NC 2 #26434500: Divider to all 200kohm,0.1%
w 1
R2706
VEE
ROOM=ACC_BUCK
NC
1
#25987909: To Resistor Divider
R2703
1
200K 200K
0.1% 0.1%
1/32W 1/32W
TF TF
2 01005 2 01005
ROOM=ACC_BUCK ROOM=ACC_BUCK
A SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
spare
DRAWING NUMBER SIZE
D D
M2800 M2800
TRINITY TRINITY
SIP SIP
SYM 1 OF 5 SYM 4 OF 5
53 52
27 26 25 23 21 19 18 10 9 4 PP_VDD_MAIN
D5 VDD TIG B5 TIGRIS_BUCK_LX 21
53 52
27 26 25 23 21 19 18 10 9 4 PP_VDD_MAIN
D2 VDD BL1 F6 BL_SW1_LX 37
C C
m
46 41 40 39 37 35 34 33 31 28 46 41 40 39 37 35 34 33 31 28
D6 VDD TIG B6 D3 VDD BL1 G6
F2 VDD BL1 H6
A3 GND
M2800 GND H1
G2 VDD BL1 J6 TRINITY
A4 H3
o
H2 GND SIP GND
VDD A5 H4
J2 BL2 B2 BL_SW2_LX 37 GND SYM 5 OF 5 GND
VDD A6 H5
BL2 B3
.c
GND GND
A7 GND GND H7
B1 GND GND J1
B4 GND GND J3
x
B7 GND GND J4
C1 J5
M2800 GND GND
fi
TRINITY C2 GND GND J7
SIP C3 K1
SYM 2 OF 5 GND GND
a
C4 GND GND K2
L2 VDD ARC N2 ARC1_LX 35 C5 GND GND K3
L3 VDD ARC N3
in
C6 GND GND K4
C7 GND GND K5
D1 GND GND K6
D4 K7
h
GND GND
D7 GND GND L1
E1 GND GND L4
.c
E2 GND GND L7
E3 GND GND M1
M2800 E4 GND GND M2
w
TRINITY E5 M3
SIP GND GND
E6 GND GND M4
w
L5 N5 SPEAKERAMP1_LX E7 GND GND M5
B B
34
L6 N6 F1 GND GND M6
F3 GND GND M7
w F4
F5
F7
GND
GND
GND
GND
GND
GND
N1
N4
N7
G1 GND GND P1
G3 GND GND P2
G4 GND GND P3
G5 GND GND P4
G7 GND GND P5
GND1S
GND2S
GND1
GND2
A1
A2
P7
P6
A SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
spare
DRAWING NUMBER SIZE
D FL2902 D
33-OHM-25%-1500MA
19 PP1V2_NH_NV_DVDD 1 2 PP1V2_NH_DVDD_CONN 45
0201
ROOM=FOREHEAD 1 C2916 1 C2915 1 C2903
20%
2.2UF 0.1UF
20% 5%
220PF FL2910
150OHM-25%-200MA-0.7DCR
6.3V 6.3V
2 X5R-CERM 2 X5R-CERM 2 10V
C0G-CERM
0201-1 01005 01005 1 2
ROOM=FOREHEAD ROOM=FOREHEAD 53 41 40 19 PP3V0_TRISTAR_ANT_PROX PP3V0_PROX_CONN
ROOM=FOREHEAD
01005
ROOM=FOREHEAD 1 C2927 1 C2908
FL2903 2.2UF
20%
220PF
5%
10-OHM-750MA #24511567: Remove C2918
2 6.3V 2 10V
X5R-CERM C0G-CERM
19 PP2V9_NH_AVDD 1 2 PP2V9_NH_AVDD_CONN 45
0201-1 01005
ROOM=FOREHEAD ROOM=FOREHEAD
01005-1
ROOM=FOREHEAD 1 C2909 1 C2901 1 C2904
2.2UF 0.1UF 220PF
20% 20% 5%
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 10V
C0G-CERM
0201-1 01005 01005
ROOM=FOREHEAD ROOM=FOREHEAD ROOM=FOREHEAD
FL2907
150OHM-25%-200MA-0.7DCR
SPEAKER2 2
220PF
5%
10V
C0G-CERM
01005
1 2 ROOM=FOREHEAD
9 AP_TO_NH_CLK AP_TO_NH_CLK_CONN 45
01005
1 C2910 SPEAKERAMP2_TO_SPEAKER_OUT_POS
C C
m
46 45 33
ROOM=FOREHEAD
56PF NO_XNET_CONNECTION=1
5%
25V
2 NP0-C0G-CERM
1 C2935
220PF
o
01005 5%
ROOM=FOREHEAD 10V
2
FL2908 C0G-CERM
01005
.c
150OHM-25%-200MA-0.7DCR ROOM=FOREHEAD
1 2 SPEAKERAMP2_TO_SPEAKER_OUT_NEG 33 45 46
9 AP_TO_NH_SHUTDOWN_L AP_TO_NH_SHUTDOWN_CONN_L
01005
1 C2911 NO_XNET_CONNECTION=1
C2931 1
x
ROOM=FOREHEAD
220PF
5%
10V
220PF
5%
fi
2 C0G-CERM 10V 2
01005 C0G-CERM
ROOM=FOREHEAD
01005
ROOM=FOREHEAD
a
R2903
0.00
SPEAKER_TO_SPEAKERAMP2_VSENSE_P 1 2 SPEAKER_TO_SPEAKERAMP2_VSENSE_CONN_P
in
33 45
0% NO_XNET_CONNECTION=1
1/32W
1 C2933
CONVOY I/O
MF
01005
ROOM=FOREHEAD 220PF
5%
h
#25657495: Update FL2905 to 100ohm 2 10V
C0G-CERM
01005
R2905 ROOM=FOREHEAD
.c
33 PDM_ADARE_TO_CONVOY_CLK 1
100 2 PDM_ADARE_TO_CONVOY_CLK_CONN 45
R2904
0.00
SPEAKER_TO_SPEAKERAMP2_VSENSE_N 1 2 SPEAKER_TO_SPEAKERAMP2_VSENSE_CONN_N
5%
1/32W 1 C2905 33 45
w
MF 0%
56PF NO_XNET_CONNECTION=1
01005
ROOM=FOREHEAD 5%
2 25V
1/32W
MF
01005
1 C2934
NP0-C0G-CERM ROOM=FOREHEAD 220PF
w
01005 5%
B FL2906
ROOM=FOREHEAD 2 10V
C0G-CERM
01005 B
ROOM=FOREHEAD
150OHM-25%-200MA-0.7DCR
33 PDM_CONVOY_TO_ADARE_DATA 1 2 PDM_CONVOY_TO_ADARE_DATA_CONN
01005
ROOM=FOREHEAD 1 C2906
45 w
56PF
5%
2 25V
NP0-C0G-CERM
01005
ROOM=FOREHEAD MIC3 FL2914
150OHM-25%-200MA-0.7DCR
32 PP_CODEC_TO_FRONTMIC3_BIAS 1 2 PP_CODEC_TO_FRONTMIC3_BIAS_CONN 45
01005
ROOM=FOREHEAD 1 DZ2905
PROX/ALS I/O #25170697: R2915 to 240ohm/C2921 to 220pF
2
6.8V-100PF
01005
ROOM=FOREHEAD
R2915
PROX_BI_AP_AOP_INT_PWM_L 1
240 2 PROX_BI_AP_AOP_INT_PWM_L_CONN
FL2904
13 12 45 150OHM-25%-200MA-0.7DCR
1%
1/32W
MF
1 C2921 31 FRONTMIC3_TO_CODEC_AIN4_N 1 2 FRONTMIC3_TO_CODEC_AIN4_CONN_N 45
01005 220PF 01005 NO_XNET_CONNECTION=1
5%
ROOM=FOREHEAD
2 10V
C0G-CERM
ROOM=FOREHEAD 1 DZ2906
01005 6.8V-100PF
01005
ROOM=FOREHEAD ROOM=FOREHEAD
2
FL2911 FL2909
150OHM-25%-200MA-0.7DCR 150OHM-25%-200MA-0.7DCR
A 12 ALS_TO_AP_INT_L 2 1 ALS_TO_AP_INT_CONN_L
01005
45 31 FRONTMIC3_TO_CODEC_AIN4_P 2
01005
1
NO_XNET_CONNECTION=1
FRONTMIC3_TO_CODEC_AIN4_CONN_P 45
SYNC_MASTER=Sync
A
DZ2907
SYNC_DATE=05/17/2016
1 PAGE TITLE
1 C2924 ROOM=FOREHEAD
6.8V-100PF spare
ROOM=FOREHEAD 56PF 01005
ROOM=FOREHEAD
5% 2 DRAWING NUMBER SIZE
2 25V
NP0-C0G-CERM
01005
ROOM=FOREHEAD Apple Inc. 051-00419 D
REVISION
R
8.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
D D
C C
m
o
.c
x
fi
a
in
h
.c
w
w
B B
w
A SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
spare
DRAWING NUMBER SIZE
D CRITICAL
D
ROOM=CODEC
U3101
WLCSP-1
41 LOWERMIC1_TO_CODEC_AIN1_P L2 AIN1+ SYM 1 OF 3 AOUT1+ L9 NC
LOWERMIC1_TO_CODEC_AIN1_N AOUT1-
WAS FOR RECEIVER; REPLACED BY SPEAKER IN D1xy
41 L1 AIN1- M9NC
CS42L71
AOUT2+ L8 NC
AOUT2- M8NC
HPOUTA K10NC
41 LOWERMIC4_TO_CODEC_AIN2_P K3 AIN2+ HPOUTB K11NC
41 LOWERMIC4_TO_CODEC_AIN2_N L3 AIN2-
HS3 M5
HS4 M4
HS3_REF L10
HS4_REF M10
44 REARMIC2_TO_CODEC_AIN3_P K2 AIN3+
44 REARMIC2_TO_CODEC_AIN3_N K1 AIN3-
HSIN+ D1 NC
HSIN- E1 NC
29 FRONTMIC3_TO_CODEC_AIN4_P J3 AIN4+
For Borealis
29 FRONTMIC3_TO_CODEC_AIN4_N J4 AIN4-
C C
m
HPDETECT J9 NC
NC F1 AIN5+
o
NC G1 AIN5-
.c
F2 AIN6+
x
NC ROOM=CODEC
NC F3 AIN6- C3107
100PF
fi
1 2
5%
16V
a
44 HAWKING_TO_CODEC_AIN7_P G2 AIN7+
R3104
20.0
NP0-C0G
01005
1 2 90_MIKEYBUS_DATA_P 40
in
44 HAWKING_TO_CODEC_AIN7_N G3 AIN7-
5%
1/32W
MF
NC A4 DMIC1_CLK DP J12 90_MIKEYBUS_CALTRA_DATA_P 01005
ROOM=CODEC
90_MIKEYBUS_CALTRA_DATA_N
h
NC B4 DMIC1_DATA DN H12
C4 DMIC2_CLK
MBUS_REF G10 MIKEYBUS_REFERENCE 41
R3103
20.0
.c
NC C3 DMIC2_DATA 1 2 90_MIKEYBUS_DATA_N 40
5%
NC A3 DMIC3_CLK 1/32W
NC B3 DMIC3_DATA 1
R3101
MF
01005 C3106
w
ROOM=CODEC 100PF
100
NC A2 DMIC4_CLK 5% 1 2
1/32W
B2 DMIC4_DATA MF
w
NC 01005 5%
B 33 PDM_CODEC_TO_SPKAMP2_CLK A9 PDM_CLK
2ROOM=CODEC 16V
NP0-C0G
01005
B
33 PDM_CODEC_TO_SPKAMP2_DATA
w B9 PDM_DATA
ROOM=CODEC
53
27 26 25 23 21 19 18 10 9 4
52 46 41 40 39 37 35 34 33 28
PP_VDD_MAIN
A 1 C3112 1 C3113 SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
220PF 220PF PAGE TITLE
5%
2 10V
C0G-CERM
5%
2 10V
C0G-CERM
spare
01005 01005 DRAWING NUMBER SIZE
ROOM=CODEC ROOM=CODEC
Apple Inc. 051-00419 D
AC return path for Mikeybus which is referenced to GND and VDD_MAIN REVISION
Radar 21203307
R
8.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
CODEC_AGND 32
53 38 37 25 23 19 PP_VDD_BOOST
1 C3212 1 C3214 1 C3205
0.1UF 0.1UF 2.2UF
20% 20% 20%
6.3V 6.3V 6.3V
2 X5R-CERM 2 X5R-CERM 2 X5R-CERM
01005 01005 0201-1 47 41 40 37 36 32 21 20 18 16 PP1V8_SDRAM
ROOM=CODEC ROOM=CODEC ROOM=CODEC 53 52 48
47 41 40 37 36 32 21 20 18 16 PP1V8_SDRAM
1
R3201
53 52 48 1.00K
1 C3211 1 C3213 1 C3215 5%
1/32W
MF
10UF 0.1UF 0.1UF
20% 20% 20% 2 01005
ROOM=CODEC
6.3V 6.3V 6.3V
2 CERM-X5R 2 X5R-CERM 2 X5R-CERM D3
CODEC_RESET_L H3 RESET* JTAG_TMS
0402-9
ROOM=CODEC
01005
ROOM=CODEC
01005
ROOM=CODEC PP1V2_VD_FILT R3202 1
JTAG_TCK D4
NC
NC
100K D2
JTAG_TDI
1 C3217 1 C3221
5%
1/32W
MF
U3101 JTAG_TDO C2
NC
01005 2 K8 WAKE* WLCSP-1 NC
1.0UF 1.0UF NC SYM 3 OF 3
VD G12
20% 20%
VD D12
VPROG_CP H11
VP_MBUS H10
VD_FILT E12
VCP J11
ROOM=CODEC D11
VP M7
VD_FILT C1
VL A5
6.3V 6.3V AUDIO_TO_AOP_INT_L
VA J1
2 X5R 2 X5R 35 34 33 13 K9 INT* CS42L71 TSTO NC
0201-1 0201-1 ROOM=CODEC
TSTO B10
CRITICAL NC
ROOM=CODEC ROOM=CODEC
SPI_AP_TO_CODEC_CS_L C9 CS* TSTO D5
11
NC
C C
m
SPI_AP_TO_CODEC_MAGGIE_SCLK C8 CCLK TSTO D6
36 11
NC
TSTO E5
NC
C3203 SPI_AP_TO_CODEC_MAGGIE_MOSI B8 MOSI TSTO E6
NC
o
36 11
4.7UF PP_CODEC_TO_LOWERMIC1_BIAS M6 MIC1_BIAS FLYP K12NC
LOWERMIC1_TO_CODEC_BIAS_FILT_RET 1 2
41
LOWERMIC1_BIAS_FILT_IN K7 MIC1_BIAS_FILT
U3101 36 11 SPI_CODEC_MAGGIE_TO_AP_MISO A8 MISO TSTO E7
NC
41
WLCSP-1 TSTO K4
NC
.c
20% SYM 2 OF 3 I2S_AP_TO_CODEC_MCLK C12 MCLK
11
6.3V
X5R-CERM1 CS42L71 C10
402 ROOM=CODEC TSTI
ROOM=CODEC CRITICAL I2S_MAGGIE_TO_AP_L26_CODEC_BCLK C6 ASP_SCLK TSTI D10
C3204
36 35 34 33 11
x
I2S_MAGGIE_TO_AP_L26_CODEC_LRCLK C5 ASP_LRCK/FSYNC TSTI D7
36 35 34 33 11
4.7UF 41 PP_CODEC_TO_LOWERMIC4_BIAS L6 MIC2_BIAS D9
1 2 LOWERMIC4_BIAS_FILT_IN 36 35 34 33 I2S_MAGGIE_TO_L26_CODEC_DOUT B5 ASP_SDIN TSTI
LOWERMIC4_TO_CODEC_BIAS_FILT_RET J7 MIC2_BIAS_FILT FLYC L12NC
fi
41
36 35 34 33 I2S_L26_CODEC_TO_MAGGIE_DIN B6 ASP_SDOUT TSTI E8
20% TSTI E9
6.3V
X5R-CERM1 I2S_CODEC_XSP_TO_AOP_BCLK B11 XSP_SCLK TSTI G11
a
13
402
ROOM=CODEC I2S_CODEC_XSP_TO_AOP_LRCLK C11 XSP_LRCK/FSYNC TSTI H4
C3201
13
in
13
4.7UF 44 PP_CODEC_TO_REARMIC2_BIAS K6 MIC3_BIAS
REARMIC2_TO_CODEC_BIAS_FILT_RET 1 2 REARMIC2_BIAS_FILT_IN 13 I2S_CODEC_XSP_TO_AOP_DIN A10 XSP_SDOUT
45 L5 MIC3_BIAS_FILT
20% 11 I2S_AP_TO_CODEC_MSP_BCLK B7 MSP_SCLK GND A1
6.3V FLYN
h
M12NC A12
X5R-CERM1
402 11 I2S_AP_TO_CODEC_MSP_LRCLK C7 MSP_LRCK/FSYNC GND
ROOM=CODEC I2S_AP_TO_CODEC_MSP_DOUT D8 MSP_SDIN GND B12
C3202
11
.c
+VCP_FILT J10NC 11 I2S_CODEC_TO_AP_MSP_DIN A7 MSP_SDOUT GND E2
4.7UF 29 PP_CODEC_TO_FRONTMIC3_BIAS J6 MIC4_BIAS E3
GND
FRONTMIC3_TO_CODEC_BIAS_FILT_RET 1 2 FRONTMIC3_BIAS_FILT_IN K5 MIC4_BIAS_FILT 20 PMU_TO_CODEC_DIGLDO_PULLDN H5 DIGLDO_PULLDN E4
GND
J5 DIGLDO_PDN
w
20% GND E10
6.3V
2
X5R-CERM1
402
1 C3223 1 C3224 GND F4
ROOM=CODEC 1.0UF 1.0UF GND F5
w
XW3203 20% 20%
B SHORT-20L-0.05MM-SM
ROOM=FOREHEAD
2 6.3V
X5R
0201-1
2 6.3V
X5R
0201-1 GNDCP L11
GND
GND
F6
F7
B
1NO_XNET_CONNECTION ROOM=CODEC ROOM=CODEC
OMIT w GND
GND
GND
F8
F9
F10
1 C3222 1 C3225 GND G4
1.0UF 1.0UF GND G5
20% 20%
2 6.3V 2 6.3V GND G6
X5R X5R
0201-1 0201-1 GND G7
ROOM=CODEC ROOM=CODEC
-VCP_FILT M11NC GND G8
F12 GND G9
LP_FILT+ CALTRA_LP_FILTP H6
GND
GND H7
1 C3220 GND H8
0.1UF GND H9
20%
2 6.3V
X5R-CERM
01005 GND J8
NC M3 HS_BIAS_FILT ROOM=CODEC
1 C3208
10UF
20%
2 6.3V
CERM-X5R
0402-9
GNDHS
ROOM=CODEC
GNDD
GNDD
GNDD
GNDD
GNDP
GNDA
FILT- H2
A A
A6
B1
E11
F11
L4
L7
J2
SYNC_MASTER=Sync SYNC_DATE=05/17/2016
PAGE TITLE
CODEC_AGND 32
spare
DRAWING NUMBER SIZE
8.0.0
2 1 NOTICE OF PROPRIETARY PROPERTY: BRANCH
D D
53
27 26 25 23 21 19 18 10 9 4
52 46 41 40 39 37 35 34 31 28
PP_VDD_MAIN PP1V8_VA 19 32 34 35
A5
F5
CRITICAL
L3302 VP VA
C C
m
1.2UH-20%-3.0A-0.080OHM
1 2 SPEAKERAMP2_LX A2 SW U3301 VBST_B A1 PP_SPKR2_VBOOST
o
PIQA20161T-SM B2 SW CS35L26-A1 VBST_B B1
ROOM=SPKAMP2
WLCSP
1 C3312 1 C3311 1 C3324 1 C3325 1 C3306 1 C3308
47 I2C2_AP_SDA D6 SDA VBST_A C1 220PF 0.1UF 10UF 10UF 10UF 10UF
.c
ROOM=SPKAMP2 5% 10% 20% 20% 20% 20%
VBST_A D1 2 10V
C0G-CERM 2 16V
X5R-CERM 2 10V
X5R-CERM 2 10V
X5R-CERM 2 10V
X5R-CERM 2 10V
X5R-CERM
47 I2C2_AP_SCL E6 SCL CRITICAL 01005 0201 0402-8 0402-8 0402-8 0402-8
ROOM=SPKAMP2 ROOM=SPKAMP2 ROOM=SPKAMP2 ROOM=SPKAMP2 ROOM=SPKAMP2 ROOM=SPKAMP2
35 34 32 13 AUDIO_TO_AOP_INT_L A7 INT*
x
12 AP_TO_SPKAMP2_RESET_L A6 RESET*
1 C3319
fi
1
R3301 34 SPKAMP1_TO_SPKAMP2_SYNC F6 ALIVE/SYNC ISNS+ F1 SPEAKERAMP2_ISENSE_P 0.01UF
100K ISNS- E1 SPEAKERAMP2_ISENSE_N 10%
6.3V
5% 29 PDM_ADARE_TO_CONVOY_CLK PDM_ADARE_TO_CONVOY_CLK E5 AD0/PDM_CLK1 2 X5R
a
1/32W MAKE_BASE=TRUE 01005
MF
2 01005 I2S_AOP_TO_MAGGIE_L26_MCLK B7 MCLK ROOM=SPKAMP2
R3304
36 35 34 13
1 NO_XNET_CONNECTION
VSNS+ E2 SPEAKER_TO_SPEAKERAMP2_VSENSE_P
in
ROOM=SPKAMP2 29
100K 36 35 34 32 11 I2S_MAGGIE_TO_AP_L26_CODEC_BCLK C7 SCLK
5% VSNS- E3 SPEAKER_TO_SPEAKERAMP2_VSENSE_N 29
1/32W
MF 36 35 34 32 11 I2S_MAGGIE_TO_AP_L26_CODEC_LRCLK C6 LRCK/FSYNC
2 01005
ROOM=SPKAMP2
I2S_MAGGIE_TO_L26_CODEC_DOUT
h
36 35 34 32 D7 SDIN SPEAKERAMP2_TO_SPEAKER_OUT_POS
OUT+ D2 29 45 46
.c
31 PDM_CODEC_TO_SPKAMP2_CLK F7 PDM_CLK0 C3331 1 1 C3323
1000PF 1000PF
31 PDM_CODEC_TO_SPKAMP2_DATA E7 PDM_DATA0 FILT+ F4 SPEAKERAMP2_FILT 10%
10V 2
10%
10V Pg46: Compass Compensation Coil
2
w
X5R X5R
PDM_CONVOY_TO_ADARE_DATA D5 01005 01005
29 PDM_DATA1 AD1 F3
GNDP GNDA ROOM=SPKAMP2 ROOM=SPKAMP2
1 C3318
1UF
w
A3
A4
B3
B4
C3
C4
C5
D3
D4
B5
E4
F2
B 2
10%
10V
X5R B
402-1
w ROOM=SPKAMP2
A SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
spare
DRAWING NUMBER SIZE
SPEAKER AMPLIFIER 1
(South)
D D
#25112685,Remove C3414
See SPKAMP1 C3424 on Pg46
53
27 26 25 23 21 19 18 10 9 4
52 46 41 40 39 37 35 33 31 28
PP_VDD_MAIN PP1V8_VA 19 32 33 35
A5
F5
C C
m
VP VA
A2 A1
U3402
o
TO TRINITY 28 SPEAKERAMP1_LX SW VBST_B PP_SPKR1_VBOOST
B2 B1
SW CS35L26-A1 VBST_B 1 C3427 1 C3428 1 C3403 1 C3404 1 C3431 1 C3432
.c
D6 WLCSP C1 220PF 0.1UF 10UF 10UF 10UF 10UF
48 I2C_AOP_SDA SDA VBST_A 5% 10% 20% 20% 20% 20%
ROOM=SPKAMP1 D1 10V 16V 10V 10V 10V 10V
E6 VBST_A 2 C0G-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM
48 I2C_AOP_SCL SCL CRITICAL 01005 0201 0402-8 0402-8 0402-8 0402-8
A7
x
ROOM=SPKAMP1 ROOM=SPKAMP1 ROOM=SPKAMP1 ROOM=SPKAMP1 ROOM=SPKAMP1 ROOM=SPKAMP1
35 33 32 13 AUDIO_TO_AOP_INT_L INT*
PULLED LOW ON PG 35
A6
AOP_TO_SPKAMP1_ARC_RESET_L RESET*
fi
35 13
SPKAMP1_TO_SPKAMP2_SYNC
F6
ALIVE/SYNC ISNS+
F1
SPEAKERAMP1_ISENSE_P
1 C3430
33
E1 0.01UF
E5 ISNS- SPEAKERAMP1_ISENSE_N 10%
a
MAKE_BASE=TRUE GND AD0/PDM_CLK1 2 6.3V
X5R
B7 01005
I2S_AOP_TO_MAGGIE_L26_MCLK MCLK
in
36 35 33 13 ROOM=SPKAMP1
E2 NO_XNET_CONNECTION
C7 VSNS+ SPEAKER_TO_SPEAKERAMP1_VSENSE_P 41
36 35 33 32 11 I2S_MAGGIE_TO_AP_L26_CODEC_BCLK SCLK E3
VSNS- SPEAKER_TO_SPEAKERAMP1_VSENSE_N 41
C6
36 35 33 32 11 I2S_MAGGIE_TO_AP_L26_CODEC_LRCLK LRCK/FSYNC
h
D7
36 35 33 32 I2S_MAGGIE_TO_L26_CODEC_DOUT SDIN D2
OUT+ SPEAKERAMP1_TO_SPEAKER_OUT_POS 41
B6 C2
.c
36 35 33 32 I2S_L26_CODEC_TO_MAGGIE_DIN SDOUT OUT- SPEAKERAMP1_TO_SPEAKER_OUT_NEG 41
F7
NC PDM_CLK0
E7 F4 C3422 1 1 C3434
w
NC PDM_DATA0 FILT+ SPEAKERAMP1_FILT 1000PF 1000PF
D5 F3 10% 10%
PDM_DATA1 AD1 10V 2 2 10V
GNDP GNDA 1 C3429 X5R X5R
w
01005 01005
A3
A4
B3
B4
C3
C4
C5
D3
D4
B5
E4
F2
20%
2 6.3V
X5R-CERM
w 0201-1
ROOM=SPKAMP1
A SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
spare
DRAWING NUMBER SIZE
ARC DRIVER
D D
C C
m
A5
F5
o
VP VA
.c
A2 A1 VOLTAGE=8.0V
TO TRINITY 28 ARC1_LX
B2
SW U3502 VBST_B
B1
PP_ARC1_VBOOST
SW CS35L26-A1 VBST_B
D6 WLCSP C1
1 C3526 1 C3535 1 C3537 1 C3524 1 C3538 1 C3539
x
48 I2C_AOP_SDA SDA VBST_A 220PF 0.1UF 10UF 10UF 10UF 10UF
ROOM=SPKAMP2 D1 5% 10% 20% 20% 20% 20%
E6 VBST_A 2 10V 2 16V 2 10V 2 10V 2 10V 2 10V
I2C_AOP_SCL SCL CRITICAL C0G-CERM X5R-CERM X5R-CERM X5R-CERM X5R-CERM X5R-CERM
fi
48 01005 0201 0402-8 0402-8 0402-8 0402-8
A7 ROOM=ARC1 ROOM=ARC1 ROOM=ARC1 ROOM=ARC1 ROOM=ARC1 ROOM=ARC1
34 33 32 13 AUDIO_TO_AOP_INT_L INT*
A6
a
34 13 AOP_TO_SPKAMP1_ARC_RESET_L RESET*
in
1
R3508 NC E1 0.01UF
E5 ISNS- ARC1_ISENSE_N 10%
100K 35 34 33 32 19 PP1V8_VA MAKE_BASE=TRUE PP1V8_VA AD0/PDM_CLK1 2 6.3V
X5R
5% 01005
1/32W B7
MF 36 34 33 13 I2S_AOP_TO_MAGGIE_L26_MCLK MCLK ROOM=ARC1
h
2 01005 E2 NO_XNET_CONNECTION
ROOM=ARC1
I2S_MAGGIE_TO_AP_L26_CODEC_BCLK C7 VSNS+ SOLENOID1_TO_ARC1_VSENSE_POS 41
36 34 33 32 11 SCLK E3
VSNS- SOLENOID1_TO_ARC1_VSENSE_NEG 41
NOSTUFF C6
.c
I2S_MAGGIE_TO_AP_L26_CODEC_LRCLK LRCK/FSYNC
C3501 1 36 34 33 32 11
D7
10PF 36 34 33 32 I2S_MAGGIE_TO_L26_CODEC_DOUT SDIN D2 VOLTAGE=8.0V
5%
16V 2 OUT+ ARC1_TO_SOLENOID1_OUT_POS 41
B6 C2
w
CERM I2S_L26_CODEC_TO_MAGGIE_DIN SDOUT OUT- VOLTAGE=8.0V ARC1_TO_SOLENOID1_OUT_NEG
01005 36 34 33 32 41
ROOM=ARC1 F7
NC PDM_CLK0
w
E7 F4
B NC PDM_DATA0 FILT+ ARC1_FILT C3529 1 1 C3542 B
D5 F3 1000PF 1000PF
PDM_DATA1 AD1 10% 10%
C3536
w GNDP GNDA 1
2.2UF
10V 2
X5R
01005
2 10V
X5R
01005
A3
A4
B3
B4
C3
C4
C5
D3
D4
B5
E4
F2
20% ROOM=ARC1 ROOM=ARC1
2 6.3V
X5R-CERM
0201-1
ROOM=ARC1
A SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
spare
DRAWING NUMBER SIZE
D D
MAGGIE LDO
APN: 353S00842
MAGGIE
APN: 336S00020
U3603
LD39130S-1.2V/AP
47 41 40 37 36 32 21 20 18 16 PP1V8_SDRAM A1 IN CSP OUT A2 PP1V2_MAGGIE
53 52 48
B1 EN 1 C3605 1 C3601
GND
4UF
20%
0.1UF
20%
6.3V 6.3V
2 CER-X5R 2 X5R-CERM
B2
0201 01005
ROOM=ARC_CTRL ROOM=ARC_CTRL
R3601
100
1 2 PP1V2_MAGGIE_PLL
C3602
5%
1/32W 1
MF
01005 0.1UF
ROOM=ARC_CTRL 20%
2 6.3V
X5R-CERM
01005
ROOM=ARC_CTRL
C C
m
VPP_2V5 must be > 1.71V for SPI Slave programming
o
36 24 18 PP1V8_MAGGIE_IMU
1 C3604 1 C3606
.c
2.2UF 0.1UF
C4
D4
C3
A4
B3
A5
20% 20%
6.3V 6.3V
2 X5R-CERM 2 X5R-CERM
SPI_VCCIO1
VCCIO_0
VCCIO_2
VCCPLL
VPP_2V5
VCC
0201-1 01005
x
ROOM=ARC_CTRL ROOM=ARC_CTRL
fi
ICE5LP4K-SWG36I
A2 IRLED U3602 IOB_10A B4 R3604
a
NC NC MAGGIE DRIVES TO ARC, SPKRS, AP, CODEC
F4 33.2
IOB_11B_G5 I2S_MAGGIE_TO_AP_L26_CODEC_BCLK_R 1 2 I2S_MAGGIE_TO_AP_L26_CODEC_BCLK
HOMER STM32L0 MICRO NC
C6 RGB0 WLCSP
IOB_12A_G4_CDONE E4 MAGGIE_TO_AP_CDONE 1%
11 32 33 34 35
in
B6 RGB1 12
1/32W
STM32L03 APN: 337S00231 NC IOB_16A F3 UART_AOP_TO_MAGGIE_TXD
BANK 0
MF
A6 RGB2 13
01005
NC IOB_20A E3 I2S_MAGGIE_TO_AP_DIN 11 ROOM=ARC_CTRL MAGGIE <-> AP (SDIN)
36 MAGGIE_TO_HOMER_WAKE B5 IOT_46B_G0 IOB_25B_G3 C2 I2S_AOP_TO_MAGGIE_L26_MCLK 13 33 34 35
BANK 1
IOB_26A B1 I2S_MAGGIE_TO_L26_CODEC_DOUT 32 33 34 35 MAGGIE <-> ARC, SPKRS, CODEC (SDOUT)
D2 PP1V8_MAGGIE_IMU 18 24 36
F6 IOB_27B I2S_L26_CODEC_TO_MAGGIE_DIN 32 33 34 35 MAGGIE <-> ARC, SPKRS, CODEC (SDIN)
SPI_MAGGIE_TO_HOMER_POS_SCLK IOB_2A
.c
E6 IOB_3B_G6
IOB_29B E2 I2S_AP_TO_MAGGIE_DOUT 11 MAGGIE <-> AP (SDOUT) 1
R3605 1
R3602
BANK 2
PP1V8_SDRAM IOB_30A C1 10K 10K
47 41 40 37 36 32 21 20 18 16
53 52 48 D6 IOB_4A 5% 5%
NC IOB_31B B2 I2S_MAGGIE_TO_AP_L26_CODEC_LRCLK MAGGIE DRIVES TO ARC, SPKRS, AP, CODEC 1/32W 1/32W
SPI_HOMER_TO_MAGGIE_POS_MISO D5 IOB_5B
11 32 33 34
C3603
35 MF MF
F2
w
1 IOB_32A_SPI_SO SPI_CODEC_MAGGIE_TO_AP_MISO
AOP_TO_MAGGIE_EN F5 IOB_6A
11 32
2 01005 2 01005
2.2UF 13
IOB_33B_SPI_SI D1 SPI_AP_TO_CODEC_MAGGIE_MOSI
20% MAGGIE_TO_AOP_INT E5 IOB_7B
11 32
6.3V 13
IOB_34A_SPI_SCK E1 SPI_AP_TO_CODEC_MAGGIE_SCLK
X5R-CERM 2
w
11 32
B
0201-1
ROOM=HOMER IOB_35B_SPI_CSN F1 SPI_AP_TO_MAGGIE_CS_L 9
B
CRESET_B D3 AP_TO_MAGGIE_CRESETB_L
w 12
GND_LED
ROOM=ARC_CTRL
PP3601
P2MM-NSM
SM PP 1
CRITICAL 1
R3603
GND
GND
ROOM=HOMER 511K
D1
C4
1%
PP3602 SM PP 1
VDD VDDA
1/32W
A1
C5
A3
P2MM-NSM MF
2 01005
ROOM=HOMER
U3601
STM32L031E6Y6D
E5 PA0_CLK_INROOM=HOMER PB0 E2
NC
B4 PA1 PB1 D2 SPI_MAGGIE_TO_HOMER_POS_MOSI
NC WLCSP
12 UART_HOMER_TO_AP_RXD D4 PA2 PB3 B2
12 UART_AP_TO_HOMER_TXD E4 PA3 PB6 A3
36 MAGGIE_TO_HOMER_WAKE
B3 PA4 PB7 A4
NC
R3607 NC
D3 PA5
B5
1
100 2 AP_BI_HOMER_BOOTLOADER_ALIVE_R E3 PA6 PC14_OSC32_IN NC
PC15_OSC32_OUT C5
5% C3 PA7 NC NOTE: RESET HAS INTERNAL 65K PULLUP
1/32W NC
MF 13 HOMER_TO_AOP_WAKE_INT C1 PA8 RST* D5 PMU_TO_HOMER_RESET_L 20
01005
I2C_HOMER_SCL B1 PA9
ROOM=HOMER 47 41
ROOM=HOMER
spare
DRAWING NUMBER SIZE
C3 E2
39 20 LCM_TO_CHESTNUT_PWR_EN LCM_EN VNEG(SUB)
200K INT PD
C2 A4
40 20 13 7 PMU_TO_AOP_TRISTAR_ACTIVE_READY RESET* HVLDO1 PP5V7_MESON_AVDDH 39
NO INT PULL
E1 A3
20 CHESTNUT_TO_PMU_ADCMUX ADCMUX HVLDO2 PP5V7_LCM_AVDDH 39
PGND1
PGND2
AGND
A1
HVLDO3 PP5V1_TOUCH_VDDH 39
C1
B1
D4
1UF
20%
10UF 10UF 10UF 4.7UF 4.7UF 220PF
20% 20% 20% 20% 20% 5%
16V 10V 10V 10V 10V 10V 10V
2 CER-X5R 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 C0G-CERM
0201 0402-8 0402-8 0402-8 0402 0402 01005
ROOM=CHESTNUT ROOM=CHESTNUT ROOM=CHESTNUT ROOM=CHESTNUT ROOM=CHESTNUT ROOM=CHESTNUT ROOM=CHESTNUT
m
APN:353s00640 D3701
DSN2
BL_SW2_LX A K
o
28
25V
NSR05F30NXT5G
.c
ROOM=BACKLIGHT
TO TRINITY
CRITICAL
D3702
x
NSR0530P2T5G
53 52 46 PP_VDD_MAIN BL_SW1_LX A K PP_LCM_BL_ANODE
27 26 25 23 21 19 18 10 9 4 28 39
fi
41 40 39 37 35 34 33 31 28 25V
C3702 1 SOD-923-1
ROOM=BACKLIGHT
1 C3703 1 C3725 1 C3704 1 C3706 1 C3705 1 C3721
10UF 220PF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 2% 20% 20% 20% 20% 20%
a
VOLTAGE=6.3V 2 2 50V 2 35V 2 35V 2 35V 2 35V 2 35V
CERM-X5R C0G X5R X5R X5R X5R X5R
0402-9 U3701
LM3539A1
0201
ROOM=BACKLIGHT
0402 0402 0402 0402 0402
in
ROOM=BACKLIGHT
PLACE_NEAR=U3701:2MM
D4 IN DSBGA OUT A1
CRITICAL
48 47 41 40 36 32 21 20 18 16
53 52
PP1V8_SDRAM D3 VIO/HWEN SW1 C4
h
11 DWI_PMGR_TO_BACKLIGHT_DATA C2 SDI SW2_1 A3
11 DWI_PMGR_TO_BACKLIGHT_CLK C3 SCK SW2_2 A4
.c
47 I2C0_AP_SDA B2 SDA LED1 C1 PP_LCM_BL_CAT1 39
47 I2C0_AP_SCL A2 SCL LED2 B1 PP_LCM_BL_CAT2 39
w
9 AP_TO_MUON_BL_STROBE_EN D1 TRIG ROOM=BACKLIGHT
53 26 BB_TO_STROBE_DRIVER_GSM_BURST_IND D2 INHIBIT
GND
GND
w
B B
B3
B4
1
R3701
200K
1%
1/32W
w
MF
01005
2
ROOM=BACKLIGHT
L3703
1.0UH-20%-0.4A-0.636OHM
53 52
27 26 25 23 21 19 18 10 9 4 PP_VDD_MAIN 1 2 POS18V0_MESA_LX
46 41 40 39 37 35 34 33 31 28
0403
C3718 1 ROOM=MOJAVE
CRITICAL
10UF
20% U3702
6.3V LM3638A0 PP16V0_MESA
CERM-X5R 2 BGA
0402-9
ROOM=MOJAVE B1 SW
ROOM=MOJAVE
CRITICAL
1 C3708 1 C3720
100PF 2.2UF
53 38 32 25 23 19 PP_VDD_BOOST A2 VIN VOUT C3 5% 20%
2 35V
NP0-C0G 2 35V
X5R
MESA_TO_BOOST_EN B2 EN_M 01005 0402
C3724 1 38 4
ROOM=MOJAVE ROOM=MOJAVE
A 10UF
20%
6.3V 2
A3 EN_S
A
PP17V0_MOJAVE_LDOIN C2 LDOIN PMID C1
SYNC_MASTER=Sync SYNC_DATE=05/17/2016
PGND
AGND
B3
D MAMBA_TO_LCM_MDRIVE_CONN_MESA
GUARD 10
12
9
11
I2C_MESA_TURTLE_SCL_CONN
MESA_TO_BOOST_EN_CONN
48
D
FL3801 LCM_TO_MAMBA_MSYNC_CONN
38
14 13 MESA_TO_AP_INT_CONN
38
150OHM-25%-200MA-0.7DCR 45 38
2.2UF
ROOM=MAMBA_MESA
1 C3802 5%
56PF PP3801 47
I2C_TOUCH_TO_MAMBA_SCL 22 21 SPI_MESA_TO_AP_MISO_CONN
38
2 6.3V
X5R-CERM
5%
10V
NP0-C0G-CERM
01005 38 PP1V8_TOUCH_TO_MAMBA_CONN 24 23 PP2V75_MAMBA_CONN 38
0201-1 2 C0G-CERM
01005 ROOM=MAMBA_MESA
ROOM=MAMBA_MESA
ROOM=MAMBA_MESA 28 27
FL3802 30
150OHM-25%-200MA-0.7DCR ROOM=MAMBA_MESA
37 4 PP16V0_MESA 1 2 PP16V0_MESA_CONN 38
01005 53 37 32 25 23 19 PP_VDD_BOOST
ROOM=MAMBA_MESA 1 C3803
5%
2 35V
100PF
NP0-C0G
MAMBA POWER NOTE: OUTPUT IMPDEANCE MUST BE >0.005-OHM TI:353S00576
01005 C3828 1 IN ORDER TO MEET CAP ESR REQUIREMENT PER LDO SPEC.
VENDOR ALSO RECOMMENDS CIN = COUT FOR STABILITY
ST:353S00932
ROOM=MAMBA_MESA 2.2UF
20%
5
11 38 X5R-CERM C0G-CERM
0402-8 01005
C
01005
C C3816
m
1
R3807 ROOM=MAMBA_MESA 1
56PF
ROOM=MAMBA_MESA ROOM=MAMBA_MESA
511K 5%
1%
1/32W 2 25V R3805
o
NP0-C0G-CERM
MF 01005
2 01005 PP1V8_TOUCH 0.00
ROOM=MAMBA_MESA ROOM=MAMBA_MESA 47 46 39 38 18 1 2 PP1V8_TOUCH_TO_MAMBA_CONN 38
.c
0%
R3809
1/32W
MF
01005
1 C3824 1 C3811
ROOM=MAMBA_MESA 2.2UF 220PF
0.00 20% 5%
SPI_AP_TO_MESA_SCLK 1 2 SPI_AP_TO_MESA_SCLK_CONN 2
6.3V 10V
2 C0G-CERM
x
11 38 X5R-CERM
1
R3808
0%
1/32W 1 C3817 MAMBA DIGITAL I/O 0201-1
ROOM=MAMBA_MESA
01005
ROOM=MAMBA_MESA
fi
MF 56PF
511K
1%
01005
ROOM=MAMBA_MESA 5%
2 25V
FL3804
1/32W
MF NP0-C0G-CERM 150OHM-25%-200MA-0.7DCR
01005
a
2 01005
ROOM=MAMBA_MESA ROOM=MAMBA_MESA 45 MAMBA_TO_LCM_MDRIVE 1 2 MAMBA_TO_LCM_MDRIVE_CONN_MESA 38
01005 NOSTUFF
C3805 1 1 C3806
in
ROOM=MAMBA_MESA
56PF 56PF
R3811 5%
25V
NP0-C0G-CERM 2 2
5%
25V
33.2 01005 NP0-C0G-CERM
11 SPI_MESA_TO_AP_MISO 1 2 SPI_MESA_TO_AP_MISO_CONN 38 01005
h
ROOM=MAMBA_MESA ROOM=MAMBA_MESA
1%
1/32W
MF
1 C3818
56PF
.c
01005
ROOM=MAMBA_MESA 5%
2 25V
NP0-C0G-CERM
01005
ROOM=MAMBA_MESA
w
R3801
w
681
B 11 MESA_TO_AP_INT 1 2 MESA_TO_AP_INT_CONN 38
B
1%
1/32W 1 C3819
MF
01005
ROOM=MAMBA_MESA 5%
100PF
2 16V
NP0-C0G
01005
w
ROOM=MAMBA_MESA
R3802
681
37 4 MESA_TO_BOOST_EN 1 2 MESA_TO_BOOST_EN_CONN 38
FL3806
1%
1/32W
MF
1 C3801 150OHM-25%-200MA-0.7DCR
01005 100PF 13 MESA_TO_AOP_FDINT 1 2 MESA_TO_AOP_FDINT_CONN 38
ROOM=MAMBA_MESA 5%
2 16V 01005
NP0-C0G
01005 ROOM=MAMBA_MESA 1 C3826
ROOM=MAMBA_MESA 100PF
5% #24543342: stuff 100pF
2 16V
NP0-C0G
01005
FL3811
150OHM-25%-200MA-0.7DCR
ROOM=MAMBA_MESA
13 AOP_TO_MESA_BLANKING_EN 1 2 AOP_TO_MESA_BLANKING_EN_CONN 38
01005
1 C3825
56PF
5%
2 25V
NP0-C0G-CERM
01005
ROOM=MAMBA_MESA
A SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
spare
DRAWING NUMBER SIZE
L3902
FL3906 65OHM-0.7-2GHZ-3.4OHM
PP1V8
240-OHM-25%-0.42A-0.31DCR
2 1 4
TAM0605 CRITICAL
SYM_VER-1
1
AP/TOUCH INTERFACE
25 18 17 16 13 12 11 9 8 7 5
52 48 47 46 29
PP1V8_LCM_CONN 45 9 90_MIPI_AP_TO_LCM_DATA0_P 90_MIPI_AP_TO_LCM_DATA0_CONN_P 45
D
0201
ROOM=DISPLAY_B2B 1 C3934 1 C3914 3 2
D
2.2UF 220PF 9 90_MIPI_AP_TO_LCM_DATA0_N 90_MIPI_AP_TO_LCM_DATA0_CONN_N 45
20% 5% ROOM=DISPLAY_B2B
2 6.3V 2 10V
L3903
X5R-CERM C0G-CERM
0201-1 01005
ROOM=DISPLAY_B2B ROOM=DISPLAY_B2B 65OHM-0.7-2GHZ-3.4OHM
TAM0605
SYM_VER-1
CRITICAL
4 1
9 90_MIPI_AP_TO_LCM_DATA1_P 90_MIPI_AP_TO_LCM_DATA1_CONN_P 45
3 2
FL3904
9 90_MIPI_AP_TO_LCM_DATA1_N 90_MIPI_AP_TO_LCM_DATA1_CONN_N 45
150OHM-25%-200MA-0.7DCR
ROOM=DISPLAY_B2B 2 1
12 AP_TO_TOUCH_MAMBA_RESET_L AP_TO_TOUCH_MAMBA_RESET_CONN_L 38 45
FL3913
01005
ROOM=DISPLAY_B2B 1 C3915 1 C3902
150OHM-25%-200MA-0.7DCR 220PF 220PF
5% 5%
37 20 LCM_TO_CHESTNUT_PWR_EN 2 1 LCM_TO_CHESTNUT_PWR_EN_CONN 45 2 10V 10V
C0G-CERM 2 C0G-CERM
01005 01005
ROOM=DISPLAY_B2B 1 C3916 ROOM=DISPLAY_B2B
01005
ROOM=MAMBA_MESA
220PF
5%
10V
2 C0G-CERM To Display B2B To Mamba/Mesa B2B
01005
FL3908 ROOM=DISPLAY_B2B
240-OHM-25%-0.42A-0.31DCR
37 PN5V7_LCM_MESON_AVDDN 2 1 PN5V7_LCM_MESON_AVDDN_CONN
0201
ROOM=DISPLAY_B2B 1 C3909
5%
220PF FL3915
10V
2 C0G-CERM
150OHM-25%-200MA-0.7DCR
01005
01005
12 AP_TO_LCM_RESET_L 1 2 AP_TO_LCM_RESET_CONN_L 45
FL3909 ROOM=DISPLAY_B2B
1 1 C3917
240-OHM-25%-0.42A-0.31DCR R3901
C C
m
100K 220PF
37 PP5V7_MESON_AVDDH 2 1 PP5V7_MESON_AVDDH_CONN 5% 5%
1/32W 2 10V
C0G-CERM
0201
ROOM=DISPLAY_B2B 1 C3910 1 C3940 MF
01005 01005
o
ROOM=DISPLAY_B2B 2 ROOM=DISPLAY_B2B
220PF 2.2UF
20%
5%
10V
2 C0G-CERM
6.3V
2 X5R-CERM R3915
.c
FL3910
01005 0201-1
PMU_TO_LCM_PANICB 1
10 2 PMU_TO_LCM_PANICB_CONN
FL3922
ROOM=DISPLAY_B2B ROOM=DISPLAY_B2B 20 45 150OHM-25%-200MA-0.7DCR
33-OHM-25%-1500MA
PP1V8_TOUCH 1 2 PP1V8_TOUCH_CONN
5%
1/32W
MF
1 C3918 11 SPI_AP_TO_TOUCH_CS_L 2 1 SPI_AP_TO_TOUCH_CS_CONN_L 45
x
47 46 38 18
100PF 01005
C3932 1
0201
1 C3911
01005
ROOM=DISPLAY_B2B
2
5%
16V ROOM=DISPLAY_B2B 1 C3924
ROOM=DISPLAY_B2B NP0-C0G 56PF
fi
2.2UF 220PF
20%
6.3V
X5R-CERM 2
5%
2 10V
C0G-CERM
AOP/TOUCH INTERFACE 01005
ROOM=DISPLAY_B2B
5%
2 25V
NP0-C0G-CERM
01005
0201-1 01005 ROOM=DISPLAY_B2B
a
ROOM=DISPLAY_B2B
FL3911 ROOM=DISPLAY_B2B
R3923
240-OHM-25%-0.42A-0.31DCR 0.00 2
in
2 1 11 SPI_AP_TO_TOUCH_SCLK 1 SPI_AP_TO_TOUCH_SCLK_CONN 45
PP5V1_TOUCH_VDDH PP5V1_TOUCH_VDDH_CONN
37
NOSTUFF 0%
0201
ROOM=DISPLAY_B2B 1 C3912 C3922 1
1/32W
MF
1 C3923
220PF 56PF 01005 56PF
h
5% 5% ROOM=DISPLAY_B2B 5%
2 10V 25V 2 25V
C0G-CERM
01005 FL3916 NP0-C0G-CERM 2
01005
NP0-C0G-CERM
01005
.c
150OHM-25%-200MA-0.7DCR ROOM=DISPLAY_B2B
ROOM=DISPLAY_B2B
LCM_TO_MANY_BSYNC 2 1 LCM_TO_MANY_BSYNC_CONN
ROOM=DISPLAY_B2B
FL3924
BACKLIGHT FL3901 53 23 20 13
01005
45 150OHM-25%-200MA-0.7DCR
33-OHM-25%-1500MA ROOM=DISPLAY_B2B 1 C3919 SPI_AP_TO_TOUCH_MOSI 2 1 SPI_AP_TO_TOUCH_MOSI_CONN 45
w
11
w
01005 5%
B 2%
220PF
2 50V
#26634069: nostuff C3903 to help desense
ROOM=DISPLAY_B2B 2 25V
NP0-C0G-CERM
01005
ROOM=DISPLAY_B2B
B
C0G
FL3919
FL3902
0201
ROOM=DISPLAY_B2B
w FL3917
150OHM-25%-200MA-0.7DCR 11 SPI_TOUCH_TO_AP_MISO
150OHM-25%-200MA-0.7DCR
2 1 SPI_TOUCH_TO_AP_MISO_CONN 45
UART_TOUCH_TO_AOP_RXD 2 1 UART_TOUCH_TO_AOP_RXD_CONN 01005
33-OHM-25%-1500MA 13
01005
45
ROOM=DISPLAY_B2B 1 C3926
37 PP_LCM_BL_CAT1 1 2 PP_LCM_BL_CAT1_CONN ROOM=DISPLAY_B2B 1 C3920 5%
56PF
0201 56PF 2 25V
ROOM=DISPLAY_B2B 1 C3904 5%
2 25V
NP0-C0G-CERM
01005
100PF NP0-C0G-CERM
01005 ROOM=DISPLAY_B2B
5%
2 35V
NP0-C0G FL3920
01005 FL3918 ROOM=DISPLAY_B2B 150OHM-25%-200MA-0.7DCR
FL3903 ROOM=DISPLAY_B2B 150OHM-25%-200MA-0.7DCR 12 TOUCH_TO_AP_INT_L 2 1 TOUCH_TO_AP_INT_L_CONN 45
33-OHM-25%-1500MA UART_AOP_TO_TOUCH_TXD 2 1 UART_AOP_TO_TOUCH_TXD_CONN 01005
PP_LCM_BL_CAT2 1 2 PP_LCM_BL_CAT2_CONN
13
01005
45
ROOM=DISPLAY_B2B 1 C3927
37
0201 ROOM=DISPLAY_B2B 1 C3921 5%
100PF
ROOM=DISPLAY_B2B 1 C3905 56PF
5% 2 16V
NP0-C0G
100PF 2 25V
NP0-C0G-CERM
01005
ROOM=DISPLAY_B2B
5%
2 35V 01005
NP0-C0G
01005 ROOM=DISPLAY_B2B R3908
ROOM=DISPLAY_B2B
AP_TO_CUMULUS_CLK32K 33.2
11 2 1 AP_TO_CUMULUS_CLK_32K_CONN 45
1%
1/32W
MF
1 C3928
01005 100PF
ROOM=DISPLAY_B2B 5%
2 16V
AC Coupling Caps NP0-C0G
01005
ROOM=DISPLAY_B2B
A A
PP_VDD_MAIN
SYNC_MASTER=Sync SYNC_DATE=05/17/2016
28 27 26 25 23 21 19 18 10 9 4
53 52 46 41 40 37 35 34 33 31 PAGE TITLE
For placement "along the way" as we route from SOC to B2B. I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
6 OF 53
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 6 OF 81
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
53 41 29 19 PP3V0_TRISTAR_ANT_PROX PP_ACC_VAR 19 27 46
PP5V0_USB
1 C4003 1 C4002 4 21 41
TRISTAR 2
53 52
6.3V 6.3V
2 X5R
0201-1
2 X5R-CERM
01005
1 C4004 D CRITICAL
ROOM=TRISTAR ROOM=TRISTAR 0.01UF
Q4001
10%
6.3V
C C
m
2
z=0.45mm X5R
01005 RV3CA01ZP
TRISTAR_REVERSE_GATE 1 G
<rdar:/24285280> EVT: 343S00091 (P2:343S00078) ROOM=TRISTAR DFN
o
ROOM=TRISTAR
R4002
ACC_PWR D5
1
VDD_1V8 F3
VDD_3V0 F4
S
10K 2 Sm Footprint: 376S00135
.c
5%
R4001 1/32W
MF
6.34K 2 2 01005
20 TRISTAR_TO_PMU_USB_BRICK_ID 1 ROOM=TRISTAR
1%
x
1 C4001 1/32W
MF U4001
0.01UF 01005
CBTL1610A3BUK
fi
10% ROOM=PMU
C3 WLCSP
2 6.3V
X5R 31 90_MIKEYBUS_DATA_P DIG_DP P_IN F6 PP5V0_USB_RVP
C4
01005 90_MIKEYBUS_DATA_N DIG_DN ACC1 C5 PP_TRISTAR_ACC1
31 4 41
1 C4006
a
ROOM=PMU
A1 ACC2 E5 PP_TRISTAR_ACC2 4 41
1UF
53 90_USB_BB_DATA_P USB1_DP 20%
B1
90_USB_BB_DATA_N USB1_DN DP1 A2 90_TRISTAR_DP1_CONN_P 2 16V
in
53 4 41
CER-X5R
L4022 TRISTAR_USB_BRICK_ID_R C2
BRICK_ID
DN1 B2 90_TRISTAR_DP1_CONN_N 4 41
0201
15NH-250MA ROOM=TRISTAR
A3 DP2 A4 90_TRISTAR_DP2_CONN_P 4 41
90_USB_AP_DATA_P 1 2 90_USB_AP_DATA_L_P USB0_DP
DN2 B4
7
90_TRISTAR_DP2_CONN_N
h
0201 90_USB_AP_DATA_L_N B3 4 41
USB0_DN
ROOM=TRISTAR
CON_DET_L E3 TRISTAR_CON_DETECT_L
L4021 UART_AP_TO_ACCESSORY_TXD E2
UART0_TX
4 41
.c
12
15NH-250MA 12 UART_ACCESSORY_TO_AP_RXD E1
UART0_RX POW_GATE_EN*
21
D6 TRISTAR_TO_TIGRIS_VBUS_OFF
7 90_USB_AP_DATA_N 1 2
12 UART_AP_DEBUG_TXD F2
UART1_TX SWITCH_EN E4
POW_GATE_EN* is 6V-tolerant
PMU_TO_AOP_TRISTAR_ACTIVE_READY 7 13 20 37
PP4001
P2MM-NSM
#25714843: Remove R4003 Weak PD
0201 SM
F1
HOST_RESET B6
w
ROOM=TRISTAR 12 UART_AP_DEBUG_RXD UART1_RX TRISTAR_TO_PMU_HOST_RESET 20 1
PP
D2 D3
UART2_TX SDA I2C0_AP_SDA 47
D1
w
UART2_RX SCL D4 I2C0_AP_SCL
B NC
B
53 47
27 26 25 23 21 19 18 10 9 4 PP_VDD_MAIN C6
52 46 41 39 37 35 34 33 31 28
A5 INT TRISTAR_TO_AOP_INT 13
7 SWD_DOCK_TO_AP_SWCLK JTAG_CLK E6
BYPASS TRISTAR_BYPASS
C4007 C4008 B5
1
220PF
1
220PF
7
w
SWD_DOCK_BI_AP_SWDIO JTAG_DIO
DVSS
DVSS
DVSS
5% 5%
2 10V
C0G-CERM 2 10V
C0G-CERM
1 C4005
01005 01005 1.0UF
20%
F5
C1
A6
ROOM=SOC ROOM=SOC 6.3V
2 X5R
0201-1
ROOM=TRISTAR
AC return path for USB pairs which is referenced to GND and VDD_MAIN
A SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
spare
DRAWING NUMBER SIZE
ROOM=DOCK_B2B 1 C4128
56PF
5%
FL4103 #26118161: Update FL4104 to 49.9ohm 25V
2 NP0-C0G-CERM
150OHM-25%-200MA-0.7DCR 01005
2 1 PP3V0_LAT_CONN R4104 ROOM=DOCK_B2B
01005
41
I2C_HOMER_SCL 1
49.9 2
I2C_HOMER_SCL_CONN FL4117
C4134
47 36 41
ROOM=DOCK_B2B 1 CKPLUS_WAIVE=I2C_PULLUP 150OHM-25%-200MA-0.7DCR
1%
1 C4135 LOWERMIC1_TO_CODEC_AIN1_CONN_NEG
220PF
D
1/32W 2 1
LOWERMIC1_TO_CODEC_AIN1_N
D MF 31 41
5% 56PF
10V 01005 01005
2 C0G-CERM
01005
ROOM=DOCK_B2B
2
5%
25V
NP0-C0G-CERM
ROOM=DOCK_B2B 1 C4129
ROOM=DOCK_B2B 01005 5%
56PF
FL4112 ROOM=DOCK_B2B 25V
2 NP0-C0G-CERM
01005
150OHM-25%-200MA-0.7DCR
FL4107 I2C_HOMER_SDA 1 2 I2C_HOMER_SDA_CONN FL4118 ROOM=DOCK_B2B
150OHM-25%-200MA-0.7DCR 47 36
CKPLUS_WAIVE=I2C_PULLUP
41
150OHM-25%-200MA-0.7DCR
01005
53 40 29 19 PP3V0_TRISTAR_ANT_PROX 2 1 PP3V0_LAT1_CONN 41 1 C4136 32 PP_CODEC_TO_LOWERMIC1_BIAS 2 1 PP_CODEC_TO_LOWERMIC1_BIAS_CONN 41
01005 56PF
ROOM=DOCK_B2B 1 C4119 VOLTAGE=3.0V
2
5%
25V
01005
ROOM=DOCK_B2B
1 C4130
220PF
5%
NP0-C0G-CERM
01005 220PF
10V
2 C0G-CERM
01005 ARC1 ROOM=DOCK_B2B
5%
10V
2 C0G-CERM
01005
FL4108 ROOM=DOCK_B2B
ROOM=DOCK_B2B
150OHM-25%-200MA-0.7DCR 41 35 ARC1_TO_SOLENOID1_OUT_POS FL4119
2 1
150OHM-25%-200MA-0.7DCR
53 52
32 21 20 18 16 PP1V8_SDRAM PP1V8_LAT_ARC_CONN 41
48 47 40 37 36
01005 LOWERMIC4_TO_CODEC_AIN2_P 2 1 LOWERMIC4_TO_CODEC_AIN2_CONN_POS
C4120
31 41
ROOM=DOCK_B2B 1
01005
220PF ROOM=DOCK_B2B 1 C4131
5%
10V 41 35 ARC1_TO_SOLENOID1_OUT_NEG 56PF
2 C0G-CERM 5%
01005 C4101 1 C4102 1 25V
2 NP0-C0G-CERM
01005
ROOM=DOCK_B2B 220PF 220PF
5% 5% ROOM=DOCK_B2B
R4109 10V
C0G-CERM 2
10V
C0G-CERM 2 FL4120
1
0.00 2
01005 01005 150OHM-25%-200MA-0.7DCR
53 BB_TO_LAT_ANT_SCLK BB_TO_LAT_ANT_SCLK_CONN 41 ROOM=DOCK_B2B ROOM=DOCK_B2B
LOWERMIC4_TO_CODEC_AIN2_N 2 1 LOWERMIC4_TO_CODEC_AIN2_CONN_NEG
C4121
0% 31 41
1/32W 1
01005
C4132
MF
01005
ROOM=DOCK_B2B 5%
33PF
16V
2 NP0-C0G-CERM
Antenna GPIO ROOM=DOCK_B2B 1
56PF
C
5%
C
m
25V
01005 2 NP0-C0G-CERM
ROOM=DOCK_B2B
FL4101 01005
150OHM-25%-200MA-0.7DCR
R4110 FL4121 ROOM=DOCK_B2B
o
0.00 53 BB_TO_LAT_GPO1 2 1 BB_TO_LAT_GPO1_CONN 41 150OHM-25%-200MA-0.7DCR
53 BB_TO_LAT_ANT_DATA 1 2 BB_TO_LAT_ANT_DATA_CONN 41
01005
0%
C4122
1 C4110 32 PP_CODEC_TO_LOWERMIC4_BIAS 2 1 PP_CODEC_TO_LOWERMIC4_BIAS_CONN 41
.c
1 ROOM=DOCK_B2B
1/32W
56PF 01005
MF
01005
5%
33PF 5%
25V
ROOM=DOCK_B2B
1 C4133
ROOM=DOCK_B2B 2 220PF
2 16V
NP0-C0G-CERM
NP0-C0G-CERM 01005 5%
10V
01005
SPEAKER1 2 C0G-CERM
x
ROOM=DOCK_B2B
ROOM=DOCK_B2B 01005
FL4102 ROOM=DOCK_B2B
FL4114
fi
150OHM-25%-200MA-0.7DCR
2 1
150OHM-25%-200MA-0.7DCR
53 BB_TO_LAT_GPO2 BB_TO_LAT_GPO2_CONN 41
SPEAKER_TO_SPEAKERAMP1_VSENSE_P 2 1 SPEAKER_TO_SPEAKERAMP1_VSENSE_CONN_POS
a
01005 34 41
ROOM=DOCK_B2B 1 C4111 01005
ROOM=DOCK_B2B 1 C4126
56PF
in
5% 220PF
25V 5%
2 NP0-C0G-CERM 2 10V
01005 C0G-CERM
01005
ROOM=DOCK_B2B
FL4115 ROOM=DOCK_B2B
h
150OHM-25%-200MA-0.7DCR
Per ANT Erdinc, change to cap
SPEAKER_TO_SPEAKERAMP1_VSENSE_N 2 1 SPEAKER_TO_SPEAKERAMP1_VSENSE_CONN_NEG
.c
34 41
01005
ROOM=DOCK_B2B 1 C4127
220PF
5%
w
VOLTAGE=14.0V 2 10V
C0G-CERM
01005
ROOM=DOCK_B2B
PP5V0_USB
w
40 21 4
B J4101 41 34 SPEAKERAMP1_TO_SPEAKER_OUT_POS B
C4109 1 C4105 1 C4106 1 C4107 1 C4108 1 245857 1 C4103
0.1UF
10%
25V
X5R 2
0201
0.1UF
10%
25V
X5R 2
0201
0.1UF
10%
25V 2
X5R
0201
330PF
10%
16V 2
CER-X7R
01005
330PF
10%
16V
CER-X7R 2
01005
53
49
F-ST-SM
50
w 5%
220PF
2 10V
C0G-CERM
01005
ROOM=DOCK_B2B ROOM=DOCK_B2B ROOM=DOCK_B2B ROOM=DOCK_B2B ROOM=DOCK_B2B ROOM=DOCK_B2B
1 2 41 34 SPEAKERAMP1_TO_SPEAKER_OUT_NEG
41 34 SPEAKERAMP1_TO_SPEAKER_OUT_NEG #25429221:Carrier Dock flex to add +1 ACC2 pin
41 SPEAKER_TO_SPEAKERAMP1_VSENSE_CONN_NEG 3 4 1 C4104
46 BB_TO_LAT_GPO3_CONN 5 6 PP_TRISTAR_ACC2_CONN 41
220PF
5%
LOWERMIC4_TO_CODEC_AIN2_CONN_NEG 7 8 BB_TO_LAT_GPO2_CONN 2 10V
41
41
41
PP_CODEC_TO_LOWERMIC4_BIAS_CONN
PP_TRISTAR_ACC1_CONN
9
11
10
12
LOWERMIC4_TO_CODEC_AIN2_CONN_POS
LOWERMIC4_TO_CODEC_BIAS_FILT_RET
41
41
32
TRISTAR C0G-CERM
01005
ROOM=DOCK_B2B
40 4
40 4
90_TRISTAR_DP2_CONN_P
90_TRISTAR_DP2_CONN_N
15
17
16
18
BB_TO_LAT_ANT_SCLK_CONN
BB_TO_LAT_ANT_DATA_CONN
41
41
TRISTAR_CON_DETECT_L
R4102
2
1.00K 1
TRISTAR_CON_DETECT_CONN_L 41
USB AC Coupling
AC return path for USB pairs which is referenced to GND and VDD_MAIN
19 20 PP1V8_LAT_ARC_CONN 41
40 4
5%
90_TRISTAR_DP1_CONN_N 21 22 PP3V0_LAT1_CONN 53
PP_VDD_MAIN
C4116
40 4 41 1/32W 27 26 25 23 21 19 18 10 9 4
MF 1 52 46 40 39 37 35 34 33 31 28
90_TRISTAR_DP1_CONN_P 23 24 01005
40 4
27PF
25 26 ROOM=DOCK_B2B 5%
2 16V
1 C4143
MIKEYBUS_REFERENCE 27 28 NP0-C0G 220PF
31
LOWERMIC1_TO_CODEC_AIN1_CONN_POS 29 30 LOWERMIC1_TO_CODEC_AIN1_CONN_NEG
FL4105 01005 5%
2 10V
41 41 10-OHM-1.1A ROOM=DOCK_B2B C0G-CERM
32 LOWERMIC1_TO_CODEC_BIAS_FILT_RET 31 32 PP_CODEC_TO_LOWERMIC1_BIAS_CONN 41
1 2
01005
33 34 40 4 PP_TRISTAR_ACC1 PP_TRISTAR_ACC1_CONN 41
TRISTAR_CON_DETECT_CONN_L
ROOM=SOC
41
01005
47 I2C_MIC1_SDA_CONN 35 36 ROOM=DOCK_B2B 1 C4117 VOLTAGE=4.3V
47 I2C_MIC1_SCL_CONN 37 38 100PF
5%
A ARC1_TO_SOLENOID1_OUT_POS
39
41
40
42
ARC1_TO_SOLENOID1_OUT_NEG
ARC1_TO_SOLENOID1_OUT_POS
35 41
FL4106
2 16V
NP0-C0G
01005 SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
41 35 35 41
PAGE TITLE
SOLENOID1_TO_ARC1_VSENSE_POS 43 44 SOLENOID1_TO_ARC1_VSENSE_NEG 22-OHM-25%-1800MA ROOM=DOCK_B2B
35
41 PP3V0_LAT_CONN 45 46 I2C_HOMER_SDA_CONN
35
41 40 4 PP_TRISTAR_ACC2 1 2 PP_TRISTAR_ACC2_CONN 41
spare
DRAWING NUMBER SIZE
SPEAKER_TO_SPEAKERAMP1_VSENSE_CONN_POS 47 48 I2C_HOMER_SCL_CONN 0201
41 41
ROOM=DOCK_B2B 1 C4118 VOLTAGE=4.3V
Apple Inc. 051-00419 D
#25098110: Decrease DCR 100PF REVISION
5%
41 34 SPEAKERAMP1_TO_SPEAKER_OUT_POS 51 52 2 16V
NP0-C0G
R
8.0.0
01005 NOTICE OF PROPRIETARY PROPERTY: BRANCH
54 ROOM=DOCK_B2B
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
SHEET
6 OF 53
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 6 OF 81
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
C C
m
o
.c
x
fi
a
in
h
.c
w
w
B B
w
A SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
spare
DRAWING NUMBER SIZE
D D
C C
m
o
.c
x
fi
a
in
h
.c
w
w
B B
w
A SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
spare
DRAWING NUMBER SIZE
CHASSIS_GND_BS401 4 44
PP_STROBE_DRIVER1_COOL_LED 26 45 PP_STROBE_DRIVER2_COOL_LED 26 45
FL4407
C4406 1 1 C4408 C4411 1 1 C4412 120-OHM-0.220A
220PF
5%
27PF 220PF
5%
27PF
5% 20 BUTTON_RINGER_A 1 2 BUTTON_RINGER_A_CONN 45
5%
10V 16V 10V 16V 01005
C0G-CERM 2
01005
2 NP0-C0G
01005
C0G-CERM 2
01005
2 NP0-C0G
01005 C4418 1 ROOM=LEFT_BUTTON 1
ROOM=RIGHT_BUTTON ROOM=RIGHT_BUTTON ROOM=RIGHT_BUTTON ROOM=RIGHT_BUTTON 27PF
5%
6.3V 0201
NP0-C0G 2 5.5V-6.2PF
ROOM=LEFT_BUTTON
0201 DZ4402
ROOM=LEFT_BUTTON
2
FL4404
150OHM-25%-200MA-0.7DCR CHASSIS_GND_BS401 4 44
26 STROBE_MODULE_NTC 1 2 STROBE_MODULE_NTC_CONN 45
01005
R4401 1 ROOM=RIGHT_BUTTON
1 C4407
27K 220PF
0.5%
1/32W 5% R4405
MF 2 10V
C0G-CERM 100
01005 2 01005 20 BUTTON_VOL_DOWN_L 1 2 BUTTON_VOL_DOWN_CONN_L 45
ROOM=RIGHT_BUTTON
C HAWKING C
m
R4406
100
#24678255:DOE with 10% and/20% cap 20 12 BUTTON_VOL_UP_L 1 2 BUTTON_VOL_UP_CONN_L 45
o
C4417 C4420 1
5%
1/32W
MF
1 DZ4404
0.22UF 100PF 01005 12V-33PF
.c
5% 01005-1
1 2 16V 2 ROOM=LEFT_BUTTON
31 HAWKING_TO_CODEC_AIN7_N HAWKING_TO_CODEC_AIN7_N_CONN 45
NP0-C0G 2 ROOM=LEFT_BUTTON
01005
20%
6.3V ROOM=LEFT_BUTTON CHASSIS_GND_BS401 4 44
X5R
x
01005
ROOM=RIGHT_BUTTON
fi
C4421 FL4405
a
0.22UF 150OHM-25%-200MA-0.7DCR
HAWKING_TO_CODEC_AIN7_P 1 2 HAWKING_TO_CODEC_AIN7_C_P 1 2 HAWKING_TO_CODEC_AIN7_P_CONN
in
31 45
01005
20% CKPLUS_WAIVE=MISS_N_DIFFPAIR
ROOM=RIGHT_BUTTON NOSTUFF
6.3V
X5R
01005
1 C4415 1 C4422
56PF 180PF
h
ROOM=RIGHT_BUTTON 5% 10%
2 25V 2 10V
NP0-C0G-CERM CERM
01005 01005
.c
ROOM=RIGHT_BUTTON ROOM=RIGHT_BUTTON
w
FL4406
150OHM-25%-200MA-0.7DCR
w
PP1V8_HAWKING 1 2 PP1V8_HAWKING_CONN
B B
19 45
01005
ROOM=RIGHT_BUTTON 1 C4416 1 C4414
2
2.2UF
20%
6.3V
X5R-CERM
0201-1
2
5%
10Vw
220PF
C0G-CERM
01005
FL4403
150OHM-25%-200MA-0.7DCR
32 PP_CODEC_TO_REARMIC2_BIAS 2 1 PP_CODEC_TO_REARMIC2_BIAS_CONN 45
01005
ROOM=RIGHT_BUTTON 1 C4403
220PF
5%
2 10V
C0G-CERM
01005
ROOM=RIGHT_BUTTON
FL4401
150OHM-25%-200MA-0.7DCR
31 REARMIC2_TO_CODEC_AIN3_P 2 1 REARMIC2_TO_CODEC_AIN3_CONN_P 45
01005
ROOM=RIGHT_BUTTON 1 C4404
56PF
5%
2 25V
NP0-C0G-CERM
01005
A ROOM=RIGHT_BUTTON
A
FL4402
SYNC_MASTER=Sync SYNC_DATE=05/17/2016
PAGE TITLE
150OHM-25%-200MA-0.7DCR
2 1
spare
31 REARMIC2_TO_CODEC_AIN3_N REARMIC2_TO_CODEC_AIN3_CONN_N 45 DRAWING NUMBER SIZE
01005
Apple Inc. 051-00419 D
ROOM=RIGHT_BUTTON 1 C4405 REVISION
56PF R
8.0.0
5%
2 25V
NP0-C0G-CERM NOTICE OF PROPRIETARY PROPERTY: BRANCH
01005 THE INFORMATION CONTAINED HEREIN IS THE
ROOM=RIGHT_BUTTON PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
6 OF 53
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 6 OF 81
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
LPDP_UT_BI_AP_AUX_CONN
2
4
1
3 90_LPDP_UT_TO_AP_D0_CONN_N COMBINED BUTTON FLEX CONNECTOR
D
25 25
D 25 AP_TO_UT_SHUTDOWN_CONN_L
UT_AND_NV_TO_LED_DRIVER_STROBE_EN_CONN
6
8
5
7
90_LPDP_UT_TO_AP_D0_CONN_P 25
MLB APN: 516S00150
25
FLEX APN: 516S00149
48 I2C_UT_SDA_CONN 10 9 90_LPDP_UT_TO_AP_D1_CONN_N 25
I2C_UT_SCL_CONN 12 11 90_LPDP_UT_TO_AP_D1_CONN_P
48
14 13
25
J4504
AA37D-S014SVA1
25 PP3V0_UT_SVDD_CONN 16 15 AP_TO_UT_CLK_CONN 25 F-ST-SM
19 20
46 25 PP2V9_UT_AVDD_CONN 18 17
20 19
MAKE_BASE=TRUE GND 15 16 PP_STROBE_DRIVER2_COOL_LED 26 44
25 PP1V8_UT_CONN 22 21
44 PP_CODEC_TO_REARMIC2_BIAS_CONN 1 2 STROBE_MODULE_NTC_CONN 44
25 PP2V8_UT_AF_VAR_CONN 26 25
44 REARMIC2_TO_CODEC_AIN3_CONN_N 3 4 PP1V8_HAWKING_CONN
44 REARMIC2_TO_CODEC_AIN3_CONN_P
5 6 HAWKING_TO_CODEC_AIN7_P_CONN
44
44
XW4501
SHORT-20L-0.05MM-SM
32 REARMIC2_TO_CODEC_BIAS_FILT_RET 7 8 1 2 HAWKING_TO_CODEC_AIN7_N_CONN 44
47 I2C_MIC2_SDA_CONN
9 10 BUTTON_RINGER_A_CONN 44 ROOM=RIGHT_BUTTON
47 I2C_MIC2_SCL_CONN
11 12 BUTTON_VOL_UP_CONN_L 44
44 BUTTON_POWER_KEY_CONN_L
13 14 BUTTON_VOL_DOWN_CONN_L
DISPLAY / TOUCH FLEX CONNECTOR
44
44 26 PP_STROBE_DRIVER1_COOL_LED 17 18 PP_STROBE_DRIVER2_WARM_LED 26 44
THIS ONE ---> 516S00138 RCPT (USED ON MLB)
516S00137 PLUG 44 26 PP_STROBE_DRIVER1_WARM_LED 21 22
J4502
BB35C-RA40-3A
F-ST-SM
45
41 42
m
39 47
PP5V7_MESON_AVDDH_CONN 50MA 3 4 I2C_DISP_EEPROM_SCL_CONN 47
R4501
39
o
39 PP1V8_LCM_CONN 20MA 7 8 I2C_TOUCH_SCL_CONN 2 1 47
.c
11 12 MF
#24543369: Keep PP 39 39
01005
TOUCH_TO_AP_INT_L_CONN 13 14 SPI_AP_TO_TOUCH_SCLK_CONN ROOM=DISPLAY_B2B
PP4501
39 39
SM PP 1 SPI_AP_TO_TOUCH_CS_CONN_L 15 16 AP_TO_CUMULUS_CLK_32K_CONN
39 39
P2MM-NSM
ROOM=TEST UART_AOP_TO_TOUCH_TXD_CONN 17 18 SPI_AP_TO_TOUCH_MOSI_CONN
x
39 39
TP_LCM_PIFA 21 22
fi
38 LCM_TO_MAMBA_MSYNC_CONN 23 24 90_MIPI_AP_TO_LCM_DATA0_CONN_P 39
PMU_TO_LCM_PANICB_CONN 25 26 90_MIPI_AP_TO_LCM_DATA0_CONN_N
1 C4507 39 39
a
56PF 39 UART_TOUCH_TO_AOP_RXD_CONN 27 28
5% 39 LCM_TO_CHESTNUT_PWR_EN_CONN 29 30 90_MIPI_AP_TO_LCM_DATA1_CONN_P 39
2 25V
in
NP0-C0G-CERM
01005 38 MAMBA_TO_LCM_MDRIVE 31 32 90_MIPI_AP_TO_LCM_DATA1_CONN_N 39
ROOM=DISPLAY_B2B 39 AP_TO_LCM_RESET_CONN_L 33 34
39 4 PP_LCM_BL_CAT1_CONN 100MA 35 36 90_MIPI_AP_TO_LCM_CLK_CONN_P 39
PP_LCM_BL_ANODE_CONN 37 38 90_MIPI_AP_TO_LCM_CLK_CONN_N
h
39 4 200MA 39
39 4 PP_LCM_BL_CAT2_CONN 100MA 39 40
.c
43 44
46
w
w
B B
FOREHEAD516S00146
FLEX CONNECTOR
w
THIS ONE ---> RCPT (USED ON MLB)
516S00145 PLUG
J4503
245858036201829
F-ST-SM
41
37 38
29 PP2V9_NH_AVDD_CONN 1 2 90_MIPI_NH_TO_AP_DATA0_P 9
29 PP1V8_NH_IO_CONN 3 4 90_MIPI_NH_TO_AP_DATA0_N 9
5 6
29 AP_TO_NH_SHUTDOWN_CONN_L 7 8 90_MIPI_NH_TO_AP_CLK_P 9
29 AP_TO_NH_CLK_CONN 9 10 90_MIPI_NH_TO_AP_CLK_N 9
29 SPEAKER_TO_SPEAKERAMP2_VSENSE_CONN_P 11 12
29 PP3V0_ALS_CONVOY_CONN 13 14 90_MIPI_NH_TO_AP_DATA1_P 9
47 I2C_ALS_CONVOY_SCL_CONN 15 16 90_MIPI_NH_TO_AP_DATA1_N 9
48 I2C_PROX_SCL_CONN 17 18
29 PROX_BI_AP_AOP_INT_PWM_L_CONN 19 20 PP1V2_NH_DVDD_CONN 29
29 PDM_CONVOY_TO_ADARE_DATA_CONN 21 22 I2C_NH_SCL_CONN 48
A 29 FRONTMIC3_TO_CODEC_AIN4_CONN_N 23 24 I2C_NH_SDA_CONN 48
A
PP3V0_PROX_CONN SPEAKERAMP2_TO_SPEAKER_OUT_POS
SYNC_MASTER=Sync SYNC_DATE=05/17/2016
29 25 26 29 33 46
PAGE TITLE
29
29
PDM_ADARE_TO_CONVOY_CLK_CONN
PP_CODEC_TO_FRONTMIC3_BIAS_CONN
27
29
28
30
SPEAKERAMP2_TO_SPEAKER_OUT_NEG
SPEAKER_TO_SPEAKERAMP2_VSENSE_CONN_N
29 33 46
29
spare
DRAWING NUMBER SIZE
31 32 ALS_TO_AP_INT_CONN_L
33 34 I2C_ALS_CONVOY_SDA_CONN
29
D 25 18 17 16 13 12 11 9 8 7 5
52 48 47 39 29
PP1V8 NOSTUFF 10 NC_AP_LPDP_AUX2
MAKE_BASE=TRUE
NC_AP_LPDP_AUX2
D
1 R4603 1 R4604
1
R4711
2.2K 2.2K 10K
5% 5% 5%
1/32W 1/32W 1/32W
MF MF MF
01005 01005 2 01005
2 ROOM=SOC 2 ROOM=SOC ROOM=MAMBA_MESA
I2C_TOUCH_TO_MAMBA_SCL 47
9 I2C_ISP_NV_SCL MAKE_BASE=TRUE I2C_ISP_NV_SCL 26
9 I2C_ISP_NV_SDA
MAKE_BASE=TRUE I2C_ISP_NV_SDA 26
NC Nets in Small FF
10 NC_90_LPDP_NV_TO_AP_D2_P NC_90_LPDP_NV_TO_AP_D2_P
MAKE_BASE=TRUE
UT B2B 10 NC_90_LPDP_NV_TO_AP_D2_N
MAKE_BASE=TRUE
NC_90_LPDP_NV_TO_AP_D2_N
1 C2531 1 C2507
2.2UF 2.2UF 10 NC_90_LPDP_NV_TO_AP_D3_N NC_90_LPDP_NV_TO_AP_D3_N
MAKE_BASE=TRUE
20% 20%
2 6.3V 2 6.3V
X5R-CERM X5R-CERM
0201-1 0201-1
ROOM=RCAM_B2B ROOM=RCAM_B2B
C C
m
o
Top Speaker Compass Coil
.c
VDD_MAIN Cap
#26634069:D10x Only, 5x VDD_MAIN CAPS Change to 10UF/10V
x
Pg21 Pg34 Pg35 Pg37 SPEAKERAMP2_TO_SPEAKER_OUT_POS
PP_VDD_MAIN
fi
29 33 45
53
28 27 26 25 23 21 19 18 10 9 4
52 46 41 40 39 37 35 34 33 31
SPEAKERAMP2_TO_SPEAKER_OUT_NEG 29 33 45
a
10UF 10UF 10UF 10UF 10UF
20% 20% 20% 20% 20%
VOLTAGE=10V 2 10V 10V 10V 10V
X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2
in
X5R-CERM
0402-8
ROOM=BACKLIGHT
0402-8
ROOM=CHARGER
0402-8
ROOM=SPKAMP1
0402-8
ROOM=ARC1
0402-8
ROOM=CHESTNUT
1
R3332 1
R3333
910 910
1% 1%
1/32W 1/32W
TK
h
TK
2 01005 2 01005
ROOM=SPKAMP2 ROOM=SPKAMP2
.c
NEG_COMPASS_COIL_COMP POS_COMPASS_COIL_COMP
w
1
XW3333
w
SHORT-20L-0.05MM-SM
B
NO_XNET_CONNECTION
B 2
ROOM=MAMBA_MESA
OMIT
w 1 C3332
220PF
1 C3333
220PF
5% 5%
2 10V
C0G-CERM 2 10V
C0G-CERM
01005 01005
#25742582,Add back C3531 in layout at ARC #26104509:C3525 Change to 1UF 0201 in DVT ROOM=SPKAMP2 ROOM=SPKAMP2
53 52
27 26 25 23 21 19 18 10 9 4
PP_VDD_MAIN 53 52
27 26 25 23 21 19 18 10 9 4 PP_VDD_MAIN
46 41 40 39 37 35 34 33 31 28 46 41 40 39 37 35 34 33 31 28
C3531 1 C3525 1
10UF 1.0UF
20%
20%
10V 6.3V
X5R-CERM 2 X5R 2
0402-8 0201-1
ROOM=ARC1 ROOM=ARC1
A
53 41
01005
ROOM=DOCK_B2B 1 C4608 1 C2707
SYNC_MASTER=Sync
PAGE TITLE
SYNC_DATE=05/17/2016
56PF
5%
2 25V
NP0-C0G-CERM
2.2UF
20%
spare
01005 2 6.3V DRAWING NUMBER SIZE
X5R-CERM
ROOM=DOCK_B2B 0201-1
ROOM=TRISTAR Apple Inc. 051-00419 D
REVISION
R
8.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
AP TOUCH
PP1V8 46 39 38 18
PP1V8_TOUCH
25 18 17 16 13 12 11 9 8 7 5
52 48 47 46 39 29
NOSTUFF NOTE:MAMBA I2C 2.2K PULL-UPS TO PP1V8_TOUCH INSIDE GALILEO
I2C0 R4701
4.02K
1%
1
R4702
4.02K
1%
1 1
R4712
10K
ADDING R3803, R3804 AS OPTION FOR TWEAKING VALUE
1/32W 1/32W 5%
MF MF #26682438:Move to Page 46 1/32W
MF
D
01005 2
ROOM=SOC
01005 2
ROOM=SOC 2 01005
ROOM=MAMBA_MESA D
46 I2C_TOUCH_TO_MAMBA_SCL MAKE_BASE=TRUE I2C_TOUCH_TO_MAMBA_SCL 38 TO MAMBA / MESA FLEX
11 I2C0_AP_SCL MAKE_BASE=TRUE I2C0_AP_SCL 37 I2C_TOUCH_BI_MAMBA_SDA MAKE_BASE=TRUE I2C_TOUCH_BI_MAMBA_SDA 38
11 I2C0_AP_SDA MAKE_BASE=TRUE I2C0_AP_SDA 37
NOSTUFF NOSTUFF
C4709 1 1 C4710
NOSTUFF NOSTUFF I2C0_AP_SCL 23
56PF 56PF
#24544434 C4701 1 1 C4702 I2C0_AP_SDA 23
5%
NP0-C0G-CERM
225V 2
5%
25V
NP0-C0G-CERM
56PF 56PF 01005 01005
5% 5% I2C0_AP_SCL ROOM=MAMBA_MESA ROOM=MAMBA_MESA
2 25V 2 25V 40
NP0-C0G-CERM NP0-C0G-CERM I2C0_AP_SDA 40
01005 01005
ROOM=SOC ROOM=SOC
I2C_TOUCH_TO_MAMBA_SCL 45
TO DISPLAY / TOUCH FLEX
I2C_TOUCH_BI_MAMBA_SDA 45
I2C0_AP_SCL 20 37
I2C0_AP_SDA 37
C4711 1 1 C4712
I2C1 5%
56PF
2 25V
5%
56PF
2 25V
25 18 17 16 13 12 11 9 8 7 5 PP1V8 NP0-C0G-CERM NP0-C0G-CERM
52 48 47 46 39 29 01005 01005
ROOM=DISPLAY_B2B ROOM=DISPLAY_B2B
R4703 1 R4704 1
4.02K 4.02K
1% 1%
1/32W 1/32W
HOMER
MF MF
I2C5
01005 01005
ROOM=SOC 2 ROOM=SOC 2
C #24544426
m
1 1 53 52
I2C1_AP_SCL 20
1 1
56PF 56PF 1 1
5%
2 25V 2
5%
25V
I2C1_AP_SDA 20 R4713 R4714 R4715
2.2K
R4716
2.2K
1.00K 1.00K
o
NP0-C0G-CERM NP0-C0G-CERM 5% 5%
01005 01005 5% 5% 1/32W 1/32W
ROOM=PMU ROOM=PMU 1/32W 1/32W MF MF
MF MF 01005 010052
2 01005 2 01005 ROOM=SOC 2
.c
ROOM=SOC
ROOM=HOMER ROOM=HOMER
I2C_HOMER_SCL I2C5_SCL
I2C2 I2C_HOMER_SDA
36 41
36 41 I2C5_SDA
11
11
x
fi
I2C1_AP_SCL 21
25 18 17 16 13 12 11 9 8 7 5
52 48 47 46 39 29
PP1V8 I2C1_AP_SDA 21
a
1 1
R4705 R4706
2.2K
5%
2.2K
5% I2C3
in
1/32W 1/32W
MF MF 25 18 17 16 13 12 11 9 8 7 5 PP1V8
01005 01005 52 48 47 46 39 29
ROOM=SOC 2 ROOM=SOC 2
1 1
R4709 R4710
h
11 I2C2_AP_SCL MAKE_BASE=TRUE I2C2_AP_SCL 33
2.2K 2.2K
11 I2C2_AP_SDA MAKE_BASE=TRUE I2C2_AP_SDA 33
5% 5%
1/32W 1/32W
.c
ROOM=FOREHEAD MF MF ROOM=DOCK
R4707
01005
ROOM=SOC 2
01005
ROOM=SOC 2 FL4730
0.00 150OHM-25%-200MA-0.7DCR ckplus_waive=I2C_PULLUP
1 2 I2C_ALS_CONVOY_SCL_CONN 45
I2C3_AP_SCL 2 1 I2C_MIC1_SCL_CONN
w
0% MF 11 41
1/32W 01005 01005
R4708 #26633265:mitigate MIC1 undershoot
TO DOCK FLEX
0.00
w
I2C_ALS_CONVOY_SDA_CONN FL4729
B
1 2
B 0% MF
45
I2C3_AP_SDA 2
100 1
CKPLUS_WAIVE=I2C_PULLUP
I2C_MIC1_SDA_CONN
1/32W 01005
ROOM=FOREHEAD
C4707 C4708 TO FOREHEAD FLEX 11 41
56PF
5%
25V 2
NP0-C0G-CERM
1 1
5%
56PF
2 25V
NP0-C0G-CERM
w 5%
1/32W
MF
01005
ROOM=DOCK
C4730
56PF
5%
1 1
5%
C4729
56PF
01005 01005 25V 25V
ROOM=FOREHEAD ROOM=FOREHEAD NP0-C0G-CERM 2 2 NP0-C0G-CERM
01005 01005
ROOM=DOCK_B2B ROOM=DOCK_B2B
ROOM=RIGHT_BUTTON
FL4732
150OHM-25%-200MA-0.7DCR
2 1 I2C_MIC2_SCL_CONN 45
CKPLUS_WAIVE=I2C_PULLUP
01005
FL4731 TO COMBINED BUTTON FLEX
150OHM-25%-200MA-0.7DCR
2 1 I2C_MIC2_SDA_CONN 45
CKPLUS_WAIVE=I2C_PULLUP
01005
ROOM=RIGHT_BUTTON
C4732 1 1 C4731
56PF 56PF
5% 5%
25V 2 2 25V
NP0-C0G-CERM NP0-C0G-CERM
01005 01005
ROOM=RIGHT_BUTTON ROOM=RIGHT_BUTTON
FL4742
150OHM-25%-200MA-0.7DCR
A 2 1 I2C_DISP_EEPROM_SCL_CONN 45
SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
01005 PAGE TITLE
ROOM=DISPLAY_B2B
AOP
PP1V8_SDRAM
ISP
47 41 40 37 36 32 21 20 18 16
53 52 48
PP1V8_SDRAM
1 C4807
I2C 47 41 40 37 36 32 21 20 18 16
53 52 48 0.1UF
20%
I2C0
VCC B1
1 1 2 6.3V
R4801
2.2K
R4802
2.2K
X5R-CERM
01005
5% 5% ROOM=SOC PP1V8 #24550735: ISP I2C0 PU
1/32W
MF
1/32W
MF
#24544699: Support 1MHz 25 18 17 16 13 12 11 9 8 7 5
52 48 47 46 39 29
2
01005
2
01005 U4802 1 1
MAX20312 R4808 R4809
D 13 I2C_AOP_SCL MAKE_BASE=TRUE
WLP
A2 IOVCC1 ROOM=SOC
5%
1.00K 5%
1.00K D
1/32W 1/32W
I2C_AOP_SDA B2 IOVCC2 MF MF
13 MAKE_BASE=TRUE 2 01005 2 01005
ROOM=SOC ROOM=SOC
A1 GND
9
I2C_ISP_UT_SCL MAKE_BASE=TRUE I2C_ISP_UT_SCL 26
R4816
I2C_AOP_SCL
I2C1 1
0.00
2 I2C_UT_SCL_CONN 45
I2C_AOP_SDA
34
34
See page 46 0%
1/32W 1 C4817
CKPLUS_WAIVE=I2C_PULLUP
MF
01005 56PF
ROOM=RCAM_B2B 5%
2 25V
I2C_AOP_SCL 35 NP0-C0G-CERM
01005
I2C_AOP_SDA 35
R4817 ROOM=RCAM_B2B
ROOM=FOREHEAD
FL4815 TO FCAM FLEX
I2C2 1
0.00 2
1
I2C_UT_SDA_CONN 45
CKPLUS_WAIVE=I2C_PULLUP
150OHM-25%-200MA-0.7DCR 25 18 17 16 13 12 11 9 8 7 5
52 48 47 46 39 29
PP1V8
0%
1/32W
MF
C4816
56PF
01005 5%
2 1 I2C_PROX_SCL_CONN 45 ROOM=RCAM_B2B 25V
01005 CKPLUS_WAIVE=I2C_PULLUP 2 NP0-C0G-CERM
1 1
R4810
2.2K
R4811
2.2K
01005
ROOM=RCAM_B2B
ROOM=FOREHEAD 5% 5% MF
C 56PF
C
m
25V 25V 01005
2 NP0-C0G-CERM 2 NP0-C0G-CERM ROOM=FOREHEAD 5%
Intentional R4815 Change 01005 01005 2 25V
ROOM=FOREHEAD ROOM=FOREHEAD NP0-C0G-CERM
01005
ROOM=FOREHEAD
o
38 19 PP1V8_MESA R4813
0.00
PP1V8_SDRAM
.c
16 18 20 21 32 36 37 40 41 47 1 2 I2C_NH_SDA_CONN 45
48 52 53 1
R4803 1
R4804 0% 1
C4813 CKPLUS_WAIVE=I2C_PULLUP
5 4.7K 4.7K 1/32W
1% 1% MF 56PF
VCC 1/32W 1/32W 01005 5%
25V
x
ROOM=FOREHEAD
6S U4805 3
MF
2 01005
MF
2 01005 R4806
2 NP0-C0G-CERM
74LVC1G3157GX Y0 NC ROOM=MAMBA_MESA ROOM=MAMBA_MESA
01005
ROOM=FOREHEAD
X2SON6 0.00
fi
4Z Y1 1 I2C_AOP_SCL_ISO 2 1 I2C_MESA_TURTLE_SCL_CONN 38
GND
2 0% 1/32W
MF 01005 ROOM=MAMBA_MESA
a
13 AOP_TO_MESA_I2C_ISO_EN 1 C4809
1
R4805 56PF
in
PP1V8_SDRAM 5%
1%
511K 16 18 20 21 32 36 37 40 41 47
48 52 53 2 25V
NP0-C0G-CERM TO MAMBA/MESA FLEX
1/32W 5 01005
MF ROOM=MAMBA_MESA
VCC
2 01005
h
6S U4806 3
R4807
74LVC1G3157GX Y0 NC
X2SON6 0.00
.c
4Z Y1 1 I2C_AOP_SDA_ISO 2 1 I2C_MESA_TURTLE_SDA_CONN 38
GND
2 0% 1/32W
MF 01005 ROOM=MAMBA_MESA
1 C4810
w
56PF
5%
2 25V
w
NP0-C0G-CERM
B 01005
ROOM=MAMBA_MESA B
w
A SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
spare
DRAWING NUMBER SIZE
D D
C C
m
o
.c
x
fi
a
in
h
.c
w
w
B B
w
A SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
spare
DRAWING NUMBER SIZE
D D
C C
m
o
.c
x
fi
a
in
h
.c
w
w
B B
w
A SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
spare
DRAWING NUMBER SIZE
D D
C C
m
o
.c
x
fi
a
in
h
.c
w
w
B B
w
A SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
spare
DRAWING NUMBER SIZE
This page contains items which differ accross all MLB designs
PCIe lanes
PP0801
P2MM-NSM 1
D
SM ROOM=SOC
PP
D
90_AP_PCIE3_RXD_C_P 8 52
90_AP_PCIE3_RXD_C_N 8 52
PP0802
P2MM-NSM PP
1
SM ROOM=SOC
1 2 0.1UF 90_PCIE_BB_TO_AP_RXD_P
8 90_AP_PCIE2_RXD_C_P C0816
ROOM=SOC 20% 6.3V GND_VOID=TRUE
53 MAKE_BASE=TRUE
X5R-CERM 01005
1 2 0.1UF 90_PCIE_BB_TO_AP_RXD_N
8 90_AP_PCIE2_RXD_C_N C0817 53 MAKE_BASE=TRUE
C C
m
ROOM=SOC 20% 6.3V GND_VOID=TRUE
X5R-CERM 01005
1 2 0.1UF 90_PCIE_AP_TO_BB_TXD_P
90_AP_PCIE2_TXD_C_P C0815 53 MAKE_BASE=TRUE
o
8
ROOM=SOC 20% 6.3V GND_VOID=TRUE
X5R-CERM 01005
.c
1 2 0.1UF
8 90_AP_PCIE2_TXD_C_N C0818
ROOM=SOC 20% 6.3V GND_VOID=TRUE
90_PCIE_AP_TO_BB_TXD_N 53 MAKE_BASE=TRUE
X5R-CERM 01005
x
PP1V8
fi
25 18 17 16 13 12 11 9 8 7 5
48 47 46 39 29
1 R0807
100K
a
5%
1/32W
MF
2 01005
in
ROOM=SOC
52 PCIE_WLAN_BI_AP_CLKREQ_L
1 2
C0811 0.1UF
h
8 90_AP_PCIE3_RXD_C_P 90_PCIE_WLAN_TO_AP_RXD_P 53 MAKE_BASE=TRUE
ROOM=SOC 20% 6.3V GND_VOID=TRUE
X5R-CERM 01005
.c
1 2
8 90_AP_PCIE3_RXD_C_N C0812
ROOM=SOC 20% 6.3V
0.1UF 90_PCIE_WLAN_TO_AP_RXD_N
GND_VOID=TRUE
53 MAKE_BASE=TRUE
X5R-CERM 01005
w
1 2
8 90_AP_PCIE3_TXD_C_P C0814
ROOM=SOC 20% 6.3V
0.1UF 90_PCIE_AP_TO_WLAN_TXD_P
GND_VOID=TRUE
53 MAKE_BASE=TRUE
X5R-CERM 01005
w
B 8 90_AP_PCIE3_TXD_C_N C0813
ROOM=SOC
1
20%
2
6.3V
0.1UF 90_PCIE_AP_TO_WLAN_TXD_N 53 MAKE_BASE=TRUE B
X5R-CERM 01005
8 90_PCIE_AP_TO_WLAN_REFCLK_P
GND_VOID=TRUE
90_PCIE_AP_TO_WLAN_REFCLK_P 53 MAKE_BASE=TRUE
w
8 90_PCIE_AP_TO_WLAN_REFCLK_N 90_PCIE_AP_TO_WLAN_REFCLK_N 53 MAKE_BASE=TRUE
8 90_PCIE_AP_TO_BB_REFCLK_P 90_PCIE_AP_TO_BB_REFCLK_P 53 MAKE_BASE=TRUE 47 41 40 37 36 32 21 20 18 16 PP1V8_SDRAM
53 48
8 90_PCIE_AP_TO_BB_REFCLK_N 90_PCIE_AP_TO_BB_REFCLK_N 53 MAKE_BASE=TRUE
8 PCIE_AP_TO_WLAN_RESET_L PCIE_AP_TO_WLAN_RESET_L 53 MAKE_BASE=TRUE R52061
8 PCIE_AP_TO_BB_RESET_L PCIE_AP_TO_BB_RESET_L 53 MAKE_BASE=TRUE 100K #24556007:Parallel to 100kohm R5906_RF(nostuff)
1%
8 PCIE_WLAN_BI_AP_CLKREQ_L PCIE_WLAN_BI_AP_CLKREQ_L 52 53 MAKE_BASE=TRUE 1/32W
MF
8 PCIE_BB_BI_AP_CLKREQ_L PCIE_BB_BI_AP_CLKREQ_L 52 53 MAKE_BASE=TRUE 01005 2
ROOM=RADIO_BB
53 52 PCIE_BB_BI_AP_CLKREQ_L
#25811920: D10 CRB: 2x 01005 Cap for Backlight Desense #24535235: D10 EVT 1x Desense Cap (68pF)
D101 CRB: No additional Cap #24535276: D101 EVT 1x Desense Cap (220pF)
53
27 26 25 23 21 19 18 10 9 4
46 41 40 39 37 35 34 33 31 28
PP_VDD_MAIN PP3V0_NAND
A
17 19
Wifi/BT
27 26 25 23 21 19 18 10 9 4 PP_VDD_MAIN
46 41 40 39 37 35 34 33 31 28 27 26 25
77
23
58
21
55
19
53
18
52
10
46
9 4 PP_VDD_MAIN PP_VDD_MAIN
47 41 40 37 36 32 21 20 18 16 PP1V8_SDRAM PP1V8_SDRAM 41 40 39 37 35 34 33 31 28
68 60 58 55 53 52 48 47 41 40 37 36 32 21 20 18 16 PP1V8_SDRAM PP1V8_SDRAM
Cellular
68 60 58 55 53 52 48
55 20 PMUGPIO_TO_WLAN_CLK32K PMU_TO_WLAN_32K
65 38 37 32 25 23 19 PP_VDD_BOOST PP_VDD_BOOST_RF
65 20 BBPMU_TO_PMU_AMUX1 BBPMU_TO_PMU_AMUX1
55 20 PMU_TO_WLAN_REG_ON PMU_TO_WLAN_REG_ON
PMU_TO_BT_REG_ON 65 20 BBPMU_TO_PMU_AMUX2 BBPMU_TO_PMU_AMUX2
55 20 PMU_TO_BT_REG_ON
BT_TO_PMU_HOST_WAKE 69 20 BBPMU_TO_PMU_AMUX3 BBPMU_TO_PMU_AMUX3
55 20 BT_TO_PMU_HOST_WAKE
55 12
AP_TO_BT_WAKE AP_TO_BT_WAKE
64 12 AP_TO_BBPMU_RADIO_ON_L AP_TO_BBPMU_RADIO_ON_L
55 52 90_PCIE_AP_TO_WLAN_REFCLK_P 100_PCIE_AP_TO_WLAN_REFCLK_P
PMU_TO_BBPMU_RESET_L PMU_TO_BBPMU_RESET_L
D
20
90_PCIE_AP_TO_WLAN_REFCLK_N 100_PCIE_AP_TO_WLAN_REFCLK_N Opposite polarity on Karoo -->
D
55 52 64
64 12 AP_TO_BB_RESET_L AP_TO_BB_RESET_L
55 52 90_PCIE_AP_TO_WLAN_TXD_P 100_PCIE_AP_TO_WLAN_TX_P
BB_TO_AP_RESET_ACT_L
55 52 90_PCIE_AP_TO_WLAN_TXD_N 100_PCIE_AP_TO_WLAN_TX_N
68 12 BB_TO_AP_RESET_DETECT_L BB_TO_AP_RESET_DETECT_L
55 52 90_PCIE_WLAN_TO_AP_RXD_P 100_PCIE_WLAN_TO_AP_RX_P RADIO_MLB
68 37 26 BB_TO_STROBE_DRIVER_GSM_BURST_IND BB_TO_AP_GSM_TXBURST
55 52 90_PCIE_WLAN_TO_AP_RXD_N 100_PCIE_WLAN_TO_AP_RX_N
WIFI_MLB 68 12 AP_TO_BB_MESA_ON AP_TO_BB_MESA_ON
55 52 PCIE_AP_TO_WLAN_RESET_L PCIE_AP_TO_WLAN_PERST_L
68 12 AP_TO_BB_TIME_MARK AP_TO_BB_TIME_MARK
55 52 PCIE_WLAN_BI_AP_CLKREQ_L PCIE_AP_BI_WLAN_CLKREQ_L
68 12 AP_TO_BB_COREDUMP AP_TO_BB_COREDUMP_TRIG
55 20 WLAN_TO_PMU_HOST_WAKE PCIE_WLAN_TO_PMU_WAKE
64 39 23 20 13 LCM_TO_MANY_BSYNC TOUCH_TO_BBPMU_FORCE_PWM
55 12 AP_TO_WLAN_DEVICE_WAKE AP_TO_WLAN_DEV_WAKE
68 12 AP_TO_BB_IPC_GPIO1 AP_TO_BB_IPC_GPIO
AP_TO_BB_IPC_GPIO2
55 12 UART_AP_TO_WLAN_TXD UART_AP_TO_WLAN_TXD
55 12 UART_WLAN_TO_AP_RXD UART_WLAN_TO_AP_RXD 67 52 90_PCIE_AP_TO_BB_REFCLK_P 100_PCIE_AP_TO_BB_REFCLK_P
55 12 UART_AP_TO_WLAN_RTS_L UART_AP_TO_WLAN_RTS_L 67 52 90_PCIE_AP_TO_BB_REFCLK_N 100_PCIE_AP_TO_BB_REFCLK_N
55 12 UART_WLAN_TO_AP_CTS_L UART_WLAN_TO_AP_CTS_L 67 52 90_PCIE_AP_TO_BB_TXD_P 100_PCIE_AP_TO_BB_TX_P
67 52 90_PCIE_AP_TO_BB_TXD_N 100_PCIE_AP_TO_BB_TX_N
55 12
UART_AP_TO_BT_TXD UART_AP_TO_BT_TXD 67 52 90_PCIE_BB_TO_AP_RXD_P 100_PCIE_BB_TO_AP_RX_P
55 12
UART_BT_TO_AP_RXD UART_BT_TO_AP_RXD 67 52 90_PCIE_BB_TO_AP_RXD_N 100_PCIE_BB_TO_AP_RX_N
55 12
UART_AP_TO_BT_RTS_L UART_AP_TO_BT_RTS_L 68 52 PCIE_AP_TO_BB_RESET_L PCIE_AP_TO_BB_PERST_L
55 12
UART_BT_TO_AP_CTS_L UART_BT_TO_AP_CTS_L 68 52 PCIE_BB_BI_AP_CLKREQ_L PCIE_AP_BI_BB_CLKREQ_L
68 20 BB_TO_PMU_PCIE_HOST_WAKE_L PCIE_BB_TO_PMU_WAKE_L
55 13 AOP_TO_WLAN_CONTEXT_A AOP_TO_WLAN_CONTEXT_A
55 13 AOP_TO_WLAN_CONTEXT_B AOP_TO_WLAN_CONTEXT_B
UART_AP_TO_BB_TXD
55 11
I2S_AP_TO_BT_BCLK I2S_AP_TO_BT_BCLK
UART_BB_TO_AP_RXD
55 11
I2S_AP_TO_BT_LRCLK I2S_AP_TO_BT_LRCK 68 13 UART_AOP_TO_BB_TXD UART_AOP_TO_BB_TXD
55 11
I2S_BT_TO_AP_DIN I2S_BT_TO_AP_DIN 68 13 UART_BB_TO_AOP_RXD UART_BB_TO_AOP_RXD
55 11
I2S_AP_TO_BT_DOUT I2S_AP_TO_BT_DOUT UART_AOP_TO_GNSS_TXD
C C
m
UART_GNSS_TO_AOP_RXD
UART_BB_TO_WLAN_COEX I16
68 11 I2S_BB_TO_AP_BCLK I2S_AP_TO_BB_BCLK
ieee
ieee.std_logic_1164.all
work.all
UART_WLAN_TO_BB_COEX TRUE
o
68 11 I2S_BB_TO_AP_LRCLK I2S_AP_TO_BB_LRCLK
59
56 68 11 I2S_AP_TO_BB_DOUT I2S_AP_TO_BB_DOUT
50_UAT_WLAN_5G_WEST 50_UAT_WLAN_5G_WEST I2S_BB_TO_AP_DIN
.c
68 11 I2S_BB_TO_AP_DIN
50_UAT_WLAN_2G_EAST 50_UAT_WLAN_2G_EAST
50_LAT_WLAN_5G_EAST 50_UAT_WLAN_5G_EAST
68 55
UART_BB_TO_WLAN_COEX UART_BB_TO_WLAN_COEX
50_LAT_WLAN_G_1 50_WLAN_G_1 68 55 UART_WLAN_TO_BB_COEX UART_WLAN_TO_BB_COEX
x
50_LAT_WLAN_A_1 50_WLAN_A_1
50_UAT2_M 50_UAT2_M
NFC_SWP
fi
81 58 53 NFC_SWP
NFC_TO_BB_CLKREQ
BB_TO_NFC_CLK
a
78 58 53 NFC_SWP_MUX NFC_SWP_MUX
I15
SE2_READY
in
RADIO_MLB_FF
12 AP_TO_ICEFALL_FW_DWLD_REQ MAKE_BASE=TRUE
78
AP_TO_ICEFALL_FW_DWLD_REQ AP_TO_ICEFALL_FW_DWLD
50_WLAN_A_1 50_UAT_WLAN_2G_WEST_PLEXER
SE2_PWR_REQ
50_WLAN_G_1 50_UUAT_LB_MLB_NORTH
81 58 53 SE2_PRESENT SE2_PRESENT
ICEFALL_LDO_ENABLE
h
50_UAT_WLAN_5G_EAST 50_UAT_MB_HB_SOUTH 78 58 ICEFALL_LDO_ENABLE
50_UAT_WLAN_2G_EAST 50_UAT_LB_MLB_SOUTH
50_UAT_WLAN_5G_WEST 50_UAT1_WEST
.c
50_UAT2_M 50_UAT1_TUNER
36 17 13 SWD_AP_TO_MANY_SWCLK SWD_AP_TO_BB_CLK
67
PP3V0_TRISTAR_ARC_PROX PP3V0_TRISTAR_ANT_PROX 19 29 40 41 60 SWD_AOP_BI_BB_SWDIO SWD_AP_BI_BB_IO
67 13
VDD_TUNER_RFFE_VIO_1V8 PP1V8_SDRAM 16 18 20 21 32 36 37 40 41 47
48 52 53 55 58 60 68 PMU_TO_BB_USB_VBUS_DETECT USB_BB_VBUS
w
UAT_TUNER_RFFE_CLK
64 20
w
BUFFER_GPO2
B B
BB_TO_LAT_ANT_SCLK BB_TO_LAT_ANT_SCLK 41 53 60 68 50_UAT_WLAN_2G_WEST_PLEXER
BB_TO_LAT_ANT_SDATA BB_TO_LAT_ANT_DATA 41 53 60 68
To UAT 76 59 50_UAT_WLAN_2G_WEST_PLEXER
73 59 50_UAT_LB_MLB_SOUTH 50_UAT_LB_MLB_SOUTH
P2MM-NSM
SM
ROOM=UAT_DEBUG
P2MM-NSM
SM
PP5304 PP
PP5301 PP
1
1
w 73 59
75 59
75 59
50_UAT_MB_HB_SOUTH
50_UUAT_LB_MLB_NORTH
50_UAT1_WEST
50_UAT_MB_HB_SOUTH
50_UUAT_LB_MLB_NORTH
50_UAT1_WEST
FF SPECIFIC
ROOM=UAT_DEBUG
P2MM-NSM
SM PP5302 PP 1
ROOM=UAT_DEBUG
P2MM-NSM BB_TO_UAT_SCLK
SM PP5303 PP 1 MAKE_BASE=TRUE UAT_RFFE_CLK
ROOM=UAT_DEBUG
I2 MAKE_BASE=TRUE BB_TO_UAT_DATA UAT_RFFE_DATA
76 60 50_UAT1_TUNER 50_UAT1_TUNER
77 58 55 53 52
27 26 25 23 21 19 18 10 9 4 PP_VDD_MAIN PP_VDD_MAIN 68 60 BB_BUFFER_GPO1 BUFFER_GPO1
46 41 40 39 37 35 34 33 31 28
47 41 40 37 36 32 21 20 18 16 PP1V8_SDRAM PP1V8_SDRAM 68 60 BB_BUFFER_GPO2 BUFFER_GPO2
68 60 58 55 53 52 48 To LAT
68 60 53 41 BB_TO_LAT_ANT_SCLK LAT_RFFE_CLK
UART_GNSS_TO_AP_RXD
58 12 UART_AP_TO_NFC_TXD UART_AP_TO_NFC_TXD UART_AP_TO_GNSS_RTS_L
58 12 UART_NFC_TO_AP_RXD UART_NFC_TO_AP_RXD UART_GNSS_TO_AP_CTS_L
58 12 UART_AP_TO_NFC_RTS_L UART_AP_TO_NFC_RTS_L GNSS_TO_PMU_HOST_WAKE
58 12 UART_NFC_TO_AP_CTS_L UART_NFC_TO_AP_CTS_L AP_TO_GNSS_TIME_MARK
A NFC_SWP NFC_SWP
A
NFC
81 58 53
78 58 SE2_READY SE2_READY
SYNC_MASTER=Sync SYNC_DATE=05/17/2016
PAGE TITLE
SE2_PWR_REQ
78 58
81 58 53 SE2_PRESENT
SE2_PWR_REQ
SE2_PRESENT
spare
DRAWING NUMBER SIZE
PDF PAGE
TABLE_TABLEOFCONTENTS_HEAD
CSA PAGE CONTENTS
2 76 PERENNIAL
TABLE_TABLEOFCONTENTS_ITEM
3TABLE_TABLEOFCONTENTS_ITEM
77 WIFI FRONT-END
BOM OPTIONS:
D10_JP: D11_JP:
TRUE POWER
TABLE_5_HEAD TABLE_5_HEAD
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION PART# TRUE
QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
TABLE_5_ITEM TABLE_5_ITEM
55 53 IN PP_VDD_MAIN
131S0648 1 CAP,CER,0.3PF,+/-0.05,01005 C7705_RF CRITICAL D10_JP 152S00273 TRUE
1 IND,0.6NH,UH-Q,01005 R7703_RF CRITICAL D11_JP
TABLE_5_ITEM TABLE_5_ITEM
55 53 IN PP1V8_SDRAM
152S00029 1 IND,1.1NH,UH-Q,01005 R7703_RF CRITICAL D10_JP 152S1976 1
TRUE IND,0.7NH,UH-Q,01005 R7711_RF CRITICAL D11_JP
131S0400 1
TRUE CAP,CER,3.5PF+/-0.1,01005 R7702_RF CRITICAL D11_JP
TABLE_5_ITEM
CLOCKS
TABLE_5_ITEM TABLE_5_ITEM
55 53 IN PMUGPIO_TO_WLAN_CLK32K
117S0161 1 RES,MF,0 OHM,1/32W,01005 R7711_RF CRITICAL D10_JP 152S1986 1
TRUE IND,FILM,2.2NH,UH-Q,01005 R7704_RF CRITICAL D11_JP
CONTROL
TABLE_5_ITEM TABLE_5_ITEM
C
PMU_TO_WLAN_REG_ON
C
m
152S1980 1 IND,1.0NH,UH-Q,01005 R7704_RF CRITICAL D10_JP 131S0593 1
TRUE CAP,3.9PF,+/-1.0PF,0201,HI-Q R6711_RF CRITICAL D11_JP 55 53 IN
TABLE_5_ITEM TABLE_5_ITEM
55 53 IN PMU_TO_BT_REG_ON
131S0404 1 CAP,3.9PF,+/-1.0PF,01005 R6711_RF CRITICAL D10_JP 152S2055 1
TRUE IND,7.5NH,UH-Q,0201 C6729_RF CRITICAL D11_JP
TABLE_5_ITEM TABLE_5_ITEM
55 53 OUT BT_TO_PMU_HOST_WAKE
o
152S2061 1 IND,7.5NH,UH-Q,01005 C6729_RF CRITICAL D10_JP 117S0161 1
TRUE RES,MF,0 OHM,1/32W,01005 R7700_RF CRITICAL D11_JP 55 53 IN AP_TO_BT_WAKE
TABLE_5_ITEM TABLE_5_ITEM
.c
TABLE_5_ITEM TABLE_5_ITEM
x
TABLE_5_ITEM TABLE_5_ITEM
55 53 IN 90_PCIE_AP_TO_WLAN_TXD_P
152S2043 1 IND,6.2NH,UH-Q,01005 L7701_RF CRITICAL D10_JP 131S0893 1
TRUE CAP,CER,0.2PF,+/-0.05PF,01005 C7705_RF CRITICAL D11_JP
55 53 IN 90_PCIE_AP_TO_WLAN_TXD_N
fi
TABLE_5_ITEM TABLE_5_ITEM
117S0161 1 RES,MF,0 OHM,1/32W,01005 R7701_RF CRITICAL D10_JP 131S0893 1 CAP,CER,0.2PF,+/-0.05PF,01005 C7729_RF CRITICAL D11_JP 55 53 OUT 90_PCIE_WLAN_TO_AP_RXD_P
55 53 OUT 90_PCIE_WLAN_TO_AP_RXD_N
NOSTUFF:C7729_RF,C7711_RF,C7709_RF,C7710_RF, C7707_RF, C7708_RF NOSTUFF:C7706_RF, C7711_RF,C7709_RF,C7710_RF, C7707_RF PCIE_AP_TO_WLAN_RESET_L
a
55 53 IN
C7700_RF, C7703_RF,C7704_RF C7700_RF,C7702_RF, C7703_RF,C7704_RF PCIE_WLAN_BI_AP_CLKREQ_L
D10_ROW: 2 IO
WLAN_TO_PMU_HOST_WAKE
in
55 53 OUT
TABLE_5_HEAD
D11_ROW:
131S0648 1 CAP,CER,0.3PF,+/-0.05,01005 C7705_RF CRITICAL D10_ROW TABLE_5_HEAD
WLAN UART
h
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
TABLE_5_ITEM
55 53 OUT UART_WLAN_TO_AP_RXD
TABLE_5_ITEM
.c
131S0893 1 CAP,CER,0.2PF,+/-0.05,01005 C7706_RF CRITICAL D10_ROW TABLE_5_ITEM
55 53 IN UART_AP_TO_WLAN_TXD
TABLE_5_ITEM
55 53 IN UART_AP_TO_WLAN_RTS_L
TABLE_5_ITEM
w
TRUE
BLUETOOTH UART
TABLE_5_ITEM
TABLE_5_ITEM
w
55 53 IN
TABLE_5_ITEM
117S0161 TRUE
1 RES,MF,0 OHM,1/32W,01005 R6711_RF CRITICAL D10_ROW
B 152S1853 TRUE
1 IND,9.1NH,UH-Q,01005 C6729_RF CRITICAL D10_ROW
TABLE_5_ITEM
152S2054
TRUE
1 IND,9.1NH,UH-Q,0201 C6729_RF CRITICAL D11_ROW
TABLE_5_ITEM
55
55
53 OUT
53 IN
UART_BT_TO_AP_RXD
UART_AP_TO_BT_RTS_L
B
117S0161
152S2043
TRUE
1
1 RES,MF,0 OHM,1/32W,01005
IND,6.2NH,UH-Q,01005
R7700_RF
C7702_RF
CRITICAL
CRITICAL
D10_ROW
D10_ROW
TABLE_5_ITEM
TABLE_5_ITEM
117S0161
117S0161
1
1
w
RES,MF,0 OHM,1/32W,01005
RES,MF,0 OHM,1/32W,01005
R7700_RF
L7700_RF
CRITICAL
CRITICAL
D11_ROW
D11_ROW
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
55 53 OUT UART_BT_TO_AP_CTS_L
AOP
TABLE_5_ITEM
55 53 IN AOP_TO_WLAN_CONTEXT_B
TABLE_5_ITEM
TABLE_5_ITEM
D101_WIFI: COEX
D111_WIFI:
TABLE_5_HEAD
55 53 OUT UART_WLAN_TO_BB_COEX
131S0648 1 CAP,CER,0.3PF,+/-0.05,01005 C7705_RF CRITICAL D101 PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
ANTENNA
TABLE_5_ITEM TABLE_5_ITEM
3 IO
50_UAT_WLAN_5G_WEST
131S0893 1 CAP,CER,0.2PF,+/-0.05,01005 C7706_RF CRITICAL D101 152S1976 1 IND,0.7NH,UH-Q,01005 R7711_RF CRITICAL D111
3 IO
50_UAT_WLAN_2G_EAST
TABLE_5_ITEM TABLE_5_ITEM
117S0161 1 RES,MF,0 OHM,1/32W,01005 R7711_RF CRITICAL D101 131S0400 1 CAP,CER,3.5PF+/-0.1,01005 R7702_RF CRITICAL D111 3 IO
50_LAT_WLAN_5G_EAST
TABLE_5_ITEM
TRUE TABLE_5_ITEM
2 IO
50_LAT_WLAN_G_1
117S0161 1 RES,MF,0 OHM,1/32W,01005 R7702_RF CRITICAL D101 152S1986 1 IND,FILM,2.2NH,UH-Q,01005 R7704_RF CRITICAL D111
2 IO
50_LAT_WLAN_A_1
TRUE TABLE_5_ITEM
TRUE TABLE_5_ITEM
152S1988 1 IND,2.4NH,UH-Q,01005 R7704_RF CRITICAL D101 118S0724 1 RES,MF, 0 OHM,1/20W, 0201 R6711_RF CRITICAL D111 3 IO
50_UAT2_M
TRUE TABLE_5_ITEM
TRUE TABLE_5_ITEM
A 131S0648 1
TRUE
CAP,CER,0.3PF,+/-0.05PF,01005 C7708_RF CRITICAL D101
TABLE_5_ITEM
152S2054 1 IND,9.1NH,UH-Q,0201 C6729_RF CRITICAL D111
TABLE_5_ITEM
SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
118S0724 1 RES,MF, 0 OHM,1/20W, 0201 R6711_RF CRITICAL D101 117S0161 1 RES,MF,0 OHM,1/32W,01005 R7700_RF CRITICAL D111 PAGE TITLE
152S2054
TRUE
1 IND,9.1NH,UH-Q,0201 C6729_RF CRITICAL D101
TABLE_5_ITEM
spare
DRAWING NUMBER SIZE
TABLE_5_ITEM TABLE_5_ITEM
117S0161 1 RES,MF,0 OHM,1/32W,01005 R7700_RF CRITICAL D101 152S1853 1 IND,9.1NH,UH-Q,01005 L7701_RF CRITICAL D111
TRUE TABLE_5_ITEM TABLE_5_ITEM
152S2043 1 IND,6.2NH,UH-Q,01005 L7701_RF CRITICAL D101 131S0893 1 CAP,CER,0.2PF,+/-0.05PF,01005 C7729_RF CRITICAL D111 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
TABLE_5_ITEM
C7700_RF, C7703_RF,C7704_RF CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST IV ALL RIGHTS RESERVED 6 OF 81
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
WIFI/BT
1 106
4 WLAN_RF 107
D 6 LBEE5W11GJ-943
LGA
108 D
2 1 PP1V8_SDRAM PP_VDD_MAIN 1
18 SYM 2 OF 2
109
21 110
1 C7600_RF 1 C7601_RF 1 C7602_RF 1 C7606_RF 1 C7607_RF 24 111
27PF 0.01UF 10UF 0.01UF 27PF
5% 10% 20% 10% 5% 27 112
2 16V
NP0-C0G
6.3V
2 X5R 2 6.3V
CERM-X5R 2 6.3V
X5R 2 16V
NP0-C0G 32 113
01005 01005 0402-9 01005 01005
WLAN WLAN WLAN WLAN 34 114
VDDIO_1P8V 15
VBAT_VCC 28
VBAT_VCC 29
VBAT_RF_VCC 30
VBAT_RF_VCC 31
36 115
45 116
46 117
55 54 53 PMUGPIO_TO_WLAN_CLK32K 54 LPO_IN 47 118
IN
48 119
UART_BB_TO_WLAN_COEX 8 SECI_RX GND
54 53 IN 49 120
UART_WLAN_TO_BB_COEX 7 SECI_TX
54 53 OUT 50 121
51 122
PP1V8_SDRAM
WLAN_RF BT_DEV_WAKE 55 AP_TO_BT_WAKE IN 53 54 55
53 123
1 PMU_TO_WLAN_REG_ON 92 WL_REG_ON LBEE5W11GJ-943 57 124
R7600_RF 54 53
55 IN
10K LGA 58 125
5% 93 BT_REG_ON SYM 1 OF 2 60 126
1/32W 55 54 53 IN
PMU_TO_BT_REG_ON
MF 41 65 127
01005
2 WLAN BT_UART_RXD UART_AP_TO_BT_TXD IN 53 54 55
m
OUT 53 54
BT_PCM_IN 39 I2S_AP_TO_BT_DOUT 53 54
135
IN
55 54 53 UART_WLAN_TO_AP_RXD 11 FAST_UART_TX 74 136
OUT
10 FAST_UART_RX 75 137
o
55 54 53 IN UART_AP_TO_WLAN_TXD
76 138
77 139
.c
UART_WLAN_TO_AP_CTS_L 9 FAST_UART_RTS_OUT
54 53 OUT 78 140
79 141
UART_AP_TO_WLAN_RTS_L 12 FAST_UART_CTS_IN
54 53 IN 80 142
x
55 54 53 AP_TO_WLAN_DEVICE_WAKE 13 WL_DEV_WAKE WL_HOST_WAKE 14 WLAN_TO_PMU_HOST_WAKE 53 54 55
81 143
IN OUT
82 144
fi
83 145
55 54 53 BT_TO_PMU_HOST_WAKE 56 BT_HOST_WAKE PCIE_CLKREQ* 17 PCIE_WLAN_BI_AP_CLKREQ_L 53 54
84 146
OUT BI
a
PCIE_PERST* 16 PCIE_AP_TO_WLAN_RESET_L 53 54 55
85 147
IN
86 148
in
56 50_WLAN_G_0 52 2G_ANT_CORE0 87 THRM_PAD 149
BI
1 50_LAT_WLAN_G_1 5 2G_ANT_CORE1 PCIE_RDP 19 90_PCIE_AP_TO_WLAN_TXD_P 53 54 55
88 150
IO IN
PCIE_RDN 20 90_PCIE_AP_TO_WLAN_TXD_N 53 54 55
89 151
IN
59 5G_ANT_CORE0 90 152
h
56 BI 50_WLAN_A_0 22
66 5G_ANT_CORE1 PCIE_TDP 90_PCIE_WLAN_TO_AP_RXD_P OUT 53 54
91 153
1 IO
50_LAT_WLAN_A_1 23
PCIE_TDN 90_PCIE_WLAN_TO_AP_RXD_N OUT 53 54
94 154
.c
PCIE_REFCLK_P 25 90_PCIE_AP_TO_WLAN_REFCLK_P 53 54 55
95 155
IN
PCIE_REFCLK_N 26 90_PCIE_AP_TO_WLAN_REFCLK_N 96 156
IN 53 54 55 C7604_RF
7.5UF 97 157
63
w
CXT_A/JTAG_TDI AOP_TO_WLAN_CONTEXT_A 53 54 55 20% 98 158
3
IN
L7600_RF 4V
CXT_B/JTAG_TDO AOP_TO_WLAN_CONTEXT_B IN 55 2.2UH-20%-0.68A-0.25OHM CERM 99 159
0402
w
SR_VLX 33 SR_LVX 1 2 SR_LVX_1 1 3 100 160
B VIN_LDO 35 VIN_LDO
0806
2 4
101 161 B
102 162
w 1 C7603_RF
100PF
5%
103
104
105
163
2 16V
NP0-C0G
01005
WLAN
PP7600_RF PP7610_RF
P2MM-NSM OMIT P2MM-NSM OMIT
SM SM TABLE_ALT_HEAD
2 1 AOP_TO_WLAN_CONTEXT_A 1 2 1 PMUGPIO_TO_WLAN_CLK32K 1 PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
PP PP
TDI PART NUMBER
PP7601_RF PP7611_RF TABLE_ALT_ITEM
P2MM-NSM OMIT P2MM-NSM OMIT 339S00201 339S00199 ALTERNATE WLAN_RF ALT WIFI/BT MODULE
SM SM
2 1 AOP_TO_WLAN_CONTEXT_B 1 2 1 WLAN_TO_PMU_HOST_WAKE 1
PP PP
TDO
PP7612_RF
P2MM-NSM OMIT
SM
2 1 90_PCIE_AP_TO_WLAN_REFCLK_P 1
PP
PP7603_RF PP7613_RF
P2MM-NSM OMIT P2MM-NSM OMIT
SM SM
2 1 UART_WLAN_TO_AP_RXD 1 2 1 90_PCIE_AP_TO_WLAN_REFCLK_N 1
PP PP
PP7604_RF PP7614_RF
P2MM-NSM OMIT P2MM-NSM OMIT
SM SM
2 1 UART_AP_TO_WLAN_TXD 1 2 1 90_PCIE_AP_TO_WLAN_TXD_P 1
PP PP
A PP7606_RF
P2MM-NSM OMIT
PP7616_RF
P2MM-NSM OMIT
PP7621_RF
P2MM-NSM OMIT
SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
SM SM SM PAGE TITLE
1 1 1
2 JTAG_WLAN_TMS PP 2 1 PCIE_AP_TO_WLAN_RESET_L PP 2 1 UART_BT_TO_AP_RXD PP
spare
PP7607_RF PP7617_RF PP7622_RF DRAWING NUMBER SIZE
P2MM-NSM OMIT P2MM-NSM OMIT P2MM-NSM OMIT
2 JTAG_WLAN_TRST_L 1
SM
2 JTAG_WLAN_SEL
SM
1 2 1 UART_AP_TO_BT_RTS_L
SM
1 Apple Inc. 051-00419 D
PP PP PP
REVISION
PP7608_RF
P2MM-NSM OMIT
PP7618_RF
P2MM-NSM OMIT
PP7623_RF
P2MM-NSM OMIT
R
8.0.0
1
SM SM
1
SM
1 NOTICE OF PROPRIETARY PROPERTY: BRANCH
2 1 AP_TO_WLAN_DEVICE_WAKE PP 2 1 PMU_TO_WLAN_REG_ON PP 2 1 UART_BT_TO_AP_CTS_L PP
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
PP7609_RF PP7619_RF PP7624_RF THE POSESSOR AGREES TO THE FOLLOWING: PAGE
P2MM-NSM OMIT P2MM-NSM OMIT P2MM-NSM OMIT
2 1 BT_TO_PMU_HOST_WAKE 1
SM
2 1 PMU_TO_BT_REG_ON
SM
1 2 1 AP_TO_BT_WAKE
SM
1
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
6 OF 53
PP PP PP
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 6 OF 81
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
WIFI UPPER ANTENNA FEEDS OMIT_TABLE
D
R7704_RF
2.4NH+/-0.1NH-0.370A
55 BI
50_WLAN_G_0 1 2 50_UAT_WLAN_2G_EAST BI 53
54
2GHZ UAT
01005
1 C7707_RF 1 C7708_RF
0.2PF 0.6PF
+/-0.1PF +/-0.05PF
16V
2 NP0-C0G 16V
2 CERM
01005 01005
WLAN_UP_RFFE WLAN_UP_RFFE
NOSTUFF OMIT_TABLE
OMIT_TABLE
R7703_RF
1
0.00 2
50_WLAN_A_0 50_LAT_WLAN_5G_EAST
55 BI
0%
BI 53
54 5GHZ UAT
1 C7705_RF 1/32W 1 C7706_RF
MF
0.2PF 01005 0.2PF
+/-0.1PF +/-0.1PF
2 16V 16V
2 NP0-C0G
NP0-C0G
01005 01005
WLAN_UP_RFFE WLAN_UP_RFFE
OMIT OMIT
C C
m
JUAT2_RF
MM8830-2600B
o
F-RT-SM
W5BPF_RF
OMIT_TABLE 5.15-5.85GHZ-1.2DB OMIT_TABLE
.c
R7711_RF LFB185G53CGZE200 R7702_RF
1
0.00 2 1 3 1
0.00 2 1 2
54 53 BI
50_UAT_WLAN_5G_WEST 50_UAT_WLAN_5G_BPF 50_UAT2_BPF 50_UAT2_TEST 50_UAT2_M 1
C R
0% 0%
1/32W 1 C7709_RF 1/32W 1 C7710_RF
x
2
MF MF
1 C7729_RF 01005 1 C7711_RF 0.2PF 01005 0.2PF GND
+/-0.1PF +/-0.1PF
0.2PF 0.2PF 2 16V
16V
fi
+/-0.1PF +/-0.1PF NP0-C0G 2 NP0-C0G
3
UP_RFFE
2 16V
NP0-C0G 2 16V
NP0-C0G
01005
WLAN_UP_RFFE
01005
WLAN_UP_RFFE
01005 01005 OMIT OMIT
WLAN_UP_RFFE WLAN_UP_RFFE
a
OMIT OMIT
in
h
.c
w
w
B B
w
A SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
spare
DRAWING NUMBER SIZE
D D
STOCKHOLM_MLB
JUNE 9, 2016
58 53 PP_VDD_MAIN
58 53 IN PP1V8_SDRAM
58 53 IN PMU_TO_NFC_EN
C
NFC_TO_PMU_HOST_WAKE
C
m
58 53 OUT
58 53 IN AP_TO_NFC_DEV_WAKE
58 53 IN AP_TO_NFC_FW_DWLD_REQ
o
58 53 OUT NFC_TO_BB_CLK_REQ
58 53 IN BB_TO_NFC_CLK
.c
58 53 IN UART_AP_TO_NFC_TXD
58 53 OUT UART_NFC_TO_AP_RXD
UART_AP_TO_NFC_RTS_L
x
58 53 IN
58 53 OUT UART_NFC_TO_AP_CTS_L
fi
2 IO
NFC_SWP
58 53 IN SE2_READY
a
58 53 IN SE2_PWR_REQ
58 53 IN SE2_PRESENT
in
58 53 OUT NFC_SWP_MUX
58 53 OUT ICEFALL_LDO_ENABLE
h
.c
ALTERNATES
w
PART NUMBER ALTERNATE FOR REFERENCE DESIGNATOR(S) DESCRIPTION BOM OPTION
PART NUMBER
w
B 132S0436 132S0400 C7504_RF 0.22UF 20% 6.3V 01005 ? B
w
BOM OPTIONS
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
TABLE_5_HEAD
TABLE_5_HEAD
TABLE_5_ITEM
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
TABLE_5_ITEM
131S00081 1 270PF, 0201 2% 25V C7514_RF D111
131S00055 1 22PF, 0201 2% 50V C7512_RF D101 TABLE_5_ITEM
TABLE_5_ITEM
131S00118 1 180PF, 0201 2% 50V C7518_RF D111
131S00117 1 120PF, 0201 2% 50V C7518_RF D101 TABLE_5_ITEM
TABLE_5_ITEM
131S00033 1 680PF, 0201 2% 50V C7516_RF D111
131S00026 1 820PF, 0201 2% 50V C7516_RF D101 TABLE_5_ITEM
TABLE_5_ITEM
131S00081 1 270PF, 0201 2% 25V C7514_RF D11_JP
131S0883 1 220PF, 0201 2% 50V C7514_RF D10_JP TABLE_5_ITEM
TABLE_5_ITEM
131S0731 1 100PF, 0201 2% 50V C7518_RF D11_JP
131S00055 1 22PF, 0201 2% 50V C7512_RF D10_JP TABLE_5_ITEM
TABLE_5_ITEM
131S00033 1 680PF, 0201 2% 50V C7516_RF D11_JP
131S00019 1 150PF, 0201 2% 50V C7518_RF D10_JP TABLE_5_ITEM
TABLE_5_ITEM
131S00081 1 270PF, 0201 2% 25V C7514_RF D11_ROW
131S0825 1 560PF, 0201 2% 50V C7516_RF D10_JP TABLE_5_ITEM
TABLE_5_ITEM
131S00118 1 180PF, 0201 2% 50V C7518_RF D11_ROW
131S0883 1 220PF, 0201 2% 50V C7514_RF D10_ROW TABLE_5_ITEM
TABLE_5_ITEM
131S00033 1 680PF, 0201 2% 50V C7516_RF D11_ROW
131S00055 1 22PF, 0201 2% 50V C7512_RF D10_ROW
TABLE_5_ITEM
spare
DRAWING NUMBER SIZE
FAN48614BUC50X
2 PP_VDD_MAIN_NFC A3 VIN VOUT A1 VDD_NFC_5V 2
L7502_RF VOUT A2
D
1 C7521_RF
100PF
1 C7511_RF
15UF 1
1.8UH-0.7A
2 NFC_BOOST_SW
B1 SW
B2 SW
1 C7517_RF
15UF
1 C7522_RF
100PF
D
5% 20% 20% 5%
16V
2 NP0-C0G 6.3V
2 X5R 0603 6.3V
2 X5R 16V
2 NP0-C0G
NFC 2 NFC_BOOST_EN B3 EN
01005 0402-1 0402-1 01005
C1 PGND
C2 PGND
C3 AGND
NFC NFC NFC NFC
2 VDD_NFC_5V
1 C7520_RF
1UF
20%
VUP G2
C6
C7
ESE_VDD C5
AVDD D7
D3
B5
SVDD B7
TVDD E7
01005 1UF 1UF 0.22UF 20% 560
NFC 20% 20% 20% 10V
2 X5R 2 NFC_RXP 1 2 NFC_RXP_CAP 1 2
10V
2 X5R 10V
2 X5R 6.3V
2 X5R
VDD
VBAT
SIM_PMU_VCC
PVDD
0201 1%
0201 0201 01005 NFC 2% 1/20W
NFC NFC NFC 25V MF
C0G-NP0 201
0201 NFC
NFC
L7500_RF
160NH-10%-0.48A-0.33OHM
C C
m
NFC_RF NFC_TXP 1 2 NFC_BALP
IC00 F1 2
PN67VEU3-B001D004 NC 0402
58 57 53 NFC_TO_PMU_HOST_WAKE D1 IRQ UFLGA SIM_SWIO A4 NFC_SWP 53 57
NFC 1 C7509_RF
BAL0 2
GND 1
o
OUT BI
57 53 SE2_PRESENT A5 SVDD_REQ GPIO0 A7 NFC_TEST_OUT 2
680PF
IN 2%
AP_TO_NFC_FW_DWLD_REQ B2 DWL IC01 A6 25V
2 C0G-NP0
57 53 IN NC
.c
NFC_TO_BB_CLK_REQ A2 CLK_REQ TX_PWR_REQ D5 NFC_BOOST_EN 0201
ATB161006F-20011
57 53 OUT 2
NFC
BB_TO_NFC_CLK A3 NFC_CLK_XTAL1
ESE_DWPM_DBG G7
57 53 IN
BALUN_RF
UART_AP_TO_NFC_TXD C1 RX NC 180 PHASE SHIFT INTRODUCED BY BALUN
ESE_DWPS_DBG G6
58 57 53 IN
x
B1
SM
58 57 53 UART_NFC_TO_AP_RXD TX NC DONE FOR BEST ROUTING
OUT
58 57 53 UART_AP_TO_NFC_RTS_L D2 CTS RX+ F6 NFC_RXP 2
IN
fi
58 57 53 UART_NFC_TO_AP_CTS_L A1 RTS RX- F5 NFC_RXN 2
OUT
4 UNBAL
PMU_TO_NFC_EN E1 VEN
3 BAL1
TX1 G3
58 57 53 IN
NFC_TXP 2
L7501_RF
a
2 VDD_NFC_ESE E3 SMX_RST* TX2 G5 NFC_TXN 2
C7514_RF
160NH-10%-0.48A-0.33OHM 220PF
E4 SMX_CLK TP7500_RF
NC WKUP_REQ E5 AP_TO_NFC_DEV_WAKE NFC_TXN 1 2 NFC_BALN NFC_ANT_MATCH 1 2 NFC_ANT 1
in
F4 ESE_IO1 IN 53 57 58 2
A
0402 SM-TP1P25-TOP
B3
57 53 IN
SE2_READY SE2_BUSY VMID F7 NFC_VMID NFC 1 C7510_RF 2%
50V 1 C7515_RF 1 C7516_RF 1 C7518_RF OMIT
ICEFALL_LDO_ENABLE B4 IC2 680PF C0G
SE2_ENABLE F2
57 53 OUT
SE2_PWR_REQ 2% 0201 1000PF 820PF 120PF
E6 OUT 53 57 58
25V OMIT_TABLE 2% 2% 2%
h
NFC_SWP_MUX EXT_MUX 2 C0G-NP0
SE2_SVDD_IN G1
57 53 OUT
PP1V8_SDRAM 53 57 58
25V
2 C0G-NP0 25V
2 C0G-NP0 50V
2 NP0-C0G
IN 0201
C3 XTAL2 C7508_RF NFC C7512_RF 0201 0201 0201
NC R7509_RF NFC NFC OMIT_TABLE
.c
1000PF 22PF
B6 DVSS
C4 DVSS
D4 AVSS
D6 AVSS
F3 AVSS
C2 PVSS
G4 TVSS
560 OMIT_TABLE
E2 VSS
w
C0G-NP0 201 C0G-CERM
01005 0201 NFC 0201 TP7505_RF
NFC NFC OMIT NFC_TEST_OUT 1
2
A
TP-P55
w
NFC
B 2 1 SE2_PWR_REQ
OMIT
B
1
R7599_RF
1.00K
5%
1/32W
MF
w
2 01005
B1
PP7505_RF PP7509_RF
P2MM-NSM P2MM-NSM
SM SM
2 1 UART_AP_TO_NFC_RTS_L 1 PP 2 1 AP_TO_NFC_DEV_WAKE 1 PP
OMIT OMIT R7520_RF
0.00
PP7506_RF 2 1 PP_VDD_MAIN 1 2 PP_VDD_MAIN_NFC 2
P2MM-NSM
A
SM 1%
2 1 UART_NFC_TO_AP_CTS_L 1 PP
OMIT
1/20W
MF
0201
SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
NOSTUFF
spare
DRAWING NUMBER SIZE
D
D10 RADIO_MLB_FF D
m
EAST MLB MCEW_RF WEST MLB
FLTPSSL-382E
o
3 SM
7
UPPER MLB MCNS_RF LOWER MLB IO
INOUT
50_UAT_WLAN_2G_EAST
1
SIGNAL1-E SIGNAL1-W
10
50_UAT_WLAN_2G_WEST 1
.c
FLTPSSL-381E IO
50_LAT_WLAN_5G_EAST SIGNAL2-E SIGNAL2-W 50_UAT_WLAN_5G_WEST IO
SM INOUT 50_UAT1_EAST 5 SIGNAL3-E SIGNAL3-W 11 50_UAT1_WEST INOUT
50_UAT1_EAST 6 SIGNAL1-U SIGNAL1-L 7 50_UAT_MB_HB_SOUTH
59 BI IO INOUT
59 BI OUT 53 INOUT
1 50_LAT_WLAN_NORTH 2 SIGNAL2-U SIGNAL2-L 11 50_LAT_WLAN_SOUTH 1
2 23 INOUT
x
53 50_UUAT_LB_MLB_NORTH 4 SIGNAL3-U SIGNAL3-L 9 50_UAT_LB_MLB_SOUTH 4 24
IN IO
6 25
1 33
fi
8 GND 26
3 34
9 GND 27
5 35
GND 12 28
a
8 36
21
10 37
22
in
12 38
GND GND
21 TRUE TRUE
I11 I12
22
23
h
24 GND
25
.c
26
27
R6711_RF
3.9PF
28 50_UAT_WLAN_2G_WEST 1 2 50_UAT_WLAN_2G_WEST_PLEXER
w
1 IO
29 INOUT
+/-0.1PF INOUT
30 16V
NP0-C0G
w
31 01005-1
B UP_RFFE 1
B
COAX
32
W2BPF_RF
WLAN-BT-LTE
885118
TRUE
LGA C7701_RF
L7700_RF 3.6PF
1 0.00 1 1 INPUT
IO
50_LAT_WLAN_G_1 1 2 50_WLAN_G_1_BPF OUTPUT 4 50_WLAN_G_1_M 1 2 50_WLAN_G_1_DPLX JLAT3_RF
0% MM7829-2700
1/32W 1 GND +/-0.1PF W25DI_RF F-ST-SM
MF 1 16V 1 LFD212G45MP2E013
01005 WLAN_RFFE NP0-C0G 2
01005 LGA
2
3
5
WLAN_RFFE
OMIT L7701_RF WLAN_RFFE L7703_RF R7701_RF
L7702_RF 0.00 2
9.1NH-3%-0.17A-1.7OHM 9.1NH-3%-0.17A-1.7OHM 4.0NH-+/-0.1NH-0.27A 4 P1 P3 2 50_LAT_WLAN_M 1 50_LAT_WLAN_NORTH 1 1 50_LAT_WLAN_SOUTH 1
01005 01005 01005
OMIT WLAN_RFFE WLAN_RFFE 0%
6 P2 1/32W
1 C7703_RF MF 1 C7704_RF 3
2 GND 01005
2 2 0.2PF WLAN_RFFE 0.2PF
WLAN_RFFE +/-0.1PF OMIT +/-0.1PF
2 16V
16V
1
3
5
NP0-C0G 2 NP0-C0G
01005 01005
R7700_RF WLAN_RFFE WLAN_RFFE
0.00 2 OMIT OMIT
IO
50_LAT_WLAN_A_1 1 50_WLAN_A_1_DPLX
0%
1 C7700_RF
0.2PF
1/32W
MF
01005
1 THROUGH METROCIRC
A +/-0.1PF
16V
2 NP0-C0G
WLAN_RFFE
OMIT
C7702_RF SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
01005 4.3NH-3%-0.270A PAGE TITLE
WLAN_RFFE
OMIT
01005
WLAN_RFFE
OMIT
spare
DRAWING NUMBER SIZE
2
Apple Inc. 051-00419 D
REVISION
R
8.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
2 BB_TO_UAT_SCLK
1 C5904_RF
120PF
10%
10V
2 CER-X7R PLEASE CONTACT ANTENNA (MATT MOW)
53 IN
BB_TO_LAT_ANT_DATA
1 C5909_RF
33PF
5%
2 16V
C C
m
NP0-C0G-CERM
01005
o
LB/MLB/GNSS/MB/HB
.c
STANDOFF
x
fi
PP3V0_TRISTAR_ANT_PROX
2
a
1 C6720_RF
0.01UF
10%
in
2 6.3V
X5R
01005
R6706_RF SUAT1_RF
L8007_RF
C6716_RF 560NH-5%-2.80OHM
C6704_RF 2.2NH+/-0.1NH-0.6A STDOFF-2.56OD1.4ID.99H-SM
h
18PF 1 2
PP3V0_TRISTAR_ANT_PROX
1
0.00 2 1 2 50_UAT1_NOTCH 1 2 50_UAT1_FEED
USPDT_VDD 2
IO
50_UAT1_TUNER 50_UAT1_TUNER_M 1
0201
0201-1
.c
1%
1/20W
MF
1 UP_RFFE 2%
25V UP_RFFE 1 C8007_RF
0201 C0H-CERM 0.01UF
0201 10%
UP_RFFE
C6714_RF 1
4
UP_RFFE 2 6.3V
X5R
VDD 5.6NH+/-3%-0.4A
w
01005
USPDT2_RF 0201 1 C6700_RF L6707_RF
RF1341 1.2PF
+/-0.05PF 9.1NH+/-0.3%-0.3A
w
WLCSP 2 2 25V 0201
B 53 BB_BUFFER_GPO2 3 CB 1 USPDT2_RF C0G-CERM UP_RFFE
B
4
IN 0201
RF1 6 VDD
2
1
5%
C6721_RF
33PF GNDA RFGND
w USPDT_RF
RF1341
L8008_RF
3.0NH+/-0.1NH-0.6A
5
2 16V
NP0-C0G-CERM 3 CB
WLCSP
1 1 2
01005 53 IN
BB_BUFFER_GPO1 USPDT_RF DC_BLOCK
RF1 6 0201
1 C8005_RF GNDA RFGND
5%
33PF 1 C8008_RF
2
16V
2 NP0-C0G-CERM 18PF
2%
01005 2
25V
C0H-CERM
0201
ALT_GND 1 TP8000_RF
A
SM-TP1P25-TOP
OMIT
5G WIFI
UAT GROUND RING STANDOFF
1
OMIT_TABLE
L8009_RF
9.1NH-0.4A
C7731_RF SUAT2_RF
STDOFF-2.56OD1.4ID.99H-SM
03015
1.2PF
IO
50_UAT2_M 1 2 50_UAT2_FEED 1 2 PP8000_RF
P2MM-NSM
SM
+/-0.05PF UP_RFFE 2 CHASSIS_GND 1
2 CHASSIS_GND 25V 1 1 PP
C0G-CERM
0201 NOSTUFF
1 C6734_RF 1 C6735_RF 1 C6730_RF 1 C6731_RF 1 C6732_RF 1 C6733_RF 1 C7730_RF L7709_RF
1.8NH+/-0.1NH-0.8A 3.0NH+/-0.1NH-0.6A
A 5%
100PF
5%
18PF
5%
220PF
5%
56PF 4.0PF
+/-0.1PF 5%
220PF NOSTUFF 0201 0201
A
2 16V
NP0-C0G 2 16V
CERM 2 6.3V
CERM 2 16V
NP0-C0G 2 16V
NP0-C0G 2 6.3V
CERM L6710_RF SGND_RF
SYNC_MASTER=Sync
PAGE TITLE
SYNC_DATE=05/17/2016
2
UP_RFFE Apple Inc. 051-00419 D
REVISION
R
8.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
BOM LIST
TABLE_5_HEAD
D D
C C
m
o
.c
x
fi
a
in
h
.c
w
w
B B
w
A SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
spare
DRAWING NUMBER SIZE
MAV16 RADIO_MLB
8 0006400877 ENGINEERING RELEASED 2016-06-14
AP CONNECTIONS
LAST_MODIFICATION=Wed Jun 8 12:54:09 2016 POWER D
D 81 77 65 64 53 IN PP_VDD_MAIN
63
64
<CSA_PAGE2>
<CSA_PAGE3>
BOM_OMIT_TABLE
PMU: CONTROL AND CLOCKS
<SYNC_MASTER2>
<SYNC_MASTER3>
<SYNC_DATE2>
<SYNC_DATE3>
65 OUT
AMUX
BBPMU_TO_PMU_AMUX1
DEBUG
81 67 53 IN SWD_AP_TO_MANY_SWCLK
<CSA_PAGE4> <SYNC_DATE4> 65 OUT BBPMU_TO_PMU_AMUX2
65 PMU: SWITCHERS AND LDOS <SYNC_MASTER4>
65 OUT BBPMU_TO_PMU_AMUX3
20 6 IO
SWD_AOP_BI_BB_SWDIO
<CSA_PAGE5> <SYNC_DATE5> 81 78 64 53 IN PMU_TO_BB_USB_VBUS_DETECT
66 BASEBAND: POWER2 <SYNC_MASTER5> 90_USB_BB_DATA_P
67 <CSA_PAGE6>
<CSA_PAGE7>
BASEBAND: CONTROL <SYNC_MASTER6>
<SYNC_DATE6>
<SYNC_DATE7> 81 78 64 53 IN
BB CONTROL
AP_TO_BBPMU_RADIO_ON_L
20 17 6
20 17 6
IO
IO 90_USB_BB_DATA_N
81
64 53 IN
64 53 IN
PMU_TO_BBPMU_RESET_L
AP_TO_BB_RESET_L
15
ANTENNA
50_UAT_WLAN_2G_WEST_PLEXER
IO
<CSA_PAGE9> <SYNC_DATE9> 78 68 53 OUT BB_TO_AP_RESET_DETECT_L
70 TRANSCEIVER0/1: TX PORTS <SYNC_MASTER9>
78 68 53 OUT BB_TO_STROBE_DRIVER_GSM_BURST_IND
14 IO
50_UAT1_WEST
<CSA_PAGE10> <SYNC_DATE10> 12 50_UAT_LB_MLB_SOUTH
71 TRANSCEIVER0/1: PRX PORTS <SYNC_MASTER10> 68 53 IN AP_TO_BB_MESA_ON
12
IO
50_UAT_MB_HB_SOUTH
IO
<CSA_PAGE11> <SYNC_DATE11> 78 68 53 IN AP_TO_BB_TIME_MARK
72 RECEIVE MATCHING <SYNC_MASTER11>
78 68 53 IN AP_TO_BB_COREDUMP
14 IO
50_UUAT_LB_MLB_NORTH
<CSA_PAGE12> <SYNC_DATE12>
73 LOWER ANTENNA & COUPLERS <SYNC_MASTER12> 64 53 IN LCM_TO_MANY_BSYNC
<CSA_PAGE13> <SYNC_DATE13> 68 53 IN AP_TO_BB_IPC_GPIO1
74 DIVERSITY RECEIVE ASM'S <SYNC_MASTER13>
75 <CSA_PAGE14>
DIVERSITY RECEIVE LNA'S <SYNC_MASTER14>
<SYNC_DATE14>
78 67 53 IN
PCIE
90_PCIE_AP_TO_BB_REFCLK_P
<CSA_PAGE15> <SYNC_DATE15>
76 UPPER ANTENNA FEEDS <SYNC_MASTER15> 78 67 53 IN 90_PCIE_AP_TO_BB_REFCLK_N
<CSA_PAGE16> <SYNC_DATE16> 90_PCIE_AP_TO_BB_TXD_P
77 PMU: ET MODULATOR <SYNC_MASTER16> 67 53 IN
C C
m
67 53 IN 90_PCIE_AP_TO_BB_TXD_N
<CSA_PAGE17> <SYNC_DATE17>
78 TEST POINTS & BOOT CONFIG <SYNC_MASTER17> 67 53 OUT 90_PCIE_BB_TO_AP_RXD_P
<CSA_PAGE18> <SYNC_DATE18> 90_PCIE_BB_TO_AP_RXD_N
79 TDD TRANSMIT <SYNC_MASTER18> 67 53
o
68 64 53 IN PCIE_AP_TO_BB_RESET_L
<CSA_PAGE19> <SYNC_DATE19>
80 FDD TRANSMIT <SYNC_MASTER19> 7 IO
PCIE_BB_BI_AP_CLKREQ_L
.c
<CSA_PAGE20> <SYNC_DATE20> 78 68 53 OUT BB_TO_PMU_PCIE_HOST_WAKE_L
<SYNC_MASTER20>
<CSA_PAGE21>
<SYNC_MASTER21>
<SYNC_DATE21>
68 53 IN
AOP
UART_AOP_TO_BB_TXD
x
<CSA_PAGE22> <SYNC_DATE22>
<SYNC_MASTER22> 78 68 53 OUT UART_BB_TO_AOP_RXD
<CSA_PAGE23>
<SYNC_MASTER23>
<SYNC_DATE23>
AUDIO
fi
<CSA_PAGE24> <SYNC_DATE24> 68 53 IN I2S_BB_TO_AP_BCLK
<SYNC_MASTER24>
68 53 IN I2S_BB_TO_AP_LRCLK
a
<CSA_PAGE25> <SYNC_DATE25>
<SYNC_MASTER25> 68 53 IN I2S_AP_TO_BB_DOUT
<CSA_PAGE26> <SYNC_DATE26> 68 53 OUT I2S_BB_TO_AP_DIN
<SYNC_MASTER26>
WLAN
in
<CSA_PAGE27> <SYNC_DATE27>
<SYNC_MASTER27> UART_BB_TO_WLAN_COEX
81 78 68 53 IN
<CSA_PAGE28> <SYNC_DATE28>
<SYNC_MASTER28> 81 78 68 53 OUT UART_WLAN_TO_BB_COEX
h
<CSA_PAGE29>
<SYNC_MASTER29>
<SYNC_DATE29>
NFC
NFC_SWP
.c
81 53 IN
<CSA_PAGE30> <SYNC_DATE30>
<SYNC_MASTER30> 81 78 53 IN
NFC_SWP_MUX
81 78 53 OUT SE2_READY
81 78 53
AP_TO_ICEFALL_FW_DWLD_REQ
IN
w
81 78 53 IN
SE2_PWR_REQ
78 64 53 IN NFC_TO_BB_CLK_REQ
SCH: 951-00964
w
BB_TO_NFC_CLK
B B
78 64 53 OUT
81 53 OUT SE2_PRESENT
ICEFALL_LDO_ENABLE
w 81 78 53 IN
IO
BB_TO_UAT_DATA BB_TO_UAT_DATA 7 14
MAKE_BASE=TRUE
15 IO
50_UAT1_TUNER
BB_BUFFER_GPO1
ALTERNATES
68
68
53 OUT
OUT 7 17
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
PART NUMBER BB_TO_LAT_ANT_DATA BB_TO_LAT_ANT_DATA 7 17
IO
TABLE_ALT_ITEM
MAKE_BASE=TRUE
197S0565 197S0593 ALTERNATE Y5501_RF 19P2 MHZ XTAL
TABLE_ALT_ITEM
68 53 OUT
138S00101 138S00095 ALTERNATE ALL TRANSITION CAP
TABLE_ALT_ITEM
spare
DRAWING NUMBER SIZE
BOM OPTIONS:
LMBRF: NOLMBRF:
TABLE_5_HEAD TABLE_5_HEAD
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
TABLE_5_ITEM TABLE_5_ITEM
TABLE_5_ITEM TABLE_5_ITEM
152S2042 1 MLB PAD UAT OUTPUT MATCH R7106_RF CRITICAL LMBRF 155S00149 1 DCS/PCS RX FILTER GSMRX_RF CRITICAL NOLMBRF
TABLE_5_ITEM TABLE_5_ITEM
353S00627 1 MLB LNA MLBLN_RF CRITICAL LMBRF 152S2005 1 DCS/PCS RX MATCH (DCS) L6318_RF CRITICAL NOLMBRF
TABLE_5_ITEM TABLE_5_ITEM
117S0002 1 MLB LNA OUTPUT MATCH R6710_RF CRITICAL LMBRF 131S0319 1 DCS/PCS RX MATCH (DCS) C6332_RF CRITICAL NOLMBRF
TABLE_5_ITEM TABLE_5_ITEM
155S00139 1 PENTAPLEXER PPLXR_RF CRITICAL LMBRF 131S0630 1 DCS/PCS RX MATCH (DCS) C6340_RF CRITICAL NOLMBRF
TABLE_5_ITEM TABLE_5_ITEM
118S0643 1 RES,MF,4.99K OHM,01005 R7506_RF CRITICAL LMBRF 152S2005 1 DCS/PCS RX MATCH (DCS) L6319_RF CRITICAL NOLMBRF
TABLE_5_ITEM TABLE_5_ITEM
155S00193 1 FLTR,DIPLEXER,LB-MB-HB,DPX,SHIELD,0805 UATDI_RF CRITICAL LMBRF 131S0385 1 DCS/PCS RX MATCH (DCS) C6333_RF CRITICAL NOLMBRF
TABLE_5_ITEM TABLE_5_ITEM
155S00158 1 FLTR,DIPLEXER,LB-MB/HB,MIRROR,0805 UPPDI_RF CRITICAL LMBRF 131S0630 1 DCS/PCS RX MATCH (DCS) C6341_RF CRITICAL NOLMBRF
TABLE_5_ITEM TABLE_5_ITEM
337S00284 1 IC,SECURE ELEMENT,BCM20211,WLBGA25 SE2_RF CRITICAL LMBRF 155S00163 1 QUADPLEXER PPLXR_RF CRITICAL NOLMBRF
TABLE_5_ITEM TABLE_5_ITEM
138S0739 1 CAP,1UF,0201 C7201_RF CRITICAL LMBRF 155S00199 1 FLTR,DPX,PASS THRU,LB-MB-HB,SHLD,0805 UATDI_RF CRITICAL NOLMBRF
TABLE_5_ITEM TABLE_5_ITEM
138S0739 1 CAP,1UF,0201 C7528_RF CRITICAL LMBRF 155S00234 1 FLTR,DPX,PASS THRU,LB-MB-HB,UNSHLD,0805 UPPDI_RF CRITICAL NOLMBRF
TABLE_5_ITEM TABLE_5_ITEM
132S0316 1 CAP,0.1UF,01005 C7501_RF CRITICAL LMBRF 118S0724 1 RES,MF,0OHM,1/20W,0201 R6404_RF CRITICAL NOLMBRF
TABLE_5_ITEM TABLE_5_ITEM
138S0739 1 CAP,1UF,0201 C7523_RF CRITICAL LMBRF 152S2044 1 IND,2.2NH,+/-0.1NH,600MA,0201 R7104_RF CRITICAL NOLMBRF
TABLE_5_ITEM TABLE_5_ITEM
138S0739 1 CAP,1UF,0201 C7524_RF CRITICAL LMBRF 152S00157 1 1.2NH,+/-0.05NH,1.1A,UH-Q,0201 R6703_RF CRITICAL NOLMBRF
TABLE_5_ITEM TABLE_5_ITEM
138S00032 1 CAP,2.2UF,0201 C7529_RF CRITICAL LMBRF 131S0549 1 18PF,0201,25V R6708_RF CRITICAL NOLMBRF
TABLE_5_ITEM TABLE_5_ITEM
138S00032 1 CAP,2.2UF,0201 C7530_RF CRITICAL LMBRF 131S0445 1 CAP,CER,12PF,5%,25V,0201,HI-Q R6606_RF CRITICAL NOLMBRF
TABLE_5_ITEM
C C
m
118S0627 1 RES,10KOHM,01005 R7512_RF CRITICAL LMBRF
TABLE_5_ITEM
o
131S0630 1 CAP,CER,NPO/COG,27PF,2%,16V,01005 C6345_RF CRITICAL LMBRF TABLE_5_HEAD
.c
TABLE_5_ITEM
TABLE_5_ITEM
x
152S2006 1 IND,FILM,6.2NH,3%,400MA,UH-Q,0201 L6305_RF CRITICAL LMBRF
D11 SPECIFIC:
fi
TABLE_5_ITEM
a
TABLE_5_ITEM
TABLE_5_ITEM
in
TABLE_5_ITEM
h
118S0724 1 RES,MF,0OHM,1/20W,0201 R6703_RF CRITICAL LMBRF
TABLE_5_ITEM
.c
TABLE_5_ITEM
w
TABLE_5_ITEM
w
RES,MF,0OHM,1/20W,0201
B
118S0608
152S1356
1
1
RES,MF,1K OHM,1%,1/32W,01005
IND,10NH,3%,250MA,HI-Q,0201
R5911_RF
C6613_RF
CRITICAL
CRITICAL
LMBRF
LMBRF
TABLE_5_ITEM
TABLE_5_ITEM
w
A SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
spare
DRAWING NUMBER SIZE
BBPMU_RF BBPMU_RF D
D R5502_RF PMD9645 PMD9645
1.00K 2 WLNSP WLNSP
81 62 53 AP_TO_BB_RESET_L 1 58 52
IN AP_TO_BBPMU_RADIO_ON_L CBL_PWR* SYM 1 OF 5 OPT_1 PCIE PERST OPTION SYM 5 OF 5
1% MF
62 53
8178 IN NC 36 GND GND
1/32W 75 PON_1 CONTROL OPT_2 42 PP_VDD_MAIN PP_VDD_MAIN RADIO_PMIC
01005 RADIO_PMIC
1 4 16 20 46 GND
PMU_TO_BBPMU_RESET_L 43 RESIN* GND 98
HW_REV_ID R5505 R5501 REVISION R5504_RF
1
20.0K 2
RADIO_PMIC 62 53 IN
78
78 67 OUT PMIC_RESOUT_L 63
82
PON_RST*
PS_HOLD
BAT_ID_THERM 53
MAKE_BASE=TRUE 57
62
GND
GND
51.1K DEV1
PS_HOLD PS_HOLD_PMIC
0.10V 887K 67 IN
5%
1/32W
01005
MF 78 67 BI
SPMI_CLK
SPMI_DATA
25
31
SPMI_CLK
SPMI_DATA
GND 67
m
40.2K
1.10V 51.1K 82.5K EVT DOE 1%
1/32W
MF BBPMU_RF
1.20V 50.0K 100K 2 01005
o
EVT ALT/CARBON PMD9645
WLNSP
1.30V 39.0K 100K DEV6 13 26
.c
PMU_TO_BB_USB_VBUS_DETECT MPP_01 SYM 3 OF 5 GPIO_01
81 78 62 53 IN
GPIO_MPP NC
HW_REV1_ID 51 MPP_02 RADIO_PMIC GPIO_02 15 NFC_TO_BB_CLK_REQ 62
PCIE PERST OPTION
R5511_RF
IN 53 78
x
NC IN 53 62 68
fi
R5501_RF NC 53 62
1 IN
a
1/32W
MF
2 01005
in
h
.c
w
66 65 64 PP_1V8_LDO7
w
1
R5503_RF
B 1 C5501_RF
0.1UF 1%
100K Y5501_RF
19.2MHZ-10PPM-7PF-80OHM
B
20% 1/32W 2.0X1.6-SM
6.3V
2 X5R-CERM
01005
RADIO_PMIC
MF
01005
2 RADIO_PMIC 3
3
XTAL_19P2M_OUT
XO_THERM
1
4
3
2
XTAL_19P2M_IN 3
w BBPMU_RF
PMD9645
1 RADIO_PMIC
C5502_RF WLNSP
1000PF 78 67 XO_OUT_D0_EN 56 BB_CLK_EN SYM 2 OF 5 LN_BB_CLK 45 50_MDM_PCIE_CLK 67 78
10% IN OUT
6.3V
2 X5R-CERM 76
CLOCK BB_CLK 35 SHIELD_MDM_19P2M_CLK OUT 67
01005 3 XO_THERM XO_THERM RADIO_PMIC
RADIO_PMIC 41 GND_XOADC RF_CLK1 66 SHIELD_WTR_19P2M_CLK 70
OUT
A SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
spare
DRAWING NUMBER SIZE
D
PP_VDD_MAIN 4
D
1 1 L5601_RF
C5620_RF C5621_RF 1UH-20%-0.054OHM-3.4A
15UF 15UF MDM MODEM
20% 20% PP_VSW_S1 1 2 BBPMU_TO_PMU_AMUX1 0.90V/2685MA
BBPMU_TO_PMU_AMUX1-53[I16]
66 65
2 6.3V 6.3V OUT
CERM 2 CERM 2520 XO SHUTDOWN: OFF
0402
RADIO_PMIC
0402
RADIO_PMIC GND
MAKE_BASE=TRUE RADIO_PMIC 1 C5614_RF
MAKE_BASE=TRUE 43UF
20%
4V
2
81
64 62 53 IN
PP_VDD_MAIN PP_VDD_MAIN 4 L5602_RF X5R
0603
77 65
2.2UH-20%-0.14OHM-1.6A GND 4
PP_VDD_MAIN 4 PP_VSW_S2 1 2 LOW VOLTAGE LDOS PP_1V225_SMPS2 4 1.25V/693MA
RADIO_PMIC 0806
XO SHUTDOWN: ON
1 C5622_RF 1 C5615_RF
15UF BBPMU_RF RADIO_PMIC
20UF
1 C5631_RF
20% PMD9645 20% 20UF
2 6.3V
CERM 2
6.3V
CERM-X5R
20%
6.3V
WLNSP
0402
4 GND
MAKE_BASE=TRUE
PP_VDD_MAIN 5 VDD_S1 SYM 4 OF 5 VREG_S1 10 L5603_RF 0402
GND
2 CERM-X5R
0402
4 1.0UH-20%-2.7A-0.056OHM 4
16 VDD_S1 POWER VSW_S1 11
MAKE_BASE=TRUE PP_VSW_S3 2 1 MDM MEMORY, MDM USB
81 PP_VDD_MAIN PP_VDD_MAIN GND 6 RADIO_PMIC 22 BBPMU_TO_PMU_AMUX2 4 1.16V/1951MA
64 62 53 IN 4 4 GND_S1 VSW_S1 0806
XO SHUTDOWN: ON
77 65
17 GND_S1 VSW_S1 27 1 C5616_RF
RADIO_PMIC
PP_VDD_MAIN 4 28 25UF
1 C5632_RF
GND_S1 20% 25UF
33 GND_S1 2 6.3V 20%
1 C5623_RF L5604_RF X5R
0402
6.3V
2 X5R
15UF 4 PP_VDD_MAIN 92 VDD_S2 VREG_S2 91 2.2UH-20%-0.14OHM-1.6A GND 0402
4
20%
2 6.3V 103 VDD_S2 VSW_S2 97 PP_VSW_S4 1 2 HIGH VOLTAGE LDOS BBPMU_TO_PMU_AMUX3 1.85V/1241MA
CERM MAKE_BASE=TRUE XO SHUTDOWN: ON OUT BBPMU_TO_PMU_AMUX3-53[I16]
69 65
0402 GND 102 GND_S2 0806
C5617_RF
4
RADIO_PMIC 1
C
GND
C
m
4 RADIO_PMIC
70
1 C5633_RF
4 PP_VDD_MAIN VDD_S3 VREG_S3 69 25UF
20% 25UF
GND 49 VSW_S3 59 6.3V 20%
4
54
GND_S3
VSW_S3 64
L5605_RF 2 X5R 6.3V
2 X5R
o
GND_S3 0402
1.0UH-20%-2.7A-0.056OHM GND 0402
4
.c
1 XO SHUTDOWN: ON
GND GND_S4 VSW_S4 2 0806
C5618_RF
4
RADIO_PMIC 1
7 GND_S4 1 C5634_RF
25UF
94
20% 25UF
MAKE_BASE=TRUE PP_VDD_MAIN VDD_S5 VREG_S5 87 2
6.3V 20%
x
4 X5R
93 2 6.3V
VSW_S5 99
PP_VDD_MAIN PP_VDD_MAIN 0402 X5R
81 77 65 64 62 53 IN 4
4 GND GND_S5 0402
GND 4
fi
PP_VDD_MAIN 4
4 PP_1V225_SMPS2 86 VDD_L1_2_16 VREG_L1 80 MDM LOW VOLTAGE ANALOG XO SHUTDOWN: OFF PP_1V5_LDO1 66 1.23V/124MA
OUT
VREG_L2 81 MDM EBI1, DDR CORE XO SHUTDOWN: BYP PP_1V2_LDO2 1.20V/569MA
1 BBPMU_TO_PMU_AMUX2 44 VDD_L3_4 OUT 66
C5624_RF 4
VREG_L3 39 MDM CORE XO SHUTDOWN: OFF PP_0V9_LDO3 1.00V/610MA
a
OUT 69
15UF BBPMU_TO_PMU_AMUX3 14 48 MDM PCIE XO SHUTDOWN: BYP
20% 69 65 BBPMU_TO_PMU_AMUX3-53[I16]
IN VDD_L5_6_15 VREG_L4_16 PP_0V95_LDO4 OUT 66 1.00V/88MA
2 6.3V
CERM VREG_L5 19 MDM HIGH VOLTAGE ANALOG XO SHUTDOWN: ON PP_1V7_LDO5 1.80V/52MA
in
0402 4 GND MAKE_BASE=TRUE 23 VDD_L7_8 OUT 66
VREG_L6 3 MDM 1.8V I/O, DDR, SHARED 1.8V VOLTAGE RAIL XO SHUTDOWN: BYP PP_1V8_LDO6 1.80V/366MA
RADIO_PMIC OUT
89 VDD_L9 VREG_L7 18 MDM PLL XO SHUTDOWN: OFF PP_1V8_LDO7 64 66 1.80V/15MA
OUT
VREG_L8 29 MDM LOW VOLTAGE USB XO SHUTDOWN: OFF PP_1V8_LDO8 1.80V/133MA
90 OUT 66
h
MAKE_BASE=TRUE 81 IN PP_VDD_BOOST VIN_VPH1 100 MEMORY XO SHUTDOWN: ON
PP_VDD_MAIN PP_VDD_MAIN 47 VREG_L9 PP_1V0_LDO9 OUT 66 1.11V/1253MA
81 77 65 64 62 53 IN 4
77 65 64 62 53 IN
PP_VDD_MAIN VIN_VPH2 84 MDM HIGH VOLTAGE USB XO SHUTDOWN: OFF
VREG_L10 PP_3V075_LDO10 OUT 66 3.20V/15MA
.c
PP_VDD_MAIN 4 81
VDD_OTP 73 VDD_OTP VREG_L11 95 UIM1 XO SHUTDOWN: ON VDD_SIM1 81
66 1.80V/60MA
OUT
VREG_L12 85 FRONT END SUPPLY XO SHUTDOWN: OFF PP_2V7_LDO12 75
2.70V/62MA
1 MDM_VREF_LPDDR2 78 VREF_DDR OUT 73
C5625_RF 67 OUT
VREG_L13 96 UIM2 XO SHUTDOWN: OFF VDD_SIM2 OUT
74
66 1.80V/60MA
15UF 74 101
w
20% AVDD_BYP AVDD_BYP VREG_L14 GPS LNA XO SHUTDOWN: OFF PP_1V8_LDO14 71 2.70V/5MA
OUT
2 6.3V
CERM REF_BYP 79 REF_BYP VREG_L15 30 RFFE VIO XO SHUTDOWN: BYP PP_1V8_LDO15 68 1.80V/245MA
OUT
0402 4 GND 73 74 75 77 79 80
RADIO_PMIC 68 34
w
GND_REF VREG_XO VREG_XO
B B
4
GND_XO 40 VREG_XO_GND
1 C5629_RF 1 C5601_RF 24 VDD_XO_RF
4
VREG_RF 60 VREG_RF_CLK
MAKE_BASE=TRUE 0.47UF
10%
2 6.3V
CERM-X5R
0201
0.1UF
10%
2 6.3V
CER-X5R
01005
RADIO_PMIC
1
R5601_RF
0.00
0%
w
GND_RF_CLK 50
4
VREG_RF_CLK_GND
1 C5626_RF
1UF
1 C5604_RF
10UF 1 C5605_RF
1 C5609_RF
1UF
1 C5630_RF
20UF
1 C5610_RF
1UF
1 C5611_RF
1UF
1 C5613_RF
1UF
AVDD_BYP_GND 1/32W 20% 20% 20% 20% 20% 20% 20%
MF 2 10V 2 6.3V 1UF 10V
2 X5R 2 6.3V 2 10V 10V
2 X5R 2 10V
GND_REF X5R CERM-X5R 20% CERM-X5R X5R X5R
2 01005 VREG_XO VREG_RF_CLK 0201 0402 2 10V 0201 0402 0201 0201 0201
OMIT 4 4
RADIO_PMIC RADIO_PMIC X5R RADIO_PMIC RADIO_PMIC RADIO_PMIC RADIO_PMIC
2 0201
OMIT 1 C5602_RF 1 C5603_RF RADIO_PMIC
XW5616_RF 2
DESENSE CAPS SHORT-10L-0.1MM-SM
1
XW5617_RF
SHORT-10L-0.1MM-SM
1UF
20%
2 10V
X5R
1UF
20%
2 10V
X5R
1 C5627_RF
10UF
20%
6.3V
1 C5608_RF
4.7UF
1 C5628_RF
1UF
1 C5612_RF
1UF
0201 0201 2 CERM-X5R 20% 20% 20%
81 77 65 64 62 53 PP_VDD_MAIN 1 0402
IN RADIO_PMIC RADIO_PMIC
RADIO_PMIC 2
6.3V
X5R-CERM1 2 10V
X5R 2 10V
X5R
1
402 0201 0201
1 C5635_RF C5636_RF RADIO_PMIC RADIO_PMIC RADIO_PMIC
100PF 27PF VREG_XO_GND 4 VREG_RF_CLK_GND
5% 2%
2 16V
NP0-C0G
2 16V
CERM
1 C5607_RF
01005 01005
1UF
20%
PLACE XW CLOSE TO PMU 2
OMIT
2
OMIT 10V
2 X5R
PLACE C5635 AND C5636 NEAR THE PMU
VIA XW DOWN TO THE GND PLANE XW5614_RF
SHORT-10L-0.1MM-SM
XW5615_RF
SHORT-10L-0.1MM-SM
0201
RADIO_PMIC
1 1
XO_GND RF_CLK_GND
BBPMU_TO_PMU_AMUX1 MAKE_BASE=TRUE BBPMU_TO_PMU_AMUX1
A PLACE XW CLOSE TO PMU 5 4 OUT 62
SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
VIA XW DOWN TO THE GND PLANE BBPMU_TO_PMU_AMUX2 MAKE_BASE=TRUE
PAGE TITLE
4 BBPMU_TO_PMU_AMUX2 OUT 62
spare
DRAWING NUMBER SIZE
BBPMU_TO_PMU_AMUX3 MAKE_BASE=TRUE BBPMU_TO_PMU_AMUX3 051-00419 D
8 4 OUT 62
Apple Inc. REVISION
R
8.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
BASEBAND: POWER
D BB_RF
MDM9645 A1 GND GND H7 D
PP_1V0_SMPS5 V16 VDD_CORE
BGA A11 GND BB_RF GND J10
5 4
SYM 6 OF 8
A12 GND MDM9645 GND J16
V17 VDD_CORE BGA
PWR1 A15 GND GND J17
F12 VDD_CORE VDD_MODEM F7 BBPMU_TO_PMU_AMUX1 SYM 8 OF 8
4 5 A17 GND GND J22
F13 VDD_CORE VDD_MODEM F8 GND
A2 GND GND J6
F9 VDD_CORE VDD_MODEM G7
A22 GND GND J9
G11 VDD_CORE VDD_MODEM J11
A23 GND GND K1
G12 VDD_CORE VDD_MODEM K10
A4 GND GND K12
G16 VDD_CORE VDD_MODEM K11
A6 K13
G17 VDD_CORE VDD_MODEM K14 BB_RF A7
GND GND
K16
G8 K6 MDM9645 PP_1V8_LDO6 GND GND
VDD_CORE VDD_MODEM BGA 4 5 6 7 17 20 A9 K17
G9 K7 GND GND
VDD_CORE VDD_MODEM SYM 7 OF 8 AA5 K8
H15 L10 1 GND GND
VDD_CORE VDD_MODEM PWR2 C5745_RF AB1 K9
H16 L13 C22 B23 2.2UF GND GND
VDD_CORE VDD_MODEM PP_1V2_LDO2 VDD_P1 VDD_DDR_CORE_1P8
5 4
20% AB10 GND GND L11
J18 VDD_CORE VDD_MODEM L14 D22 VDD_P1 VDD_DDR_CORE_1P8 E1 2 6.3V
X5R-CERM AB15 GND GND L12
J19 VDD_CORE VDD_MODEM L6 G22 VDD_P1 VDD_DDR_CORE_1P8 K23 0201-1
1 C5755_RF 1 C5729_RF 1 C5733_RF 1 C5736_RF 1 1 RADIO_PMIC AB21 L16
K15 VDD_CORE VDD_MODEM L9 C5739_RF C5742_RF H22 VDD_P1 VDD_DDR_CORE_1P8 U1 GND GND
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF AB23 GND GND L23
L15 VDD_CORE VDD_MODEM M8 20% 20% 20% 20% 20% 20% L22 VDD_P1 5 4 PP_1V2_LDO2
6.3V
2 X5R-CERM 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V VDD_DDR_CORE_1P2 AA1 AB5 GND GND L7
M15 VDD_CORE VDD_MODEM M9 X5R-CERM X5R-CERM X5R-CERM X5R-CERM X5R-CERM M22 VDD_P1
0201-1 0201-1 0201-1 0201-1 0201-1 0201-1 VDD_DDR_CORE_1P2 C23 1 C5746_RF AB7 GND GND L8
M16 VDD_CORE VDD_MODEM N11 RADIO_PMIC RADIO_PMIC RADIO_PMIC RADIO_PMIC RADIO_PMIC RADIO_PMIC T22 VDD_P1 VDDPX_BIAS_UIM2
VDD_DDR_CORE_1P2 D1 2.2UF 3 AB9 GND GND M10
M17 VDD_CORE VDD_MODEM N8 U22 VDD_P1 20%
VDD_DDR_CORE_1P2 J23 6.3V
2 X5R-CERM PP_1V0_LDO9 B13 GND GND M11
P15 VDD_CORE VDD_MODEM P10 W2 VDD_P1 1 C5750_RF
4 5
m
VDD_A3 E7 0201-1 B5 GND GND N10
U7 VDD_CORE VDD_MODEM R14 AB16 VDD_P3 RADIO_PMIC
VDD_A3 E17 C1 GND GND N13
U8 VDD_CORE VDD_MODEM R8 E2 VDD_P3
1 C5730_RF 1 C5734_RF 1 C5737_RF 1 C5740_RF 1 C5704_RF C11 GND GND N14
R9 K2 B12
o
PP_1V0_LDO9 E19 VDD_MODEM 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF VDD_P3 VDD_A2 PP_1V7_LDO5 4 C16 N15
5 4 VDD_MEM T13 20% 20% 20% 20% 20% P2 B3 GND GND
F18 VDD_MODEM 6.3V VDD_P3 VDD_A1 C2 N16
VDD_MEM T8 2 X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM B15 GND GND
.c
F19 VDD_MODEM 0201-1 0201-1 0201-1 0201-1 0201-1 VDD_A2 1 1 C20 N17
VDD_MEM T9 RADIO_PMIC RADIO_PMIC RADIO_PMIC RADIO_PMIC RADIO_PMIC B7 C5747_RF C5751_RF GND GND
G18 VDD_MODEM VDD_A1 2.2UF 2.2UF C21 N18
VDD_MEM NOSTUFF B18 20% 20% GND GND
H10 VDD_A2 C4 N6
VDD_MEM B8 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM GND GND
VDD_A1
x
H13 VDD_MEM 0201-1 0201-1 C9 GND GND N9
RADIO_PMIC RADIO_PMIC
H14 VDD_MEM VDD_A2 C12 D2 GND GND P1
fi
H8 VDD_MEM VDD_A2 C15 D21 GND GND P12
H9 VDD_MEM VDD_SIM1 (PP_UIM1_LDO11) AA21 VDD_P4 PP_1V5_LDO1 D23 GND GND P13
VDD_A1 B10
20 4 4
J12 VDD_MEM E14 GND GND P17
a
J13 4 VDD_SIM2 (PP_UIM2_LDO13) AA15 VDD_P5 VDD_A1 E10 E15 P18
VDD_MEM 1 GND GND
J14 AB11 C18 C5748_RF E16 P8
VDD_MEM PP_1V8_LDO6 VDD_P7 VDD_A2 GND GND
in
20 17 7 6 5 4
2.2UF
J15 VDD_MEM M19 VDD_P7 VDD_A2 C6 20% E18 GND GND P9
J7 C7 2 6.3V
X5R-CERM E21 R11
VDD_MEM VDD_A2 0201-1 GND GND
J8 VDD_MEM 4 PP_1V8_LDO8 V9 VDD_USB_HS_1P8 VDD_A2 E3 RADIO_PMIC E22 GND GND R12
h
K18 VDD_MEM PP_3V075_LDO10 AA10 VDD_USB_HS_3P3 E23 GND GND R17
VDD_USB_HS_MX V11
4
PP_0V95_LDO4
L17 VDD_MEM
4 5 E6 GND GND R18
AB3 VDD_USB_SS_0P9
.c
L18 VDD_MEM NC VDD_ALWAYS_ON U14 NC E8 GND GND R7
W3 VDD_USB_SS_0P9
M12 VDD_MEM NC E9 GND GND T10
M13 NC
AA3 VDD_USB_SS_1P8 VDD_PLL E13 PP_1V8_LDO7 3 4 5 F11 T11
VDD_MEM GND GND
N12 Y5 VDD_PLL P19 F14 T14
w
VDD_MEM 5 4 PP_0V95_LDO4 VDD_PCIE_0P9 GND GND
N7 VDD_MEM Y6 VDD_PCIE_0P9 VDD_QFPROM_PRG F10 PP_1V8_LDO7 3 4 5
F15 GND
P6 VDD_MEM Y7 VDD_PCIE_1P8 F16 GND GND T15
w
B P7
T12
VDD_MEM
VDD_MEM
1 C5749_RF 1 C5753_RF
F17
F23
GND
GND
GND
GND
T16
T17 B
2.2UF 2.2UF
T18
T6
U11
VDD_MEM
VDD_MEM
VDD_MEM
1 C5731_RF
2.2UF
1 C5732_RF
2.2UF
1 C5735_RF
2.2UF
1 C5738_RF
2.2UF
w 1 C5741_RF
0.1UF
1 C5743_RF
2.2UF
1 C5744_RF
2.2UF
20%
2 6.3V
X5R-CERM
0201-1
RADIO_PMIC
NOSTUFF
20%
2 6.3V
X5R-CERM
0201-1
RADIO_PMIC
G10
G13
G14
GND
GND
GND
GND
GND
GND
T23
T7
U10
U12 VDD_MEM 20% 20% 20% 20% 20% 20% 20% G15 GND GND U15
U13 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V 2 4V
X5R 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM G19 U17
VDD_MEM 0201-1 0201-1 0201-1 0201-1 01005 0201-1 0201-1 GND GND
U18 VDD_MEM RADIO_PMIC RADIO_PMIC RADIO_PMIC RADIO_PMIC RADIO_PMIC RADIO_PMIC RADIO_PMIC G23 GND GND U23
U6 NOSTUFF H11 U9
VDD_MEM GND GND
V18 VDD_MEM H12 GND GND V1
H17 GND GND V6
H18 GND GND Y4
H19 GND GND Y8
H23 GND
H6 GND
NOSTUFF AT CARRIER
PP_1V8_LDO6
20 17 7 6 5 4
NOSTUFF
C C
m
U5801_RF
74AUP1G34GX
5
SOT1226
o
SWD_AP_TO_MANY_SWCLK 2 4 SWD_AP_TO_BB_CLK_BUFFER
20 1 6 17
NC
.c
3
1
NC
x
fi
a
BB_RF
in
MDM9645
BGA
SYM 2 OF 8
h
B9 ANALOG_RF
SHIELD_XCVR0_PRX_CA2_I BBRX_IP_CH0 BBRX_IP_FB C10 SHIELD_XCVR0_TX_FB_RX_I
71 IN IN 70 71
BB_RF
MDM9645
.c
71 IN
SHIELD_XCVR0_PRX_CA2_Q A10 BBRX_QP_CH0 BBRX_QP_FB B11 SHIELD_XCVR0_TX_FB_RX_Q IN 70 71 BGA
SYM 5 OF 8
A8 USB_PCIE
SHIELD_XCVR0_DRX_CA2_I BBRX_IP_CH1 GNSS_BB_IP E11 SHIELD_GPS_RX_I
AA9 PCIE_REFCLK_P V8
w
71 IN IN 71
78 64 IN
50_MDM_PCIE_CLK PCIE_USB_SYSCLK 90_PCIE_AP_TO_BB_REFCLK_P IN 53 62 78
BB_USB_TRXTUNE Y9 USB_HS_REXT PCIE_REFCLK_M V7 90_PCIE_AP_TO_BB_REFCLK_N
71 SHIELD_XCVR0_DRX_CA2_Q C8 BBRX_QP_CH1 GNSS_BB_QP E12 SHIELD_GPS_RX_Q 71
IN 53 62 78
IN IN
w
90_USB_BB_DATA_P V10 USB_HS_DP PCIE_TX_P AB6 90_PCIE_BB_TO_AP_RXD_P
B B
78 62 53 BI OUT 53 62
81
90_USB_BB_DATA_N Y10 USB_HS_DM PCIE_TX_M AA6 90_PCIE_BB_TO_AP_RXD_N
71 SHIELD_XCVR1_DRX_I C5 BBRX_IP_CH2 TX_DAC0_IP C17 SHIELD_XCVR0-1_TX_I_P 70
78 62 53
81
OUT 53 62
IN OUT
71 IN
SHIELD_XCVR1_DRX_Q B6 BBRX_QP_CH2
TX_DAC0_IM
TX_DAC0_QP
TX_DAC0_QM
B17
A16
B16
SHIELD_XCVR0-1_TX_I_N
SHIELD_XCVR0-1_TX_Q_P
SHIELD_XCVR0-1_TX_Q_N
w OUT
OUT
OUT
70
70
70
1
1%
R5806_RF
4.02K
1/32W
MF
NC
NC
AB2
AA2
AA4
USB_SS_TX_P
USB_SS_TX_M
USB_SS_RX_P
PCIE_RX_P AA8
PCIE_RX_M AB8
IN
53 62
53 62
NC
SHIELD_XCVR1_PRX_I B4 BBRX_IP_CH3 TX_DAC1_IP C14 2 01005 AB4 USB_SS_RX_M
71 IN NC NC
TX_DAC1_IM B14 PLACE 1
NC R5803_RF
SHIELD_XCVR1_PRX_Q A5 BBRX_QP_CH3 TX_DAC1_QP A13 CLOSE Y1 1.43K
71 IN NC TO U12 USB_SS_REXT 1%
TX_DAC1_QM A14 NC 1/32W
NC MF
VREF_DAC_BIAS C13 TX_DAC_VREF ET_DAC0_P A20 SHIELD_ET_DAC_P 2 01005
64 IN OUT 77 RADIO_BB
C19 TX_DAC_VREF ET_DAC0_M A21 SHIELD_ET_DAC_N OUT 77
PLACE
A18 CLOSE
1 A3 ET_DAC1_P NC TO AA10
C5801_RF 71 IN
SHIELD_XCVR0_PRX_CA1_I BBRX_IP_CH5 A19
0.1UF C3 ET_DAC1_M NC
71 IN
SHIELD_XCVR0_PRX_CA1_Q BBRX_QP_CH5
20%
2 6.3V DNC F1
X5R-CERM SHIELD_XCVR0_DRX_CA1_I B2 BBRX_IP_CH6 NC
01005 71 IN
DNC F6
SHIELD_XCVR0_DRX_CA1_Q B1 BBRX_QP_CH6 NC
71 IN
DNC G1
NC
F21 NC DNC G6
NC NC
F22 NC DNC Y3
NC NC
H21 NC
NC
J21 NC
NC
A SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
spare
DRAWING NUMBER SIZE
BASEBAND: GPIOS
PP_1V8_LDO6
20 17 7 6 5 4
BB_RF
R5911_RF 1 MDM9645
R5912_RF 1 1.00K V15
BGA
F3
BUFFER ON RFFE5
GPIO_0 GPIO_40
1.00K
1%
1%
1/32W
MF
NC
AA19 GPIO_1
SYM 3 OF 8
GPIO GPIO_41 K3
NC
SHIELD_GSM_TX_PHASE
SCLK/SDATA_A IS OUTPUT
1/32W 01005 2
NC OUT 70
MF
AB14 GPIO_2 GPIO_42 K5
RADIO_BB NC NC
01005 2 Y15 GPIO_3 GPIO_43 J3 1 C5902_RF
D SKU R5911_RF R5912_RF RADIO_BB
NOSTUFF
OMIT_TABLE
SKU_ID
NC
T1 GPIO_4 GPIO_44 J2
NC
75_RFFE3_SDATA BI 74 78
22PF
2%
16V
PLACE CAP CLOSE TO MDM
RFBUF_RF
D
SKU_ID2 R3 GPIO_5 GPIO_45 J1 75_RFFE3_SCLK 74 78
2 CERM IMPROVES RXBN BY 4DB
OUT
RF1352
ROW NOSTUFF NOSTUFF NC
NC
R2
R1
GPIO_6
GPIO_7
GPIO_46
GPIO_47
J5
H3
75_RFFE4_SDATA
75_RFFE4_SCLK OUT
BI 70 78
70 78
01005
19 18 16 14 13 12 4 PP_1V8_LDO15
4 VIO
WLCSP
GPO1 1 BB_BUFFER_GPO1 1
T5 H2
JP 1.0 KOHM NOSTUFF BB_EEPROM_I2C_SDA
NC
NC
P3
R5
GPIO_8
GPIO_9
GPIO_48
GPIO_49 H1
Y16
BB_TO_LAT_ANT_DATA
BB_TO_LAT_ANT_SCLK
1 7 17
1 7 17
17 7 1
BB_TO_LAT_ANT_SCLK 2 SCLK
GPO2 8
SCLK_A 5
BB_BUFFER_GPO2
BB_TO_UAT_SCLK
1
1 7 14
7 GPIO_10 GPIO_50 NC
7 BB_EEPROM_I2C_SCL P5 GPIO_11 GPIO_51 N23 AP_TO_BB_TIME_MARK 53 62 78 17 7 1
BB_TO_LAT_ANT_DATA 3 SDATA SDATA_A 6 BB_TO_UAT_DATA 1 7 14
IN
62 53 I2S_BB_TO_AP_LRCLK V13 GPIO_12 GPIO_52 AA16 UART_BB_TO_WLAN_COEX 53 62 WDOG DIS CONFLICT
IN OUT 78 81
I2S_AP_TO_BB_DOUT AA12 GPIO_13 GPIO_53 V12 UART_WLAN_TO_BB_COEX
62 53 IN IN 53 62 78 81 GND
62 53 OUT I2S_BB_TO_AP_DIN Y13 GPIO_14 GPIO_54 K19
NC USID=0XF
7
62 53 I2S_BB_TO_AP_BCLK AA13 GPIO_15 GPIO_55 Y23 BB_TO_AP_RESET_DETECT_L 53 62 78
IN OUT
78 62 53 UART_BB_TO_AOP_RXD V14 GPIO_16 GPIO_56 L19 AP_TO_BB_COREDUMP 53 62 78
OUT IN
62 53 UART_AOP_TO_BB_TXD AA14 GPIO_17 GPIO_57 AA22 AP_TO_BB_IPC_GPIO1 53 62
IN BI
Y14 GPIO_18 GPIO_58 M23
NC NC RFCAL_QCN
AB13 GPIO_19 GPIO_59 AB22
NC NC
AB19 GPIO_20 GPIO_60 Y12
NC NC
P21 GPIO_21 GPIO_61 AB17 BB_TO_PMU_PCIE_HOST_WAKE_L
NC OUT 53 62 78
P23 GPIO_22 GPIO_62 Y22
NC
Y18 GPIO_23 GPIO_63 M21
NC
BB_TO_LAT_ANT_SCLK R5909_RF
1 2 BB_TO_UAT_SCLK
NC NC 17 7 1 1 7 14
m
5%
NC NC 2 16V BB_TO_LAT_ANT_DATA 1 BB_TO_UAT_DATA
MAV13 = WDOG DIS M2 GPIO_31 GPIO_71 AB12 NP0-C0G 17 7 1 1 7 14
NC NC 01005
0%
M1 GPIO_32 GPIO_72 H5 75_RFFE2_SDATA 1/32W
NC BI 77 78
MF
M5 G3
o
GPIO_33 GPIO_73 75_RFFE2_SCLK 01005
NC OUT 77 78
RADIO_BB
L5 GPIO_34 GPIO_74 G2 75_RFFE1_SDATA
NC BI 70 78
NOSTUFF
L3 G5
.c
NC GPIO_35 GPIO_75 75_RFFE1_SCLK BI 70 78
L2 Y21 20 1 PP1V8_SDRAM
78 62 53 OUT BB_TO_STROBE_DRIVER_GSM_BURST_IND GPIO_36 GPIO_76 SIM1_IO BI 78 81
x
78 73 OUT 78 81
fi
10% 5%
2 6.3V 2 16V
X5R NP0-C0G-CERM
01005 01005
a
GPIO_RF
in
QM18064
WLCSP
A3 VIO GPO1 A4 BB_TO_LAT_GPO1
h
GPO2 B1 BB_TO_LAT_GPO2 1
GPO3 B2 BB_TO_LAT_GPO3
BB_TO_LAT_ANT_SCLK A1 SCLK 1
.c
17 7 1
GPO4 B4
NC
RFFE1 WTR3925 17 7 1
BB_TO_LAT_ANT_DATA A2 SDATA
w
RFFE2 QFE3100 GND
B3
w
B RFFE3 DIV MODULES USID=0X8 B
RFFE4 w
WTR4905
RFFE5 TUNERS + ELNAS
RFFE6 2G PA,MLB PA,MB/HB TDD PA,MB/HB FDD PA
RFFE7 LB PA, COUPLERS
20 17 7 6 5 4 PP_1V8_LDO6
BB EEPROM
1
R5906_RF PP_1V8_LDO6 4 5 6 7 17 20
100K
1% 1
1/32W 1 C5901_RF 1
MF
01005 2 R5907_RF 1UF R5908_RF
RADIO_BB 10K 20% 10K
NOSTUFF 1% 2 10V
X5R 1%
1/32W 0201 1/32W
MF RADIO_BB MF
PCIE_BB_BI_AP_CLKREQ_L
7 1
2 01005 2 01005
A1
RADIO_BB RADIO_BB
VCC
TRANSCEIVER: POWER
m
0.00 PP_VDD_XCVR0_RF1_RX1 40MA DEFAULT_CAPACITOR_100000pF_2_1 DEFAULT_CAPACITOR_4700pF_2_1 48
1 2 GND
0% DEFAULT_CAPACITOR_100000pF_2_1
DEFAULT_CAPACITOR_27.000000pF_2_1 1 C6003_RF 1 C6005_RF
1/32W
0.47UF 4700PF GND 38
o
MF
01005 1 C6021_RF 1 C6013_RF 20% 10%
6.3V GND 25
2 4V 2
0.1UF 27PF CERM-X5R-1
201
X5R
01005 GND 31
.c
20% 5%
2 6.3V 2 16V RADIO_TRANSCEIVER RADIO_TRANSCEIVER
X5R-CERM NP0-C0G
01005
DEFAULT_RESISTOR_0.001OHM_2_1 01005
RADIO_TRANSCEIVER
R6008_RF
x
0.00 PP_VDD_XCVR0_RF1_RX2 250MA
1 2
fi
0% DEFAULT_CAPACITOR_100000pF_2_1
DEFAULT_CAPACITOR_27.000000pF_2_1
1/32W
MF
01005 1 C6022_RF 1 C6014_RF
0.1UF 27PF
a
20% 5%
2 6.3V
X5R-CERM 2 16V
NP0-C0G
01005 01005
in
RADIO_TRANSCEIVER
h
.c
XCVR1_RF
WTR4905
WLNSP
w
SYM 5 OF 5
9 GND GND GND 32
13 35
w
GND GND
B 16 GND GND 37 B
21 GND GND 39
STAR ROUTING DEFAULT_RESISTOR_0.001OHM_2_1
R6002_RF
w 250MA BBPMU_TO_PMU_AMUX3 BBPMU_TO_PMU_AMUX3-53[I16]
65 69
24
25
26
GND
GND
GND
GND
GND
GND
40
42
45
IN
PP_0V9_LDO3 1
0.00 2
25MA 27 48
69 65 IN
PP_VDD_XCVR1_RF1_DIG GND GND
DEFAULT_CAPACITOR_4700pF_2_1 29 52
0% GND GND
1 C6006_RF 1/32W
MF
01005 1 C6007_RF 1 C6015_RF XCVR1_RF
1 C6002_RF 1 C6004_RF 30 GND
2.2UF RADIO_TRANSCEIVER 0.47UF 4700PF
20% 0.1UF 27PF WTR4905 20% 10%
6.3V
2 X5R-CERM 20% 5% 2 4V
CERM-X5R-1 2 6.3V
X5R
0201-1 2 6.3V
X5R-CERM 2 16V
NP0-C0G WLNSP 201 01005
RADIO_TRANSCEIVER 01005 01005 SRM 4 OF 5 RADIO_TRANSCEIVER RADIO_TRANSCEIVER
RADIO_TRANSCEIVER RADIO_TRANSCEIVER
50 VDD_RF1_DIG PWR VDD_RF2 44
R6003_RF
0.00 40MA 33 VDD_RF1_RX
1 2 PP_VDD_XCVR1_RF1_RX VDD_RF2_LDO 34 VDD_XCVR1_RF2_LDO_BYPASS
23 VDD_RF1_TX
0%
1/32W
MF
DEFAULT_CAPACITOR_27.000000pF_2_1 1 C6023_RF
01005 1 C6008_RF 1 C6016_RF 2.2UF
RADIO_TRANSCEIVER 20%
0.1UF 27PF 6.3V
2 X5R-CERM
20% 5%
2 6.3V
X5R-CERM 2 16V
NP0-C0G
0201-1
01005 01005
RADIO_TRANSCEIVER
R6004_RF
1
0.00 2 PP_VDD_XCVR1_RF1_TX
175MA
0%
1/32W
MF
01005 1 C6009_RF 1 C6017_RF
0.1UF 27PF
20% 5%
A 2 6.3V
X5R-CERM
01005
2 16V
NP0-C0G
01005 SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
RADIO_TRANSCEIVER RADIO_TRANSCEIVER PAGE TITLE
spare
DRAWING NUMBER SIZE
TRANSCEIVER: TX PORTS
OMIT_TABLE
C6106_RF
27PF
9
50_XCVR0_TX_HMB1_B11_B21 1 2 50_XCVR0_TX_B11_B21_PA_IN 80
OUT
2%
16V
CERM
01005
RADIO_TRANSCEIVER
DEFAULT_INDUCTOR_2.800000nH_2_1
DEFAULT_CAPACITOR_22.000000pF_2_1
L6110_RF C6116_RF
D
2.8NH-+/-0.1NH-0.36A 22PF D
50_XCVR0_TX_HMB2_B38_B40_B41 1 2 50_XCVR0_TX_HMB2_B38_B40_B41_MATCH 1 2 50_XCVR0_TX_B38_B40_B41_PA_IN
XCVR0_RF
9 OUT 79
01005 DEFAULT_CAPACITOR_1.200000pF_2_15%
WTR3925-2-TR-03-1 1 C6113_RF 16V
CERM
WLPSP 1.2PF 01005
+/-0.05PF
SHIELD_XCVR0-1_TX_I_P 76 SYM 3 OF 5 66 16V
70 67 IN TX_BB_IP TX_LB1 NC 2 NP0-C0G-CERM
SHIELD_XCVR0-1_TX_I_N 75 TX 59 01005
70 67 IN TX_BB_IM TX_LB2 NC
SHIELD_XCVR0-1_TX_Q_P 68 RADIO_TRANSCEIVER 51
70 67 IN TX_BB_QP TX_LB3 NC
SHIELD_XCVR0-1_TX_Q_N 60 44
70 67 IN TX_BB_QM TX_LB4 NC
SHIELD_XCVR0_TX_FB_RX_I 9 101 50_XCVR0_TX_HMB1_B11_B21
71 67 OUT TX_FBRX_BBI TX_MHB1 9
SHIELD_XCVR0_TX_FB_RX_Q 1 100 50_XCVR0_TX_HMB2_B38_B40_B41
71 67 OUT TX_FBRX_BBQ TX_MHB2 9 C6107_RF
TX_MHB3 93 50_XCVR0_TX_HMB3_B1_B3_B4_B25 27PF
75_RFFE1_SCLK 47 9
78 68 IN RFFE_CLK 86 50_XCVR0_TX_HMB4_B7_B30 50_XCVR0_TX_HMB3_B1_B3_B4_B25 1 2 50_XCVR0_TX_B1_B3_B4_B25_PA_IN
75_RFFE1_SDATA 62 TX_MHB4 9 9 OUT 80
78 68 IN RFFE_DATA
DEFAULT_CAPACITOR_1000pF_2_1
TX_HMLB1 80 NC 2% 1
C6110_RF TX_HMLB2 74 50_XCVR0_TX_HMLB2_B34_B39 L6111_RF C6105_RF
16V
CERM
1000PF
9 3.0NH+/-0.1NH-200MA 27PF 01005
46 RADIO_TRANSCEIVER L6102_RF
70 64 IN
SHIELD_WTR_19P2M_CLK 1 2 XO_IN TX_FBRX_P 8 100_XCVR0_TX_FBRX_IN_WTR 1 2 50_XCVR0_TX_FBRX_IN_UNBAL 1 2 50_XCVR0_TX_FBRX_IN IN 73
10NH-3%-140MA
SHIELD_XCVR0_19P2M_CLK_WTR_IN TX_FBRX_M 16 01005 01005
10% NC 2% NOSTUFF
6.3V 16V
1 RADIO_TRANSCEIVER
X5R-CERM C6112_RF CERM
01005
1.0PF
1 C6118_RF 1 C6117_RF 01005
RADIO_TRANSCEIVER
2
+/-0.1PF
16V
1.5PF 1.5PF DEFAULT_INDUCTOR_2.800000nH_2_1
2 NP0-C0G +/-0.1PF +/-0.1PF DEFAULT_CAPACITOR_22.000000pF_2_1
01005
16V
2 NP0-C0G 2 16V
NP0-C0G
L6109_RF C6115_RF
NOSTUFF 01005-1 01005-1 2.8NH-+/-0.1NH-0.36A 22PF
9
50_XCVR0_TX_HMB4_B7_B30 1 2 50_XCVR0_TX_HMB4_B7_B30_MATCH 1 2 50_XCVR0_TX_B7_B30_PA_IN 80
OUT
01005 DEFAULT_CAPACITOR_1.200000pF_2_1
5%
1 C6114_RF 16V
C
CERM
C
m
1.2PF 01005
+/-0.05PF
2 16V
NP0-C0G-CERM
01005
o
.c
C6108_RF
27PF
x
9
50_XCVR0_TX_HMLB2_B34_B39 1 2 50_XCVR0_TX_B34_B39_PA_IN 79
OUT
2%
fi
16V
CERM
01005
RADIO_TRANSCEIVER
a
in
C6101_RF
h
27PF
9
50_XCVR1_TX_HMLB1_G1800_G1900 1 2 50_XCVR1_TX_G1800_G1900_PA_IN 79
OUT
.c
2% 1
16V
CERM
01005
RADIO_TRANSCEIVER L6101_RF
10NH-3%-140MA
w
01005
NOSTUFF
RADIO_TRANSCEIVER
w
2
B B
C6102_RF
XCVR1_RF
WTR4905
w 9
50_XCVR1_TX_HMLB2_B8_B20_B26_B27
27PF
1 2 50_XCVR1_TX_B8_B20_B26_B27_PA_IN
OUT 80
WLNSP 2% 1
16V
SYM 2 OF 5 CERM
01005
70 67
SHIELD_XCVR0-1_TX_I_P 14 TX_BB_IP TX TX_DA1 1 50_XCVR1_TX_HMLB1_G1800_G1900 9 RADIO_TRANSCEIVER L6103_RF
IN
70 67
SHIELD_XCVR0-1_TX_I_N 19 TX_BB_IM TX_DA2 18 50_XCVR1_TX_HMLB2_B8_B20_B26_B27 9
10NH-3%-140MA
IN 01005
TX_DA3 12 NOSTUFF
SHIELD_XCVR0-1_TX_Q_P 3 TX_BB_QP NC
70 67 IN
TX_DA4 2 50_XCVR1_TX_HMLB4_B12_B13_B28 RADIO_TRANSCEIVER
SHIELD_XCVR0-1_TX_Q_N 8 TX_BB_QM
9
2
70 67 IN
TX_DA5 7 50_XCVR1_TX_HMLB5_G850_G900 9
68
SHIELD_GSM_TX_PHASE 57 GP_DATA TX_FBRX 31 50_XCVR1_TX_FBRX_IN 12
IN
C6103_RF
75_RFFE4_SDATA 56 27PF
78 68 IN RFFE_DATA 50_XCVR1_TX_HMLB4_B12_B13_B28 1 2 50_XCVR1_TX_B12_B13_B28_PA_IN
78 68
75_RFFE4_SCLK 51 RFFE_CLK
9 OUT 80
DEFAULT_CAPACITOR_1000pF_2_1 2%
16V
55 XO_IN CERM
C6109_RF 01005
100PF RADIO_TRANSCEIVER
70 64
SHIELD_WTR_19P2M_CLK 1 2 SHIELD_XCVR1_19P2M_CLK_WTR_IN
IN
5%
6.3V
CERM
01005
1 C6111_RF
68PF
5%
2 25V
NP0-C0G-CERM C6104_RF
01005 27PF
A NOSTUFF
9
50_XCVR1_TX_HMLB5_G850_G900 1 2 50_XCVR1_TX_G850_G900_PA_IN
OUT 79
SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
2% PAGE TITLE
OFFPAGE=TRUE
16V 1
CERM
01005 spare
RADIO_TRANSCEIVER DRAWING NUMBER SIZE
L6104_RF
10NH-3%-140MA Apple Inc. 051-00419 D
01005 REVISION
NOSTUFF
RADIO_TRANSCEIVER
R
8.0.0
2 NOTICE OF PROPRIETARY PROPERTY: BRANCH
D XCVR0_RF D
XCVR0_RF WTR3925-2-TR-03-1
WTR3925-2-TR-03-1 WLPSP
WLPSP SYM 2 OF 5
SYM 1 OF 5 5 DRX_LB1 DRX_CA1_BBI 78 SHIELD_XCVR0_DRX_CA1_I
104 PRX_CA1_BBI 69 NC OUT 67
PRX_LB1 SHIELD_XCVR0_PRX_CA1_I 67
DRX_GPS
NC PRX OUT 12 DRX_LB2
96 PRX_LB2 RADIO_TRANSCEIVER NC DRX_CA1_BBQ 70 SHIELD_XCVR0_DRX_CA1_Q
NC PRX_CA1_BBQ 77
67
SHIELD_XCVR0_PRX_CA1_Q 67 4 DRX_LB3 OUT
103 PRX_LB3 OUT NC RADIO_TRANSCEIVER
NC 11 DRX_LB4
95 PRX_LB4 NC
NC
15 DRX_MB1 DRX_CA2_BBI 34 SHIELD_XCVR0_DRX_CA2_I
99 PRX_CA2_BBI 39 NC 67
11
50_XCVR0_PRX_PMB1_B4 PRX_MB1 SHIELD_XCVR0_PRX_CA2_I 67
OUT
OUT 50_XCVR0_DRX_DMB2_B34 22 DRX_MB2
DRX_CA2_BBQ 40
72
50_XCVR0_PRX_PMB2_B1_B4 92 PRX_MB2 IN SHIELD_XCVR0_DRX_CA2_Q
PRX_CA2_BBQ 33
11 50_XCVR0_DRX_DMB3_B1_B4 67
SHIELD_XCVR0_PRX_CA2_Q 67 72 7 DRX_MB3
OUT
11
50_XCVR0_PRX_PMB3_B3 106 PRX_MB3 OUT IN
72
50_XCVR0_DRX_DMB4_B39 14 DRX_MB4
11
50_XCVR0_PRX_PMB4_B34_B39 98 PRX_MB4 IN
72
50_XCVR0_DRX_DMB5_B3_B25 6 DRX_MB5
11
50_XCVR0_PRX_PMB5_B25 105 PRX_MB5 IN
72
50_XCVR0_DRX_DMLB6_B11_B21 13 DRX_MLB6
11
50_XCVR0_PRX_PMLB6_B11_B21 97 PRX_MLB6 IN
50_XCVR0_PRX_PHB1_B7 73 NC
43 DRX_HB1 GNSS_BBI 18 SHIELD_GPS_RX_I OUT 67
11 PRX_HB1 50_XCVR0_DRX_DHB2_B7_B38_B41 50 DRX_HB2
GNSS_BBQ 32
72
11
50_XCVR0_PRX_PHB2_B40_EXT 65 PRX_HB2 IN SHIELD_GPS_RX_Q 67
29 DRX_HB3
OUT
11
50_XCVR0_PRX_PHB3_B38_B40_B41 85 PRX_HB3 NC
72
50_XCVR0_DRX_DHB4_B30_B40 35 DRX_HB4
11
50_XCVR0_PRX_PHB4_B30 79 PRX_HB4 IN
2 DNC GP_DATA 24 NC
NC
10
50_GPS_RX 10 GNSS_L1
C C
m
o
.c
XCVR1_RF
x
WTR4905
WLNSP
fi
SYM 3 OF 5
50_XCVR1_PRX_PLB1_B12_B13_B20_B28_B29 17 PRX_LB1 PRX PRX_BBI 15 SHIELD_XCVR1_PRX_I
11
50_XCVR1_PRX_PLB2_B8_B26_B27 11 PRX_LB2
OUT 67
XCVR1_RF
a
11
6 WTR4905
NC PRX_LB3 PRX_BBQ 20 SHIELD_XCVR1_PRX_Q
OUT 67
WLNSP
in
50_XCVR1_PRX_PMB1_G1800 4 SYM 1 OF 5
PRX_MB1 49 DRX_BBI 47
11
50_XCVR1_DRX_DLB1_B12_B13_B20_B28_B29 DRX_LB1 DRX_GPS SHIELD_XCVR1_DRX_I
50_XCVR1_PRX_PMB2_G1900 10 PRX_MB2
72 IN OUT 67
11
50_XCVR1_DRX_DLB2_B8_B26_B27 54 DRX_LB2
5 PRX_MB3
72 IN
DRX_BBQ 36 SHIELD_XCVR1_DRX_Q
NC 60 OUT 67
h
NC DRX_LB3
28 PRX_HB1
NC 59 DRX_MB1
.c
22 PRX_HB2 NC
NC 50_XCVR1_DRX_DMB2_B3 53
11 DRX_MB2
38 DRX_HB1
NC
43
w
NC DRX_HB2
w
NC OUT 67 70
PP_1V8_LDO14
1
L6200_RF
120NH-5%-40MA
2
GPS FILTER
4
0201
GNSS 1 C6201_RF PLACE NEAR U_WTR
0.1UF
20%
6.3V
2 X5R-CERM
01005
GNSS
GFILT_RF
7
GPS-GNSS
VDD DEFAULT_RESISTOR_0.001OHM_2_1 SAFGB1G56XA0F57 L6201_RF
GLNA_RF R6201_RF LGA 10NH-3%-0.170A
SKY65766-13 0.00
76
50_GNSS 1 RFIN LGA RFOUT 9 50_DRX_GPS_LNA_OUT 1 2 50_DRX_GPS_LNA_MATCH 1 UNBAL_PRT UNBAL_PRT 4 50_GPS_FILTER_OUT 1 2 50_GPS_RX 10
IN
A 3 LNA_EN 1 C6204_RF
0%
1/32W
MF
1 C6205_RF GND 1 C6203_RF
01005
SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
GND 2.0PF 01005 2.0PF 1.6PF PAGE TITLE
+/-0.1PF +/-0.1PF +/-0.1PF
spare
2
3
5
6
GNSS 2 16V
NP0-C0G 2 16V
NP0-C0G 2 16V
NP0-C0G
2
4
5
6
8
C6332_RF
2.0PF
C6340_RF OMIT_TABLE
27PF
2%
16V
1 2
50_XCVR1_PRX_PMB1_G1800
10
2 OMIT_TABLE
R6301_RF 1 CERM
01005
27PF GSM1800 4 50_XCVR1_G1800_DIPLEX_IN
+/-0.1PF RADIO_TRANSCEIVER
80 50_LAT_MLB_G1800_G1900_PA_RX 1 2 50_XCVR1_G1800_G1900_DIPLEX_OUT 1 COMMON 25V
IN C0G-CERM
5% 1 GSM1900 3 50_XCVR1_G1900_DIPLEX_IN 0201
6.3V
NP0-C0G OMIT_TABLE L6319_RF RADIO_TRANSCEIVER
C6341_RF
0201 5.1NH-3%-0.4A 27PF
RADIO_TRANSCEIVER L6320_RF GND 1 2 50_XCVR0_PRX_PMB2_G1900_MATCH 1 2
50_XCVR1_PRX_PMB2_G1900
3.6NH+/-0.1NH-0.5A C6333_RF
10
0201 0201
2.0PF 2%
D
6
5
2
RADIO_TRANSCEIVER RADIO_TRANSCEIVER
D 2
OMIT_TABLE 1 2 OMIT_TABLE 16V
CERM
01005
+/-0.1PF RADIO_TRANSCEIVER
16V OMIT_TABLE
NP0-C0G
01005
L6312_RF C6328_RF
20NH-3%-0.25A-0.8OHM 27PF
1 2 50_XCVR1_PRX_PLB1_B12_B13_B20_B28_B29_MATCH 1 2
50_XCVR1_PRX_PLB1_B12_B13_B20_B28_B29
80
50_XCVR1_B12_B13_B20_B28_B29_PA_PRX 10
IN
0201
RADIO_TRANSCEIVER NOSTUFF 2%
16V
C6314_RF L6304_RF 1 C6351_RF CERM
01005
27PF 1.6NH-+/-0.1NH-1A-0.05OHM 27PF RADIO_TRANSCEIVER
50_XCVR0_PRX_PMB5_B25 2%
50_XCVR0_B25_PA_PRX 1 2 50_XCVR0_PRX_PMB5_B25_MATCH 1 2 16V
80 IN 10 2 CERM
2% C6305_RF 0201 01005
16V 3.1NH-+/-0.1NH-0.5A-0.17OHM RADIO_TRANSCEIVER
CERM
01005
RADIO_TRANSCEIVER
1 2 L6313_RF C6329_RF
0201 15NH-3%-0.3A-0.7OHM 27PF
RADIO_TRANSCEIVER 50_XCVR1_PRX_PLB2_B8_B26_B27
OMIT_TABLE 80
50_XCVR1_B8_B26_B27_PA_PRX 1 2 50_XCVR1_PRX_PLB2_B8_B26_B27_MATCH 1 2 10
IN
OMIT_TABLE
L6305_RF C6315_RF
0201
RADIO_TRANSCEIVER NOSTUFF 2%
6.2NH-3%-0.4A 27PF
16V
50_XCVR0_PRX_PMLB6_B11_B21
1 C6352_RF CERM
01005
80
50_XCVR0_B11_B21_PA_PRX 1 2 50_XCVR0_PRX_PMLB6_B11_B21_MATCH 1 2 10 27PF
IN RADIO_TRANSCEIVER
2%
0201
C6306_RF 2%
16V
2
16V
CERM
3.0PF OMIT_TABLE CERM 01005
1 2 01005
RADIO_TRANSCEIVER
+/-0.05PF
25V
C6316_RF
C0G-CERM
0201 L6306_RF
RADIO_TRANSCEIVER 1.9NH-+/-0.1NH-0.6A-0.12OHM
C 27PF
C
m
50_XCVR0_PRX_PMB3_B3
80
50_XCVR0_B3_PRX-DSPDT_OUT 1 2 50_XCVR0_PRX_PMB3_B3_MATCH 1 2 10
IN
2% C6307_RF RADIO_TRANSCEIVER
0201
3.0NH+/-0.1NH-0.6A
o
16V
CERM
01005 1 2
RADIO_TRANSCEIVER
.c
0201
RADIO_TRANSCEIVER
L6307_RF C6342_RF
4.3NH+/-3%-0.5A 27PF
x
50_XCVR0_PRX_PMB1_B4
80
50_XCVR0_B4_PA_PRX 1 2 50_XCVR0_PRX_PMB1_B4_MATCH 1 2
IN 10
0201
C6308_RF
fi
2%
RADIO_TRANSCEIVER 16V
1.2PF CERM
1 2 01005 L6328_RF C6334_RF
3.0NH+/-0.1NH-0.6A
a
RADIO_TRANSCEIVER
+/-0.1PF
27PF 50_XCVR0_DRX_DHB2_B7_B38_B41
L6308_RF 25V
C0G-CERM
C6343_RF
74 IN
50_XCVR0_B7_B41_B38_MBHB-DRX-ASM_OUT 1 2 50_XCVR0_DRX_DHB2_B7_B38_B41_MATCH 1 2 10
in
4.3NH+/-3%-0.5A 0201
27PF 50_XCVR0_PRX_PMB2_B1_B4
C6350_RF 0201
2%
16V
50_XCVR0_B1_B4_PA_PRX 1 2 50_XCVR0_PRX_PMB2_B1_B4_MATCH 1 2 2.2PF
1
80 IN 10 CERM
25V 01005
0201
C6309_RF 2% DC BLOCKING CAP VALUES CANNOT BE MORE THAN 33PF +/-0.1PF
RADIO_TRANSCEIVER
h
RADIO_TRANSCEIVER C0G-CERM
2
1.2PF 16V
CERM 0201
1 2 01005 RADIO_TRANSCEIVER C6335_RF
RADIO_TRANSCEIVER 27PF
.c
+/-0.1PF 50_XCVR0_DRX_DHB4_B30_B40
50_XCVR0_B30_B40_MBHB-DRX-ASM_OUT 1 2
L6309_RF 25V
C0G-CERM C6317_RF
74 IN 10
w
79
50_XCVR0_B34_B39_PA_PRX 10 CERM
IN 01005
0201 C6301_RF 2%
RADIO_TRANSCEIVER
3.3NH+/-0.1NH-0.5A 16V C6336_RF
w
CERM
27PF
B
1 2
B
01005 50_XCVR1_DRX_DLB1_B12_B13_B20_B28_B29
RADIO_TRANSCEIVER 74
50_XCVR1_B12_B13_B20_B28_B29_LB-DRX-ASM_OUT 1 2 10
0201 IN
C6318_RF
27PF
RADIO_TRANSCEIVER
L6310_RF
3.9NH+/-0.1NH-0.5A
w 2%
16V
CERM
01005
RADIO_TRANSCEIVER
80 IN
50_XCVR0_B7_PA_PRX 1 2 50_XCVR0_PRX_PHB1_B7_MATCH 1 2
50_XCVR0_PRX_PHB1_B7
10 C6323_RF C6337_RF
27PF 27PF
2%
16V
C6302_RF 0201
74 IN
50_XCVR0_B34_MBHB-DRX-ASM_OUT 1 2
50_XCVR0_DRX_DMB2_B34
10 74 IN
50_XCVR1_B8_B26_B27_LB-DRX-ASM_OUT 1 2
50_XCVR1_DRX_DLB2_B8_B26_B27
10
CERM 1.0PF
01005 1 2 2% 2%
16V 16V
RADIO_TRANSCEIVER CERM CERM
+/-0.1PF 01005 01005
25V RADIO_TRANSCEIVER
C0G RADIO_TRANSCEIVER
C6310_RF 201 C6319_RF C6324_RF
50_XCVR0_B38_B40_B41_PA_PRX 1
0.00 2
RADIO_TRANSCEIVER
50_XCVR0_PRX_PHB3_B38_B40_B41_MATCH
27PF
1 2
50_XCVR0_PRX_PHB3_B38_B40_B41
50_XCVR0_B1_B4_MBHB-DRX-ASM_OUT
27PF
1 2
50_XCVR0_DRX_DMB3_B1_B4 L6324_RF C6338_RF
79 IN 10 74 IN 10 2.4NH+/-0.1NH-0.6A 27PF
1%
1/20W
L6301_RF 2% 2% 50_XCVR1_B3_DRX-DSPDT_OUT 1 2 50_XCVR1_DRX_DMB2_B3_MATCH 1 2
50_XCVR1_DRX_DMB2_B3
MF 2.5NH+/-0.1NH-0.6A 16V 16V 74 IN 10
80 IN
50_XCVR0_B11_B21_PA_DRX 1 2 50_XCVR0_DRX_DMLB6_B11_B21_MATCH 1 2 50_XCVR0_DRX_DMLB6_B11_B21 10
0201 RADIO_TRANSCEIVER
spare
2% C6348_RF 0201
OMIT_TABLE L6321_RF DRAWING NUMBER SIZE
16V
3.0PF 4.3NH+/-3%-0.5A RADIO_TRANSCEIVER C6346_RF 051-00419 D
CERM
01005 1 2 27PF 50_XCVR0_PRX_PHB2_B40_EXT
Apple Inc. REVISION
RADIO_TRANSCEIVER 50_XCVR0_B40_PA_PRX_EXT_FIL 1 2 50_XCVR0_PRX_PHB2_B40_EXT_MATCH 1 2
OMIT_TABLE +/-0.05PF
80 IN
0201
10 R
8.0.0
25V 2%
C0G-CERM RADIO_TRANSCEIVER 16V NOTICE OF PROPRIETARY PROPERTY: BRANCH
0201 CERM
RADIO_TRANSCEIVER SHUNT COMPONENT WITH BAND 40 FILTER 01005 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
OMIT_TABLE RADIO_TRANSCEIVER THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
6 OF 53
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST IV ALL RIGHTS RESERVED 6 OF 81
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
9
18PF 0.7PF
VDD 2% +/-0.05PF
25V 25V
LATDI_RF R6401_RF LATCP_RF
2 C0H-CERM
0201
2 C0G-CERM
0201
LFD21829MMY1E339 2NH+/-0.1NH-0.6A
50_LAT_LB_COMBINER_IN 6 LB 0805-LGA SKY16705-21 NOSTUFF NOSTUFF
80 BI
ANT 2 50_LAT_LB_MB_HB_COMBINER_OUT 1 2 50_LAT_LB_MB_HB_CPL_IN 1 RFIN1 LGA RFOUT1 2 50_LAT_LB_MB_HB_CPL_ANT
50_LAT_MB_HB_COMBINER_IN 4 MB-HB
80 BI 0201 13 RFIN2 RFOUT2 14
NC NC
GND 1 C6403_RF 1 C6402_RF
FL6402_RF 6 USID
10-OHM-1.1A
18PF 18PF
2% 2% PP_1V8_LDO15 1 2 PP_1V8_LDO15_LATCP 5 VIO RF_CPL1 4 50_XCVR0_LAT_CPLD
1
3
5
80 79 77 75 74 73 68 65 12
2 25V 2 25V
IN
C0H-CERM C0H-CERM 80 73 68 75_RFFE7_SDATA 01005 12 SDATA RF_CPL2 16 50_XCVR1_LAT_CPLD 12
0201 0201 BI
NOSTUFF NOSTUFF 80 73 68 75_RFFE7_SCLK 8 SCLK
IN
GND
3
7
10
11
15
18PF 18PF 0.033UF
2% 2% 20%
16V
2 CERM
16V
2 CERM
4V
2 X5R-CERM
14 13 12 4 PP_2V7_LDO12 01005 01005 01005 USID=0X6
1 C6414_RF
18PF
2%
16V
2 CERM
8
01005
VDD
C SWLATCP_RF C
m
CXA4439GC-E
70 OUT 50_XCVR0_TX_FBRX_IN 6 RF1 LGA-1 RF1A 5 50_XCVR0_LAT_CPLD 12
o
70 OUT 50_XCVR1_TX_FBRX_IN 10 RF2 RF1B 4 50_XCVR0_UAT_CPLD 12
.c
17 7 FBRX-DSPDT_CTL2 9 VCTL2 RF2B 1 50_XCVR1_LAT_CPLD 12
GND
x
3
fi
a
in
UPPER ANTENNA COUPLER
h
R6405_RF
.c
14 13 12 4 PP_2V7_LDO12 0.00
1 2 50_UAT_LB_MLB_SOUTH OUT 53 62
1 C6406_RF 1 C6408_RF 1%
1/20W
18PF 0.1UF 1 C6417_RF MF 1 C6418_RF
2% 20% 0201
9
w
16V
2 CERM
6.3V
2 X5R-CERM 18PF 18PF
2% 5%
VDD 01005 01005 25V
2 C0H-CERM 2 16V
CERM
UATDI_RF UATCP_RF 0201 01005
w
SKY16705-21 NOSTUFF NOSTUFF
B 50_UAT_LB_COMBINER_IN 6 LB
LFD21829MMY1E339
0805-LGA
R6400_RF
0.00
50_UAT_LB_MLB_CPL_IN 1 RFIN1 LGA RFOUT1 2 50_UAT_LB_MLB_CPL_OUT B
80
OMIT_TABLE ANT 2 50_UAT_LB_MLB_COMBINE 1 2 50_UAT_MB_HB_CPL_IN 13 RFIN2 RFOUT2 14 50_UAT_MB_HB_CPL_ANT
80 BI
50_UAT_MLB_COMBINER_IN 4 MB-HB
GND 1 C6405_RF
1%
1/20W
MF
0201 1 C6404_RF
19
PP_1V8_LDO15
w FL6401_RF
10-OHM-1.1A
1 2 PP_1V8_LDO15_UATCP
6 USID
25V 25V
2 C0H-CERM
80 73 68 BI 12
2 C0H-CERM 8 SCLK 1 2
0201 0201 80 73 68 IN
75_RFFE7_SCLK 50_UAT_MB_HB_SOUTH OUT 53 62
3
7
10
11
15
0.033UF
20% 2 25V
C0H-CERM 2 25V
C0G-CERM
4V
2 X5R-CERM 0201 201
NOSTUFF OMIT_TABLE
01005
USID=0X7
A SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
spare
DRAWING NUMBER SIZE
9
01005 01005
VDD R6501_RF
3.9NH+/-0.1NH-0.5A
50_XCVR1_B12_B13_B20_B28_B29_LB-DRX-ASM_OUT 2 VLB_RX0
LBDSM_RF ANT 16 50_LAT-UAT_LB-DRX-ASM_ANT 1 2 50_LB_DRX
11
HFQSWEWUA IN 80
12 VLB_RX1 LGA 0201
NC 1 C6507_RF 1 C6510_RF
50_XCVR1_B8_B26_B27_LB-DRX-ASM_OUT 3 LB_RX0
11
11
2.0PF
+/-0.1PF
2.0PF
LB_RX1 25V
+/-0.1PF
2 C0G-CERM 2 25V
C0G-CERM
0201 0201
80 79 77 75 74 73 68 65 PP_1V8_LDO15 5 VIO NOSTUFF NOSTUFF
IN
78 74 68 BI 75_RFFE3_SDATA 7 SDATA
78 74 68 75_RFFE3_SCLK 6 SCLK
IN
GND EPAD
1 C6514_RF 1 C6503_RF
19
20
21
1
4
8
10
13
14
15
17
18
18PF 0.033UF
2% 20%
2 16V 2 4V
CERM
01005
X5R-CERM
01005 USID=0X9
C C
m
o
MB HB DRX ASM
.c
x
fi
14 13 12 4 PP_2V7_LDO12
a
14 13 12 4 PP_2V7_LDO12
1 C6502_RF 1 C6506_RF
in
0.1UF 18PF
1 C6504_RF 20% 2%
18PF 2 6.3V
X5R-CERM 2 16V
CERM
2% 01005 01005
16V
2 CERM
18
h
01005
MIPI_VDD
3
50_XCVR0-1_B3_B25_MBHB-DRX-ASM_OUT 2 B3_B25_RX
.c
VDD
11 50_XCVR0_B1_B4_MBHB-DRX-ASM_OUT 3 B1_B4_RX MHBDSM_RF
SWDSM_RF 11 50_XCVR0_B30_B40_MBHB-DRX-ASM_OUT 15 B30_B40_RX D5315
CXA4430GC-E 16 LGA
2 11 50_XCVR0_B7_B41_B38_MBHB-DRX-ASM_OUT B7_B38/B41B_B41_RX
50_XCVR1_B3_DRX-DSPDT_OUT 4 RF1 LGA RFIN 13 R6502_RF
w
11
11 50_XCVR0_B34_MBHB-DRX-ASM_OUT B34_RX
50_XCVR0_B3_B25_DRX-DSPDT_OUT 6 RF2 0
11
50_XCVR0_B39_MBHB-DRX-ASM_OUT 14 B39_RX ANT1 10 50_LAT_MB-HB-DRX-ASM_ANT1 1 2 50_LAT_MB_HB_DRX
CTRL 1
RX-DSPDT_CTL2 11 IN 80
7 17
5%
w
PP_1V8_LDO15 22 MIPI_VIO 1 C6508_RF 1/20W 1 C6511_RF
B ANT2 8
B
80 79 77 75 74 73 68 65
GND 1 C6513_RF IN
MF
78 74 68 BI 75_RFFE3_SDATA 20 MIPI_SDATA 2.0PF 201 2.0PF
18PF +/-0.1PF +/-0.1PF
5
w IN
1 C6515_RF
GND THRM_PAD
C0G-CERM
0201
NOSTUFF
C0G-CERM
0201
NOSTUFF
1
4
5
6
7
9
11
12
17
19
23
24
25
26
R6503_RF
18PF 0
2% 50_UAT_MB-HB-DRX-ASM_ANT2 1 2 50_UAT_MB-HB-DRX-LNA_OUT_RX 75
2 16V
IN
CERM
01005 USID=0XA 1 C6509_RF
2.0PF
5%
1/20W
MF
1 C6512_RF
2.0PF
201
+/-0.1PF +/-0.1PF
2 25V
C0G-CERM 2 25V
C0G-CERM
0201 0201
NOSTUFF NOSTUFF
A SYNC_MASTER=Sync SYNC_DATE=04/17/2015
SYNC_DATE=05/17/2016
A
PAGE TITLE
spare
DRAWING NUMBER SIZE
10
VDD
80 79 77 75 74 73 68 65 PP_1V8_LDO15 9 VIO
75 68 BB_TO_UAT_DATA
62 BB_TO_UAT_DATA-53[I16]
7 SDATA
BI
75 68 BB_TO_UAT_SCLK
62 BB_TO_UAT_SCLK-53[I16]
8 SCLK
IN
GND EPAD
1 C6617_RF 1 C6619_RF 1 C6620_RF
18PF 18PF 0.033UF
1
2
4
5
6
11
12
13
15
16
17
18
19
20
21
22
23
24
25
2% 2% 20%
2 16V
CERM 2 16V
CERM 2 4V
X5R-CERM
01005 01005 01005
USID=0X2
R6606_RF
FL6602_RF
MB/HB DRX LNA C
C
m
0.00
50_UAT_LB_SPLIT_OUT 1 2 50_UAT_LB-DRX-LNA_TX_RX 14 150OHM-25%-200MA-0.7DCR
1%
1/20W PP_2V7_LDO12 1 2 14 PP_MHBLN_RF
o
14 13 12 4
MF
0201 01005
OMIT_TABLE 1 C6614_RF 1 C6629_RF 1 C6625_RF
UPPDI_RF 1 C6611_RF
.c
18PF 0.1UF 18PF
LFD21829MMP5E222 2% 20% 2%
R6601_RF 18PF 25V
2 C0H-CERM
6.3V
2 X5R-CERM
16V
2 CERM
0.00 2
LGA LB 4 2%
0201 01005 01005
1 2 2 25V
20
50_UUAT_LB_MLB_NORTH 50_UAT_LB_MLB_SPLIT_IN ANT OMIT_TABLE
MB-HB 6
53 BI C0H-CERM
0201 NOSTUFF
1%
x
1/20W NOSTUFF VDD
1 C6601_RFMF 1 C6602_RF
18PF
0201
18PF
GND
R6605_RF 50_UAT1_WEST 4 IN_TX
MHBLN_RF ANT 16 50_UAT_MB-HB-DRX-LNA_ANT
fi
2% 2%
2.7NH+/-0.1NH-0.6A
1 SKY13703-19 15
C0H-CERM C0H-CERM 13
0201 0201 50_UAT_MLB_SPLIT_OUT 1 2 50_UAT_MLB-DRX-LNA_TX_RX 14
NOSTUFF NOSTUFF
a
0201
OMIT_TABLE
1
in
PP_1V8_LDO15 21 VIO
80 79 77 75 74 73 68 65 IN
23 SDATA
1 C6610_RF C6613_RF 75 68 BI
BB_TO_UAT_DATA
62 BB_TO_UAT_DATA-53[I16]
BB_TO_UAT_SCLK 22 SCLK
10NH-3%-250MA 75
68 62 BB_TO_UAT_SCLK-53[I16]
IN
1.5PF GND EPAD
h
0201
+/-0.05PF
2 25V
C0G-CERM
1
3
5
6
7
8
9
10
11
12
13
14
15
17
18
19
24
25
26
27
28
0201
.c
2 OMIT_TABLE
OMIT_TABLE
USID=0X3
w
w
B
w MLB DRX LNA
FL6603_RF
B
150OHM-25%-200MA-0.7DCR
14 13 12 4 PP_2V7_LDO12 1 2 PP_MLBLN_RF
01005
1 C6627_RF 1 C6622_RF
0.1UF 18PF
20% 2%
2 6.3V
X5R-CERM 2 16V
CERM
1
01005 01005
VDD
LGA
OMIT_TABLE
80 79 77 75 74 73 68 65 PP_1V8_LDO15 2 VIO
IN
75 68 BB_TO_UAT_DATA
62 BB_TO_UAT_DATA-53[I16]
4 SDATA
BI
75 68 BB_TO_UAT_SCLK
62 BB_TO_UAT_SCLK-53[I16]
3 SCLK
IN
GND EPAD
15
16
5
7
8
9
10
11
12
14
USID=0X4
A SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
spare
DRAWING NUMBER SIZE
OMIT_TABLE
R6708_RF
1
0.00 2
75 BI
50_UAT_LB-DRX-LNA_ANT 50_UUAT_LB_PLEXER
1%
1/20W
1 C6726_RF
UAT1
MF
0201
UP_RFFE 18PF
2%
25V
2 C0H-CERM
0201
UP_RFFE
NOSTUFF
OMIT_TABLE
R6710_RF JUAT1_RF
0.00 MM8830-2600B
75 50_UUAT_MLB 1 2 50_UUAT_MLB_PLEXER
BI F-RT-SM
1% 10
PPLXR_RF 50_UAT1_TUNER
1/20W
MF 1 C6728_RF LB ACFM-W312-AP1
0201 8 MLB LGA R6705_RF R6715_RF TO ANTENNA TUNER
UP_RFFE 18PF OMIT_TABLE 0.00 0.00
2% 14 MB-HB ANT 5 50_UAT1 1 2 50_UAT1_MATCH 1 2 50_UAT1_TEST 1 2 53 62
25V
2 C0H-CERM C R BI
1 WIFI 1% 1%
0201 1/20W 1/20W
OMIT_TABLE UP_RFFE 17
R6703_RF NOSTUFF GNSS MF MF
0201 0201 GND
1
0.00 2
UP_RFFE UP_RFFE
75 BI
50_UAT_MB-HB-DRX-LNA_ANT 50_UUAT_HB_PLEXER UP_RFFE
3
1%
1/20W 1
MF 1 C6711_RF GND EPAD 1
0201 18PF C6713_RF
UP_RFFE 2% 18PF L6700_RF
2
3
4
6
7
9
11
12
13
15
16
18
19
2 25V
C0H-CERM
2%
56NH-100MA-3.9OHM
0201 2 25V
C0H-CERM
C C
0201
m
UP_RFFE 0201 UP_RFFE
NOSTUFF NOSTUFF NOSTUFF
2
o
62 53 BI 50_UAT_WLAN_2G_WEST_PLEXER
.c
x
fi
R6709_RF
1
0.00 2
71 50_GNSS 50_GNSS_PLEXER
a
1%
1/20W
MF 1 C6727_RF
0201
in
UP_RFFE 18PF
2%
2 25V
C0H-CERM
0201
UP_RFFE
NOSTUFF
h
.c
w
w
B B
w
A SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
spare
DRAWING NUMBER SIZE
PMU: ET MODULATOR
D D
C
PP_VPA_APT
C
PP_1V8_LDO15
m
18 IN 65 68 73 74 75 79 80
19 18 PP_QPOET_VCC_PA
PP_VDD_MAIN
o
53 62 64 65 77 81
PP_PA_VBATT 1 1 C6805_RF
19 18
1 C6801_RF 1 C6802_RF
1 C6803_RF C6804_RF
2.2UF 2.2UF 2.2UF
.c
2.2UF
20%
2.2UF 20% 20% 20%
20% 6.3V 6.3V 2 6.3V
6.3V 6.3V 2 2 X5R-CERM X5R-CERM
2 X5R-CERM 2 X5R-CERM X5R-CERM 0201-1
0201-1 0201-1
VDD_1P8 15
VDD_BUCK 20
VDD_BUCK 21
VDD_LDO 24
VDD_LDO 25
VDD_VBATT 12
VDD_VBATT 13
PA_VBATT 10
0201-1 0201-1
VCC_PA_ET 5
VCC_PA_ET 6
VCC_PA_GSM 7
VCC_PA_GSM 8
x
fi
SHIELD_ET_DAC_P 2 AMP_IN+ TRIM_14 26
a
67 IN
SHIELD_ET_DAC_N 3 23
AMP_IN- TRIM_18
67 IN
QPOET_RF NC
2103-601507-10
in
17 7 75_RFFE2_SCLK 17 SCLK USID_LSB 19
16 LGA
17 7 75_RFFE2_SDATA SDATA
GND
h
4
11
18
27
28
29
30
31
32
1
9
14
22
.c
w
w
B B
w DESENSE CAPS
81 77 65 64 62 53 IN
PP_VDD_MAIN
1 C6806_RF 1 C6807_RF
100PF 27PF
5% 2%
16V
2 16V
NP0-C0G
2 CERM
01005 01005
A SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
spare
DRAWING NUMBER SIZE
OMIT
PP
OMIT 2 2
OMIT PP6900_RF 7 FAST_BOOT_SELECT1
P2MM-NSM
PP6943_RF
P2MM-NSM PP6921_RF SM 7 FAST_BOOT_SELECT0
SM PP6908_RF P2MM-NSM PP
1 PMU_TO_BBPMU_RESET_L 1 3
1 P2MM-NSM SM
75_RFFE2_SDATA 7 16 SM OMIT
PP 1 FBRX-DSPDT_CTL2 7 12
OMIT PP
1 NFC_TO_BB_CLK_REQ 1 3
PP
OMIT
OMIT
PP6944_RF PP6923_RF
P2MM-NSM P2MM-NSM
SM PP6909_RF SM
1 P2MM-NSM 1
PP
75_RFFE2_SCLK 7 16 SM PP
BB_TO_PMU_PCIE_HOST_WAKE_L 1 7
PP
1 75_RFFE3_SDATA 7 13
P2MM-NSM
SM
PP
1 SPMI_CLK 3 6
SIM
OMIT OMIT
PP6911_RF
P2MM-NSM
SM PP6925_RF
PP6940_RF 1 50_MDM_PCIE_CLK
P2MM-NSM PP6953_RF
P2MM-NSM PP 3 6 SM P2MM-NSM
SM SM
OMIT 1 SPMI_DATA 3 6
1 75_RFFE3_SCLK 7 13
PP 1 SIM1_IO 7 20
PP PP
OMIT
C C
m
OMIT OMIT
PP6912_RF PP6926_RF
PP6941_RF P2MM-NSM P2MM-NSM PP6969_RF
P2MM-NSM SM SM P2MM-NSM
SM SM
o
1 XO_OUT_D0_EN 3 6 1 UART_BB_TO_AOP_RXD 1 7
1 75_RFFE4_SDATA 7 9
PP PP 1 SIM1_DETECT 7 20
PP PP
OMIT OMIT
OMIT OMIT
.c
PP6913_RF
P2MM-NSM
PP6942_RF SM PP6972_RF
P2MM-NSM 1 P2MM-NSM
SM PP
BB_TO_NFC_CLK 1 3 SM
x
1 75_RFFE4_SCLK 7 9 OMIT 1 SIM1_RST 7 20
PP PP
OMIT OMIT
PP6929_RF
fi
PP6914_RF P2MM-NSM
PP6903_RF P2MM-NSM SM PP6973_RF
P2MM-NSM SM
1 P2MM-NSM
SM AP_TO_BB_TIME_MARK 1 7 SM
1 SHIELD_SLEEP_CLK_32K PP
a
3 6
PP
1 BB_TO_LAT_ANT_DATA 1 7
PP
OMIT PP
1 SIM1_CLK 7 20
OMIT
OMIT OMIT
in
PP6930_RF
PP6904_RF P2MM-NSM PP6974_RF
P2MM-NSM SM P2MM-NSM
SM PP6933_RF 1 BB_TO_AP_RESET_DETECT_L
SM
1 P2MM-NSM PP 1 7
1
PP
BB_TO_LAT_ANT_SCLK 1 7 SM PP
90_USB_BB_DATA_P 1 6 20
h
1 OMIT
OMIT PP
BB_TO_STROBE_DRIVER_GSM_BURST_IND
1 7 OMIT
PP6931_RF
ICEFALL
OMIT
PP6935_RF PP6977_RF
.c
P2MM-NSM
P2MM-NSM SM P2MM-NSM
SM SM
1 AP_TO_BB_COREDUMP
1 75_RFFE6_SCLK PP 1 7
1 90_USB_BB_DATA_N
PP 7 18 19
PP6917_RF OMIT
PP 1 6 20
w
SM
1 P2MM-NSM P2MM-NSM
UART_BB_TO_WLAN_COEX SM SM
PP6936_RF PP 1 7 20
w
PP 1 20 PP 1 20
B
SM
B PP
1 75_RFFE6_SDATA 7 18 19
OMIT OMIT
OMIT PP6918_RF
P2MM-NSM
SM
PP
OMIT
1 UART_WLAN_TO_BB_COEX 1 7 20
PP6938_RF
P2MM-NSM
SM
1
w
RX-DSPDT_CTL2 7 13
PP6979_RF
P2MM-NSM
SM
PP
1 SIM1_SWP 20
PP7501_RF
P2MM-NSM
SM
PP
1 NFC_SWP_MUX 1 20
PP
OMIT OMIT
OMIT
PP6980_RF
P2MM-NSM PP7502_RF
SM P2MM-NSM
SM
1 SE2_SWP
PCIE
20
PP 1 SE2_PWR_REQ 1 20
PP
OMIT
PP6915_RF OMIT
P2MM-NSM
SM
PP
1 90_PCIE_AP_TO_BB_REFCLK_P 1 6 PP6981_RF
P2MM-NSM
OMIT SM
1 ICEFALL_LDO_ENABLE 1 20
PP
PP6916_RF OMIT
P2MM-NSM
SM
1 90_PCIE_AP_TO_BB_REFCLK_N 1 6
PP
OMIT
PCIE GND
PP6970_RF PP6971_RF
P2MM-NSM P2MM-NSM
A SM
PP
1
SM
PP
1 SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
OMIT OMIT
spare
DRAWING NUMBER SIZE
TDD TRANSMIT
D 2G PA D
FL7001_RF
600-OHM-25%-0.1A
PP_PA_VBATT PP_VPA_APT
19 16
1 2 2GPA_VBATT 16
0201-1
1 C7006_RF 1 C7007_RF 1 C7008_RF 1 C7001_RF
1 C7004_RF 1 C7005_RF
1.0UF 27PF
2.2UF 2.2UF 18PF 0.1UF
20% 20% 2% 20%
20% 5% 6.3V
2 X5R-CERM
6.3V
2 X5R-CERM
16V
2 CERM
6.3V
2 X5R-CERM
6.3V 16V
2 X5R 2 NP0-C0G 0201-1 0201-1 01005 01005
0201-1 01005
3
VBATT VCC C7011_RF
GSMPA_RF 1
27PF
2
50_TX_G850_G900_PA_OUT_M
SKY77363 50_TX_G850_G900_PA_OUT OUT 80
LGA 5%
70 50_XCVR1_TX_G850_G900_PA_IN 7 LBRFIN LBRFOUT 1 6.3V
IN 1 C7009_RF NP0-C0G 1 C7013_RF
0201
70 50_XCVR1_TX_G1800_G1900_PA_IN 12 HBRFIN HBRFOUT 6 18PF 18PF
IN 2% 2%
2 25V
C0H-CERM 2 25V
C0H-CERM
80 79 77 75 74 73 68 65 PP_1V8_LDO15 11 VIO 0201 0201
IN
9 SDATA NOSTUFF NOSTUFF
80 79 78 68 BI 75_RFFE6_SDATA
80 79 78 68 75_RFFE6_SCLK 10 SCLK
IN
C C
m
GND C7012_RF
EPAD 27PF
1 C7017_RF 50_TX_G1800_G1900_PA_OUT_M
1 2
MB HB TDD PA
50_TX_G1800_G1900_PA_OUT
2
4
5
13
80
27PF OUT
o
5%
2 16V
NP0-C0G
5%
6.3V
01005 1 C7010_RF NP0-C0G 1 C7014_RF
.c
0201
18PF 18PF
2% 2%
USID=0X5 25V
2 C0H-CERM
0201
25V
2 C0H-CERM
0201
NOSTUFF NOSTUFF PP_1V8_LDO15
x
IN 65 68 73 74 75 77 79 80
75_RFFE6_SDATA BI 68 78 79 80
fi
19 16 PP_QPOET_VCC_PA
1 C7016_RF
5.6PF
20% MF
75_RFFE6_SCLK 68 78 79 80
+/-0.1PF
IN 16V
2 NP0-C0G
01005
R7002_RF
in
01005
MLB_PA_VBATT
19 0.00 1 C7015_RF
5.6PF
1/32W
1
+/-0.1PF
h
2 16V
NP0-C0G
TDD_PAD_VCC1 01005
.c
VBATT 11
VIO 14
SDATA 12
SCLK 13
VCC1 8
VCC2 9
w
TDDPA_RF
w
B 70 IN
50_XCVR0_TX_B34_B39_PA_IN 3 RFIN_MB AFEM-8065-AP1 B
LGA-1
w 70 IN
50_XCVR0_TX_B38_B40_B41_PA_IN 5 RFIN_HB
ANT 16 50_TDD_PA_ANT_M
OUT 80
72 50_XCVR0_B38_B40_B41_PA_PRX 27 RX_B38_B40_B41
OUT
72 50_XCVR0_B34_B39_PA_PRX 25 RX_B34_B39
OUT
GND THRM_PAD
1
2
4
6
7
10
15
17
19
21
22
24
26
28
23
20
18
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
USID=0XF
A SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
spare
DRAWING NUMBER SIZE
FDD TRANSMIT
19 18 16 PP_QPOET_VCC_PA DEFAULT_RESISTOR_0.001OHM_2_1
NOSTUFF
1
1%
R7130_RF
1.00 PP_1V8_LDO15_PA R7112_RF
1
R7114_RF
10-OHM-1.1A
2 PP_1V8_LDO15 65 68 73 74 75 77 79 80
DEFAULT_RESISTOR_0.001OHM_2_1 IN
R7107_RF 1/32W R7111_RF 0.00
MF 75_RFFE7_SDATA_PA 1 2 01005 75_RFFE7_SDATA BI 68 73
0.00 1 1 C7105_RF 0.00
19 18 16 PP_PA_VBATT 1 2 LB_PA_VBATT R7108_RF 2 01005 75_RFFE7_SCLK_PA 1 2 0% 75_RFFE7_SCLK 68 73
DEFAULT_CAPACITOR_1e+06pF_2_1 0.00 18PF LB_SNUBBER 1/32W IN
2%
0%
1/32W
MF 1 C7103_RF 1 C7104_RF
0%
1/32W
16V
2 CERM 1 C7130_RF 1 C7126_RF 1 C7127_RF 1 C7101_RF 1/32W
MF
0% MF
01005 1 C7128_RF 1 C7129_RF 1 C7133_RF
01005
1.0UF 18PF
MF 01005 68PF 33PF 0.033UF
20%
180PF 01005 33PF 0.033UF
20%
0.033UF
2 01005 2% 5% 10% 5% 20%
20% 2% 6.3V 16V 4V 10V 16V 4V 4V
6.3V 16V 2 NP0-C0G 2 NP0-C0G-CERM 2 X5R-CERM 2 CERM 2 NP0-C0G-CERM 2 X5R-CERM 2 X5R-CERM
2 X5R 2 CERM LB_PAD_VCC1 01005 01005
01005 01005 01005 01005 01005
0201-1 01005 NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF
R7101_RF D
VCC1 41
VCC2 40
VIO 10
D
VBATT 7
SDATA 8
SCLK 9
18PF
50_LAT_LB_PA_ANT 1 2 50_LAT_LB_COMBINER_IN 73
BI
2%
LBPA_RF 1 25V
C0H-CERM
2 RFIN0 SKY78100-14 0201
70 IN
50_XCVR1_TX_B8_B20_B26_B27_PA_IN
LGA1 C7111_RF
1 C7120_RF
50_XCVR1_TX_B12_B13_B28_PA_IN 3 RFIN1 1.0PF 824-915
70 IN 22NH-3%-0.25A +/-0.1PF
25V
0201 2 C0G
18 201
LB PA
79 IN
50_TX_G850_G900_PA_OUT_M 2G_TX
OMIT_TABLE
12 ANT1 16 2
74 OUT 50_LB_DRX LB_DIV
72 OUT
50_XCVR1_B8_B26_B27_PA_PRX 26 LB_RX0 ANT2 14
25 LB_RX1 R7102_RF
NC 0.00
50_UAT_LB_PA_ANT 1 2 50_UAT_LB_COMBINER_IN 824-915
72 50_XCVR1_B12_B13_B20_B28_B29_PA_PRX 24 VLB_RX0 BI 73
OUT
1%
23 1/20W
NC VLB_RX1 1 C7112_RF
MF 1 C7121_RF
0201
18PF 18PF
2% 2%
GND THRM_PAD
2 25V
C0H-CERM 2 25V
C0H-CERM
0201 0201
NOSTUFF NOSTUFF
1
4
5
6
11
13
15
17
19
20
21
22
27
28
29
30
31
32
33
34
35
36
37
38
39
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
NOSTUFF
1
R7131_RF
USID=0XD 1%
1.00
1/32W
MF
19 18 16 PP_QPOET_VCC_PA DEFAULT_RESISTOR_0.001OHM_2_1 2 01005
R7113_RF MLB_TDD_SNUBBER
C C7131_RF C
m
0.00 1 C7117_RF 1
PP_PA_VBATT 1 2 18 MLB_PA_VBATT
19 18 16
18PF 68PF
0% 2% 2%
1/32W 16V
2 CERM 2 6.3V
o
MF 1 C7113_RF 1 C7114_RF NP0-C0G
01005 01005 01005
1.0UF 18PF NOSTUFF PP_1V8_LDO15 65 68 73 74 75 77 79 80
20% 2% IN
16V
.c
2 6.3V 2 CERM 75_RFFE6_SDATA 68 78 79 80
X5R BI
0201-1 01005 75_RFFE6_SCLK 68 78 79 80
IN
VBATT 25
VCC1 28
VCC2 27
VIO 22
SDATA 24
SCLK 23
x
fi
RXFIL_RF MLBPA_RF
BAW-B40F-RX 50_XCVR0_TX_B11_B21_PA_IN 2 RFIN_MLB HRPDAF025
a
70 IN R7105_RF
QM21140
LGA LGA 1
0.00
2
50_LAT_MLB_G1800_G1900_PA_RX
BI 72 1428-1463
OMIT_TABLE 80
in
1%
19 50_XCVR0_B40B_PA_PRX 1 B40RXOUT B40ANT 4 50_XCVR0_B40_PA_PRX_EXT_FIL 72 1/20W
OUT MF
1 C7122_RF
MLB PA
GND 0201
ANT1 14 50_LAT_MLB_PA_ANT
18PF OMIT_TABLE
2%
h
2 25V
6
5
3
2
1 C0H-CERM
ANT2 12 50_UAT_MLB_PA_ANT 0201
.c
L7122_RF
1 L7123_RF NOSTUFF
1.0PF 20
4.7NH-3%-0.270A
01005
+/-0.1PF
2 16V
72 OUT
50_XCVR0_B11_B21_PA_PRX PRX
R7106_RF 1428-1463
NP0-C0G 50_XCVR0_B11_B21_PA_DRX 18 DRX 1.8NH+/-0.1NH-0.8A
w
01005 72 OUT
50_UAT_MLB_COMBINER_IN
1 2 73
BI
2
0201
OMIT_TABLE
w
B
GND THRM_PAD 1 C7123_RF B
0.6PF
NOSTUFF +/-0.05PF
1
3
4
5
6
7
8
9
10
11
13
15
16
17
19
21
26
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
w 1
1%
R7132_RF
1.00
1/32W USID=0XB
2 25V
CERM
0201
OMIT_TABLE
MF
PP_QPOET_VCC_PA DEFAULT_RESISTOR_0.001OHM_2_1
19 18 16
2 01005
R7109_RF MBHB_SNUBBER
PP_PA_VBATT 1
0.00
2 MBHB_FDD_PA_VBATT
1
R7110_RF
1 C7110_RF 1 C7132_RF
19 18 16
DEFAULT_CAPACITOR_1e+06pF_2_1 0.00
18PF 68PF
0% 2% 2%
1/32W 0% 16V
2 CERM 2 6.3V
MF 1 C7106_RF 1 C7108_RF 1/32W NP0-C0G
01005 MF 01005 01005
1.0UF 18PF 2 01005 NOSTUFF PP_1V8_LDO15 65 68 73 74 75 77 79 80
20% 2% IN
2 6.3V 16V
2 CERM 75_RFFE6_SDATA 68 78 79 80
X5R BI
0201-1 01005 MBHB_FDD_PAD_VCC1 75_RFFE6_SCLK IN 68 78 79 80
29
37
38
26
28
27
VBATT
VCC1
VIO
SDATA
SCLK
VCC2
79 50_TX_G1800_G1900_PA_OUT_M 34 RFIN_GSM
IN
70 50_XCVR0_TX_B1_B3_B4_B25_PA_IN 31 RFIN_MB
IN
70 IN
50_XCVR0_TX_B7_B30_PA_IN 32 RFIN_HB MBHBPA_RF R7103_RF
AFEM-8055-AP1 1.8NH+/-0.1NH-0.8A
LGA 50_LAT_MB_HB_PA_ANT 1 2 50_LAT_MB_HB_COMBINER_IN
79 50_TDD_PA_ANT_M 7 TRX2 BI 73
IN 0201
8 1710-2690
80 72 OUT
50_LAT_MLB_G1800_G1900_PA_RX TRX3
1 NOSTUFF
C7118_RF
1 C7124_RF
14
MB/HB PA
10 ANT1 18PF 18PF
74 OUT
50_LAT_MB_HB_DRX MB_HB_DRX 2% 2%
11 2 25V 2 25V
A DCS_PCS_RX
50_XCVR0_B40B_PA_PRX
A
19
C0H-CERM C0H-CERM
13 0201 0201
1 ANT2 R7104_RF NOSTUFF SYNC_DATE=04/17/2015
RX_B1
SYNC_MASTER=Sync
50_XCVR0_B1_B4_PA_PRX
SYNC_DATE=05/17/2016
72
OUT
50_XCVR0_B25_PA_PRX 19 RX_B25 1 C7119_RF
1 C7125_RF
Apple Inc. 051-00419 D
OUT 18PF REVISION
50_XCVR0_B30_PA_PRX 21 RX_B30 0.1PF 2%
72
2
+/-0.05PF
25V
25V
2 C0H-CERM
R
8.0.0
GND EPAD C0G 0201 NOTICE OF PROPRIETARY PROPERTY: BRANCH
0201 NOSTUFF
OMIT_TABLE THE INFORMATION CONTAINED HEREIN IS THE
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
2
4
12
15
16
18
20
22
23
24
25
30
33
35
36
39
40
41
42
6
9
6 OF 81
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VDD1P2 C2
VDD1P8 C3
VDD1P8_BYP D2
VDDC C5
VDDC E5
VDDO_HOST_2 A5
VDDO_NFC E1
0201 SE2 1UF 01005 5 VCC
0201 SE2 OMIT_TABLE 1UF 20% SE2 GND 2
SE2 20% 10V
2 X5R
2 10V
X5R 0201
OMIT_TABLE 0201 SE2
NOSTUFF SE2 4 A B0 3 SIM1_SWP 17 20
OMIT_TABLE
R7510_RF VER 1
OMIT_TABLE
PP1V8_SDRAM 0.00
1 7 20
62 53 NFC_SWP 1 2 NFC_SWP_R
IN
1
SE2_RF 0%
1/32W
R7506_RF B3 SPI_CLK BCM20211CP DB_RX B4 AP_TO_ICEFALL_FW_DWLD_REQ MF
NC WLBGA
IN 53 62 78
01005
4.99K A3 SPI_CS DB_TX A4 NFC
1% NC NC
1/32W B1 SPI_INT
MF NC
A1 DWP E2 NC
2 01005 SPI_MISO
ICEFALL LDO
NFC NC SWP E3 SE2_SWP
OMIT_TABLE A2 SPI_MOSI
17 20
NC
SE2_PRESENT SE2_READY E4 GPIO_0 REG_PU D3 SE2_PWR_REQ IN 53 62 78
53 OUT 78 62 53
D4 GPIO_1 TCAL_CLK B2
NC NC
C1 NC OMIT_TABLE
VSS
VSS
VSS
VSS
1
R7512_RF SE2
SE2LDO_RF
10K LP5907UVX-1.825-S
B5
D5
C4
D1
OMIT_TABLE
1%
A1 VIN DSBGA
1/32W 20 16 4 3 1 PP_VDD_MAIN VOUT A2 PP1V8_ICEFALL_LDO 20
MF
2 01005
C C
m
OMIT_TABLE 17 1 ICEFALL_LDO_ENABLE B1 VEN
1 C7530_RF GND
1 C7529_RF
2.2UF
B2
2.2UF
o
20%
2 6.3V 20%
R7511_RF X5R-CERM
0201-1
6.3V
2 X5R-CERM
0201-1
1 C7531_RF
100PF
.c
0.00 SE2
81 68 62 53 PP1V8_SDRAM 1 2 PP1V8_ICEFALL_LDO 20 OMIT_TABLE SE2 5%
IN 6.3V
OMIT_TABLE 2 CERM
1% 01005
1/20W
MF OMIT_TABLE
0201
DEBUG CONNECTOR
x
NOSTUFF
fi
a
20 17 7 SIM1_IO 20 17 SIM1_SWP
J_DEBUG
in
20-5857-036-001-829
F-ST-SM
1 1 41
DZ6905_RF DZ6902_RF 20 16 4 3 1 PP_VDD_MAIN 37 38
h
SG-WLL-2-2 SG-WLL-2-2
9 SIM_DETECT_GND SIM_DETECT 8 SIM1_DETECT OUT 68 78 81
ESD202-B1-CSP01005 ESD202-B1-CSP01005
SIM SIM 1 2
.c
2 2 17 3 1 PMU_TO_BB_USB_VBUS_DETECT VDD_SIM1 4 5 20
81 78 68 IN
SIM1_CLK 3 CLK J_SIM_RF IO 7 SIM1_IO BI 68 78 81 78 67 62 53 BI 90_USB_BB_DATA_P 3 4 SIM1_RST IN 68 78 81
w
81 78 68 IN 17 20 78 64 62 53 OUT BI 68 78 81
SIM 9 10 SIM1_SWP 17 20
1 2 11 12
20 5 4 VDD_SIM1 VCC
DZ6900_RF SIM1_RST SIM1_CLK
SIM1_DETECT OUT 68 78 81
w
GND 20 17 7 20 17 7
13 14
5.5V-6.2PF
B
1 C6900_RF
B 1
0201 15 16
14
15
16
5
10
11
12
13
2.2UF DZ6901_RF
20% 1 C6901_RF 17 18
12V-33PF SIM AP_TO_BB_RESET_L
20 5 4 VDD_SIM1
6.3V
2 X5R-CERM
0201-1
SIM
2 01005-1
SIM
1
100PF
5%
2 16V
NP0-C0G
01005
w 1
DZ6903_RF
SG-WLL-2-2
1
DZ6904_RF
SG-WLL-2-2
64
67
67
62 53
62 53
62 53
OUT
OUT
OUT
SWD_AP_TO_MANY_SWCLK
SWD_AOP_BI_BB_SWDIO
19
21
23
20
22
24
SIM ESD202-B1-CSP01005 ESD202-B1-CSP01005
SIM SIM 25 26 BB_JTAG_RST_L 67 78
OUT
2 2 27 28 UART_BB_TO_WLAN_COEX IN 53 62 68 78
1 29 30 UART_WLAN_TO_BB_COEX
R6900_RF IN 53 62 68 78
15.00K 4 1 PP_VDD_BOOST 31 32
1% 17 7 6 5 4 PP_1V8_LDO6
1/32W 33 34
MF 35 36
2 01005
SIM
39 40
20 17 7 SIM1_IO 42
NOSTUFF
1
R6904_RF
100K
1%
1/32W
MF
01005 2
SIM
SIM1_DETECT 7 17 20
A SYNC_MASTER=Sync SYNC_DATE=05/17/2016
A
PAGE TITLE
spare
DRAWING NUMBER SIZE