Nxbyte Arm-Legv8

nxbyte / ARM-LEGv8 Public
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ARM-LEGv8 / Pipelined-Only / ARM_CPU.v
nxbyte Improving source formatting History
1 contributor
ARM-LEGv8/ARM_CPU.v at master · nxbyte/ARM-LEGv8 · GitHub https://github.com/nxbyte/ARM-LEGv8/blob/master/Pipelined-Only...
32
33 /* Stage : Instruction Fetch */
34 wire PCSrc_wire;
35 wire [63:0] jump_PC_wire;
36 wire [63:0] IFID_PC;
37 wire [31:0] IFID_IC;
38 IFID cache1 (CLOCK, PC, IC, IFID_PC, IFID_IC);
39
40
41 /* Stage : Instruction Decode */
42 wire [1:0] CONTROL_aluop; // EX
43 wire CONTROL_alusrc; // EX
44 wire CONTROL_isZeroBranch; // M
45 wire CONTROL_isUnconBranch; // M
46 wire CONTROL_memRead; // M
47 wire CONTROL_memwrite; // M
48 wire CONTROL_regwrite; // WB
49 wire CONTROL_mem2reg; // WB
50 ARM_Control unit1 (IFID_IC[31:21], CONTROL_aluop, CONTROL_alusrc, CONTROL_isZeroBranch, CONTROL_isUn
51
52 wire [4:0] reg2_wire;
53 ID_Mux unit2(IFID_IC[20:16], IFID_IC[4:0], IFID_IC[28], reg2_wire);
54
55 wire [63:0] reg1_data, reg2_data;
56 wire MEMWB_regwrite;
57 wire [4:0] MEMWB_write_reg;
58 wire [63:0] write_reg_data;
59 Registers unit3(CLOCK, IFID_IC[9:5], reg2_wire, MEMWB_write_reg, write_reg_data, MEMWB_regwrite, reg
60
61 wire [63:0] sign_extend_wire;
62 SignExtend unit4 (IFID_IC, sign_extend_wire);
63
64 wire [1:0] IDEX_aluop;
65 wire IDEX_alusrc;
66 wire IDEX_isZeroBranch;
67 wire IDEX_isUnconBranch;
68 wire IDEX_memRead;
69 wire IDEX_memwrite;
70 wire IDEX_regwrite;
71 wire IDEX_mem2reg;
72 wire [63:0] IDEX_reg1_data;
73 wire [63:0] IDEX_reg2_data;
74 wire [63:0] IDEX_PC;
75 wire [63:0] IDEX_sign_extend;
76 wire [10:0] IDEX_alu_control;
77 wire [4:0] IDEX_write_reg;
78 IDEX cache2 (CLOCK, CONTROL_aluop, CONTROL_alusrc, CONTROL_isZeroBranch, CONTROL_isUnconBranch, CONT
79
80
81 /* Stage : Execute */
82 wire [63:0] shift_left_wire;
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83 wire [63:0] PC_jump;

84 wire jump_is_zero;
85 Shift_Left unit5 (IDEX_sign_extend, shift_left_wire);
86 ALU unit6 (IDEX_PC, shift_left_wire, 4'b0010, PC_jump, jump_is_zero);
87
88 wire [3:0] alu_main_control_wire;
89 wire [63:0] alu_data2_wire;
90 wire alu_main_is_zero;
91 wire [63:0] alu_main_result;
92 ALU_Control unit7(IDEX_aluop, IDEX_alu_control, alu_main_control_wire);
93 ALU_Mux mux3(IDEX_reg2_data, IDEX_sign_extend, IDEX_alusrc, alu_data2_wire);
94 ALU main_alu(IDEX_reg1_data, alu_data2_wire, alu_main_control_wire, alu_main_result, alu_main_is_zer
95
96 wire EXMEM_isZeroBranch;
97 wire EXMEM_isUnconBranch;
98 wire EXMEM_regwrite;
99 wire EXMEM_mem2reg;
100 wire EXMEM_alu_zero;
101 wire [4:0] EXMEM_write_reg;
102 EXMEM cache3(CLOCK, IDEX_isZeroBranch, IDEX_isUnconBranch, IDEX_memRead, IDEX_memwrite, IDEX_regwrit
103
104
105 /* Stage : Memory */
106 Branch unit8 (EXMEM_isUnconBranch, EXMEM_isZeroBranch, EXMEM_alu_zero, PCSrc_wire);
107
108 wire MEMWB_mem2reg;
109 wire [63:0] MEMWB_address;
110 wire [63:0] MEMWB_read_data;
111 MEMWB cache4(CLOCK, mem_address_out, mem_data_in, EXMEM_write_reg, EXMEM_regwrite, EXMEM_mem2reg, ME
112
113
114 /* Stage : Writeback */
115 WB_Mux unit9 (MEMWB_address, MEMWB_read_data, MEMWB_mem2reg, write_reg_data);
116 endmodule
117
118
119 module IFID
120 (
121 input CLOCK,
122 input [63:0] PC_in,
123 input [31:0] IC_in,
124 output reg [63:0] PC_out,
125 output reg [31:0] IC_out
126 );
127
128 always @(negedge CLOCK) begin
129 PC_out <= PC_in;
130 IC_out <= IC_in;
131 end
132 endmodule
133
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134
135 module IDEX
136 (
137 input CLOCK,
138 input [1:0] aluop_in, // EX Stage
139 input alusrc_in, // EX Stage
140 input isZeroBranch_in, // M Stage
141 input isUnconBranch_in, // M Stage
142 input memRead_in, // M Stage
143 input memwrite_in, // M Stage
144 input regwrite_in, // WB Stage
145 input mem2reg_in, // WB Stage
146 input [63:0] PC_in,
147 input [63:0] regdata1_in,
148 input [63:0] regdata2_in,
149 input [63:0] sign_extend_in,
150 input [10:0] alu_control_in,
151 input [4:0] write_reg_in,
152 output reg [1:0] aluop_out, // EX Stage
153 output reg alusrc_out, // EX Stage
154 output reg isZeroBranch_out, // M Stage
155 output reg isUnconBranch_out, // M Stage
156 output reg memRead_out, // M Stage
157 output reg memwrite_out, // M Stage
158 output reg regwrite_out, // WB Stage
159 output reg mem2reg_out, // WB Stage
160 output reg [63:0] PC_out,
161 output reg [63:0] regdata1_out,
162 output reg [63:0] regdata2_out,
163 output reg [63:0] sign_extend_out,
164 output reg [10:0] alu_control_out,
165 output reg [4:0] write_reg_out
166 );
167
169 /* Values for EX */
170 aluop_out <= aluop_in;
171 alusrc_out <= alusrc_in;
172
173 /* Values for M */
174 isZeroBranch_out <= isZeroBranch_in;
175 isUnconBranch_out <= isUnconBranch_in;
176 memRead_out <= memRead_in;
177 memwrite_out <= memwrite_in;
178
179 /* Values for WB */
180 regwrite_out <= regwrite_in;
181 mem2reg_out <= mem2reg_in;
182
183 /* Values for all Stages */
184 PC_out <= PC_in;
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185 regdata1_out <= regdata1_in;

186 regdata2_out <= regdata2_in;
187
188 /* Values for variable stages */
189 sign_extend_out <= sign_extend_in;
190 alu_control_out <= alu_control_in;
191 write_reg_out <= write_reg_in;
192 end
193 endmodule
194
195
196 module EXMEM
197 (
198 input CLOCK,
199 input isZeroBranch_in, // M Stage
200 input isUnconBranch_in, // M Stage
201 input memRead_in, // M Stage
202 input memwrite_in, // M Stage
203 input regwrite_in, // WB Stage
204 input mem2reg_in, // WB Stage
205 input [63:0] shifted_PC_in,
206 input alu_zero_in,
207 input [63:0] alu_result_in,
208 input [63:0] write_data_mem_in,
210 output reg isZeroBranch_out, // M Stage
211 output reg isUnconBranch_out, // M Stage
212 output reg memRead_out, // M Stage
213 output reg memwrite_out, // M Stage
214 output reg regwrite_out, // WB Stage
215 output reg mem2reg_out, // WB Stage
216 output reg [63:0] shifted_PC_out,
217 output reg alu_zero_out,
218 output reg [63:0] alu_result_out,
219 output reg [63:0] write_data_mem_out,
220 output reg [4:0] write_reg_out
221 );
222
224 /* Values for M */
225 isZeroBranch_out <= isZeroBranch_in;
226 isUnconBranch_out <= isUnconBranch_in;
227 memRead_out <= memRead_in;
228 memwrite_out <= memwrite_in;
229
230 /* Values for WB */
233
234 /* Values for all Stages */
235 shifted_PC_out <= shifted_PC_in;
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236 alu_zero_out <= alu_zero_in;

237 alu_result_out <= alu_result_in;
238 write_data_mem_out <= write_data_mem_in;
240 end
241 endmodule
242
243
244 module MEMWB
245 (
246 input CLOCK,
247 input [63:0] mem_address_in,
248 input [63:0] mem_data_in,
250 input regwrite_in,
251 input mem2reg_in,
252 output reg [63:0] mem_address_out,
253 output reg [63:0] mem_data_out,
254 output reg [4:0] write_reg_out,
255 output reg regwrite_out,
256 output reg mem2reg_out
257 );
258
262 mem_address_out <= mem_address_in;
263 mem_data_out <= mem_data_in;
265 end
266 endmodule
267
268
269 module Registers
270 (
271 input CLOCK,
272 input [4:0] read1,
273 input [4:0] read2,
274 input [4:0] writeReg,
275 input [63:0] writeData,
276 input CONTROL_REGWRITE,
277 output reg [63:0] data1,
278 output reg [63:0] data2
279 );
280
281 reg [63:0] Data[31:0];
282
283 integer initCount;
284
285 initial begin
286 for (initCount = 0; initCount < 31; initCount = initCount + 1) begin
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287 Data[initCount] = initCount;

288 end
289
290 Data[31] = 64'h00000000;
291 end
292
293 always @(posedge CLOCK) begin
294
295 data1 = Data[read1];
296 data2 = Data[read2];
297
298 if (CONTROL_REGWRITE == 1'b1) begin
299 Data[writeReg] = writeData;
300 end
301
302 // Debug use only
304 $display("REGISTER[%0d] = %0d", initCount, Data[initCount]);
305 end
306 end
307 endmodule
308
309
310 module IC
311 (
312 input [63:0] PC_in,
313 output reg [31:0] instruction_out
314 );
315
316 reg [8:0] Data[63:0];
317
318 initial begin
319 // CBZ x31 #5 (Set PC = (5*4) = 20)
320 /*
321 Data[0] = 8'hb4;
322 Data[1] = 8'h00;
323 Data[2] = 8'h00;
324 Data[3] = 8'hbf;
325 /*
326
327 // B #1 (Set PC = (1*4) = 8)
328 /*
329 Data[0] = 8'h14;
330 Data[1] = 8'h00;
331 Data[2] = 8'h00;
332 Data[3] = 8'h01;
333 */
334
335 // LDUR x2, [x9, #1]
336 Data[0] = 8'hf8;
337 Data[1] = 8'h40;
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338 Data[2] = 8'h11;

339 Data[3] = 8'h22;
340
341 // ADD x3, x10, x5
342 Data[4] = 8'h8b;
343 Data[5] = 8'h05;
344 Data[6] = 8'h01;
345 Data[7] = 8'h43;
346
347 // SUB x4, x10, x5
348 Data[8] = 8'hcb;
349 Data[9] = 8'h05;
350 Data[10] = 8'h01;
351 Data[11] = 8'h44;
352
353 // ORR x5, x30, x10
354 Data[12] = 8'haa;
355 Data[13] = 8'h0a;
356 Data[14] = 8'h03;
357 Data[15] = 8'hc5;
358
359 // AND x6, x30, x10
360 Data[16] = 8'h8a;
361 Data[17] = 8'h0a;
362 Data[18] = 8'h03;
363 Data[19] = 8'hc6;
364
365 // STUR x2, [x31]
366 Data[20] = 8'hf8;
367 Data[21] = 8'h00;
368 Data[22] = 8'h03;
369 Data[23] = 8'he2;
370
371 end
372
373 always @(PC_in) begin
374 instruction_out[8:0] = Data[PC_in + 3];
377 instruction_out[31:24] = Data[PC_in];
378 end
379 endmodule
380
381
382 module Data_Memory
383 (
384 input [63:0] inputAddress,
385 input [63:0] inputData,
386 input CONTROL_MemWrite,
387 input CONTROL_MemRead,
388 output reg [63:0] outputData
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389 );
390
391 reg [63:0] Data[31:0];
392
393 integer initCount;
394
395 initial begin
397 Data[initCount] = initCount * 100;
398 end
399
400 Data[10] = 1540;
401 Data[11] = 2117;
402 end
403
404 always @(*) begin
405 if (CONTROL_MemWrite == 1'b1) begin
406 Data[inputAddress] = inputData;
407 end else if (CONTROL_MemRead == 1'b1) begin
408 outputData = Data[inputAddress];
409 end else begin
410 outputData = 64'hxxxxxxxx;
411 end
412
413 // Debug use only
415 $display("RAM[%0d] = %0d", initCount, Data[initCount]);
416 end
417 end
418 endmodule
419
420
421 module ALU
422 (
423 input [63:0] A,
424 input [63:0] B,
425 input [3:0] CONTROL,
426 output reg [63:0] RESULT,
427 output reg ZEROFLAG
428 );
429
431 case (CONTROL)
432 4'b0000 : RESULT = A & B;
433 4'b0001 : RESULT = A | B;
434 4'b0010 : RESULT = A + B;
435 4'b0110 : RESULT = A - B;
436 4'b0111 : RESULT = B;
437 4'b1100 : RESULT = ~(A | B);
438 default : RESULT = 64'hxxxxxxxx;
439 endcase
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440
441 if (RESULT == 0) begin
442 ZEROFLAG = 1'b1;
443 end else if (RESULT != 0) begin
444 ZEROFLAG = 1'b0;
445 end else begin
446 ZEROFLAG = 1'bx;
447 end
448 end
449 endmodule
450
451
452 module ALU_Control
453 (
454 input [1:0] ALU_Op,
455 input [10:0] ALU_INSTRUCTION,
456 output reg [3:0] ALU_Out
457 );
458
459 always @(ALU_Op or ALU_INSTRUCTION) begin
460 case (ALU_Op)
461 2'b00 : ALU_Out = 4'b0010;
462 2'b01 : ALU_Out = 4'b0111;
463 2'b10 : begin
464
465 case (ALU_INSTRUCTION)
466 11'b10001011000 : ALU_Out = 4'b0010; // ADD
467 11'b11001011000 : ALU_Out = 4'b0110; // SUB
468 11'b10001010000 : ALU_Out = 4'b0000; // AND
469 11'b10101010000 : ALU_Out = 4'b0001; // ORR
470 endcase
471 end
472 default : ALU_Out = 4'bxxxx;
473 endcase
474 end
475 endmodule
476
477
478 module ALU_Mux
479 (
480 input [63:0] input1,
482 input CONTROL_ALUSRC,
483 output reg [63:0] out
484 );
485
486 always @(input1, input2, CONTROL_ALUSRC, out) begin
487 if (CONTROL_ALUSRC == 0) begin
488 out <= input1;
489 end
490
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491 else begin

492 out <= input2;
493 end
494 end
495 endmodule
496
497
498 module ID_Mux
499 (
500 input [4:0] read1_in,
501 input [4:0] read2_in,
502 input reg2loc_in,
503 output reg [4:0] reg_out
504 );
505
506 always @(read1_in, read2_in, reg2loc_in) begin
507 case (reg2loc_in)
508 1'b0 : begin
509 reg_out <= read1_in;
510 end
511 1'b1 : begin
512 reg_out <= read2_in;
513 end
514 default : begin
515 reg_out <= 1'bx;
516 end
517 endcase
518 end
519 endmodule
520
521
522 module WB_Mux
523 (
526 input mem2reg_control,
527 output reg [63:0] out
528 );
529
531 if (mem2reg_control == 0) begin
532 out <= input1;
533 end
534
535 else begin
536 out <= input2;
537 end
538 end
539 endmodule
540
541
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542 module Shift_Left

543 (
544 input [63:0] data_in,
545 output reg [63:0] data_out
546 );
547
548 always @(data_in) begin
549 data_out = data_in << 2;
550 end
551 endmodule
552
553
554 module SignExtend
555 (
556 input [31:0] inputInstruction,
557 output reg [63:0] outImmediate
558 );
559
560 always @(inputInstruction) begin
561 if (inputInstruction[31:26] == 6'b000101) begin // B
562 outImmediate[25:0] = inputInstruction[25:0];
563 outImmediate[63:26] = {64{outImmediate[25]}};
564
565 end else if (inputInstruction[31:24] == 8'b10110100) begin // CBZ
568
569 end else begin // D Type, ignored if R type
572 end
573 end
574 endmodule
575
576
577 module Branch
578 (
579 input unconditional_branch_in,
580 input conditional_branch_in,
581 input alu_main_is_zero,
582 output reg PC_src_out
583 );
584
585 reg conditional_branch_temp;
586
587 always @(unconditional_branch_in, conditional_branch_in, alu_main_is_zero) begin
588 conditional_branch_temp = conditional_branch_in & alu_main_is_zero;
589 PC_src_out = unconditional_branch_in | conditional_branch_temp;
590 end
591 endmodule
592
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593
594 module ARM_Control
595 (
596 input [10:0] instruction,
597 output reg [1:0] control_aluop,
598 output reg control_alusrc,
599 output reg control_isZeroBranch,
600 output reg control_isUnconBranch,
601 output reg control_memRead,
602 output reg control_memwrite,
603 output reg control_regwrite,
604 output reg control_mem2reg
605 );
606
607 always @(instruction) begin
608 /* B */
609 if (instruction[10:5] == 6'b000101) begin
610 control_mem2reg <= 1'bx;
611 control_memRead <= 1'b0;
612 control_memwrite <= 1'b0;
613 control_alusrc <= 1'b0;
614 control_aluop <= 2'b01;
615 control_isZeroBranch <= 1'b0;
616 control_isUnconBranch <= 1'b1;
617 control_regwrite <= 1'b0;
618 end
619
620 /* CBZ */
621 else if (instruction[10:3] == 8'b10110100) begin
630 end
631
632 /* R-Type Instructions */
633 else begin
636
637 case (instruction[10:0])
638
639 /* LDUR */
640 11'b11111000010 : begin
641 control_mem2reg <= 1'b1;
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647 end
648
649 /* STUR */
650 11'b11111000000 : begin
657 end
658
659 /* ADD */
660 11'b10001011000 : begin
667 end
668
669 /* SUB */
670 11'b11001011000 : begin
677 end
678
679 /* AND */
680 11'b10001010000 : begin
687 end
688
689 /* ORR */
690 11'b10101010000 : begin
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697 end
698
699 default : begin
700 control_isZeroBranch <= 1'bx;
701 control_isUnconBranch <= 1'bx;
703 control_memRead <= 1'bx;
704 control_memwrite <= 1'bx;
705 control_alusrc <= 1'bx;
706 control_aluop <= 2'bxx;
707 control_regwrite <= 1'bx;
708 end
709 endcase
710 end
711 end
712 endmodule
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Code Issues 2 Pull requests Actions Security Insights

ARM-LEGv8 / Pipelined-Only / ARM_CPU.v

nxbyte Improving source formatting History

2 sur 15 15/01/2022, 18:25

83 wire [63:0] PC_jump;

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185 regdata1_out <= regdata1_in;

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236 alu_zero_out <= alu_zero_in;

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287 Data[initCount] = initCount;

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338 Data[2] = 8'h11;

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491 else begin

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542 module Shift_Left

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644 control_alusrc <= 1'b1;

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695 control_aluop <= 2'b10;

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