23/7/2020 Denny Chellappa

19BEC1360

Experiment No. 2
Design and Implementation of
Adder and Subtractor
Aim:
1. To design and implement half adder using Logic Gate Simulator
2. To design and implement full adder using Logic Gate Simulator
a. Using NOT, AND and OR gates (sum of product form)
b. Using Half Adders
3. To design and implement half subtractor using Logic Gate Simulator
4. To design and implement full subtractor using Logic Gate Simulator
using Half Subtractors

Software Used:
Logic Gate Simulator

Procedure:
• Identify the input and output variables.
• Construct the truth table
• Draw the K-map using truth table
• Determine the simplified Boolean expression
• Draw the logic diagram and setup the circuit in the logic simulator.
• Vary the inputs and measure the outputs.
• Do this for all possible combination of inputs.
Half-Adder:
Truth table:
Input Output
A B Sum(S) Carry(C)
0 0 0 0
1 0 1 0
0 1 1 0
1 1 0 1

K-Map for sum:

A\B B’ B
A’ 0 1
A 1 0
S = AB’ + A’B
S= A XOR B
K-Map for Carry:
A\B B’ B
A’ 0 0
A 0 1
C = A.B
C= A AND B
Components Required:
S.No Component Quantity
1 XOR gate 1
2 AND gate 1

Full-Adder:
Truth table:

Input Output
A B C Sum(S) Carry(C)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

K-Map for sum:

A\BC B’C’ B’C BC BC’
A’ 0 1 0 1
A 1 0 1 0
S = AB’C’ + A’B’C + ABC + A’BC’
S = C’(AB’ + A’B) + C(A’B’+AB)
S= c XOR (A XOR B)
K-Map for carry:
A\BC B’C’ B’C BC BC’
A’ 0 0 1 0
A 0 1 1 1
C = AB’C + A’BC + ABC + ABC’
2a) SOP form:
Sum: C(A’B’+AB)+C(A’B+AB‘)
Carry: AB+AC+BC
Components Required:

S.No Component Quantity

1. AND gate 9
2. OR gate 4
3. NOT gate 5
2b) Half adder form:
Components Required:
S.No Component Quantity
1. AND gate 2
2. XOR gate 2
3. OR gate 1
Half-subtractor:
Truth Table:
A B D B
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

K-Map for Difference:

A\B B’ B
A’ 0 1
A 1 0
D = A’B + AB’
D = A XOR B
K-Map for Borrow:
A\B B’ B
A’ 0 1
A 0 0
B = A’.B
Full-Subtractor:
Truth Table:
A B Cin Diff Borrow
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

K-Map for difference:

A\BC B’C’ B’C BC BC’
A’ 0 1 0 1
A 1 0 1 0
D = AB’C’ + A’B’C + ABC + A’BC’
D = C’( AB’ + A’B) + C( A‘B + AB)
D= C XOR (A XOR B)
K-Map for Borrow:
A\BC B’C’ B’C BC BC’
A’ 0 1 1 1
A 0 0 1 0
B = A’B’C + A’BC + A’BC’ + ABC
B = (A’C + A’B) + BC (A’ + A)
B = A’C + A’B + BC
4a) SOP form:
Difference: C(A’B’+AB)+C’(AB‘+A’B)
Sum: A’C+A’B+BC
4b) Half-subtractor form:
Result:
Hence, the design and implementation of Half adder, Full Adder, Half
Subtractor and Full Subtractor using Logic gates were done.