EEE3222 – Microelectronic Principles

4 – Inverter Layout
by
Assoc. Prof. Dr. Roslina Mohd. Sidek
Dept. of Electrical and Electronic Engineering
Assoc. Prof. Dr. Roslina Mohd Sidek 1
 Outline
• Layout Design
• CMOS Fabrication Steps
• CMOS Layers/Masks
• MOSFET Layout
• Layout Pattern Types
• IC Layout
• Design Rules
• Exercise
• Stick Diagram
Assoc. Prof. Dr. Roslina Mohd Sidek 2
 Layout Design
• Layout design or physical layout design is a process where
engineering schematics are transposed into a set of geometric
shapes to be used to make masks for IC fabrication.

in out in out

gnd

Symbol Schematic Layout

Assoc. Prof. Dr. Roslina Mohd Sidek 3
CMOS Fabrication Steps (Rabaey, ch2)
• Active Area/ Island

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CMOS Fabrication Steps (Rabaey, ch2)
• For twin-well process
– n-well and VTH adjust implant
– p-well and VTH adjust implant

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 CMOS Fabrication Steps (Rabaey, ch2)
• PolySi gate
• S/D/bulk n-diffusion
• S/D/bulk p-diffusion
• Contact window

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CMOS Fabrication Steps (Rabaey, ch2)
• Metal 1
• Via1, Metal2, Via2, ..., passivation (not shown)

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 CMOS Fabrication Steps
• 3D view and layout Top view

Side view

Layout

https://www.sciencedirect.com/science/article/abs/pii/S0026271421001785

Assoc. Prof. Dr. Roslina Mohd Sidek 8

 CMOS Fabrication Steps
• Isolation/Active-Area
• Well
• Gate
• Source/Drain M3
• Contact Window via2
• N+1 Metalization M2
– Via1 M
via1
– M2 M1
– Via2
– M3 CW
– Via(n+1) n+ p+ P+ n+ n+ p+
– M(n+1)
• Passivation n-well
p-substrate
9

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 CMOS Layers/(Masks)
– Isolation/Active-area (ISLAND/AA)
– N well (NW)
– PolySi Gate (P1)
– N-type Source/Drain Diffusion (N-DIFF/ N-SELECT)
– P-type Source/Drain Diffusion (N-DIFF/ N-SELECT)
– Contact window (CW)
– Metal 1 (M1)
– Via 1 (VIA1)
– Metal 2 (M3)
– Via 2 (VIA2)
– Metal 3 (M3)
– Via (n+1) …….. Where n = no. of metal layers
– M (n+1)

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 MOSFET Layout
• NMOS

D
S
– NW

B
– Island/AA
– P1
– N-diff/n-select
– P-diff/p-select
– Contact
– Metalization
Gate?
Assoc. Prof. Dr. Roslina Mohd Sidek
 MOSFET Layout
• PMOS

G
– NW

D
S

B
– Island/AA
– P1
– N-diff/n-select
– P-diff/p-select
– Contact
– Metalization
Gate
Assoc. Prof. Dr. Roslina Mohd Sidek
 Layout Pattern Types
• Light Field (left) vs. Dark Field (right)

Mask design
(top view)

+ve resist
After lithography
(side view)

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 IC Layout (Physical Design)
• PMOS (left) and NMOS (right)
Top view
(mask layout)

Cross-section

Side view M M1
CW
n+ p+ P+ n+ n+ p+
n-well 14
p-substrate

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 Design Rules
• Specify minimum dimension and spacing of geometries to ensure
successful chip fabrication.
• Example:
– Poly
• Minimum size = 0.18 um
• Minimum spacings:
– Poly to poly = 0.2 um
– Poly to AA = 0.1 um
– Poly to ……..
– ………………….
– N-select
• Minimum size = 0.5 um
• Minimum spacings:
– N-select to NW = 2 um
– …………
– Contact
– Metal
– ………………….

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 Design Rules
a
• Minimum size
b

• Minimum spacing
c
e

d
f

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 Exercise
• Draw the semiconductor cross-section across X-Y cutline

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 Stick Diagram
• A short-hand technique for generating a free form plan of a circuit
layout with no regard to geometry sizing and design rules

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 Summary
• Physical layout is for making mask which will
be used in lithography process.
• Availability and attributes of mask/layout
layers depends on the fabrication technology.
• Mask/layout design must comply to design
rules (smallest dimension and spacing between
geometries) to avoid fabrication failure.
• Stick diagram is 1-dimensional representation
of 2-dimensional layout and is used to plan for
actual layout.
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Assoc. Prof. Dr. Roslina Mohd Sidek 20