Low-Power, Implantable Sensing System for
Signal Detection from the Central or Peripheral
Nervous System
Ravi S. Ananth, Edward K. Lee, Taihu Li, Anthony Lam
Alfred Mann Foundation for Scientific Research, Valencia, California, USA 91355
ananth(@aemf org
Abstract -A low-power, implantable electrode array sensing
system for picking up a number of signals from the central
or peripheral nervous system is described. The sensed and
amplified signals are intended for use in prosthetic limb
control or functional electrical stimulation (FES) of
paralyzed limbs. The sensing system itself contains dc-
blocking capacitors, low-noise amplifiers (LNA), active
filtering and threshold detection logic. Blocking capacitors
are used on the array of electrode inputs to meet safety
guidelines for electronic devices to be dc-blocked from tissue.
Voltage division loss between the dc-blocking capacitors and
the parasitic capacitance of the LNA's large input PFETs is
overcome by using positive feedback with a replica parasitic.
Programmable filtering with dc-offset correction on the
amplifier outputs gives a dc-blocked and yet ultra-low
frequency, high-pass filtering with an overall frequency
response ranging from 0.035 Hz to 7000 Hz and an input
signal range up to 200 mVpp. A 4-channel, 32 input sensing
system was designed and fabricated in a 0.5um CMOS
process and occupies an area of 3.24 mm2/channel. It
operates at 2.7 V and draws 12uA/channel, providing
programmable differential gains between 4 and 1200, and an
input referred noise voltage of 5.6 uVrms over a band of 10 Hz
to 7 kHz.
I. INTRODUCTION
Major advances in the understanding of the central and
peripheral nervous system (CNS/PNS) have led
researchers to consider the possibility of using these
signals for prosthetic limb control or for Brain-Computer
Interface (BCI) controls of functional electrical
stimulation (FES) devices [1], [2], [3]. The task of
monitoring a useful number of signals from the nervous
system for use in FES requires the implantation of a large
number of electrodes over the region of interest. This
region, for example, could be deep within the motor
cortex of the brain for cortical based control, or within the
severed fascicles of an amputated proximal nerve stump
for PNS based control as shown in Fig 1. The PNS
control, for example, is achieved when appropriate nerve
0-7803-9390-2/06/$20.00 ©)2006 IEEE
Bed of Nails
Electrode Array
Wrls FTasiso
T
alactlators in hatdwrist, andfingers
Sensor Controller
BedofN
Electrode
To all actuators in elbowt and tpper arm
From all sesorsinhand, wris andfingers
From all senisors in elbow and upperanm
Figure 1: Control of a prosthetic arm using PNS signals
fascicles in a nerve bundle are in contact with an electrode
array or "bed-of-nails". The detected signals are then
amplified by a sensing system that resides directly on the
electrode array, allowing for better SNR and hence
usability of these bio-potential signals. The processed
signals from a number of electrode arrays are then passed
on to a module called the neural interface relay module
(NIRM) in Fig 1. The NIRM, in turn, wirelessly transmits
the appropriate command signals to the prosthetic arm,
based on the signal values detected in the amputated
stump's nerve bundles. It must be mentioned that the
development of electrode arrays is itself another area of
intense research activity [4].
For an application where the array of interface
amplifiers are implanted and derive power from an
inductively recharged battery, low power operation of the
sensing system becomes a critical requirement. For a
5OmA-hr rechargeable battery that we are developing and
2573 ISCAS 2006
 channel
a 32 channel monitoring system, this requires that each ,
sensing channel consume less than 16 uA to enable 48 Filter
hour operation of the NIRM module before recharging. In ouput
order to use the same sensing system for a varietyorderof CNS To eedof nails
electrode array -~~~~~~~~~~~~~~~~~~~~~~~~
E. analog
or PNS signals, it is desirable to have the frequency c output
response and sensitivity adapt to the requirements of the Filter
application, since the traits of the bio-potential signals clock
vary as shown in Table 1. Satisfying detection capability control bits
at the lower frequency ranges for low-field cortical 1A00
Gain: 4 to fLPF -300 Hz to 7 kHz
potentials (LFP) or even CNS potentials becomes very fl-HPF -35 mHz to I kHz
to12
challenging, as an on-chip dc-blocking capacitor is
required on each input to meet safety guidelines requiring
electronic devices to be dc-blocked from tissue. Figure 2: Sensing System Architecture
The low-power requirement restricts the open-loop contribution. Fig 3 shows the LNA circuit configuration
gain of the sensing amplifiers, and the presence of low- where load resistors, RL, and capacitors, CL, set the low-
frequency signals necessitates the use of large-area input pass gain, frequency corner and common-mode output
devices to lower the '1/f noise of the LNA. Typical '1/f voltage.
noise reduction techniques using chopper-modulation as V
in [5, 6] are highly beneficial for reducing low-frequency IBi.s
noise and circuit area. Unfortunately, the presence of a dc-
blocking capacitor makes this approach less suitable. This In+
PFETpos PFETNec >I In-

paper presents an expandable sensing matrix system with

emphasis on describing a method used to achieve a dc- Cg.t.dr.in q, CL Cg.tdr.in
blocked and dc-offset corrected, ultra low-frequency, Out- 0 J Out+
high-pass amplifier for a bio-potential sensing system that VX GVt
uses relatively minimal area and power. The sensing
system was designed and fabricated in a 0.5um CMOS
process and was one of the building blocks in the overall
implantable system shown in Fig 1.
Figure 3: Differential LNA Circuit Core
II. SYSTEM AND CIRCUIT ARCHITECTURE Open-loop gain implementation with the input PFETs
Fig 2 shows the overall sensing system architecture biased at zero volts or signal ground during a period of no
used. Each of the inputs shown is obtained through direct sensing allows one to use the topology shown in Fig 4.
mechanical connection to the "bed-of-nails" electrode Higher threshold, thick-oxide PFETs are used for the
array. At any one time, however, only a subset of the input, to ensure that the PFET remains in the active region
electrode signals are simultaneously monitored, and of operation since zero volts is used as the biasing voltage.
furthermore, only a select number of electrodes will Chpf cpos
Plus electrode
realistically be positioned in the brain's cortex or
amputated stump for useful signal pickup. As a result, an
input switch matrix is used to determine which electrode V
Ao* gd
signals need to be processed. For the LNA in the sensing VbioPotental c AO*Cg Out+
system, a standard differential amplifier topology with Switch
Co LN+A Out+
large-area input PFETs is used to reduce the '1/f noise 0 Out-
AO*Cgd
Table 1: Signal Types and their Electrical Traits
Minus electrode
Signal Type Amplitude Range Frequency Range C
PNS Potentials 10 uV -10 mV 300 Hz- 3 kHz lpos
CNS Potentials 10 uV- 500 uV 100 Hz- 5 kHz
Low-Field Cortical Figure 4: LNA System for Ultra Low-Frequency, Bio-potential Sensing
Potentials 100 uV- 1 mV 0.5 Hz- 50 Hz Application
The LNA input in Fig 4 is pre-biased at zero volts and
floated during a sensing operation. Since the device is

2574
floating within the body, some of the electrodes in the
"bed-of-nails" array are used as the reference or signal
ground and true differential sensing is achieved by
detecting the potential across any other pair of electrodes
that are selected by the input switch matrix shown in Fig
2. Typical implementations require gigantic capacitor and
resistor values to achieve a very low-frequency, high-pass
filter response that can still block dc. The large valued dc-
blocking capacitor can even restrict the circuit integration
to a single-ended input implementation due to practical
size constraints. Using the topology of Fig 4, however, the
inherently large input impedance of the PFET gate and its
floating input during a differential sensing operation can
be used to advantage to obtain an ultra low-frequency
high-pass response with a very small dc-blocking
capacitor, Chpf, of only 50 pF and no bias resistors.
The size of the input PFETs is driven by two goals,
namely minimizing '1/f noise and achieving operation in
the sub-threshold mode in order to obtain a larger gm-to-
bias current ratio (given the low power requirements).
Both goals are achieved, however, at the expense of larger
aspect ratios for the input PFETs of the LNA and hence
larger parasitic capacitance from the gate-to-source and
gate-to-drain nodes of the input PFET. The Miller effect
makes the gate-to-drain capacitance dominate, as it is
increased by a factor equal to the open-loop gain, AO, of
the LNA. This capacitance, AO*Cgd, in effect goes in series
with the blocking capacitor, Chpf, as shown in Fig 4. For
small on-chip values of Chpf, this results in a large
attenuation of the bio-potential signal at the LNA's input
due to a capacitive voltage divider action.
The parasitic capacitance of Ao*Cgd can be lowered or
cancelled by using a capacitor of similar size to Cgd, in
positive feedback. This is done by Cpos and shown in Fig
4. Since Cpos is subject to the same Miller effect as Cgd, its
capacitive amplification tracks that of the LNA gain. The
open-loop gain, AO, is well controlled since the LNA
operates in the sub-threshold region where the gm is
proportional to the bias current. The bias current is set
with an on-chip reference resistor which also tracks the
load resistor, RL, so that AO, which is a product of gm and
RL , remains fairly constant. However, the actual value of
Cgd may change due to process variations and hence a
fixed capacitive value for Cpos cannot be used for reliable
parasitic cancellation. By using an exact replica of the
input PFET (with half its gate width) and shorting the
drain and source of the replica PFET to the output while
connecting the gate to the input of similar polarity, a value
for Cpos is created that closely matches the Cgd of the
dominant input parasitic capacitance. However, this
capacitance~~~ ~~~
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2575
LNA input or conversely allows for the use of a small on-
chip value for Chpf [7]. Minimum-sized gate lengths for
the replica PFET can be used in contrast to the input
PFET's gate length, as the replica PFET's channel is off.
This is due to the lower threshold voltage of the NFETs
(which set the output voltage and hence the voltage across
the shorted drain and source) in contrast to the high-
threshold voltage of the input and replica PFETs. Hence,
the replica PFET's gate length plays an insignificant role
in adding more parasitics and this factor can be used to
advantage to further minimize the area occupied.
The high-pass corner at the input is set by Chpf and the
gate impedance of the input PFET. This value is
extremely low at about 35 milli-Hertz. To achieve a
programmable high-pass frequency corner with offset
correction at the output, one needs to implement a post-
filtering and gain stage as shown in Fig 2 and Fig 5. Offset
correction at the output is imperative, since the output
common-mode voltage of the sensing system is directly
fed to either an A/D converter or threshold detector. A
standard topology, as shown in Fig 5, is used to achieve
this with the addition of a programmable high-pass filter
whose corner frequency is determined by varying CH2 and
RH2 around amplifier A3. Practical on-chip values for these
two components can be achieved to attain high-pass
corners down to 10 Hz.
To achieve offset correction at sub-Hertz frequencies
however, one needs to disable the input feedback to
amplifier A3, since the limited values of RH2 and CH2
would block the signal itself. By introducing a sample-
and-hold switch, S1, one can effectively sample the output
offsets before sensing is enabled by using the control
signal ULF to enable SI while the LNA inputs are shorted
by the "Sense-Control" switch shown in Fig 4.
CH2
ULF
R
T2s_
A3 S, detector
Vref
RL2 CL2
in
gm A V_
ToAD
R.2
0L2
Figure 5: Post-Amplification and Filter Stages
The sampled offset iS then stored on CH2 when S1 iS turned
off while the input to the LNA iS enabled by turning off
the "Sense-Control" switch. Sub-Hertz input signals are
thereby amplified while still correcting for the dc offsets
(excluding A3) inherent through the entire sensing system,
including the rail-to-rail buffer A4. The value of the output
common mode voltage is set by the voltage Vref on A3.
84 dB input dynamic range is achieved by appropriate
gain degeneration at the LNA and filter sections to give an
output that has a 10-bit resolution for the A/D converter
that follows.
III. RESULTS
A 32 electrode input, four-channel sensing system was
designed and implemented in a triple-metal 0.5um CMOS
process. Each sensing channel, with its programmable
low-pass and high-pass filters, occupied an area of 3.24
mm2 using dc-blocking capacitors of 50 pF. The overall
differential gain of the sensing system was programmable
and ranged from 4 to 1200. A maximum bandwidth of
0.035 Hz to 7 kHz was attained and could be adjusted
with programmable high-pass and low-pass filter corners.
Table 2 summarizes the measured results from test chips
for the power consumption and noise floor over various
bandwidths as well as the offset correction circuit droop
rate when used for sub-Hertz signal detection. The entire
system operated off a 2.7 V supply.
Table 2: Measured Test Results for the Sensing System
Parameter Measured Results
Overall Power dissipation 33 uW/channel
LNA Power dissipation 14 uW
Input referred noise density 64 nV/N1Hz
between 10 Hz and 7 kHz
between____________________________ 10__Hz__and__7_kHz_
Total input referred noise
between 10 Hz and 7 kHz 5.6 uVrms
Total input referred noise
between 10 Hz and 1 kHz - 2.4 uVrms
Total input referred noise 12 uVrms
between 0.035 Hz and 300 Hz
S/H offset-correction droop rate < 700nV/s
IV. SUMMARY AND DISCUSSION
A low-noise, low-power, ultra-low frequency response,
sensing system was designed for use in a sensing matrix
meant to be embedded within a bed-of-nails electrode
array. This implantable and battery-powered sensing array
is used to detect CNS or PNS signals with the objective of
using the processed signals for FES or prosthetic limb
control. The topology and circuit implementation allows
the sensing system to be used in conjunction with a
2576
number of different CNS and PNS signal types. An A/D
converter allows for further digital signal processing such
as "Rectify and Integrate" to be performed, as this appears
to be a preferred way to generate an FES control signal.
However, a threshold detection scheme after signal
amplification is also made available as an alternative FES
triggering mechanism. The sensing system described is
only a part of the overall system, as functions such as
power regulation, battery charging and RF transceiver
action through the NIRM module in Figure 1 are required
for the implantable system. To conserve power, the
current consumption in the sensing system was optimized
to meet the minimum signal detection target, rather than
increasing current for the best possible noise performance.
By the programmable tailoring of the bandwidth and gain,
an appropriate noise floor can be attained for the various
applications indicated in Table 1.
In the future, lower noise-floors may be attained by
using technologies with low threshold-voltage FETs. This
will allow one to increase the LNA current by an amount
inversely proportional to the decrease in operating
voltage. The increased gm of the LNA will result in a
lower noise floor for the same overall power consumption.
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