FOR A MULTICHANNEL
L O W POWER PROGRAMMABLE FRONT-END
NEURALRECORDING
INTERFACE
Benoit Gosselin, Virginie Simard and Mohamad Sawan
PolySTIM Neurotechnology Laboratory,
Department of Electrical Engineering, Ecole Polytechnique de Montrial
benoit.gosselinlvirginie.simardlmohamad.sawan@polymtl.ca
Abstract
We propose in this paper a programmable gain
preamplipcation front-end for a j W y implantable
multichannel data acquisition system (IMDAS) that is
dedicated for chronic neural signal recording. This
application calls for very low power and low voltage
circuit techniques. To satisfv these constraints, the
preamplifier is designed in 0.18pm CMOS technology
and 011 employed transistors operate in weak inversion.
To maximize the dynamic range ofthe recorded signals,
the preamplifier S gain is set by a 4-bit digital-to-analog
converter (DAC). This DAC is used to tune the bias
currents of a variable transconductor cell in order to
vaiy its DC gain. The simulation of the whole proposed
module gives a maximum power consumption of 530n W
at a supply voltage of 0.9K The circuit provides a
maximum gain of 47dB. has a cutoff frequency of
2.65?iHz and presents an input-refeved noise of
7.65gVrms which is suficiently low to meet the required
precision. In addition, the phase margin is higher than
50" on the entire gain range.
Keywork: preamplijkr; neural cortical recording;
implantable electronic device.
1. INTRODUCTION
Recent brain researches have shown the importance of
neural assemblies in the coding of neuronal information
[l]. In order to facilitate the collect and processing of
neural signals, data acquisition systems that implement
multiunit recording using silicon arrays of
microelectrodes and on-board electronics have been
proposed and used in experimental studies [2,3]. As
recent work on neural digital signal processing methods
may lead to the next generation of multichannel
acquisition systems [4], analog fiont-ends that enable
simultaneous recording of a vast amount of cells activity
CCECE 2003 - CCGEI 2003, Montrtal, May/mai 2003 0-
7803-7781-X/03/$17.00 0 2003 IEEE
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could act as a critical starting point in the emergence of
these new smart systems. However, since studies of
neural assemblies require to record data simultaneously
from as many neurons as possible, power consumption
imposes serious constraints on these implantable systems.
Fortunately, low power design techniques bring
solutions to push forward the limits. In the past few years,
low power techniques have been successfully applied to
various biomedical applications working under tight
consumption constraints [5,6]. Circuits built with
transistors working in weak inversion region allow the
implementation of systems working in sub-microwatt
range [7,X,9]. Amplifiers with high gain and sufficiently
low input-referred noise are fundamental blocks in a
multiunit recording system front-end. Neuronal spikes
have amplitude in the microvolt range (1 to lOOpV),
which varies, from one recording site to another,
according to the cell shape, orientation and proximity
from the electrode tip. This paper proposes a
programmable gain preamplifier for a neuronal
multichannel acquisition recording system. Due to its
ultra low-power consumption, this preamplifier will
allows to have a very large amount of channels recording
data simultaneously from the tissues. A maxi" input-
referred noise of 1OpVnns (below the electrode noise
level) and a bandwidth of more than 2.5 kHz make these
amplifiers suitable for such an application. Results from
comer analysis show that the whole front-end exhibit
appropriate behavior on a large range of process
variations.
2. DESIGN OF THE FRONT-END
AMPL1FIER
For a MOS transistor working in weak inversion, the
drain current follows an exponential law:
where W and L are width and length of the gate,
IDo=2n~C,U;'exp(-V~(nU~)is the characteristic
current, n the slope factor and U,=kT/q the thermal
voltage. Weak inversion requires the two following
conditions to he observed: ID<2npC,U;W/L and
VGs<VT&nUT; moreover transistors will be saturated if
VD-Vs>>UT.The pinch-off voltage is then approximately
3UT.
2.1 Variable transconductor
The variable transconductor drawn in Fig. 1 is fully
differential and has a folded-cascode output stage that
allows a high output impedance and a voltage offset that
leads to a common-mode voltage halfway between VDD
and VSS. Its gain is given by:
Gmi=gmi (2)
Vi" YO+
VC-
VSS
Fig. I.
Variable transconductor
However, a weak inversion-biased transistor has a
transconductance proportional to its DC current drain:
(3)
The bias current of MI is determined by the current
source implemented by M5, also polarized in weak
inversion. Thus, its drain current is related to its gate-
source voltage by:
(4)
Inserting (2) and (3) in (4) and considering IDl=ID3/2,
the
variable transconductor eain is eiven bv :
This shows that the amplifier gain, which depends on the
variable transconductor stage, will increase linearly on a
logarithmic scale. To reduce input-referred noise, the
ratio W/L of M1, M 2 and length of M3, M4 have been set
very large, then M1, M2 transconductance is maximized
while M3, M4's is decreased. Flicker noise (l/Q is
limited because WL of M1, M 2 is large.
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2.2 Output common mode voltage
While adjusting the gain, variation of I, generate a
variation of the output stage DC voltage. To avoid this
effect, MP7 and MP8 provide the current necessary to
keep the output stage bias current as constant as possible.
Moreover, the differential configuration of the output
stage causes the offset voltage to be considered as a
common-mode voltage by subsequent stage, which is a
minor drawback.
2.3 Biasing
The tuning circuit of Fig. 2 determines the bias
current Ipal and control the amount of current sink by
MP7 and MP8. This circuit works in the nonlinear region
of its bipolar type characteristic I(V,3. Voltage VI is
then linearized by MP6, so the amplifier gain varies
linearly on a logarithmic scale when the control voltage
VCelis adjusted using the DAC. As V,, increases, MP5
and MP6 gate-source voltage will decrease, so will the
current sink by MP8 and MF'7 and the variable
transconductor gain.
YSS
Fig. 2. Tuning circuit
2.4 Transimpedance stage
To convert output current in voltage, a
transimpedance stage is implemented using a
transconductor with negative feedback linearized with a
triode-biased MOS transistors [IO]. The preamplifier
output voltage is then:
A load capacitance provides the amplifier compensation :
a 0.5pF capacitance has been used for simulations. The
unity-gain fiequency of the fiont-end may then he
evaluated by
=- g., (7)
G&L
Block diagram of neural amplifier is shown in Fig. 3.
 stage; their outputs would then be multiplexed by a set of
switches toward another amplifier with large bandwidth
and constant gain after which neural signals would have
an amplitude of at least lOOmV before going through an
Gal" analog-to-digital converter (ADC).
pmgramm,ng Polamfan Vanable Tramlmwdam
trs-ndmbr
3. SIMULATION RESULTS
Fig. 3. Block diagram of the preamplifier
2.5 Digital-to-analog converter Table 1 shows some features of the preamplifier for
typical process values. These parameters have been
The DAC is made from current sources, working as evaluated for five digital gain values: DC gain, cut-off
well in weak inversion, for which currents are frequency J j d B and unity-gain 6equencyfT, phase margin
proportional to bit weight represented by each source. PM,power consumption P, output common mode voltage
The final output current is converted to a voltage using a OVcm and input-referred noise. A graph of the AC
resistor R,/ . A transistor of which gate is controlled by a response is presented in Fig. 5 where the 16 AC
clock signal phi constitutes a sample-and-hold ( S / H ) responses obtained according to different binary words of
circuit that allows to keep the analog voltage gain in a the DAC are shown. The current in the input stage of the
capacitance, in order to have a single DAC for several variable transconductor vary from 266nA to 1.58nA. A
amplifiers. The schematized DAC is drawn in Fig. 4 a) comer analysis has been performed on the design to
and a current source with a switch is shown in Fig. 4 b). exhibit the behavior of the front-end under different
process variations. Fig. 6 illustrates the changes in the
front-end parameters for typical, slow-slow, fast-fast,
slow-fast and fast-slow instances of NMOS and PMOS
transistors parameters for CMOS 0.18pn process. The
circuit exhibits vety good performance under almost all
process variation except for the fast-fast case, which
gives higher power consumption and a lower maximum
gain.
a) b)
Fig. 4. a) DAC block diagram, b) Current source
and swltch
Gain DC f.m f, PM P OVcm Noise
To achieve the desired gain range, the differential ciain W ) Wz) (7 (nw) (mv) (pvm)
input V , , must vary from 0 to 200mV with a common-
mode voltage higher than 400mV. When the digital gain
is 1111, every switches are open and no current flows
through R-,, thus the maximal output voltage is equal to
voltage source Vp,as,that has to be bigger than 750mV in
order to keep the current source transistors in proper
region of operation. Voltage step between each binary
Gain
value is given by current and Re{ a good compromise 0000
between a small current that keep power consumption at 0001
a low level and an acceptable size of resistor could he 0010
0011
133nA and 1OOkn. The DAC output range after S / H is 0100
then from 547mV (0000) to 750mV (1 11 1) with steps of 0101
0110
13.5mV. The maximal frequency of conversion is 0111
IOOkHz and maximal power for a digital gain 0000 is 1000
1001
1.65pW. 1010
1011
1100
2.6 Programmable multichannel interface 1101
1110
Several preamplifiers could be used to implement a Frequency (Hz) 1111

multichannel interface. Every channels of the interface

would have a programmable gain front-end as input
Fig. 5. Frequency response

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Fig. 6. Simulation results for typical case and 4
extreme process values
Fig. 7 shows plots of maximum low frequency gains
obtained for the typical process and the 4 extreme
processes after increasing linearly the control voltage V,,
on the entire gain range. These curves demonstrate the
linear relationship between V,,, set by the input binary
word of the DAC, and the front-end gain provided by its
weak inversion-operating mode. Slight nonlinearities
occur at smaller values of V,, where the current Ipl is
stronger. This is understandable, since the transistors of
the variable transconductor are at the edge of the weak
inversion operating region for these larger current values.
The slopes are of O.2lldBlmV for the five process
variations.
20
’....,
’-.. ... ,,
-. ...,
.... * ... .
’* ...
.*....
-. ..... ...~. .,,
$0
.. .. ’.*..... ,,,.
Fig. 7. DC gain versus V,,
4. CONCLUSION
A low-power programmable front-end dedicated to
multichannel neuronal recording is presented. All the
front-end functional blocks, the variable transconductor,
the biasing circuit, the transimpedance amplifier and the
DAC are working in the weak inversion region. For
typical process values, this makes the power consumption
of the whole circuit to stays under 53OnW on the entire
programming range. In addition, the phase margin stay
above 50” as well. Comer simulation has demooslrated
the reliability of the front-end under different process
variations. The maximum gain, the power consumption,
the gain range, the phase margin and the output common
mode voltage stay relatively close to the values obtained
for the typical process.
Acknoledgements
The authors would like to thank the National Sciences
and Engineering Research Council (NSERC) for their
support to complete this project.
References
[I] G.L. Gmtein and K.L. KirHand, ‘‘Neural assemblies:
~~
technical issues, analysis, and modeling,” Neural Network
14:589-598,2001,
[2] K. D. Wise, ‘‘Wireless Implantable Microsystems: Coming
Breakthrough in Healthcare,” Symp. on VLSI Circuifs Digest of
Tech. Papers, pp.106-l09,2002.
[3] K. D. Wise, R. H. Olsson, M. N. Gulari, “Silicon neural
recording arrays with on-chip electronicsfor in-vivo data
acquisition,’’ Symp. on VLSlCircuits Digest ofTechnica1
Papers, pp.106-109.2002.
[4] K. G . Oweiss, D.J. Anderson, “ A Unified Framework for
Advancing Array Signal Processing Technology of
Multichannel Microprobe Neural Recording Devices,” Proc. of
the Zd IEEE Conf on Microtechnology in Medicine and
Biology, pp. 245-250,2002.
[5] J. Georgiou, C. Toumazou,“A Micropower Cohlear
Prosthesis System,” 14“ Int. ConJ on Digital Signal
Processing, pp.343-348,2002,
[6] A. Gerosa, A. Novo, A. Mengalli, A. Neviani, “A
’.. micropower low noise log-domain amplifier for the sensing
chain of a cardiac pacemaker,” in Int. Symp. on Circuits and
Systems, vol. 1, pp. 296-299.2001.
[7] E. Vittoz, J. Felhth, “CMOS Analog Integrated Circuits
Based on Weak Inversion Operation,” IEEE Joumal of Solid-
State Circuits, vol. SC-12, no.3, pp.224-231, 1977.
[SI E. Rodriguez-Villegas, A.]. Payne, C. Toumazou,“ A
290nW, Weak Inversion, Gn-C Biquad,” IEEE Internotional
Symposium on Circuits andsystem, pp. 221-224,2002,
[IO] Yamu Hu;Sawan, M , “CMOS fiont-end amplifier
dedicated to monitor very low amplitude signal fiom
implantable sensors,” Circuits and Systems, 2000. Proceedings
of the 43rdIEEE Midwest Symposium o n , V01.l pp. 298 -301.
2000.
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