IEEE 2004 CUSTOM INTEGRATED CIRCUITS CONFERENCE
Efficient Capacitance Extraction Method for Interconnects with Dummy Fills
Atsush Kurokawa', 4, Toshiki Kanamoto2, Akira Kasebe3,Yasuaki In0ue4,and Hiroo Masuda'
'Semiconductor Technology Academic Research Center, Kanagawa,
'Renesas Technology Corp., Hyogo, 'Meitec Corp., Tokyo, 4Waseda University, Kitakyushu, Japan
Abstract
The accuracy of parasitic extraction has become increasingly
important for system-on-chip (SoC) designs. In this paper, we
present a practical method of dealing with the influences of
floating dummy metal fills, which are inserted to assist
planarization by the chemical-mechanical polishing (CMP)
process, in extracting interconnect capacitances. The method is
based on reducing the thicknesses of dummy metal layers
according to electrical field theory. We also clarify the
influences of dummy metal fills on the parasitic capacitance,
signal delay, and crosstalk noise. Moreover, we address that the
existence of the interlayer dummy metal fills has more significant
influences than the intralayer dummies in terms of the impact on
coupling capacitances. When dummy metal fills are ignored, the
error of capacitance extraction can be more than 30%, whereas
the error of the proposed method is less than about 10% for
many practical geometries. We also demonstrate, by comparison
with capacitance results measured for a 90-nm test chip, that the
error of the proposed method is less than 8%.
1. Introduction
With the scaling of semiconductor technology, the problems of
signal integrity, power integrity, and design for manufacturability
(DFM) have become more significant. The difficulty of timing
closure has dso become more serious. Precise reflection of
process information in the design is the key technology for
timing design. Parasitic extraction provides a starting point for
ensuring design accuracy. In general, dummy metal fills are
inserted to assist planarization by the chemical-mechanical
polishing (CMP) process [1,2]. The dummy fills introduce
several issues: 1) insertion during the design phase, 2) eMicient
insertion, 3) feature shape and size, and 4) parasitic extraction.
As solutions to some of these issues, researchers have reported
algorithms for efficiently inserting dummy fills [3,4] and feature
patterns for achieving uniformity of the capacitances of signal
line, such as the patterns shown in Fig. l(b) [SI, (c) and (d) [3].
~~~~
(a) (b) (c) (d)
Fig I Various patterns of dummy metal fills (a) traditional regular
squares, (b) cross-stitch rectangles, (c) alternate rectangles, and (d)
horizontal and vertical rectangles
Dummy fills are generally not inserted during place-and-route
nor layout timing verification, but rather just before fabricating
the mask. This is due to the reason that the placing of dummy
fills during layout design becomes an obstacle to cell placement
and routing changes. On the other hand, it is also possible to
insert dummy fills during final verification, which i s called back-
annotation. To extract the parasitic capacitances from layout
with dummy fills, however, requires enormous processor time
0-7803-8495-4/04/$20.00 02004 IEEE.
and memory for the pattern recognition and of the large number
of coupling capacitances. For example, if dummy fills consisting
of 0.8-pm square metal features and a half spacing are inserted in
a 20% area of a 1-cm2 chip with 10 metal layers, the number of
dummy fills will be more than one hundred million. As a result,
the insertion of dummy fills just before mask fabrication is a more
realistic approach.
Methods of extracting interconnect capacitances while
accounting for dummy fills have been proposed [5-81. Moreover,
optimization methods considering the dummy fills in both the
same layer and different layers have also been reported [5,6].
These methods are based on the technique of approximating the
areas of the dummy fills by utilizing the effective permittivity.
This approach is useful for selecting a critical path, and it is
necessary to extract the capacitance by employing the real
dummy fills placed more accurately. Although the proposed
method requires the calculation of the effective permittivity, it is
effective because it does not require any alteration of the design
flow or existing tools.
In this paper, we first investigate the influences of floating
metal fills on timing design for realistic LSI interconnect
geometries. Then, we propose a practical method of dealing with
such dummy fills. In the proposed method, the calculation of
parasitic capacitances can be accomplished simply by reducing
interlayer dielectric thickness of dummy fills' height. This
method is simpler than existing approaches and provides
reasonable accuracy. It requires small modifications in the
extraction tool but does not affect the current design
methodology.
The remainder of the paper is organized as follows. Section 2
examines the influences of floating dummy metal fills on the
parasitic capacitance of signal line, signal delay, and crosstalk
noise between signal lines. Section 3 discusses the electrical
phenomenon of floating conductors, presents our new method
of considering virtualheal dummy fills, and gives experimental
results demonstrating the effectiveness of this method.
2. Impact of Floating Dummy Metal-Fills
General system-on-chip (SoC) designs rarely consider dummy
fills in parasitic extraction. In this section, we analyze the
impacts of dummy fills on parasitic capacitance, signal delay, and
crosstalk noise by employing a 3-D field solver [9], with
intermediate layer parameters based on the 90-nm technology of
the ITRS [lo], as shown in Table 1.
Fig. 2 shows the results obtained by analyzing the influence
on the total capacitance of a single line. We assumed that the
width of the central signal line was equal to the minimum width,
wmin,and that the width of the dummy metal, wd,was 5 ~ , ~ ,The .
capacitance of signal line with dummy fills increases by 1535%
in the metal density range of about 20-70%.
We next analyzed the effect of the coupling capacitance with
dummy fills between signal lines. Fig. 3 shows the structure and
results for this analysis. When the spacing between the signal
24-2-1
 line and the dummy metal, s,, is the minimum width, the error of
the total capacitance, C, of the central signal line with and
without dummy fills is about 60%. If the spacing is more than S sd
0.12
0.1 60 -s .*.
-ctwitbMus
ctw/om
40
.... ccwithMus
low,,,,, the error becomes less than 20% due to the decrease of
coupling capacitances, C,, between the signal lines. This
demonstrates the importance of large spacing between the signal
Mi3 0U00
"._
0
'
E .e.Cc wlo Mus
-6-ErrorolCt

line and the dummy metal. 0 1 2 3

Fig. 4 shows the results obtained by analyzing the influence ssd (urn)

on the signal delay, based on the same structure and parameters (a) (b)
Fig. 3. Influence on capacitance with dlmmy fills between signal lines:
as those used for the results shown in Fig. 2. We assume that (a) side view of the structure, and (b) capacitance and error vs. spacing.
the wiring length is 1 mm, that the driving resistance, Rd, is 200Q,
and that the input gate capacitance of the next stage, C ,, is 5 E.
The propagation delay time was calculated by using Eq. ( I ) [ 1 11,
where R, and C, are the wiring resistance and capacitance,
respectively. The error of the propagation delay time can be
more than 20% as shown in Fig. 4(b).
Tpd = 0.693Rd(Cw+C,)+Rw(0.377Cw+0.693Cg). (1) 20 40 60
Next, we analyze the influence of dummy fills on crosstalk Densisty(%)
noise. Fig. 5 bows the results for the peak noise when the (a) (b)
Fig. 4. Influence of dummy fills on the signal delay: (a) circuit schematic,
dummy fills are not considered. The capacitances here are based and (b) delay and error vs. density.
on the results obtained by analyzing the structure shown in Fig.
3. The two lines on both sides are aggressors. The driving
resistance, wiring tngth, and input gate capacitances are the
same as those used in the above delay analysis. The peak noise
was calculated with the following equation [ 121:

0 1 2 3
Ssd (urn)
T 0.5{Ra(C,
T ~ ,= ~ +Cc)+Rv(Cv+ C , )
(a) (3)
+J(R,, (CO+ C, )- Rv (C, + Cc)p+ 4RaR,C: Fig. 5. Influence of dummy fills on crosstalk noise: (a) circuit schematic,
} '
and (h) peak voltage vs. spacing.
In the results, if the spacing between the signal line and the
dummy metal is more than 0.7 pn (i.e., k,,,),the peak noise is 3. Modeling of Dummy Metal Fills
suppressed to less than 90 mV for vdd=1 v. That is, the influence 3.1 Principle of a Floating Conductor
of dummy fills in the same layer can be limited by applying an We first discuss the principle of the capacitance around a
appropriate spacing rule between signal lines and dummy metal floating conductor that becomes the basis of our modeling in the
fills. next subsection. The capacitance of parallel planes with a
These results indicate that a design that does not consider floating conductor between them is equal to their capacitance
dummy fills may provide smaller estimates of the influences of excluding the thickness of the conductor. The capacitance of
the interconnect capacitance, delay, and crosstalk noise. Note the middle and right structures shown in Fig. 6 (a) is
that the spacing between signal lines and dummy metal fills is (3)
defined sufficiently large in existing design rules. The influences
E'W E'W
due to the interlayer are more important than those due to the
intralayer. We next propose a simple and efficient approach with where &isthe dielectric permittivity.
reasonable accuracy to these design issues. The capacitance with floating conductors between parallel
planes is approximately equal to that obtained by replacing the
Table 1. The structure arameters used in our anal sis. fills with a monolithic floating conductor, as shown in Fig. 6(a).
Parameter Value Fig. 6(b) shows the capacitance increases by inserting the
dummy fills and it is well reappeared by replacing the Boating
Dielectric Constant conductor. If the spacing between the fills, sd, is not very wide,
Minimum Width w nm 137.5
Metal Thickness t nm 233.15
the difference in capacitance is small.
ViaDe th h nm 206.25 Fig. 7(a) shows a cross-sectional structure composed of a
signal line s of width w,,,, a floating conductor 1 of width wd,and
an infinitely large ground plane g. The total capacitance of the
signal line to the ground is
1
Cs,,, =csg + (4)
Mi Z W $ I +&.I '
where C , is the capacitance between the signal line and the
Mi -2 20 30 40 SO 60 70 ground plane, C, is the capacitance between the signal line and
Density ("YO) the floating conductor, and C,, is the capacitance between the
(a) (b) ground plane and the floating conductor. Fig. 7 (b) shows a 2-D
Fig. 2. Capacitance of a signal line with and without dummy fills: (a) side
view, and (b) capacitance and error vs. density. simulated interlayer coupling capacitances as a function of the

486 24-2-2
width of the inserted floating conductor. The capacitance Cspl
increases with the conductor width, wd, and asymptotically
approaches Csl. The wider the floating metal width, the closer
the metal becomes to a virtual ground plane. Then, we have
lim cS, f=I(wd ) = c,,. (5)
Wd +-
This means that the capacitance of signal line increases when
larger sizes of floating dummy metals are inserted. Therefore, the
dummy size should be smaller from the viewpoint of signal line
capacitance.
Next, we consider a structure with two floating conductors
between the signal line and ground plane shown in Fig. 8(a).
Fig. 8(b) shows the results of the capacitance vs. spacing
obtained by a 2-D analysis. With the spacing, the capacitance is
increasing at first, decreasing while it is close to the capacitance
without the floating conductors. Assuming that two floating
conductors are symmetrical and that the voltage of floating
conductor 1, vI, equals that of floating conductor 2, v2 , the
capacitance is
As shown in Fig. 9(a), when the number of floating
conductors placed in the same layer between the signal line and
ground plane approaches infinity, by ignoring the influence of
the coupling capacitances between floating conductors, the
capacitance of signal line becomes
(7)
In addition, C, is very small, and then the conductors far from
the signal line do not influence the total capacitance of the signal
line, because the capacitances between the signal line and the
floating conductors become small with the distance. Then,
k the analysis are same as the values shown in Table 1. The width
1 of the signal line, w,, is the minimum width, w,,, and the width
where k is the number of effective floating conductors for the
approximation. Fig. 9(b) shows the validity of (8). From the
results of Figs. 8 and 9, we can see that the window size for
taking dummy fills into account is small.
h,h, h.h,
1 1
h,+h.
W - - of the proposed method with various dummy patterns, densities
0 0.5
Sd (urn)
(a) (b)
Fig. 6 . Difference in capacitance between parallel planes with floating
conductors and a monolithic floating conductor: (a) structures, and (b)
capacitance vs. fill spacing sd. The parameters are ~ 1 0 pm,
0 wd=l pm,
~ 0 . w,
4 hl= h2=0.4p,and q=4.
0.15 7 1
0 5 10
Sd (urn)
(a) @)
Fig. 8. Capacitance with two floating conductors between the signal line
and the ground plane: (a) structure, and (b) capacitance vs. the spacing sd
between the floating conductors. The parameters are ws=0.2 pm, wd=l
pm, ~ 0 . pun,
4 h=0.4 pm, and ~ = 4 .
S
"'0
="'& A'& 0.05 Eq.(8)
-g 0
0 10 20
k
(a) (b)
Fig. 9. Capacitance with floating conductors: (a) structure, and (b)
capacitance vs. the number of floating conductors for the approximation
of (8). The parameters are ws=0.2 pun, w,,=l pm, sd=0.6 pm, r 0 . 4 pm,
h=0.4 pm, and .5=4.
3.2 Proposed Modeling and Evaluation
The dummy fills used in real LSIs have small feature sizes, and
the spacings between fills are also small, so as to satisfy the
density rule. As a simple method for extracting the interconnect
capacitances, we propose to approximate the original structure of
a device by reducing the thickness of dummy fills based on the
principle described above. Fig. 10(a) and (b) shows the
illustration of the method. In this subsection, we examine the
accuracy of this method for various cases with the results
obtained by a 3-D field solver. Basically, the parameters used for
and spacing of dummy fills, wd and sd, are 5vmaand
respectively.
Fig. IO(c) shows the comparison of capacitance results
obtained by the original structures with those obtained by the
proposed approximate structures with various heights between
the signal line and dummy fills. Fig. 1 1(a) shows the validity of
the proposed method with various number of dummy fill layers.
Fig. 1l(b) shows the evaluation results of the proposed method
with various signal widths. Fig. 12 shows the evaluation results
and dummy metal widths.
From all these results, we can see that the errors with our
1 method are within about 10% for the general structures with
densities of 2 5 4 % and dummy widths up to 7wn,,,. In the case
of uniform fill placement with respect to the signal line for the
structures shown in Fig. l(bd), the errors are almost covered by
those obtained for the structures shown in Fig. 12.
3

&
0
1,. , , , , , ,,I 4 0!
E 1
- 1..............I I

0 10 20 0.2 0.25 0 3 0.35

Wd (urn) b l (urn)
(a) (b) (b) (c)
Fig. 7. Capacitance with a floating conductor between the signal line and Fig. IO. Verification of the proposed method with various heights between
the ground plane: (a) structure, and (b) capacitance vs. floating conductor the signal line and dummy fills: (a) original structure, (b) proposed
width w,. The parameters are ws=0.2pm, ~ 0 . p, 4 h=0.4 p,and t;=4. approximate stmcture, and (c) capacitance error vs. height h , .

487

1 2 3 0 0.5 1 1.5
No.of Dummy Layers ws (W
(a)
and (b) capacitance error vs. signal line width.
15
-wd=lO*wmin
20
@,.
Fig. 1 I . Verification of the proposed method with vanous number of
dummy fill layers and various signal line widths (a) capacitance error vs.
the number of dummy fill layers between the signal line and ground plane,
-wd=lO*wmin
p 10
v
*wd=7** E lo -wd=7’wmin
t s +wd=S*wmin 0 *wd=S*wrnin
$ 0
..%.- w d = 3 * m
wE -10 *wd=3*wmin
-5 -20
20 40 60 80 20 40 60 80
Density (%) Density (YO)
(a) (b)
Fig. 12. Verification of the proposed method with various dummy
patterns, densities and dummy metal widths in the structure shown in Fig.
2(a): (a) error of the proposed method for the signal line faced on the
dummy fills in the pattern shown in Fig. ](a), and (b) error of the
proposed method for the signal line faced on the spaces between dummy
fills in the pattern shown in Fig. I (a).
3.3 Application Methodologies
Dummy fills are generally not inserted during layout design. To
deal with dummy fills without altering the existing design flow,
we assume that virtual dummy fills are inserted uniformly based
on a design rule, such as the distance between the signal line
and the dummy metal. In this case, parasitic extraction can be
performed based on whether a space for the insertion of dummy
fills exists in the upper or lower layers. If there is such an area
for dummy fills, the dummy thickness is eliminated in the window
for extracting the interconnect capacitance. In contrast, if the
dummy fills are inserted before timing analysis but not just
before fabricating the mask, the characteristics of the real fills are
used. Our proposed method requires small modifications in the
parasitic extractor, such as characterization of simple structures
by reducing the dummy thickness with dielectric and recognition
of whether dummy fills or spaces exist in the window during
extraction. As a result, this method does not affect the current
design flow.
3.4 Experimental Results
We verify the validity of our proposed approach by examining
measurement results obtained using a test chip with 90-nm
process technology, 6 metal layers, and multiple dielectric
constants. The chip consists of parts of CBCM [131 circuits and
interconnects in order to obtain the objective signal line
capacitance. The interconnect structure is illustrated in Fig.
13(a) and (b). The signal line is the center line of three lines on
the third metal (M3) layer, the other two are ground lines, the line
width is 0.14 pn, and the length is 84.42 pn. The other features
are floating dummy metal fills. The fill shape is square, and the
width and spacing for the M2, M4, M5, and M6 fills are 1.68 pm
and 0.84 pn, respectively, while the width and spacing for the
M1 fills are 1 pn and 0.5 pn, respectively. The results for our
proposed method were obtained by eliminating the thicknesses
of the dummy metal layers other than the M3 layer. Fig. 13(c)
shows the comparison results. The error of the proposed
method is within about 8%. When the M2 and M4 layers are
treated as ground planes, the error becomes more than 66%. In
addition, if all the dummy fills are ignored, the error reaches more
488
$
than 27%. The proposed method is thus able to provide
reasonable accuracy in the typical, practical design environment.
-
0
1.7. I
*.-.“
., , ~,. ,
....... _ ”
~
.._.
Ground planes
_f_Mnsured
Proposed
Without fills
0 1 2 3 4 5 6 7
Spacing(urn)
(C)
Fig. 13. Comparison of the capacitances obtained by the proposed method
and measured for a test chip: (a) side view of the interconnects, @) 3-D
view of the interconnects, and (c) results for capacitance (arbitrary unit)
vs. the spacing between signal lines.
4. Conclusions
We have presented a practical approach for efficiently extracting
the interconnect capacitances with dummy metal fills. The
method is based on eliminating the thickness of the fills
according to electrical field theory. The accuracy is within 10%
for dummy fills of a practical size and density. We have also
clarified the influences of dummy fills on the capacitance, delay,
and crosstalk noise. The results measured for a test chip with
90-nm technology show good agreement with those obtained by
our proposed method.
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