IEEE ELECTRON DEVICE LETTERS, VOL. 18, NO.

1, JANUARY 1997 21

A Simple Method for On-Chip, Sub-Femto

Farad Interconnect Capacitance Measurement
Bruce W. McGaughy, James C. Chen, Dennis Sylvester, and Chenming Hu, Fellow, IEEE

Abstract— In this letter, a sensitive and simple technique for

parasitic interconnect capacitance measurement and extraction
is presented. This on-chip technique is based upon an efficient
test structure design that utilizes only two transistors in addition
to the unknown interconnect capacitance to be characterized.
No reference capacitor is needed. The measurement itself is also
simple; only a dc current meter is required. Furthermore, the ex-
traction methodology employs a self-checking algorithm to verify
that the extracted capacitance value is consistent and accurate.
The technique is demonstrated by extracting the capacitance of
a single crossover between a Metal 1 line and a Metal 2 of
0.44 fF. The resolution limit is dominated by the matching of
the minimum sized transistors used for the test structure. We
estimate this resolution limit to be about 0.03 fF.

I. INTRODUCTION

A S INTEGRATED circuits become increasingly laden

with metal interconnects, the resulting inter-metal capac-
itances are rapidly becoming the bottleneck in the design of
Fig. 1. An example of the test structures used to extract Metal 1 to Metal
2 cross-over overlap capacitance.

faster chips. Past on-chip interconnect capacitance techniques

have relied on either a reference capacitor and/or a complicated
test-structure design and measurement setup [2], [3]. Reference
capacitors can rarely be accurately designed and take up
valuable space. These methods also tend to be prone to not
only measurement error but fabrication error (e.g., variation)
of the reference capacitors as well [4]. Other methods usually
require more elaborate test structure designs [1]. Besides
consuming large area, these techniques usually provide poor
resolution capabilities. Sub-femto farad capacitances usually
cannot be measured directly.

II. TEST STRUCTURE, MEASUREMENT

SCHEME, AND EXTRACTION ALGORITHM
The proposed basic test structure is shown in Fig. 1. It
comprises a NMOS and PMOS transistor connected in a
“pseudo” inverter-like configuration (each has its own gate
input). To achieve the highest resolution, it is best to replicate
a second pseudo inverter next to the first, basic test structure
(see Fig. 1). This second test structure is identical to the first
in every manner except that it does not include the target
capacitance structure.
The and signals of Fig. 1 comprise two nonover-
lapping signals as shown in Fig. 2. The purpose of these
Manuscript received April 10, 1996; revised September 25, 1996. This
work was supported under SRC Contract IJ-148-A and HP under the MICRO
program.
The authors are with the Department of Electrical Engineering and Com-
puter Sciences, University of California, Berkeley, CA 94720-1772 USA.
Publisher Item Identifier S 0741-3106(97)00617-4.
0741–3106/97$10.00  1997 IEEE
Fig. 2. NMOS and PMOS are driven by nonoverlapping signals. These
signals ensure that no short circuit current will be measured.
nonoverlapping waveforms is to ensure that only one of
the two transistors in the basic test structure is conducting
current at any given time. Thus, any dc short-circuit current
(neglecting leakage current) from to ground is eliminated.
When the PMOS transistor turns on, it will draw charge from
to charge up the target interconnect capacitance. This
amount of charge will then be subsequently discharged through
the NMOS transistor into ground. An ammeter can be placed at
the source of the PMOSFET (or, alternatively at the source of
the NMOSFET) to measure this charging current. The actual
waveform of this charging current is of no consequence. Only
its dc current value needs to be measured. DC current can be
easily obtained from any modern current meter. The difference
22 IEEE ELECTRON DEVICE LETTERS, VOL. 18, NO. 1, JANUARY 1997

TABLE I
SUMMARY OF INTERCONNECT CAPACITANCES
EXTRACTED FROM THE SLOPES OFFIGS. 3 AND 4

Fig. 3. Inet as a function of frequency for seven Vdd values. The intercon-
nect capacitance can be extracted from the slope.

between the two dc current values in Fig. 1 is used to extract

the target interconnect capacitance as shown by

(1)
(2)

Since many pads can be shared (e.g., the pads for

well, and Ground of Fig. 1), the total number of probe pads
needed per structure is two (i.e., one for each supply). This
feature allows the basic test structure of Fig. 1 to be efficiently
replicated many times for characterization of any interconnect
capacitance structure of interest.

III. RESULTS
For this experiment, the test structure of Fig. 1 was fab- Fig. 4. Inet as a function of Vdd for three frequency values. The interconnect
ricated using an industrial 0.5 m technology. The actual capacitance can be extracted from the slope.
metal overlap area was 1.5 m 2.0 m or 3.0 m The
two nonoverlapping signals of Fig. 2 were generated on-chip between the transistors within the two test structures. For
(although they can be generated off-chip). The difference example, the measured dc current for the pseudo inverter with
between the two sets of average current values, , was then and without the target interconnect capacitance is given by (3)
measured. and (4), respectively.
In order to verify that the result is accurate, may be
plotted as a function of for specific frequency values (see
Fig. 3). The value of can then be extracted by dividing (3)
the slope of the fitted line by the appropriate frequency (4)
value. Alternatively, can also be plotted as a function of
frequency for specific values of (see Fig. 4). The value
of can then be extracted by dividing the slope by the is the unknown capacitance to be measured and is
appropriate value. The extracted capacitances have an the MOSFET gate to source/drain overlap capacitance plus
average value of 0.4431 fF with a maximum variation of 2%. junction capacitance plus any other parasitic capacitances.
This measured average value compared well to a RAPHAEL Ideally, if the two pseudo inverters are perfectly matched,
simulated value of 0.4731 fF for the identical capacitance the term would be completely subtracted out [see (1)]
structure. and would not impose a resolution limit. In reality, the
resolution limit is determined by the mismatch between the
parasitic capacitances, , of the two identical pseudo inverters
IV. DISCUSSION positioned close to each other. As a general rule, both the
In (2), an of A can be comfortably measured with NMOS and PMOS transistors of Fig. 1 should be designed
modern current meters. If MHz and V, this with small , i.e., with a small width close to the minimum
method can measure a value of F or 0.003 fF. width allowed by the design rules. We estimate that is
The real resolution limit of the proposed test method depends around 3 fF. Assuming the mismatch to be 1% [4], the
on the mismatch of the junction and overlap capacitances resolution capability of this method would be 0.03 fF.
MCGAUGHY et al.: SIMPLE METHOD FOR ON-CHIP, SUB-FEMTO FARAD INTERCONNECT CAPACITANCE MEASUREMENT
V. CONCLUSION
In this letter, a technique for characterizing interconnect
capacitances is presented. This technique has an estimated
sensitivity of 0.03 fF. For all practical purposes, this sensitivity
is more than necessary as it is a small fraction of the overlap
capacitance of a minimum width MOSFET. In addition, the
measurement setup is simple and direct—only a dc current
meter is required. Several self-checking extraction algorithms
ensure that the extracted capacitance value is robust and
accurate. A 0.44 fF capacitance of one Metal 1 to Metal 2
cross-over structure was extracted to illustrate the resolution
capability of this technique.
23
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