Fundamentals of Digital Computers: Unit - Ii

FUNDAMENTALS OF DIGITAL COMPUTERS
UNIT – II
2.1 DIGITAL LOGIC
2.1.1 THE BASIC GATES
A digital circuit having one or more input signals but only one output signal is
called a gate.
There are three basic gates,
 NOT GATE (INVERTER)
 AND GATE
 OR GATE
NOT GATE (INVERTER)
One of the most basic operations in a digital system is inversion, or negation.
This requires a circuit that will invert a digital level. This logic circuit is called an
inverter, or a NOT circuit. It is also referred as complement operation.
The complement of x is x.
The complement if x+y is x+y.
0 =1
1 =0
Inverter
The complementation operation is physically realized by a gate or circuit called
an Inverter.
Block diagram
Truth Table
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Pinout diagram of a 7404 inverter
The pinout diagram of a 7404 hex inverter. This IC contains six inverters. After
applying +5 Vdc (the supply voltage for all TTL devices) to pin 14 and grounding pin 7,
you can connect any or all inverters to other TTL devices.
OR GATE
The OR gate has two or more input but only one output. If either one or both
inputs are 1 (high) then the output will be 1 (high) otherwise the output will be 0 (low)
(or) when both input is 0 (low), the output will be 0 (low), otherwise the output will be
one (high).
Block diagram (Two Input)
Truth Table (Two Input)
Block diagram (Three Input)
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Truth Table (Three Input)
TTL OR Gate
The pinout diagram of a 7432, a TTL quad 2-input OR gate.
This digital IC contains four 2-input OR gates inside a 14-pin DIP. After
connecting a supply voltage of +5 V to pin 14 and a ground to pin 7, we can connect one
or more of the OR gates to other TTL devices.
Timing Diagram
An example of a timing diagram for a 2-input OR gate.
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The input voltages drive pins 1 and 2 of a 7432. Here the output (pin 3) is low
only when both inputs are low. The output is high the rest of the time because one or
more input pins are high.
AND GATE
The AND gate has two or more input but only one output. If both inputs are 1
then the output will be 1 otherwise the output will be 0.(or) If any one of the input is
zero, the output will be zero, otherwise the output will be one.
Truth table (Two Input)
Truth table (Three Input)
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TTL AND Gates

The pinout diagram of a 7408, a TTL quad 2-input AND gate.
This digital IC contains four 2-input AND gates. After connecting a supply
voltage of +5V to pin 14 and a ground to pin 7, you can connect one or more of the
AND gates to other TTL devices. TTL AND gates are also available in triple 3-input and
dual 4-input packages.
Timing Diagram
An example of a timing diagram for a 2-input AND gate. The input voltages
drive pins 1 and 2 of a 7408. Notice that the output (pin 3) is high only when both
inputs are high (between C and D, G and H, etc.). The output is low the rest of the time.
2.1.2 UNIVERSAL LOGIC GATES

A universal logic gate is a gate which can implement any Boolean function
without need to use any other gates type.
The universal logic gates are,
 NOR GATE
 NAND GATE
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NOR GATE
The complement of OR gate is called NOR gate. NOR has an OR gate followed
by an inverter (NOT gate).
Symbol for NOR Gate
The new IEEE rectangular symbol for the NOR gate is,
The small triangle on the output is equivalent to the bubble used on the standard
symbol. The indicator ≥ inside the box means "if one or more of the inputs are high, the
output is high."
The 7402 is a quad 2-input NOR gate in a 14-pin DIP and the new rectangular
symbol for the 7402.
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Symbol for NOR Gate
Bubbled AND Gate
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The bubbled AND gate is the combination of two NOT gates and one AND gate.
That is, the output of two NOT gates is made as input of AND gate.
The Boolean expression for the output of this gate is,
Y = A . B = A + B (Demorgan’s theorem)
Universality of NOR Gate
We can get the other basic gates (NOT, OR, AND) from NOR gate. This is called
as universality of NOR gate.
1) NOT from NOR 2) OR from NOR
3) AND from NOR
NAND GATE
The complement of AND gate is called NAND gate. NAND has an AND gate
followed by an inverter (NOT gate).
Symbol for NAND Gate
The new IEEE symbol for NAND gate is,
The small triangle on the output is equivalent to the bubble used on the standard
symbol. The indicator "&" inside the box means "the output is high only when all inputs
are high."
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The 7400 is a quad 2-input NAND gate in a 14-pin DIP and the new rectangular
symbol for the 7402.
Symbol for NAND Gate
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Bubbled OR Gate
The bubbled OR gate is the combination of two NOT gates and one OR gate.
That is, the output of two NOT gates is made as input of OR gate.
The Boolean expression for the output of this gate is,
Y = A + B = A . B (Demorgan’s theorem)
Universality of NAND Gate
We can get the other basic gates (NOT, OR, AND) from NAND gate. This is
called as universality of NAND gate.
1) NOT from NAND 2) AND from NAND:
3) OR from NAND
2.1.3 AND-OR-INVERT GATES

Here shows an AND-OR circuit and shows the De Morgan equivalent circuit, a
NAND-NAND network. The Boolean equation for these circuits is
Y=AB+CD
Since NAND gates are the preferred TTL gates, we would build the circuit.
NAND-NAND circuits like this are important because with them we can build any
desired logic circuit.
TTL Devices
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AND-OR circuits are not easily derived from the basic NAND-gate design. But it
is easy to get an ANDOR-INVERT circuit.
A variety of circuits like this are available as TTL chips. Because of the inversion,
the output has the equation shown below.
Y= AB+CD
The AND-OR-INVERT gates available in the 7400 series are
In this table, 2-wide means two AND gates across, 4-wide means four AND gates
across, and so on.
For instance, the 7454 is a 2-input 4-wide AND-OR-INVERT gate; each AND gate
has two inputs (2-input), and there are four AND gates (4-wide).
The 7464; it is a 2-2-3-4-input 4-wide AND-OR-INVERT gate.
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Connecting the output of a 2-input 2-wide AND-OR-INVERT gate to an inverter

will give us the same output as an AND-OR circuit.
Expandable AND-OR-INVERT Gates
The widest AND-OR-INVERT gate available in the 7400 series is 4-wide. When
we need a 6- or 8-wide circuit, we can use an expandable AND-OR-INVERT gate.
The logic symbol for an expandable AND-OR-INVERT gate. There are two
additional inputs, labeled bubble and arrow.
The expandable AND-OR-INVERT gates in the 7400 series are,
Expanders
We connect the output of an expander to the arrow and bubble inputs of an
expandable gate (connect bubble to bubble and arrow to arrow).
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This shows the logic circuit of the outputs expander connected to the arrow and
bubble inputs of the expandable AND-OR-INVERTER gate. This means that the
expander outputs are being ORed with the signals of the AND-OR-INVERT gate.
In other words, the logic circuit is equivalent to the AND-OR-INVERT circuit.
We can connect more expanders. The circuit shows two expanders driving the
expandable gate. Now we have a 2-2-4-4-input 4-wide AND-OR-INVERT circuit.
The 7460 is a dual 4-input expander. The 7450, a dual expandable AND-OR-
INVERT gate, is designed for use with up to four 7460 expanders. This means that we
can add two more expanders in above circuit to get a 2-2-4-4-4-4-input 6-wide AND-
OR-INVERT circuit.
2.1.4 POSITIVE AND NEGATIVE LOGIC:
If we use the binary 0 for low voltage and binary 1 for high voltage, then it is
called as positive logic.
If we use the binary 0 for high voltage and binary 1 for low voltage, then it is
called as negative logic.
Positive and Negative Gates
An OR gate in a positive logic system becomes an AND gate in a negative logic
system.
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This circuit is an OR gate when we use it in positive logic, if either the input is
high, the output is high, that is in positive logic system, binary 0 stands for low and
binary 1 stands for high.
We can convert this table to the form of binary form of 0s and 1s.
In a negative logic, binary 1 stands for low and binary 0 stands for high. With
this logic, we can convert the above the table as,
In a similar way, we can show the truth table of other gates with positive or
negative logic.
By analyzing the inputs and outputs in terms of 0s and 1s, we find these
equivalences between the positive and negative logic:
These gates and their definitions in terms of voltage levels are summarizes as,
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2.2 COMBINATIONAL LOGIC CIRCUITS

Fundamental concepts of Boolean Algebra:
When a variable is used in an algebraic formula, it is generally assumed that the
variable may take any numerical value.
The variables used in Boolean equations have unique characteristic that they may
assume only one of two possible values; these two values may be represented by the
symbol 0 and 1.
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Example,
 X+Y=Z
Each of the variables X, Y and Z may have only the values 0 or 1.
The + symbol is placed between two variables say X and Y since both X and Y
can take only the role 0 or 1.
Logical Addition
First important operation in Boolean algebra is logical Addition or the logical OR
operation. This is a logical addition table.
Input Output
0+0 0
0+1 1
1+0 1
1+1 1
Logical Multiplication
A second important operation in Boolean algebra is logical multiplication or the
logical AND operation.
Input Output
0.0 0
0.1 0
1.0 0
1.1 1
Only when both inputs are 1 the result will be 1.
Both + and . obey a mathematical rule called the associative law.
This law says for +
(X + Y) +Z = X + (Y + Z)
And for . X. (Y . Z) = (X . Y) . Z
2.1 BOOLEAN LAWS AND THEOREMS:
2.1.1 Boolean algebra rules:
X+Y=Y+X
X .Y = Y . X COMMUTATIVE LAW
X + (Y + Z) = (X + Y) + Z
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X (Y Z) = (X Y) Z ASSOCIATIVE LAW
X ( Y + Z ) = X Y +X Z - DISTRIBUTIVE LAW
0+X=X
1+X=1
X+X=X OR Operations
X+X=1
1.X=X
0.X=0
X.X=X AND Operations
X.X=0
X=X - Double Inversion
X+Y=X.Y
X.Y=X+Y DEMorgan’s Theorem
X=X
X+XZ=X
X(X+Y)=X
(X+Y)(X+Z)=X+YZ
X+XY=X+Y
XY + YZ +Y Z = XY +Z
2.1.2 PROVE THE COMMUTATIVE LAW:

1. X + Y = Y + X
2. X . Y = Y. X
1. X + Y = Y + X
L.H.S = X + Y
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R.H.S = Y + X
L.H.S = R.H.S
Hence X + Y = Y + X is proved.
Logic circuit:
2. X . Y = Y . X
L.H.S = X . Y
R.H.S = Y . X
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L.H.S = R.H.S
Hence X . Y = Y . X is proved
Logic circuit:
2.1.3 PROVE THE ASSOCIATIVE LAW:

1. X + (Y + Z) = (X + Y) + Z
2. X (Y Z) = (X Y) Z
1. X + (Y + Z) = (X + Y) + Z
L.H.S = X + (Y + Z)
R.H.S = (X + Y) + Z
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L.H.S = R.H.S
Hence X + (Y + Z) = (X + Y) +Z is proved.
Logic Circuit:
2. X (Y Z) = (X Y) Z
L.H.S = X (Y Z)
R.H.S = (X Y) Z
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L.H.S = R.H.S
Hence X(Y Z) = (X Y)Z is proved.
Logic Circuit:
2.1.4 PROVE: DISTRIBUTIVE LAW:

X (Y + Z) = XY + XZ
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The last columns are equal in R.H.S and L.H.S

Since X(Y+Z) = XY + XZ is proved
Logic Circuit:
2.1.5 DEMORGAN’S THEOREM:

X+Y=X.Y
X.Y=X+Y
In these rules, two steps are used form a complement
1. The + symbols are replaced with . Symbol and . symbols with + symbol
2. Each of the terms in the expression is complemented.
L.H.S
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R.H.S
The last columns in L.H.S and R.H.S are equal.

Hence X + Y = X . Y proved.
L.H.S
R.H.S
The last columns in L.H.S and R.H.S are equal

Hence X . Y = X + Y proved.
2.1.6 DUALITY THEOREM:
The duality theorem is one of the most elegant theorems proved in advanced
mathematics. We will state the theorem without proof.
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The basic duality of a Boolean algebra is deriving a Boolean algebra from another
Boolean algebra is,
1. Changing each OR sign to an AND sign
2. Changing each AND sign to an OR sign
3. Complementing 0 or 1 appearing in the expression
De Morgan’s theorem expresses a basic duality which underlies all Boolean
algebra.
For example,
X + 0 =X is the dual of X.1 = X
(X + Y) + Z = X + (Y + Z) is the dual of (XY)Z = X(YZ) and
2.1.7 COVERING AND COMBINATION:
The covering rule, where one term covers the condition of the other term so that
the other term becomes redundant, can be represented in dual form as,
X+XY =X
and X(X+Y) = X
The combining rules are,
XY + XY = X
And in its dual form (X+Y) (X+Y) = X
2.1.8 CONSENSUS THEOREM:
The consensus theorem finds a redundant term which is a consensus of two
other terms. The idea is that if the consensus term is true, then any of the other terms is
true and thus it becomes redundant. This can be expressed in dual form as,
In the first expression, BC is the consensus term and thus redundant. This is
because if BC= 1, then both B = 1 and C = 1 and any of the other two terms AB or AC
must be one as either A = 1 or A = 1.
Similarly, in the second expression, (B + C) is the consensus term and if this term
is 0 then both B = 0 and C = 0. This makes one of the other two sum terms 0 as either
A= 0 or A= 0.
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INTERCONNECTING GATES
The OR gates, AND gates and inverters can be interconnected to form gating or
logic networks.
The Boolean algebra expression corresponding to a given gating network can be
derived by systematically progressing from input on the gates.
It is the gating network with three inputs X, Y and Z and an output expression
(X.Y) + Z.
It is the gating network with two inputs X and Y and an output expression
(X.Y) + X.Y
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Canonical Forms for Boolean Functions:

Boolean functions are expressed as sum of minterms or product of maxterms are
said to be in “Canonical Form”
Minterms and Maxterms:
A binary variable may appear either in its normal form(X) or in its complement
form(X).
Two binary variables X and Y combined with an AND operation, since each
variable may appear in either form,
X .Y, X.Y, X.Y, X.Y
These products are called fundamental or standard products, these standard
products are also called as minterms.
Similarly the binary variables are forming an OR term provide 2 n possible
combinations are X+Y, X + Y, X + Y, X + Y called maxterms or standard sums.
Minterms and Maxterms for three variables
There are two methods widely used to convert the truth table to a logical
expression, they are
 Sum of Product ( SOP)
 Product of Sum (POS)
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2.2 SUM OF PRODUCT (SOP):

A sum of product expression is a product term or several product terms (min
term) are logically added (ORed) together.
Here shows the four possible ways to AND two input signals that are in
complemented and uncomplemented form. These outputs are called fundamental
products.
The each fundamental product next to the input conditions producing a high
output.
For example,
A B is high when A and B are low; AB is high when A is low and B is high; and
so on. The fundamental products are also called minterms.
Products A' B', A'B, AB', AB are represented by m0, m1, m2, and m3 respectively.
The suffix i of mi comes from decimal equivalent of binary values that makes
corresponding product term high.
The idea of fundamental products applies to three or more input variables. For
example, assume three input variables: A, B, C and their complements. There are eight
ways to AND three input variables and their complements resulting in fundamental
products of
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The above three variable minterms can alternatively be represented by mo, m1,
m2, m3, m4, m5, m6, and m7 respectively.
Derivation of the sum of Product

Consider the two variable A and B, these are four possible combinations,
Truth Table of 2 variables
To write the standard sop expression for the truth table, select the rows whose
output is 1.
For the first row Y=1 where A = 0 and B = 0 so A B = 1
Similarly, for the third row Y=1 where A = 1 and B = 0 so A B = 1
Hence the two standard products are A B and A B. These two standard products
are logically summed to give the SOP expression.
We can simplify using Boolean algebra rules,
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Truth Table for three variables A, B, C
Y=1 when A = 0, B = 0 and C = 1 the standard product is A B C.

A = 1, B = 0 and C = 1 the standard product is A B C.
Therefore the standard sum of product expression is
2.3 K-MAP METHOD FOR SIMPLIFYING THE EXPRESSION:

KARNAUGH MAP METHOD:
An alternative and more elegant way of simplifying Boolean expression is called
Karnaugh map (K-map) method.
Karnaugh map is a two dimensional representation of truth table.
It can be rectangular or square in shape and is divided into number of square
cells; the number of cells in a map depends on the number of variables.
TWO VARIABLES K-MAP:
Two variables take four possible values 00, 01, 10, 11. They corresponds to the
min terms
A B, A B, A B, A B and m0, m1, m2, m3 respectively.
It is useful to note the number of the min terms in one corner of the cell.
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The cell numbered 0 represents min term (m0) A B and A=0, B=0
Truth Table
The map is filled by placing 1’s in the square or cells for each term which leads to
a 1 output.
The remaining two cells are filled with 0’s and we have to use 1’s for
simplification.
Hence the expression Y=∑ (2, 3)
THREE VARIABLE K-MAP:

It has eight cells representing min terms m0, m1, m2, …to m7. Consider the three
variables A, B and C.
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The binary combination for A is taken 0 and 1, for BC these are four possible
binary combinations 00, 01, 10, 11.
But instead of using normal binary progression gray code format is used that is
the BC combination is taken as 00, 01, 11 and 10.
So that we go from one cell to the next cell. This is only one code change in the
binary combination.
To fill the K-map, we have to collect the min terms for which the output Y=1.
Truth Table:
Y=1, when A=0, B=0 and C=1 so the min term is A B C = m1

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The truth table is represented by the expression in terms of sum of minterms,
Y=A B C + A B C+ A B C +A B C
Hence 1’s entered in the cells with minterm numbers 1, 5, 6 and 7, the remaining
cells are filled with 0’s.
FOUR VARIABLES K-MAP:-

It has sixteen cells representing minterms m0 to m15; the four variables are A, B,
C, D.
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PAIRS:
A pair is a group of two1’s which are horizontally or vertically adjacent.
Example:
QUAD:
Quad is a group of four 1’s which are horizontally or vertically adjacent.
Example:
OCTET:
An octet is a group of eight 1’s an octet element.
Example:
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REDUNDANT GROUP:
If all the elements are belongs to the other group that can be eliminated.
Example:
ROLLING OF GROUP:
An element which is common to more than one group is called rolling of group.
Example:
SUB CUBES AND COVERING

A subcube is a set exactly 2m adjacent cells containing 1’s for m=0, the subcube
consists of single cell, for m=1 the subcube consists of two adjacent cells.
Example:
The subcube of two cells for the expression for m=2 a subcube has four adjacent
cells.
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Example:
There are two subcubes are available, they are

 Maximal subcube
 Minimal subcube
Maximal Subcubes:
A maximal subcube is the largest subcube that can be found around a given
minterm.
Minimal subcube:
Minimal expression is formed from a collection of few cubes as possible, each of
which is large as possible.
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2.4 KARNAUGH SIMPLIFICATION

1. Find the Boolean function for the given k-map sketch the AND-OR network
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2. Simplify the Boolean function

F(A,B,C,D)= ∑(1,2,6,7,11,12,14,15)
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2.5 DON’T CARES

Sometimes designers does not care what the outputs are for the particular input
such outputs are called don’t care output.
Since don’t care output values are of no importance, they may be filled with 1’s
and 0’s in any way.
Don’t care are mentioned as D or X.
This karnaugh map of the table of combination with D’s in the appropriate
places, a D may be used as either a 1 or 0.
So D’s are used to complete or enlarge the subcube whenever possible, otherwise
ignored.
Example:
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Simplify Y = F(A,B,C,D) =∑(2,3,4,5)+ ∑d(10,11,12,13,14,15)
The minterm m4 and m5 can form a pair and give an expression A B C, but the
two don’t care D’s at cells 12 and 13 can be treated as 1’s then minterm m4, m5, m12,
m13 form a quad to give B C.
Similarly the 1’s in cells 2 and 3 and D’s in cells 10 and 11 form a quad to give
B C.
Hence the final result is,
2.6 PRODUCT OF SUM (POS)

A product of sum expression is a sum term or several sum terms (max terms)
logically multiplied (AND ed) together.
For example,
(X + Y) . (X + Y) is a product of sums expression.
The first term is a sum of X and Y.
The second term is a sum of X and Y.
Since the sum terms (X + Y), (X + Y) are logically multiplied to give the product
of sum expression.
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The first output 0 appears for A= 0, B = 0, and C = 0. The fundamental sum for
these inputs is A+ B + C. Because this produces an output zero for the corresponding
input condition:
Y=A+B+C = 0+0+0 = 0
The second output 0 appears for the input condition of A= 0, B = 1, and C = 1.
The fundamental sum for this is A + B + C. Notice that B and Care complemented
because this is the only way to get a logical sum of 0 for the given input conditions:
Y=A+B+C = 0+1+1 = 0+0+0 = 0
Similarly, the third output 0 occurs for A = l, B = 1, and C = 0; therefore, its fundamental
sum is A + B + C:
Y=A+B+C = 1+1+0 = 0+0+0 = 0
To get the product-of-sums equation, all we have to do is AND the fundamental
sums:
Y = (A+ B + C) (A + B + C) (A + B + C)
Logic Circuit
The logic circuit for the product of sum expression is
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Derivation of product of sum

Consider the truth table is
A B Y
0 0 1
0 1 0
1 0 1
1 1 0
To write the standard POS expression for the truth table, select the rows whose
output is 0.
For the second row Y = 0 where A = 0 and B = 1 so A + B =0
Similarly, for the fourth row Y = 0 where A = 1 and B =1 so A + B = 0
Hence the two standard max terms are A + B and A + B. These two standard sum
terms are logically multiplied to give the POS expression.
We can simplify using Boolean algebra rules,
Derivation of a three input variable expression

Truth Table for three variables A, B, C
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Sum of Products
To write the standard SOP expression for the truth table, select the rows whose
output is 1.
SOP expression is
Products of sum
To write the standard POS expression for the truth table, select the rows whose
output is 0.
POS expression is
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FUNDAMENTALS OF DIGITAL COMPUTERS

Pinout diagram of a 7404 inverter

Truth Table (Two Input)

Block diagram (Three Input)

Truth Table (Three Input)

An example of a timing diagram for a 2-input OR gate.

Truth table (Two Input)

Block diagram (Three Input)

Truth table (Three Input)

TTL AND Gates

2.1.2 UNIVERSAL LOGIC GATES

Symbol for NOR Gate

Truth table (Two Input)

Block diagram (Three Input)

Symbol for NOR Gate

Truth table (Three Input)

Bubbled AND Gate

3) AND from NOR

Symbol for NAND Gate

The new IEEE symbol for NAND gate is,

Block diagram (Three Input)

Symbol for NAND Gate

Truth table (Three Input)

2.1.3 AND-OR-INVERT GATES

The 7464; it is a 2-2-3-4-input 4-wide AND-OR-INVERT gate.

Connecting the output of a 2-input 2-wide AND-OR-INVERT gate to an inverter

2.2 COMBINATIONAL LOGIC CIRCUITS

2.1.2 PROVE THE COMMUTATIVE LAW:

2.1.3 PROVE THE ASSOCIATIVE LAW:

2.1.4 PROVE: DISTRIBUTIVE LAW:

The last columns are equal in R.H.S and L.H.S

2.1.5 DEMORGAN’S THEOREM:

The last columns in L.H.S and R.H.S are equal.

The last columns in L.H.S and R.H.S are equal

Canonical Forms for Boolean Functions:

2.2 SUM OF PRODUCT (SOP):

Derivation of the sum of Product

Truth Table for three variables A, B, C

Y=1 when A = 0, B = 0 and C = 1 the standard product is A B C.

2.3 K-MAP METHOD FOR SIMPLIFYING THE EXPRESSION:

THREE VARIABLE K-MAP:

Y=1, when A=0, B=0 and C=1 so the min term is A B C = m1

Y=1, when A=1, B=1 and C=0 so the min term is A B C = m6

FOUR VARIABLES K-MAP:-

SUB CUBES AND COVERING

There are two subcubes are available, they are

2.4 KARNAUGH SIMPLIFICATION

2. Simplify the Boolean function

2.5 DON’T CARES

Simplify Y = F(A,B,C,D) =∑(2,3,4,5)+ ∑d(10,11,12,13,14,15)

2.6 PRODUCT OF SUM (POS)

Derivation of product of sum

Derivation of a three input variable expression

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