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Course Content

Foundation Course – VLSI – Level 1

Course Structure for B.Tech 2nd year 3rd & 4th semester
Analog Hardware Circuit Design – Digital CPLD & FPGA Verilog - 4th Sem (30 Hrs)
Fundamentals & (30 Hrs)- 3rd Sem Introduction (30 hrs)- 4th
Circuit Sem
Implementation on
Tools (30 hrs) -3rd
Sem
 Introduction of  Hardware Design of Various  Introduction to FPGA  Introduction of RTL Flow.
VLSI Flow Combinational & sequential & CPLD  Introduction of Verilog.
 Introduction of Circuit.  Application of FPGA  Methodologies
network  Project 1: Hardware Design of 4 & CPLD  Gate Level
elements and its bit Sign Calculator and  Advantage &  Data Flow
properties. implementation on FPGA’s. Disadvantage of FPGA  Behavioural
 Understanding  Calculator Components like: & CPLD  Test Bench
the fundamental Adder, Subtractor, Multiplier,  CPLD & FPGA  FSM Modeling
of KCL, KVL, Divider, Comparator, Mux, Architecture  Synthesis
Source Demux, Encoder, Decoder, 2s  FPGA & FLOW  RTL Flow
Transformation, Complement etc.  Implementation on  Technology Flow
Resistance  Project 2: Hardware Design of 4 Various Interfaces  Implementation of all
equivalent, Star way traffic light control system like : combination & sequential
to Delta and and implementation on FPGA’s.  LED circuit on FPGA using
Delta to star  Traffic Light Components:  Seven Segment Verilog.
transformation, Latch, SR Latch, JK latch, JK FF, Decoder  LED Implementation of 4bit
and it’s DFF, TFF, Counters (  Development Board : Sign calculator on FPGA
numerical. Synchronous , Asynchronous , Nexys A7 , Artix 7 using Gate level Verilog
 Understanding of UP- Down , Odd –Even , Mod , series development  SSD Implementation of
Theorems like Johnson & Ripple, Shift board from Digilent Traffic Light Controller on
Thevinin, Norton, Registers (SISO, SIPO , PISO & inc. FPGA using Behavioural FSM
Super-position PIPO) Modeling using Verilog
and Maximum  Project 3: Hardware Design of  SSD Implementation of
Transfer different Led Pattern & Digital Clock on FPGA using
Theorem and it’s Implementation on FPGA’s. Verilog.
numerical.  Project 4: Hardware Design of  SSD Implementation of Stop
 Understanding FIFO & LIFO Implementation on watch on FPGA using Verilog
of RC circuit with FPGA’s.  SSD Implementation of Stop
different sources.  Project 4: Hardware Design of watch on FPGA using Verilog
 Introduction of Digital Clock and Stop watch &  Interface based Project:
Electronic Device Implementation on FPGA’s.  VGA Interface
circuit.  UART Interface
 Semiconductor  Key board Interface
material and its  LCD Interface
properties, Basic  Temperature Sensor
information of  Tool
Doping,
th
PinE Training Academy LLP Address- Care of- Aujus Technology Private Limited, C 56-28, 4 Floor, Sector 62, Noida, UP India
201301, Email – info@pinetrainingacademy.com website www.pinetrainingacademy.com, LLP Registration Number –AAK-5737
 PinE TRAINING ACADEMY LLP
“Building Career is our Passion”
Diffusion,  Vivado
Conductivity,  ISE
Mobility of
material and
more on.
 Working of Diode
and its numerical
on the basis of
application.
 Introduction of
Bipolar Junction
Transistor and its
region of
operation in
terms of
numerical.
 Circuit designing
on tools and
analysis like DC
analysis, Power
analysis,
Transient
analysis,
Temperature
effect, Corner
frequency and
more on.

th
PinE Training Academy LLP Address- Care of- Aujus Technology Private Limited, C 56-28, 4 Floor, Sector 62, Noida, UP India
201301, Email – info@pinetrainingacademy.com website www.pinetrainingacademy.com, LLP Registration Number –AAK-5737