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Interconnection Topologies and Synchronizationn
Interconnection Topologies and Synchronizationn
M M M M M M
Global Interconnection Network
M M M
• Synchronous Communication
• Transmitter and receiver have their clocks synchronized
• Data rates are dependent on clock rates
• Continuously transmitting characters to remain in sync.
• The above figure indicates a basic arrangement when the CPU contains
the bus arbiter circuitry.
• In this case, the processor is normally the bus master, unless it grants the
ownership to any of the devices.
• A DMA controller indicates that it needs to become a bus master by
activating the bus request line \BR (‘BR bar’). The signal on the BR line is a
logical OR of the requests from all the devices connected to it. When BR
line is activated.
Switched Network
• Switched paths
• Higher cost
• Higher throughput
• Scalability better
Linear 2D-Mesh
Tree
Star
Ring
Torus
Fully Connected
non-blocking