Finite State

Machines
in VHDL
Eng. M. M. Shiple
Definitions
„ A finite state machine (FSM) is a
sequential circuit with “random” next-state
logic.
Introduction
„ The models selected will influence a
design but there are no general indications
as to which model is better.
 Moore FSM
Process (clock, reset)
Inputs Next State
function
Next State Present State
clock Present State
reset Register

Output Outputs
concurrent function
statements
 Mealy FSM
Process (clock, reset)
Inputs Next State
function
Next State Present State
clock Present State
reset Register

Output Outputs
concurrent function
statements
 Moore FSM - Example 1
„ Draw Moore Recognizes Sequence “1 then 0”

Condition
State Name (S0 : start)
Transition 0
Output inside the state
S0 / 0 Asynchronous Interrupt

reset
 Moore FSM - Example 1
„ Define the output if the input=‘1’;

0 1
1
S0 / 0 S1 / 0
NOP
If input= ‘1’
reset Detect if
input=‘1’
 Moore FSM - Example 1
„ The sequence complete perfectly

0 1
0
1
S0 / 0 S1 / 0 S2 / 1

reset Force
Detect if Out<= ‘1’
input=‘0’
 Moore FSM - Example 1
0 1
0
1
S0 / 0 S1 / 0 1 S2 / 1

rst i/p Crt st Nxt st o/p

reset 0
1 - - S0 0
0 0 S0 S0 0
0 1 S0 S1 0
0 0 S1 S2 1
0 1 S1 S1 0
0 0 S2 S0 0
0 1 S2 S1 0
Mealy FSM - Example 1
„ Draw sequence recognition with mealy
Condition
Output outside states

0/0 State Name (S0 : start)

S0

reset
Mealy FSM - Example 1
0/0 1/0 1/0

S0 S1

reset 0/1 rst i/p Crt st Nxt st o/p

1 - - S0 0
0 0 S0 S0 0
0 1 S0 S1 0
0 0 S1 S0 1
0 1 S1 S1 0
 Moore FSM - Example 1
„ VHDL of Moore: Again
0 1
0
1
S0 / 0 S1 / 0 1 S2 / 1

reset 0
 Moore FSM in VHDL (1)

------------------------------------------------------------
clocked : PROCESS ( clk, rst )
--------------------------------------------------------
BEGIN rst i/p Crt st Nxt st o/p
IF (rst = '1') THEN
current_state <= s0;
1 - - S0 0
-- Reset Values 0 0 S0 S0 0
ELSIF (clk'EVENT AND clk = '1') THEN
current_state <= next_state; 0 1 S0 S1 0
-- Default Assignment To Internals
END IF;
0 0 S1 S2 1
END PROCESS clocked; 0 1 S1 S1 0
0 0 S2 S0 0
0 1 S2 S1 0
 Moore FSM in VHDL (1)
nextstate : PROCESS ( a, b, current_state )
---------------------------------------------------------
BEGIN
CASE current_state IS
WHEN S0 =>IF input = ‘1’ THEN
current_state <= S1;
ELSE
current_state <= S0;
END IF;
WHEN S1 =>IF input = ‘0’ THEN rst i/p Crt st Nxt st o/p
current_state <= S2;
ELSE
1 - - S0 0
current_state <= S1; 0 0 S0 S0 0
END IF;
WHEN S2 =>IF input = ‘0’ THEN 0 1 S0 S1 0
current_state <= S0;
ELSE
0 0 S1 S2 1
current_state <= S1; 0 1 S1 S1 0
END IF;
END CASE; 0 0 S2 S0 0
END IF;
END PROCESS nextstate
0 1 S2 S1 0
 Moore FSM in VHDL (2)
Output <= ‘1’ WHEN current_state = S2 ELSE ‘0’;
---------------------------------------------------------
output : PROCESS ( current_state )
---------------------------------------------------------
BEGIN
-- Default Assignment rst i/p Crt st Nxt st o/p
o/p <= '0';
-- Default Assignment To Internals
1 - - S0 0
-- State Actions 0 0 S0 S0 0
CASE current_state IS
WHEN s2 => o/p <= '1'; 0 1 S0 S1 0
WHEN OTHERS => NULL;
END CASE;
0 0 S1 S2 1
0 1 S1 S1 0
END PROCESS output;
0 0 S2 S0 0
0 1 S2 S1 0
Mealy FSM - Example 1
„ Mealy FSM that Recognizes Sequence
“10” 0/0 1/0 1/0

S0 S1

reset 0/1
 Mealy FSM in VHDL (1)

-----------------------------------------
clocked : PROCESS ( clk, rst )
----------------------------------------
BEGIN
IF (rst = '1') THEN
current_state <= s0;
-- Reset Values
x <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
current_state <= next_state; rst i/p Crt st Nxt st o/p
-- Registered output assignments
x <= x_int;
1 - - S0 0
-- Default Assignment To Internals 0 0 S0 S0 0
END IF;
END PROCESS clocked; 0 1 S0 S1 0
0 0 S1 S0 1
0 1 S1 S1 0
 Mealy FSM in VHDL
--------------------------------------------------------
(2)
nextstate : PROCESS ( a, b, current_state )
--------------------------------------------------------------
BEGIN
CASE current_state IS 0/0 1/0 1/0
WHEN S0 =>
IF input = ‘1’ THEN S0 S1
next_state <= S1;
ELSE reset 0/1
next_state <= S0;
END IF;
WHEN S1 =>
IF input = ‘0’ THEN rst i/p Crt st Nxt st o/p
next_state <= S0;
ELSE 1 - - S0 0
next_state <= S1; 0 0 S0 S0 0
END if;
WHEN OTHERS => next_state <= s0; 0 1 S0 S1 0
END CASE; 0 0 S1 S0 1
END PROCESS; 0 1 S1 S1 0
 Mealy FSM in VHDL (3)

--------------------------------------------------------
output : PROCESS ( a, b, current_state )
---------------------------------------------------------
BEGIN
x_int <= '0';
CASE current_state IS
WHEN s0 => IF (a = '1') THEN
x_int <= ‘0';
END IF;
WHEN s1 => IF (a = '1') THEN 0/0 1/0 1/0
x_int <= '1'; S0 S1
END IF;
WHEN OTHERS => NULL;
END CASE; reset 0/1
END PROCESS output;
Challenge your mind
The answer is : Moore
Function : sequence detector for 01 or 10
Function : sequence detector for 01 or 10
Function : sequence detector for 01 or 10
Comparison of Mealy and Moore Machines
„ Mealy Machines tend to have less states
… Different outputs on arcs (n^2) rather than states (n)
„ Moore Machines are safer to use
… Outputs change at clock edge (always one cycle later)
… In Mealy machines, input change can cause output change as
soon as logic is done – a big problem when two machines are
interconnected – asynchronous feedback
„ Mealy Machines react faster to inputs
… React in same cycle – don't need to wait for clock
… In Moore machines, more logic may be necessary to decode
state into outputs – more gate delays after
Registered Mealy Machine (Really Moore)

Synchronous (or registered) Mealy Machine

… Registered state AND outputs
… Avoids ‘glitchy’ outputs
… Easy to implement in programmable logic
Mealy and Moore Examples
„ Recognize A,B = 0,1
… Mealy or Moore?
Mealy and Moore Examples
„ Recognize A,B = 1,0 then 0,1
„ Mealy or Moore?
FPGA adv point of view
Finite State Machine Editor Window
When to Use Finite State Machines
FSM Editor Design Objects Overview
End of Presentation