Paper ID: 46

Title: A 12b 1GS/s 61dB SNDR pipelined-SAR ADC with Inverter-based Residual Amplifier and Tunable Harmonic-injecting Cross-coupled-pair for
Distortion Cancellation Achieving 6.3fJ/conv-step.

Abstract: This paper presents a 1GS/s 12b 5.8mW single-channel three-stage Pipe-SAR ADC with an SNDR of 61dB and an SFDR of 75dB at
near-Nyquist input frequency implemented in 28nm CMOS. A novel inverter-based residue amplifier with tunable harmonic injection cross-coupled
pair is proposed to enhance linearity and gain of the residual amplifier with robustness against PVT variations. Measurements of multiple chip
samples have demonstrated effectiveness of the proposed techniques with a FOM of 6.3fj/c-v.
Subcommittee First Choice: Data Converters
Subcommittee Second Choice: Undecided

Submission Demographics

This paper is being submitted from University

Are you interested in participating in the Demonstration Session at ISSCC? Yes

Double-Blind Review Process

1. Have you read the Author Instructions and FAQ which outline the double-blind review submission requirements? Yes
I have read the Author Instructions and FAQ.
2. Is your manuscript fully anonymized to hide author and affiliation identities, including PDF metadata, logos on die photos, logos on
printed circuit board photos, etc.? Yes
my manuscript is fully anonymized to hide author and affiliation identities.
3. Did you cite all relevant prior work (including your own) in the third person? Yes
I have cited all relevant prior work in the third person.
4. Did you upload as Supporting Material any work of yours that is related to this submission and has been sent to another
Conference/Journal, but has not been published yet? Did you cite this work in anonymized format according to the Author Instructions?
Failure to adhere to this process may result in removal from accepted paper list even after acceptance. Yes
any work of ours which is related to this submission and has been sent to another Conference/Journal
but has not been published yet
has been uploaded as Supporting Material and has been cited in anonymized format.
5. Please check the following to show you have read and understood:
I understand that, if accepted, I will need to submit an updated version of my paper with author and affiliation data included and references
unblinded.
I understand that, if accepted, my paper will be edited by a Technical Editor who will ensure that my paper is compliant with the ISSCC editorial
guidelines.

Technology

CMOS

Originality

New design and/or architecture

Fastest published
Smallest published
Lowest power dissipation published
Best figure of merit published

Design Status

Chip testing complete, measured data supporting submitted paper

Submission Highlights

This ADC is the fastest single channel ADC with 60dB SNDR in 28nm process. This ADC achieves the best FoM compared to other designs with
GS/s sampling rate. With 5 tested samples, this ADC shows quite constant performance with SNDR and SFDR.

Introduction
1. Have you clearly highlighted what is the novelty in the reported circuit or architecture? Is the target application clearly described? Yes
2. Have you explained how your circuit or architecture advances the state of the art? If your work is part of a large system, have you
explained how your particular design advances the state-of-the-art as part of that system? Yes
3. Have you compared your results against representative examples from the recent literature? Please clarify and explain using a table, if
possible. Yes
4. Have you included performance in the form of recognized standard metrics (such as PVT sensitivity, area, noise, reliability metrics,
etc)? Yes
5. For power consumption and area measurements, have you clearly stated what blocks or functions are included (or omitted) in the
calculations? Yes
6. The ISSCC committee considers the quality of the referenced citations when judging your paper, does your reference list provide
adequate coverage of the related work (prior work by others and your own work) including papers from previous ISSCC where
applicable? Yes
7. Has your text been reviewed for correct use of grammar, punctuation, and spelling? Yes
9. ISSCC reviews circuit performance based on actual measured results (rather than simulation)-- Are the results clearly stated as
measured or simulated? Yes
10. What is the abstraction level of the primary innovation? Transistor/circuit topology level
Other. Please explain
11. Does your innovation cut across different subcommittees? No
Please list all subcommittees in which your innovation cuts across.

Data Converters

1. We ask that you provide the following measured data in the submitted paper (or in the supplemental material). If you chose not to
provide the data below, please explain why they are not appropriate to document your work.

● Nyquist ADC: SNR, SFDR, SNDR vs. Fin and Fclock; nominal (by design) input sampling capacitance (or resistance) driven by external

signal source; input voltage/current range; output spectrum.

● Oversampling ADC: SNR, SFDR, SNDR vs. Fin and Fclock; OSR; nominal (by design) input sampling capacitance (or input resistance)

driven by external signal source; input voltage/current range; output spectrum.

● Nyquist DAC: SNR (NSD preferred), SFDR (IMD preferred) vs. Fin and Fclock; output current/voltage range; output spectrum; load (e.g. off-

chip 50).
● Oversampling DAC: SNR, SFDR, SNDR vs. Fin and Fclock; OSR; output current/voltage range; output spectrum; load (e.g. 10k ||30pF).

The required data are included in the paper.

2. In what process technology was your device fabricated/measured (e.g. 65nm CMOS)?
28nm CMOS
3. What are the supply and reference voltages used in your device? Please list all voltages and the corresponding sub-blocks (e.g.
reference=0.2V/0.8V, analog=1V, digital=1.8V, analog switches=1.8V).
analog/digita=0.9V, reference=0.65V
4. What is the power dissipation breakdown of your device (e.g. total=12mW: references=2mW, analog=5mW, digital=3mW,
calibration=2mW)? Please be clear about on-chip or off-chip voltage references, and provide power in either case.
total=5.8mw, reference=0.8mw, RA(RA1&RA2=1.8mW, Clock_Gen=1.1mW, Comparator&LogicBootstrap=1.5mW.
5. If any calibration is applied, please identify whether it is on-chip or off-chip.
Two calibration are performed off-chip, comparator offset and DAC mismatch calibration.

Undecided

N/A
A 12b 1GS/s 61dB SNDR pipelined-SAR ADC with Inverter-based Residual Amplifier and Tunable

Harmonic-injecting Cross-coupled-pair for Distortion Cancellation Achieving 6.3fJ/conv-step.

[Placeholder for Author List]

[Placeholder for Affiliations]

With increasing need for high-speed high-resolution ADCs in wireless communication and other

applications, SAR-assisted pipeline ADCs have gained popularity for its superior performance and power

efficiency. The pipelined SAR ADC not only gain benefits of scaling friendly with technologies and high-power

efficiency from SAR architecture but also boosts conversion speed through pipeline operation. Recent works

have demonstrated three-stage pipeline SAR ADCs, capable of operating at 1GS/s with state-of-the-art FoMs

[1,2]. However, with the advanced nanometer processes, residual amplifiers (RA) between the stages in

pipelined SAR ADCs are still the bottlenecks limiting the overall ADC performance and power efficiency.

This paper presents a 1GS/s 61dB SNDR single-channel three-stage pipelined SAR ADC with 5.8mW,

shown in Fig. 1. To tackle challenges in RA design in nanometer CMOS, two new techniques are proposed:

1) an inverter-based RA is employed as a baseline for its power efficiency and scalability with low-voltage

nanometer CMOS; and 2) a harmonic cross-coupled pair (HXCP) is proposed to be added to the inverter-

based RA to boost its gain and linearity. Furthermore, to account for PVT variations, the proposed HXCP is

designed tunable, namely, a tunable harmonic injecting cross-coupled pair (THXCP) to achieve robustness

again PVT. The proposed ADC has three stages each with 4b, 4b and 6b respectively. The sizes of CDAC1-

CDAC3 are 700fF, 40fF and 60fF, which are limited by either KT/C noise or minimum realizable unit capacitor.

Both RA1 and RA2 have gain of 8 and the same reference voltage is shared across three stages, so one-bit

interstage redundancy is allocated between each stage.

As the first gain stage of a pipelined SAR ADC, the noise of RA1 typically sets the noise floor of the entire

ADC, which also means significant amount of power has to be burned in RA1 to reduce its noise contribution.

Gm-R based RAs have been proposed recently, which eliminate the reset phase of dynamic RA thus are
considered fastest RA to date and achieve excellent power efficiency [1]. To further reduce power

consumption, we propose an inverter-based RA especially suitable for low-voltage nanometer CMOS, as

shown in Fig. 2(a). Its overall structure consists of an input transconductor followed by a resistive load, similar

to that of the Gm-R RA, except that an inverter-based topology is implemented as the transconductor. The

inverter-based transconductor is capable of operating with low Vdd, and together with r bias current reuse

between the NMOS and PMOS pairs, it can achieve high power efficiency. However, the inferior linearity of

conventional inverter-based amplifier would prevent it from being used in high-resolution ADC. Meanwhile,

the severe channel length modulation associated with advanced nanometer process also presents challenge

in achieving sufficient gain for RA. Additionally, in the scope of discrete-time ADCs, the RAs also need to

have ultra-high bandwidth to achieve sufficient settling within a limited amplification period. All of these

constraints on noise, linearity, gain, and bandwidth impose great challenges in the design of inverter-based

RA for high-performance pipelined SAR ADC.

To improve the linearity and gain of RA, a harmonic injecting cross-coupled pair (HXCP) has been recently

presented in a Gm-R RA, which achieves >12b input referred linearity and a gain of 8 [2]. By providing a

negative resistance at the output using the HXCP, output resistance of RA is increased improving its overall

gain. The concept of HXCP can be applied in the inverter-based RA to take advantage of low-voltage CMOS.

In this design, an inverter-based RA with a Tunable HXCP (THXCP) constructed by an HXCP and additional

calibration pair is proposed, as shown in the top figure of Fig. 2(a).

The distortion cancellation capability of the proposed THXCP can be best explained and understood using

the compressive V-I and expansive I-V characteristics of the input transconductor and load, respectively.

Specifically, THXCP seeks to exploit the nonlinearity of the load transistors to post correct the distortions

generated from the input transconductor. As shown in Fig. 2(b), when the differential input voltage is large

enough, transistors M1,3 or M2,4 would be pushed into linear region and reduce their effective

transconductances, which correspond to a compressive V-I conversions of the input transconductor. In fact,
due to severe velocity saturation in nanometer processes, the V-I conversion express a compressive trend

even with a small differential input voltage [3].

As the overall transfer curve of the RA is a product of the V-I conversion of the transconductor and the I-

V conversion of the loading transistors, if we can devise a nonlinear load with expansive I-V conversion to

match the compressive nonlinearity generated from the transconductor, the overall linearity can be greatly

improved. Transistors M5-M8 in THXCP, due to the diode-like connection, are designed to provide such

expansive I-C conversion. M5-M8 can work in either subthreshold region or saturation region depending on

their gate-source voltage being larger or smaller than the transistor threshold voltage. In subthreshold, due

to the exponential relationship between voltage and current, the derivatives of V/I shows a compressive I-V

conversion [3]. On the other hand, when working in saturation, similar to the input transconductor, the THXCP

transistors present a compressive V-I and hence an expansive I-V conversion[3]. Thus, by choosing the sizes

and biasing of transistors properly, an expansive I-V can be obtained to match the compressive V-I

conversion of transconductor and improve the linearity of the overall RA. To make this technique robust to

PVT variations, an additional compressive I-V conversion is added to the THXCP load for calibration as

shown in Fig. 2 (a). Due to channel length modulation, the drain voltage of transistors working in saturation

is inversely proportional to drain currents. Seen from derivative of Vd=f(Id), a large drain current Id introduces

a compressive I-V conversion.

Overall, the transfer curve of RA is a combination of the V-I conversion of input transconductor, I-V

conversion of HXCP and I-V conversion of the tuning block. By tuning Vcn and Vcp of the push-pull structure

in the calibration pair, the relative strength of PMOS and NMOS is tuned, so the biasing points of the load

transistors are adjusted to ensure best fitting between the compressive and expansive curves. Fig. 2(c)

presents the simulated THD of the proposed inverter-based RA with THXCP across different process and

temperature corners. By tunning Vcn and Vcp of the calibration block, the inverter-based RA achieves a THD
of 61dB at its output in typical corner and a THD of 52dB in the worst case, sufficient for the targeted 10b-

ENOB given the gain of RA of 8 and maximum signal swing at the input of RA of 70mVpp.

Thanks to the relative high gain of RA1, the design challenges of RA2 is generally relieved. However, one

particular issue for RA2 is its gate parasitic capacitance (Cgg) associated with the input transistors of RA2.

Due to the small size of CDAC2, Cgg could load CDAC2 and reduce its full swing, as shown in Fig. 3(a). To

avoid using a separate high reference voltage of CDAC2, which would increase the overall power

consumption and design complexity in reference generations, the size of CDAC2 need to be set below certain

acceptable level [1], which in turn limits the size of the input transistors of RA2 and achievable

transconductance of RA2. To address this issue, reference [1] distributed the total gain into two stages. The

small sized RA2,1 has a gain of 2, while RA2,2 has gain of 4. Despite its effectiveness in reducing the loading

to CDAC2, one particular issue is associated with the smaller gain of RA1. As shown in Fig. 3(b), the gain of

this type of amplifier is the product of the effective transconductance and loading resistor. As the maximum

load resistance is limited by the bandwidth requirement, significant amount of power has to be burned in

RA2,2 to achieve a gain of 4. To relieve this issue, a cross-coupled pair (XCP) is added at the output of RA2,1

to boost its gain to be 4, while RA2,2 only needs to have a gain of 2. Also, from the perspective of power

efficiency, it makes more sense to burn more power to reduce noise contribution and increase gain of RA2,1

instead of for boosting the gain of the last gain stage RA2,2, shown in Fig. 3(c).

The ADC prototype was fabricated in 28nm CMOS. Foreground calibrations ARE performed off-chip to

calibrate the offset of comparators and RAs and the gain of RAs. A One-time DAC calibration is also

performed to correct the DAC mismatches by adjusting bit weight before measurement.

Fig. 4 shows the measured frequency spectrums at low frequency and near-Nyquist input, respectively.

The SNDR and SFDR are measured to be 61dB and 76dB with near-Nyquist input at 320MHz. The measured

INL and DNL are +2.11/−2.97LSB and +0.69/−0.58LSB. The measured SNDR and SFDR with input

frequency sweep and sampling frequency sweep across 5 chip samples are summarized in Fig. 6. All the
tested samples are capable of maintaining >60dB SNDR and >70dB SFDR up to 320MHz, which proves the

robustness of proposed HXCP technique. Overall, 5.8mW is drawn from the ADC from 0.9V supply at 1GS/s,

achieving a 6.3fJ/conv.-step FoMw and 170.5dB FoMs.

A comparison of this work to ADC with similar sampling rate and resolution is summarized in Fig. 6 [1],

[2], [4-6]. The proposed techniques enable a very lower-power 1GS/s 12-bit ADC with comparable SNDR

and SFDR with the other state of the art but with a significantly FoM.

[Placeholder for Acknowledgements]

References
(1) W. Jiang, et al., "3.2 A 7.6 mW 1GS/s 60dB SNDR Single-Channel SAR-Assisted Pipelined
ADC with Temperature-Compensated Dynamic Gm-R-Based Amplifier," ISSCC, pp. 60-62, Feb.
2019.
(2)
L. Fang, et al., “A 1GS/s 82dB Peak-SFDR 12b Single-Channel Pipe-SAR ADC with Harmonic-
Injecting Cross-Coupled-Pair and Fast N-replica Bootstrap Switch Achieving 7.5 fj/conv-step,”
IEEE CICC, pp. 1-2 April 2021.
(3) P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer, Analysis and Design of Analog
Integrated Circuits, 4th ed. New York: Wiley, 2001.
(4)
B. Hershberg, et al., "A 1MS/s to 1GS/s Ringamp-Based Pipelined ADC with Fully Dynamic
Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16nm," IEEE
Symp. VLSI Circuits, pp. 1-2, June 2020.
(5) L. Kull, et al., "28.5 A 10b 1.5GS/s pipelined-SAR ADC with background second-stage
common-mode regulation and offset calibration in 14nm CMOS FinFET," ISSCC, pp. 474-475,
Feb. 2017.
 THXCP
VDD
XCP
- +
[Inverter-based]
CDAC1 CDAC2 RA2 CDAC3
SIG_IN [600fF] [40fF] [60fF]
RA1 RA2,1 RA2,1
4b Binary 4b Binary 6b Binary
Bootstrap Const. CM Const. CM Monotonic
CKS CKRA2
[250ps] CKRA1
[200ps] 4X [200ps]
4X 6X
Global
Clk. Gen. buf. Local buf. Local buf.
Cmp. Cmp. Cmp.
Logic Clk. Gen. Logic Clk. Gen. Logic
CK1 CK2 CK3
CLK_IN

Gain Calibration, Offset Calibration (comparator & RAs) and Outputs Synchronization

CKS
CK1 13 12 11 10 13 12 11 10 13 12 11 10

CKRA1

CK2 9 8 7 6 9 8 7 6

CKRA2

CK3 5 4 3 2 1 0 5

Fig. 1 Circuit block and timing diagram of the three-stage PipeSAR with proposed tunable harmonic
injecting cross-coupled pair (THXCP) and two stage RA2 with cross-coupled pair
 VDD VDD VDD VDD VDD VDD
M4 M3
Vb M7 M8 M11 M12
RL RL
Vinp Vinn Vcp
Voutp Voutn Vcn
Voutn Voutp Voutp Voutn
VDD M5 M6 M9 M10
M1 M14 M2

Additional
CKRA M13 HXCP
calibration pair

(a) Current-reused Inverter-based RA Tunable HXCP

Iop-Ion Voutp-Voutn TT@27°C

Voutp-Voutn
SS@80°C
FF@0°C

THD@RA Output (dB)

B
X =
A
Vinp-Vinn Iop-Ion Vinp-Vinn

Compressive Gm Expansive Load(A): More Linear

HXCP: M5-M8 transfer curve
Core Inverter Cal. Pair
M1-M4 Compressive Load(B):
Cal. Pair: M9-M12 ensures better
(b) Tunable by Vcp, Vcn Fitting (c) Diff. Input (mVpp)
Fig. 2 (a)Proposed inverter-based residual amplifier with tunable harmonic injecting cross-couple
pair (THXCP) (b) Explanation of operation (c) simulated THD versus input amplitude
 𝐶2 VDD VDD
RA1 𝐹𝑢𝑙𝑙 𝑠𝑤𝑖𝑛𝑔 = 𝑅𝐸𝐹 ∙
𝐶2 + 𝐶𝑔𝑔 Vo1,p(Vo1.n)
Av,1=4 Av,2=2
Cgg CDAC3
Vo1,p Vo1,n
RA2,1 RA2,2
REF • Cgg of RA2,1 load CDAC2
GND • Reduce CDAC2 full swing
CDAC2 (C2) • Need to minimize Cgg to avoid scaling CKRA
(a) down REF XCP

VDD VDD 2
𝑉𝑁,𝑅𝐴 2,2
2 2
without XCP 𝑉𝑁,𝑅𝐴 = 𝑉𝑁,𝑅𝐴2,1 +
2
𝐴2𝑉,1
𝐴𝑉 = 𝐺𝑚 𝑅𝐿
RL
• Gm limited by Cgg Assume RA2,1, RA2,2 have
VOUT same contribution
• RL limited by Bandwidth
2
𝑉𝑁,𝑅𝐴 2,2
2
with XCP 𝑉𝑁,𝑅𝐴 =
VIN −1
2,1
𝐴2𝑉,1
𝐴𝑉 = 𝐺𝑚 (𝑅𝐿 // )
𝑔𝑚 Hence, a higher Av,1
ID ID • With the same Gm, RL
->A higher Av can be achieved -> larger VN, RA2,2

(b) RA2,1 (c) -> Less power consumption

XCP
Fig. 3 (a)Proposed two stage RA2 with cross couple pair to enhance power and noise efficiency (b)
Noise contribution budgeting (c) Explanation of operation
 DNL=+0.69/-0.58LSB
INL=+2.11/-2.97LSB
DNL(LSB)

INL(LSB)
Code Code

Fs=1GS/s
Fs=1GS/s
Fin=123.67MHz
Fin=319.95MHz

Power Spectrum (dBFS)

Power Spectrum (dBFS)

SNDR=60.8dB
SNDR=61dB
SFDR=74dB
SFDR=76dB

HD2
HD3
HD2

Normalized Frequency Normalized Frequency

Fig. 4 Measured INL/DNL and output FFT spectrum (decimated by 256, 8192 FFT points)
 SFDR

SNDR
Sample1
dB

Sample2
Sample3
Sample4
Sample5

Fin(MHz)

SFDR

SNDR Sample1
dB

Sample2
Sample3
Sample4
Sample5

FS(MS/s)

Fig. 5 Measured input frequency and sampling frequency sweep

 [5] VLSI’20 [4] ISSCC ‘17 [2] CICC ‘21 [1] ISSCC ‘19
This work
B. Hershberg L. Kull L. Fang W. Jiang
Process 28nm 16nm 14nm 28nm 28nm
Pipelined Pipelined Pipelined Pipelined
Architecture Pipeline
SAR SAR SAR SAR
Resolution (bits) 12 11 10 12 12

Sample Rate (MS/s) 1000 1000 1500 1000 1000

Supply Voltage (V) 0.9 0.9 0.95 0.9 1

Input Range (Vpp) 1.1 1.6 0.65 1.1 1.2

Input Buffer No - No No Yes

SFDR @HF. (dB) 76a 75.9 58.39 73.4 74.56

SNDR @HF. (dB) 61 59.5 50.1 60.7 60.02

Power (mW) 5.8 10.9 6.92 6.8 7.6

FoMWalden@Nyq.
6.3 14.1 17.7 7.76 9.28
(fj/conv-step)
FoMSchreier@Nyq.
170.4 166.1 160.5 169 168.2
(dB)
Active Area (mm2) 0.0062 0.095 0.0016 0.007 0.0091
a measured with input frequency @ 320MHz

Fig. 6 Comparison table with other state of the art designs

 1mm

T/H

CDAC1
1mm

RA1

CDAC2

RA2

CDAC3

Fig. 7 Chip micrograph and layout in 28nm CMOS technology

 Keithley 2230

Power Supply
R&S
SMA-100B Keysight 16861A
Signal INP
BPF Balun
Gen. INN Dout
R&S Logic Analyzer
DUT <13:0>
SMA-100B

RA Bias
<13:0>
Signal

VCAL
BPF CKs
10MHz Ref. Gen.

• Calibration Voltages and RA

biasing voltage are provided
off-chip

Power consumption:
20% 27%
5.8 mW (0.9V VDD)
RA1 and RA2 Reference
16%
36% Comparator, Logic, Bootstrap
Clock Gen

Fig. S1 Test setup and power breakdown.