Paper ID: 16

2
Title: A 10GS/s 8b 25fJ/c-s 2850um Two-Step Time-domain ADC Using Delay-Tracking Pipelined-SAR TDC with 500fs Time Step in 14nm CMOS
Technology

Abstract: This work introduces a two-step time-domain ADC that uses a first-stage Flash and second-stage SAR TDC. A delay-tracking pipelining
technique is proposed to enhance the speed of the SAR TDC and reduce circuit complexity. The 10GS/s 8bit ADC in 14nm CMOS implemented 2-
2
way time interleaving. With an active area of only 2850um , the ADC achieves 40.8dB and 37.2dB SNDR for single and dual channel operation at
Nyquist input frequency, leading to an FOM of 16.6 and 24.8fJ/conv-step, respectively.
Subcommittee First Choice: Data Converters
Subcommittee Second Choice: Data Converters

Submission Demographics

This paper is being submitted from University

Are you interested in participating in the Demonstration Session at ISSCC? No

Double-Blind Review Process

1. Have you read the Author Instructions and FAQ which outline the double-blind review submission requirements? Yes
I have read the Author Instructions and FAQ.
2. Is your manuscript fully anonymized to hide author and affiliation identities, including PDF metadata, logos on die photos, logos on
printed circuit board photos, etc.? Yes
my manuscript is fully anonymized to hide author and affiliation identities.
3. Did you cite all relevant prior work (including your own) in the third person? Yes
I have cited all relevant prior work in the third person.
4. Did you upload as Supporting Material any work of yours that is related to this submission and has been sent to another
Conference/Journal, but has not been published yet? Did you cite this work in anonymized format according to the Author Instructions?
Failure to adhere to this process may result in removal from accepted paper list even after acceptance. Yes
any work of ours which is related to this submission and has been sent to another Conference/Journal
but has not been published yet
has been uploaded as Supporting Material and has been cited in anonymized format.
5. Please check the following to show you have read and understood:
I understand that, if accepted, I will need to submit an updated version of my paper with author and affiliation data included and references
unblinded.
I understand that, if accepted, my paper will be edited by a Technical Editor who will ensure that my paper is compliant with the ISSCC editorial
guidelines.

Technology

CMOS

Originality

New design and/or architecture

Smallest published
Best figure of merit published

Design Status

Chip testing complete, measured data supporting submitted paper

Submission Highlights

1. This work proposes a new delay-tracking pipelined-SAR TDC architecture aiming for high speed and low cost. 2. The proposed selective delay
tuning cell achieves a sub-picosecond TDC resolution. 3. In terms of single-channel sampling rate, this ADC achieves 2X faster than the published
ADCs with >= 8bit resolution. 4. Best FOM (24.8fJ/conv) among published ADCs with >= 10GS/s. 5. Smallest reported area among published ADCs
with >= 10GS/s and >=8bit.

Introduction
1. Have you clearly highlighted what is the novelty in the reported circuit or architecture? Is the target application clearly described? Yes
2. Have you explained how your circuit or architecture advances the state of the art? If your work is part of a large system, have you
explained how your particular design advances the state-of-the-art as part of that system? Yes
3. Have you compared your results against representative examples from the recent literature? Please clarify and explain using a table, if
possible. Yes
4. Have you included performance in the form of recognized standard metrics (such as PVT sensitivity, area, noise, reliability metrics,
etc)? Yes
5. For power consumption and area measurements, have you clearly stated what blocks or functions are included (or omitted) in the
calculations? Yes
6. The ISSCC committee considers the quality of the referenced citations when judging your paper, does your reference list provide
adequate coverage of the related work (prior work by others and your own work) including papers from previous ISSCC where
applicable? Yes
7. Has your text been reviewed for correct use of grammar, punctuation, and spelling? Yes
9. ISSCC reviews circuit performance based on actual measured results (rather than simulation)-- Are the results clearly stated as
measured or simulated? Yes
10. What is the abstraction level of the primary innovation? Transistor/circuit topology level
Other. Please explain
11. Does your innovation cut across different subcommittees? No
Please list all subcommittees in which your innovation cuts across.

Data Converters

1. We ask that you provide the following measured data in the submitted paper (or in the supplemental material). If you chose not to
provide the data below, please explain why they are not appropriate to document your work.

● Nyquist ADC: SNR, SFDR, SNDR vs. Fin and Fclock; nominal (by design) input sampling capacitance (or resistance) driven by external

signal source; input voltage/current range; output spectrum.

● Oversampling ADC: SNR, SFDR, SNDR vs. Fin and Fclock; OSR; nominal (by design) input sampling capacitance (or input resistance)

driven by external signal source; input voltage/current range; output spectrum.

● Nyquist DAC: SNR (NSD preferred), SFDR (IMD preferred) vs. Fin and Fclock; output current/voltage range; output spectrum; load (e.g. off-

chip 50).
● Oversampling DAC: SNR, SFDR, SNDR vs. Fin and Fclock; OSR; output current/voltage range; output spectrum; load (e.g. 10k ||30pF).

SNDR against Fclock cannot be provided since clock generation is especially optimized for 10GHz
2. In what process technology was your device fabricated/measured (e.g. 65nm CMOS)?
14nm CMOS
3. What are the supply and reference voltages used in your device? Please list all voltages and the corresponding sub-blocks (e.g.
reference=0.2V/0.8V, analog=1V, digital=1.8V, analog switches=1.8V).
analog = 0.8V, IO = 1.8V
4. What is the power dissipation breakdown of your device (e.g. total=12mW: references=2mW, analog=5mW, digital=3mW,
calibration=2mW)? Please be clear about on-chip or off-chip voltage references, and provide power in either case.
Off-chip voltage reference. Total=14.8mW, (S/H+VTC)=1.2mW, First stage TDC + residue time generation= 4.7mW, second stage TDC = 6.1mW.
Local CLK buffer=2.7mW.
5. If any calibration is applied, please identify whether it is on-chip or off-chip.
off-chip
A 10GS/s 8b 25fJ/c-s 2850um2 Two-Step Time-domain ADC Using Delay-Tracking

Pipelined-SAR TDC with 500fs Time Step in 14nm CMOS Technology

[Placeholder for Author List]

[Placeholder for Affiliations]

High-speed (>GS/s) medium-resolution ADCs are in high demand for wideband communication

ICs; meanwhile, the increasing cost in advanced technology nodes favors area-efficient ADC

architectures. Traditional voltage-domain time-interleaved (TI) SAR ADC [1-2] is a popular choice

for its superior power efficiency. However, its single-channel sample rate is generally limited to

<1GS/s, necessitating a large number of TI channels in high sample rate scenarios. It inevitably

increases implementation overhead, including capacitive loading to the input driver and total area

consumption. Recently, time-domain ADCs [3-5] have shown promising sampling speed, but are

mostly based on thermometer coded time-to-digital converters (TDC). Unfortunately, the circuit

complexity for such Flash TDC grows exponentially with the target bit resolution. Existing SAR

TDCs [6] demonstrate a lower complexity but are generally limited in sample rate (MS/s). In this

work, we propose a two-step time-domain ADC that uses a first-stage Flash TDC with the residue

time quantized by the second-stage SAR TDC, targeting >GS/s regime. To further improve the

throughput of SAR TDC conversion, we propose a delay-tracking pipelining technique that allows

the SAR TDC to quantize two residue time samples, simultaneously. At the circuit level, we use

a selective delay tuning (SDT) cell to provide the time reference required for SAR conversion

without using an excessive number of delay stages. A proof-of-concept ADC prototype in 14nm

CMOS technology with 2X time interleaving achieves 10GS/s with 37.2dB SNDR at Nyquist

frequency. It measures an energy efficiency of 24.8fJ/conv-step and occupies an active area of

2850um2, which are the highest reported energy efficiency and smallest area consumption

among the state-of-the-art ADCs with >10GS/s [7].

One key design challenge for a high-speed time-domain ADC is a low-complexity TDC with fine
LSB resolution. Figure 1 shows conventional TDCs with fine time resolution and the proposed

SAR TDC using SDT cells. A time-domain ADC typically encodes the input voltage information

into a time difference between two pulses (e.g., PP and PN in Figure 1), and relies on TDC for

digitization. A traditional Vernier delay line-based TDC uses the delay difference between two

delay chains (τ2-τ1 in Figure 1) for time quantization. It requires 2N+1 delay cells and 2N time

comparators for an N-bit conversion, imposing significant power and area overhead. Prior works

on SAR TDCs [6] effectively reduce the number of time comparators; however, the time

quantization step is still derived by selecting between two different delay chains using a

multiplexer (MUX). Therefore, it still requires a large number of delay cells in addition to extra

MUX delay. To alleviate this issue, we propose a SAR TDC architecture that dynamically

changes the delay based on the time comparison result during bit trials, which is referred to as

selective delay tuning. Whenever a bit trial reaches a decision, the SDT cell will insert an extra

delay to either the positive or negative side of the TDC chain. The resulting delay difference will

be used as the reference time for the successive approximation (SA) algorithm. Therefore, the

proposed N-bit SAR TDC requires only 4·(N-1) delay cells and N time comparators without MUX,

leading to lower noise and area/power consumption.

Figure 2 shows the proposed delay-tracking pipelined SAR TDC and its timing diagram for the

binary SA search. The SAR TDC is composed of five 1-bit stages, with each stage using a time

comparator to perform a single bit trial, and an SDT cell to add or subtract a proper reference

time. The operation mode of the time comparator is controlled by CLK. When CLK is LOW, the

outputs will be reset to VDD. When CLK is HIGH, the first rising edge of the two input pulses will

trigger the comparator. Without pipelining, the same CLK signal is connected to all comparators,

and it must remain HIGH until the input pulses completely propagate through the five conversion

stages, thereby limiting the TDC throughput. Alternatively, applying conventional TDC pipelining

technique requires adding additional delay to the signal path, to match the delay of each stage
with the CLK period, which inevitably degrades the signal SNR or incurs significant power/area

overhead to lower the added noise. To resolve this issue, we propose to insert delay (τstage)

between the CLK signals for the 5-stage comparators, i.e., CLK<0:4> in Figure 2, which does

not degrade the signal SNR. The CLK delay should track with the propagation delay of the 1-bit

stage (including the comparator and SDT delay), such that the CLK signal can return to LOW as

soon as the input pulse propagates to the next 1-bit stage and the decision result is cached, thus

increasing the throughput. As a result, two input pulses can be simultaneously processed by the

SAR TDC. We refer to this implementation as delay-tracking pipelined-SAR TDC, which helps

double the throughput to reach 5GS/s.

Based on the delay-tracking pipelined SAR TDC architecture, we construct a two-step converter

that performs the first 3 MSB conversions using a Flash TDC, and generates residue time signals

(RP and RN) followed by the 5 LSB conversions via SAR TDC, as shown in Figure 3. The Flash

TDC and residue time generation help reduce the maximum delay required for SDT cells in SAR

TDC, and hence allows us to optimize the jitter performance of the SDT cells. In order to linearly

encode the sampled voltage information into the rising edge difference of two pseudo-differential

pulses (P and N in Figure 3), the sampled voltage needs to be ramped up and compared to a

certain voltage threshold in the voltage-to-time conversion (VTC) block. Traditionally, the ramps

are generated on both sampling capacitors via two separate charge pumps [3]. This ramp

generation process is vulnerable to distortion, memory effect, and signal-dependent charge

kickbacks. To improve the fidelity of VTC, we propose to create a common-mode ramp by

charging a capacitor (Ccm) at the center node (Vc) of the sampling capacitors. After the VTC is

completed, the Ccm will be reset to reduce memory effect and signal-dependent charge kickbacks

to the input. Lastly, since our ramp generation only requires a single charge pump, it avoids the

ramp slope mismatch issue as seen in the conventional case.

The schematic of the SDT cell is illustrated in Figure 3. We skew the relative strength between
the pull-up and pull-down paths to create different falling-edge slopes at the intermediate node

(MID). As a result, the transition time instant of the rising edge at SDT cell output (OUT) is

changed accordingly. This not only enables a fine time step (500fs in this design), but also yields

less delay variation compared to Vernier delay cells due to much fewer transition edges.

According to SPICE simulations, the standard deviation of the LSB time step variation is six times

smaller than the Vernier TDC’s counterpart, given the same transistor sizes in the unit delay cell.

Figure 4 shows the residue time generation and the first stage Flash TDC. The input pulses from

the VTC block are first delayed by three coarse delay cells (each with a nominal delay of 16ps).

Those delayed pulses are cross-compared with the input pulses via time comparators, which

effectively create eight quantization levels, i.e., 3-bit Flash TDC. Afterwards, the residue time is

generated by selecting the closest two rising edges between the input pulses and the coarse

delayed pulses. Note that, the residue time range is re-adjusted from [0,16ps] to [-8ps, 8ps] by

an SDT cell, to properly interface with the following-stage pseudo differential SAR TDC operation.

The ADC is fabricated in 14nm CMOS with an active area of 2850um2, as shown in Figure 7. A

foreground calibration is applied to tune the gain error between the first and second TDC stage.

Figure 5 shows the measured SFDR and SNDR vs. input frequencies and the spectrum of the

decimated ADC output for both single-channel and two-channel cases. The ADC shows <3dB

SNDR variation across 0.1 to 5GHz input frequency. The single ADC channel operating at 5GS/s

achieved a 40.78dB SNDR and a 53.65dB SFDR at Nyquist, leading to a 16.6fJ/conv-step energy

efficiency. The two channel ADC operating at 10GS/s achieved a 37.24dB SNDR and a 50.67dB

SFDR at Nyquist, leading to a 24.8fJ/conv-step energy efficiency. The performance comparison

table is shown in Figure 6. Compared with other state-of-the-art high-speed ADCs, this ADC

achieves higher energy efficiency with the smallest active area.

[Placeholder for Acknowledgements]

References
(1) M. Guo et al. "A 29mW 5GS/s Time-interleaved SAR ADC achieving 48.5dB SNDR With Fully-
Digital Timing-Skew Calibration Based on Digital-Mixing," IEEE Symp. VLSI Circuits, pp. C76-C77,
June 2019.
(2)
J. Nam et al. "A 12-Bit 1.6, 3.2, and 6.4 GS/s 4-b/Cycle Time-Interleaved SAR ADC With Dual
Reference Shifting and Interpolation," IEEE JSSC, vol. 53, no. 6, pp. 1765-1779, June 2018.
(3)
M. Zhang et al. "16.2 A 4× Interleaved 10GS/s 8b Time-Domain ADC with 16× Interpolation-Based
Inter-Stage Gain Achieving >37.5dB SNDR at 18GHz Input," ISSCC, pp. 252-254, Feb. 2020.
(4)
M. Hassanpourghadi and M. S.-W. Chen, “A 2-way 7.3-bit 10 GS/s Time-based Folding ADC with
Passive Pulse-Shrinking Cells,” IEEE CICC, pp. 1-2, Apr. 2019.
(5)
S. Zhu et al. "A 2-GS/s 8-bit Non-Interleaved Time-Domain Flash ADC Based on Remainder
Number System in 65-nm CMOS," IEEE JSSC, vol. 53, no. 4, pp. 1172-1183, April 2018.
(6) H. Chung et al. "A 10-Bit 80-MS/s Decision-Select Successive Approximation TDC in 65-nm
CMOS," IEEE JSSC, vol. 47, no. 5, pp. 1232-1241, May 2012.
(7) B. Murmann, "ADC Performance Survey 1997-2021," [Online]. Available:
http://web.stanford.edu/~murmann/adcsurvey.html.
Fig. 1. Conceptual diagram of the proposed SAR TDC using selective delay tuning (SDT) cell
versus existing TDC architectures.
Fig. 2. Proposed delay-tracking pipelined-SAR TDC and timing diagram.
Fig. 3. Block diagram of the two-step time-domain ADC and key building blocks.
Fig. 4. Implementation of the first-stage Flash TDC and the residue time generation.
 SFDR & SNDR (dB)

1 channel 2X TI
Fs=5GS/s Fs=10GS/s

Input Frequency (GHz) Input Frequency (GHz)

0 1 channel Fin=2.4979GHz 0 2X TI Fin=4.9859GHz

Fs=5GS/s SNDR=40.78dB Fs=10GS/s SNDR=37.24dB
-10 -10
SFDR=53.65dB SFDR=50.69dB
Magnitude (dB)

-20 -20
-30 -30
HD2 HD4
-40 HD4 HD7 -40 HD7
HD3
HD3 Fs/2-fin
-50 -50
-60 -60
-70 -70

0 0.5 1 1.5 2 2.5 3 0 1 2 3 4 5 6

Frequency (MHz) Frequency (MHz)

Fig. 5. Measured SNDR/SFDR versus input frequencies and the spectrum of the decimated (by
729X) ADC output for single channel and 2X time-interleaved (TI) channels.
 CICC 19
ISSCC 20 JSSC 19 JSSC 18 ISSCC 20 VLSI 19
This work M.Hassanpo
M. Zhang[3] D. Oh S. Zhu[5] Z. Zheng M.Guo[1]
urghadi[4]
Time-domian ADCs Voltage-domian ADCs
Architecture Delay-tracking Interpolation Interpolation Dynamic
Flash TDC Flash TDC TI-SAR
pipelined-SAR TDC TDC TDC Pipeline
Technology 14nm CMOS 65nm CMOS 65nm CMOS 65nm CMOS 65nm CMOS 28nm CMOS 28nm CMOS
Supply (V) 0.8 1 1 1 1 0.9 1
Resolution (bits) 8 8 7.3 6 8 6 10
# of TI channels 2 1 4 2 1 1 1 16
Sample rate (GS/s) 10 5 10 10 2.5 2 3.3 5
Power (mW) 14.8 7.4 50.8 29.7 7.5 21 5.5 29
SFDR@Nyq (dB) 50.69 53.12 52.8 40.7 45.07 48.36 45.5 59.6
SNDR@Nyq (dB) 37.2 40.8 40.1 32.5 33.84 40.68 34.2 48.5
FOM Walden
24.8 16.6 61.5 86.0 74.7 119 40.0 26.7
@Nyq(fJ/conv-step)
Active area (um 2) 2850 1425 95000 15000 120000 80000 16600 103000

ISSCC 1997-2021 VLSI 1997-2020

1,000 Envelope This work
FOMW,hf [fJ/conv-step]

100

10
3.E+09 fsnyq [Hz] 3.E+10

Fig. 6. Performance summary and comparison with the state-of-the-art high-speed ADCs
(>3GS/s).
Fig. 7. Die photo and layout of single ADC channel.
 Signal generator PCB Digilent Digital
Balun Discovery
Agilent E8257C
BPF CLKP CLKN Pattern

translator
INP generator

Voltage
Digital
Signal generator

Balun
ADC

IO
Agilent E8665B Logic
BPF INN DUT Analyzer

VCMCLK
VCMIN
VDD

VSS
DC power supply PC
Agilent E3631A LDO board

S1: Measurement setup.

 1

DNL (LSB) 0.5

-0.5

-1
SH & VTC
0 32 64 96 128 1.2 mW
8%
1
INL (LSB)

0.5

-0.5

-1
0 32 64 96 128
SFDR & SNDR (dB)

SFDR & SNDR (dB)

1 channel 2X TI
Fs=5GS/s Fs=10GS/s
Fin=100.703M Fin=100.703M

Temperature (℃ ) Temperature (℃ )
SFDR & SNDR (dB)
SFDR & SNDR (dB)

1 channel 2X TI
Fs=5GS/s Fs=10GS/s
Fin=2.49783G Fin=2.49783G

Supply Voltage (mV) Supply Voltage (mV)

S2: Measured DNL/INL (7-bit level), ADC power breakdown, and measured SNDR/SFDR over
different temperatures and supply voltages.
 10

1
Area FOM

0.1

0.01
>16nm
<=16nm
This work
0.001
1G 10G 100G
Fsnyq [Hz]
𝑨𝒓𝒆𝒂
𝑨𝒓𝒆𝒂 𝑭𝑶𝑴 = ( 𝑎𝑟𝑒𝑎 𝑢𝑛𝑖𝑡 = 𝑛𝑚2 , 𝐹𝑠 𝑈𝑛𝑖𝑡 = 𝐻𝑧)
𝑭𝒔 × 𝟐 𝑬𝑵𝑶𝑩

S3: ADC area efficiency comparison with the state-of-the-art high-speed ADCs in advanced
technology nodes.