Tessent Glossary: Software Version 2016.3 September 2016

Tessent® Glossary
Software Version 2016.3

September 2016
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Glossary
Application Specific Integrated Circuit (ASIC)

A circuit designed for a specific application, as opposed to a general purpose circuit, such as a
microprocessor. Using ASICs as components in electronic devices can improve performance,
reduce power consumption, increase safety, and reduce costs.
At-Speed Test
Refers to a variety of both memory and logic test techniques to detect timing-related defects that
are only apparent when the device is run at system speeds. See also Path Delay, Timing-Aware
ATPG, and Transition Faults.
Automated Test Equipment (ATE)

Equipment that automatically tests and analyzes functional parameters to evaluate performance
of the tested electronic devices.
Automatic Test Pattern Generator (ATPG)

A process by which the test patterns required to produce a high-fault coverage for a design are
generated by a program.
BIRA Register
A register containing the result of the Built-In Repair Analysis (BIRA) process. Its content is
transferred to the BISR register when self-repair is used. See Built-In-Repair Analysis (BIRA).
BISR Chain
A Built-In Self Repair (BISR) chain is formed by the concatenation of several BISR registers.
Currently, a single BISR chain is supported on a chip. See Built-In Self-Repair (BISR).
BISR Controller
A BISR controller, also known as a fuse box controller, performs several functions related to
self-repair. It is used to decompress the information before loading a BISR chain. The BISR
controller is also capable of reading BIRA registers and compressing the repair information
before writing it to the fuse box. The controller supports several diagnosis and verification
functions.
BISR Interface
A BISR interface is the interface giving access to the spare resources of the memory. Several
memories provide a direct parallel interface to spare resources so that the BISR register can be
connected directly. Other memories provide a serial BISR interface so that the repair information
needs to be shifted in. See Built-In Self-Repair (BISR).
Tessent® Glossary, v2016.3 3

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BISR Register
A register holding repair information for a memory. The BISR register contains the redundant
column(s) and/or row(s) allocation information that is needed to repair a defective memory
location. The redundant column(s) and/or row(s) allocation information is usually calculated by
the BIRA circuitry based on the memory addresses where failures occurred. Typically, the BISR
register is connected to the memory through a parallel BISR interface. However, some memories
contain a BISR register which is accessed through a serial BISR interface. A BISR register
located inside a memory is referred to as an internal BISR register and a BISR register located
outside a memory is referred to as an external BISR register. See Built-In Self-Repair (BISR).
Blackbox
An instance, module, or library model that does not exist. Instead a definition with only the
inputs and outputs is defined without any internal connections or logic.
Block Module
Also known as functional block. Any module within the design hierarchy instantiated one or
more times that will be laid out separately is referred to as a block module. Block modules are
defined divisions of a chip based on functionality and can be worked on independently of other
functional blocks. LV Flow tools can be used to insert various Embedded Test features in a block
module and create a database (LVDB) that allows an independent verification of the block
module and makes the block module reusable on the same or a different chip. The Embedded
Test insertion can be performed using two variations of the LV Flow: block variation and ELT
variation.
See Burst-Ready Block Module, ELT Core Module, LVDB, and Wrapper Test Access Port
(WTAP).
Bottom-Up Methodology
In the context of the Mentor Graphics hierarchical test insertion flow, a methodology where the
rules checking and the extraction of design information from the circuit description at the register
transfer (RT) or gate level is performed on individual ELT Core Modules from the lower level of
design hierarchy to the chip top level.
Boundary Scan
The practice of inserting a ring of control/observe cells around a chip's functional pins and
control port for the purpose of board level test, standardized by IEEE 1149.1.
Boundary Scan Design Language (BSDL)

The IEEE 1149.1 standard description language for components with boundary scan, used for
board-level testing.
Broadside
At-speed test method that uses two functional clock pulses; the first to launch a transition, and
the second to capture the results. See also At-Speed Test.
Built-In-Repair Analysis (BIRA)

On-chip circuitry used to determine if a memory is repairable based on the analysis of errors
detected by a memory BIST controller. The repair analysis will vary based on the specified
4 Tessent® Glossary, v2016.3

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redundancy scheme, i.e., spare columns only (or IO), spare rows only, both spare rows and spare
columns. The repair information is stored in a BIRA register for further processing by a tester or
BISR controller.
Built-In Self-Repair (BISR)

On-chip circuitry used to apply repair information to repairable memories. The repair
information is stored in BISR registers which can be loaded from BIRA registers (soft repair) or
from a fuse box (hard repair). Since the repair information contained in the fuse box is
compressed, a BISR controller is used to decompress the information before loading the BISR
chain composed of BISR registers of repairable memories. The BISR controller is also capable
of reading BIRA registers and compressing the repair information before writing it to the fuse
box.
• Hard Repair — Repair strategy making use of a fuse box to permanently store memory
repair information. The repair information is read from the fuse box and applied to the
memories each time the chip is powered up.
• Soft Repair — Repair strategy where memories are re-tested each time the chip is
powered up. The repair information is temporarily stored in the BISR registers until the
chip is powered down.
• IncrementalRepair — Also known as cumulativerepair. An incremental repair takes
into consideration repair information of previous test and repair cycles. For example,
repair information generated during a test performed at a first supply voltage can be used
as a starting point for a second test and repair cycle performed at a second supply
voltage. Another example would be to perform repair on a packaged chip using wafer
probe repair information. A combination of hard and soft repair strategies can be used in
an incremental repair scenario. However, Mentor Graphics’ technology currently does
not support incremental repair.
BurstMode
The BurstMode logic architecture is a clocking methodology used to perform an at-speed test of
a scannable circuit that is exclusive to Mentor Graphics. Scan chains are loaded using shift clock
cycles during the shift phase and bursts of functional clock cycles (2 to 5) are applied during a
burst phase. The flip-flops are organized into segments called rotation segments and perform a
combination of shift, hold, and capture operations. All scan flops perform the capture operation
in a single cycle at the end of the BurstMode. Clock bursts occur synchronously or
asynchronously with other domains based on the system timing.
Burst-Ready Block Module
A burst-ready block is a block where scan chains have been inserted using LV Flow (LV2004 or
newer version) and is compatible with the BurstMode logic test architecture.
Bypass Circuitry
Additional logic circuitry generated by Tessent TestKompress®® to bypass the decompressor
and compressor in the EDT logic. The bypass circuitry allows you to generate uncompressed test
patterns using traditional ATPG methods.

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Bypass Mode
Tessent TestKompress mode of operation when the bypass circuitry is used to bypass the
decompressor and compressor and generate uncompressed test patterns. See Bypass Circuitry.
Capture-By-Domain
Capture-by-domain is a patented Mentor Graphics technique used to test paths between
asynchronous clock domains. According to this technique, the capture operation of flip-flops that
are source or destination of cross-domain paths is selectively disabled such that destination flip-
flops always capture predictable data even when the clock skew between the domains is
unknown. The impact on test time is negligible since the capture operation is disabled on a very
small number of flip-flops at any given time.
Cell-Aware ATPG
An ATPG method that targets potential faults within the physical cell model based on cell
extractions of potential defects and spice simulations of the defect impact on stimulus at the cell
inputs. Cell-aware ATPG is a subclass of the User-Defined Fault Model (UDFM) capability.
Chain Failure
A test fail resulting from a manufacturing defect directly in the scan chain path that causes the
scan chain to operate incorrectly.
Chain-To-Channel Ratio
The ratio of the number of scan chains in the design core to the number of channels (“virtual”
scan chains) the EDT logic presents to the tester. The latter must be the same as the number of
tester channels, so is usually fixed.
Channel
Refer to Scan Channel.
Clock Domain Base (CDB)

Point from which the clock distribution tree will be balanced during the layout stage. The skew
between any two points of the clock tree is minimized to allow synchronous operation of flip-
flops and latches. Each clock domain base is associated to a clock source.
Clock-Gating Element
Combinational gate (AND or OR gate) on the clock tree which has two unblocked inputs, a clock
and a non-clock input. A clock-gating element is said to be gate-active (gate-inactive) if its
output is forced to the active (inactive) polarity of the clock domain when applying a controlling
value on the non-clock input. For example, if the gate is an AND gate, and the active polarity of
the clock domain is 1, indicating that flip-flops are triggered by a rising edge of the clock, the
clock-gating element is said to be gate-inactive because applying a controlling value of 0 on the
non-clock input of the AND gate forces the clock domain to its inactive value.
Clock Source
Pin (or port) sourcing a clock for one or more clock domain bases. Valid clock sources are as
follows:
A primary input pin of a circuit or block

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An output pin of a Phased-Lock Loop (PLL) or clock divider circuit
Collections
A collection represents a group of zero or more design objects (pins or nets, for example) that
you can access via the Tessent Shell command interface. Design introspection commands such
as get_instances and get_modules return collections of objects. Each object has a second
dimension of information associated with it.
Comma Separated Values (CSV)

Comma Separated Values is a generic format used to export and import data from one software
application to another. CSV data utilizes commas to separate data.
Common Power Format (CPF)

CPF describes features of a design that are employed to save power. It serves a similar purpose to
UPF (IEEE 1801).The three main attributes that are described are:
• Power domains and their power supplies.
• Power control logic which includes level shifters, isolation logic, state retention logic as
well as power switch logic and associated control signals.
• Power modes and transition conditions.
Compactor
The part of the EDT logic that converts the outputs of a collection of internal scan chains into
one external scan channel output. In addition to the compaction in the number of scan chain
outputs, the conversion reduces the need for space that would otherwise be required to route
multiple scan chain outputs.
Compactor Group
In the compactor circuitry, one or more stages of XOR gates compact the response from several
chains into each channel output. Scan chains compacted into the same scan channel are said to be
in the same compactor group.
Compactor Stage
A single level of logic (XOR gates) in the Compactor. Each spatial compactor is comprised of
one or more compactor stages. See also First Compactor Stage.
Compression
Refer to Effective Compression.
Core
A block module that is either targeted for use in multiple designs or a distinct portion of the
design for purposes of hierarchically partitioning design complexity. In this document, any block
that contains a Mentor Graphics embedded logicTest controller is designated as an ELT core.
See ELT Core Module.

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Core Test Language (CTL)
CTL (IEEE 1450.6) is an extension of STIL that creates a standard format to describe IP core and
SOC test information.
Current EDT Block

The EDT block that is the sole target of context-sensitive commands in the top-level Pattern
Generation Phase of a modular Tessent TestKompress flow.
Defect
A physical (manufacturing) abnormality. Normally, a scan diagnosis tool will not identify a
defect. Rather, it will typically identify a symptom that must be correlated with the physical
aspects of the device to identify a specific defect.
Design-for-Test (DFT)
The practice of adding special circuits as part of an IC to aid in the testing of the fabricated chips.
DI
Detect by Implication.
Decompressor
The component of the Tessent TestKompress logic that converts compressed patterns into
normal scan patterns and applies them to the scan-inserted design core.
Dedicated Isolation
Technique that is making use of test-dedicated flip-flops to provide isolation of a Block Module
during an internal or external test. The technique is used to minimize the amount of periphery
logic and periphery flip-flops. Input block module pins with high fanout and output block
module pins with high fanin are likely candidates to receive dedicated isolation circuitry. This
technique is complementary to the Shared Isolation technique.
Defects Per Million (DPM)

A common measure of quality in production that describes the quantity of defective product that
escapes tests and ships to end customers.
Defective Parts Per Million (DPPM)

See Defects Per Million (DPM).
Design_cells
The number of lowest level design blocks used in the netlist. This value corresponds to the
number of library models used.
Design Block
See Block Module.
Design Editing
Design editing means creating, modifying, and removing elements of your design. Tessent Shell
offers many features that allow you to modify your design after reading in the RTL or gate-level

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netlist. Tessent Shell enables you to perform gate-level netlist editing or RTL design editing with
full language support, including multiple logical libraries, VHDL, Verilog, and System Verilog.
Design Environment
The circuit design environment encompassing all tools and libraries.
Design-for-Manufacturing (DFM)
Any technique used during the design of a cell or chip to improve the ease of manufacturing and
production yield. These techniques usually take the form of relaxed (less dense) design rules and
attention to uniformity of layout.
Deterministic Test
Refers to the use of software-based techniques to intelligently generate tests to detect specific
faults. as opposed to random or pseudo-random approaches that generate random patterns.
Diagnostics
The process (or tool feature) that determines the location of a device failure, which can aid
failure analysis and improve time-to-volume production.
Distribution or Distributed Processing

The dividing up and simultaneous execution of processing tasks on multiple machines.
Double Capture
See Launch-Off-Capture (LOC).
EDT
The trademark representing the Embedded Deterministic Test technology developed by Mentor
Graphics. See also Embedded Deterministic Test Technology (EDT™).
EDT Block
A design block in a modular Tessent TestKompress design that implements a full complement of
the Tessent TestKompress hardware (decompressor, compactor, and optionally bypass logic). It
is not necessarily a module (entity) in the HDL, but rather is a decompressor/compactor/core
group. An EDT block’s EDT hardware drives all the scan chains within the block.
Embedded Boundary Scan

The embedded boundary scan feature enables boundary-scan cells to be integrated alongside
their associated I/O cells within the module (physical-region or sub-block) rather than at the top
level of the chip.
Effective Compression
The ratio of the tester memory required with standard test patterns to the tester memory required
with compressed test patterns.
Embedded Compression
Refers to a technique that utilizes on-chip circuitry to compress and decompress test data. See
also Embedded Deterministic Test Technology (EDT™).

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Embedded Deterministic Test Technology (EDT™)
The technology developed and patented by Mentor Graphics that uses on-chip hardware to allow
highly compressed data to be applied to a circuit under test (CUT) without being decompressed
first by the tester (ATE).
Embedded Logic Test

A hierarchical test solution used to simplify the implementation of logic test for large chips. A
logicTest controller is associated with each Block Module to perform an internal logic test. Logic
in the top module of the chip interconnects between physical regions associated to block modules
that are tested using another logicTest controller located in the top module.
ELT
Embedded Logic Test.
ELT Core Module

Block Module that contains (or will contain) a Mentor Graphics Embedded Logic Test
controller. Only one ELT controller can be present in a given block module. Note that in
ETChecker, ELT core modules are identified but do not contain the ELT controller yet.
EMT
Embedded Memory Test.
EST
Obsolete.
ET-Inserted Netlist
The ET-Inserted view of your netlist is your functional RT or gate-level netlist with all
embedded test structures merged into it. The pre-ET-inserted view of you netlist is the netlist that
only contains your functional logic before any embedded test hardware was added to it. At the
RLT level, this version is often referred to as the Golden RTL.
Failure Analysis
The process of analyzing test failures to determine their cause.
False Path
A path that is not specified to operate at the system frequency. A setup false path refers to a path
that is not specified to ensure a change in value down the path can propagate within one clock
cycle. A hold time false path defines a condition where the data at a capture point is not stable
long enough for the clock signal to capture it.
Fanin
Refers to the upstream gate pins feeding into an input pin or top-level output port.
Fanout
Refers to the downstream gate pins from a particular gate output pin or top-level input port.

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Fault
A model used with a fault simulator in an attempt to mimic logical behavior of a failing circuit.
Suspects and symptoms can be derived from information gathered through fault simulations.
Diagnosis tools may perform additional operations beyond fault simulation that further the
precision of symptom identification.
Fault Coverage
A testability measure determined by the percentage of faults detected by a pattern set divided by
all possible faults.
Fault Grading
The process of determining how many faults in a target fault list are detected by a pattern set.
Fault Model
An abstraction of defect behavior that allows simulation of defects and measurement of test set
quality. Common fault models include stuck-at, transition, and path delay.
Fault Simulation
See Faulty Machine Simulation.
Faulty Machine Simulation

Logic simulation while injecting a specific fault on a given pattern set. The faulty machine
simulation is typically used to determine if a specific fault is detected or not. If simulation of a
faulty machine differs from the good machine simulation for at least one pattern in the specified
pattern set, the fault is marked as detected. Otherwise, the fault remains undetected. Fault
simulation results are used to calculate fault and test coverage for a list of faults on a specific set
of patterns. Another usage of faulty machine simulation is to model a defect and derive the
mismatch bits of a given pattern set when the defect occurs.
In analysis system mode, the tool automatically selects the appropriate machine simulation
methodology based on the specified user action (such as pattern creation or fault simulation).
Field Returns
A device that passed production testing but was sent back from a customer because it was found
to be defective.
First Compactor Stage

The Compactor Stage closest to the scan chains.
Flip-Flop
Memory element sensitive to an edge of a clock. Within the LV Flow each flip-flop is associated
with a Clock Domain Base (CDB) with an active edge polarity determined by the majority of the
flip-flops of that domain. If the flip-flop is triggered by the active edge of its associated CDB, the
flip-flop is said to be a non-opposite edge flip-flop or a trailing edge (TE) flip-flop. If the flip-
flop is instead triggered by the inactive edge polarity, the flip-flop is said to be an opposite edge
flip-flop or a leading edge (LE) flip-flop.

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Functional Block
See Block Module.
Functional ECO (Functional Engineering Change Order)

A minor and valid change performed on a design netlist to accommodate last minute changes that
affects the functionality of the chip.
Fuse Box
Also known as fuse array. A non-volatile memory used to permanently store memory repair
information or any other information specific to a chip (integrated circuit). Non-volatile
memories can be electrically programmed (written to) by applying a high voltage for
programming a value different from the default (non-programmed) one. These memories can be
one-time (OTP) or multiple-time (MTP) programmable (for example, flash memory).
Golden RTL
Also known as golden functional RTL or golden netlist. A Register Transfer Level circuit
description which the designer considers golden; that is, the reference or original design without
Embedded Test. The designer maintains this circuit description and performs all functional
modifications within it.
Good Machine Simulation

Logic simulation without injecting any faults. This simulation determines the circuit’s expected
behavior and is used for calculation of expected primary output and scan cell unload values, as
well as logic BIST MISR signatures.
In analysis system mode, the tool automatically selects the appropriate machine simulation
methodology based on the specified user action (such as pattern creation or fault simulation).
Graybox
Also known as scan shell. A simplified representation of an ELT Core Module describing its
periphery logic.
Hardcoded Algorithm
A hardcoded algorithm is an algorithm that is available at the ETAssemble step of the LV Flow.
The algorithm can be user-defined or the one from the Mentor Graphics library of algorithms.
This algorithm cannot be changed after the controller is generated.
Hard Tile
A description of a major block that is designed all the way through layout and physical design
prior to integrating with other blocks.
Hierarchical Integrated Flow

See LV Flow.
Hierarchical Test
A test flow that involves DFT and test generation on design blocks which can be reused at the
top level of the design. A typical hierarchical test will reuse test generation from the block level
and map it to the top level design. Often blocks include wrapper logic to isolate the block from

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other blocks to facilitate test reuse. Wrappers also prevent other blocks from interfering with the
block tests. One benefit of hierarchical test is that the full netlist does not need to be loaded in a
DFT or ATPG session. Thus, run time and memory requirements are dramatically reduced for
large designs.
Hold Time Failure

A failure that occurs because there is a race condition between the sequential elements at the
source and sink. A hold time failure occurs when the data at the sink sequential element is not
stable long enough (less than hold time) for the clock to capture it.
IDDQ Testing
Direct drain quiescent current. A type of testing that relies on current measurements (as opposed
to voltage) for observation to determine if a part is defective. A functional IC will have very low
quiescent current, as opposed to a defective IC having a path from power to ground causing
noticeably higher current.
IEEE 1149.1
An industry standard that defines a design interface and state machine that is placed within the
design to allow test instructions and data to be serially loaded into a device and enables the
subsequent test results to be serially read out. The test logic consists of a boundary-scan register
and other building blocks and is accessed through a Test Access Port (TAP). Although initially
designed for testing circuit board interconnect between IC devices, the use of IEEE 1149.1 has
expanded to control and test internal capabilities within the IC itself.
IEEE 1149.6
Sometimes called AC-JTAG, this industry standard extension is built upon IEEE 1149.1 to
enable for the inclusion of testing with and through newer I/O test structures that are AC-
coupled, differential, or both.
IEEE 1500
The IEEE Std 1500 – Standard for Embedded Core Test (SECT), approved in 2005, describes the
architecture and the protocols for enabling test reuse for embedded cores. It targets digital cores
only. The standard includes a core test interface (wrapper) between the core and the surrounding
design. Similar to IEEE 1149.1, the wrapper contains an instruction register, a boundary register,
and a bypass register. The test access to the core is, however, not only through a serial interface,
but also possible through a parallel access to and from the wrapper’s boundary register. IEEE
1500 was not widely adopted in industry.
IEEE 1687-2014
IEEE 1687-2014 (IEEE 1687 or 1687), also known as Internal JTAG (IJTAG), describes a
standard that allows plug and play connections and usage of any embedded so-called instrument
within a chip. It is compatible with IEEE 1149.1 but goes well beyond. In the 1687 context, an
instrument is any kind of core or IP for which a 1687-compliant interface (ports and their
semantic) can be defined. The standard includes three main aspects:
• Hardware rules for 1687 instruments, including port functions, timing, and connection
rules.

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• An Instrument Connectivity Language (ICL) which describes the interface for an
instrument, as well as the connection of these instruments. ICL is a highly abstracted
language that is not necessarily a recoding of Verilog.
• A Procedural Description Language (PDL) which describes instructions to Tessent Shell
on how to compute patterns for the instrument.
It must be noted that the test patterns targeted with the 1687 standard are not ATPG scan test
patterns, but are primarily communication with embedded BIST hardware or other similarly
simple IO-based tests.
Instrument
In the IJTAG context, an instrument is any kind of core or IP for which a 1687-compliant
interface (ports and their semantic) can be defined. See also IEEE 1687-2014.
Instrument Connectivity Language (ICL)

The language in which IJTAG describes the interface for an instrument, as well as the connection
of these instruments. ICL is a highly abstracted language that is not necessarily a recoding of
Verilog. See also Internal JTAG (IJTAG) and IEEE 1687-2014.
Internal Scan Chain

Refer to Scan Chain.
Internal JTAG (IJTAG)

IJTAG is the name of the IEEE 1687-2014 standard. See IEEE 1687-2014.
IP Version
The version of the Tessent TestKompress hardware architecture. This is different than the
software version of the tool. A newer version of Tessent TestKompress, in which only the kernel
is updated but the architecture of the EDT logic it generates is the same as before, will have the
same IP version number. Only the software version would increment.
Isolation
In the context of designs with multiple power domains, isolation logic is used to assert or retain a
logic value on a circuit output that has been power down to prevent un-driven inputs of powered
logic.
Joint Test Action Group (JTAG)

The committee that formulated IEEE standard 1149.1 describing boundary scan.
JTAG
Refer to Joint Test Action Group (JTAG).
Latch
Memory element sensitive to the level of a clock. When a latch is enabled, it becomes transparent
and the data on the input is flushed to the output. When a latch is disabled, it holds the last value
on its input before the transition of the enable signal from active to inactive. In the LV Flow, if
the latch is transparent when its associated Clock Domain Base (CDB) is asserted to its active
level, the latch is said to be a type A latch or a simply an A latch. If the latch is instead

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transparent when its associated CDB is asserted to its inactive level, the latch is said to be a Type
I latch or simply an I latch.
Launch-Off-Capture (LOC)
Also know as launch-from-capture or double capture. Clocking technique used to perform an at-
speed test of a scannable circuit. Signal transitions are launched at the active edge of a clock and
captured at the next active edge. Flip-flops are configured in capture mode for both the launch
and capture operation. Also known as Broadside.
Launch-Off-Shift (LOS)
Also known as launch-from-shift or single capture. Clocking technique used to perform an at-
speed test of a scannable circuit. Signal transitions are launched at the active edge of a clock
applied to flip-flops configured in shift mode and captured at the next active clock edge.
Leaf
In Tessent Shell, leaf naming is used in the tool for items such as instances and pins. In fact,
leaf_name is a built-in attribute for instances, pins, nets, and gate_pins. It is also used for icl_pins
and icl_instances. The leaf name for one of these design objects is the lowest level of hierarchy
in the pathname to the object. For example, for an input pin on an AND gate in a design, it would
have a location of something like /top/blockA/u4/A0. The leaf_name attribute for this pin would
be A0.
Legacy Core
A core that cannot be altered to introduce design-for-test (DFT) features. Legacy cores normally
consist of a completed transistor-level layout database but are sometimes provided as an RTL
description or a gate-level netlist. A legacy core might have:
• No DFT features at all. In this case, Mentor Graphics tools will automatically provide an
isolation mechanism for the core that will allow testing of the logic surrounding the
core. However, the core itself must be tested by the user. These can be referred to as
non-scannable legacy cores.
• Existing scan chains that can be integrated with other scan chains used to implement
logic test of the parent module. These can be referred to as scannable legacy cores.
• Self-test implemented with Version LV2004 or older versions (Mentor Graphics legacy
cores). All internal tests of the core are reusable, and periphery scan chains are
integrated with other scan chains used to implement logic test of the parent module.
Level Sensitive Scan Design (LSSD)

A scan cell architecture composed of two latches controlled by non-overlapping clocks.
Level Shifter
Logic that translates logic levels between to between two power domains with different supply
voltages.
Library
A library is a collection of components sharing certain common characteristics. For example, a
given technology library is made of the individual gates or cells (combinational and sequential)

September 2016
that can be used to create a chip. To implement DFT on a design, Tessent requires additional cell
libraries to be defined. Note: These so-called “libraries” may eventually be merged with other
existing Mentor Graphics libraries:
• Pad Library — File(s) describing the various IO pads present into the design and their
ports, to properly insert and connect boundary-scan cells.
• Cell Library — File(s) describing basic combo cells (AND2, OR2, BUF, INV, MUX,
etc.) that can be used when generating and connecting Tessent RTL.
• Scang Library — A file containing mapping information between non-scan and scan
flip-flops, plus a few key basic cells to be used for proper scan insertion.
Library_primitives
The number of library primitive gates that are used by the netlist. A particular library model can
have one or primitive gates (_and, _or, _dff, …).
Linear Feedback Shift Register (LFSR)

A shift register with feedback tap points to generate repeatable random sequences or compress
input values, typically used in BIST as a PRPG and MISR.
Logic Built-In Self-Test (LBIST)

On-chip test circuitry used for testing logic without any external patterns. Typically uses a
pseudo-random pattern generator for inputs and a MISR for reading outputs.
logicTest controller
A Mentor Graphics embedded test circuit that is used to implement a test for logic. It can be
inserted in a Top Module or an ELT Core Module.
Logic Failure
A test fail resulting from a manufacturing defect in circuit logic that is not directly in the scan
chain path and does not affect the operation of the scan chains.
Low Pin Count Test (LPCT)

A test architecture that reduces the number of pins on the test interface. LPCT hardware can be
automatically generated by Tessent TestKompress using the set_lpct_controller command and
can be configured to generate all test-related signals. The test signals can be generated either
from a pre-existing JTAG TAP interface or by the LPCT hardware itself.
LV Flow
The structured flow based on the LogicVision tools and infrastructure. This design flow used to
insert and verify various Embedded Test features in a block module. There are two variations of
the flow:
• Block variation of the LV Flow for block modules that do not require the insertion of a
logicTest controller.
• ELT variation of the LV Flow or block modules that require the insertion of a logicTest
controller.

September 2016
Each of these variations can be applied to the Register Transfer Level or the gate-level
description of a block module. See Block Module, Wrapper Test Access Port (WTAP) (or Test
Access Port (TAP) if it is a Top Module) that is inserted to control the Embedded Test features.
LVDB
The Mentor Graphics database. This is a collection of Mentor Graphics internal files into a
directory structure so as to enable manufacturing and system reuse of the embedded test
capabilities. It can also be used to facilitate handoff of cores with embedded test to third parties.
lvWorkSpace
A set of data files, scripts, and directories used to generate, insert, and verify embedded test for a
block or top module. The environment is automatically created by the ETPlanner tool and
contained in the lvWorkSpace directory.
MacroTest
An option to Tessent FastScan to enable non-intrusive testing of macros or small, performance-
critical memories. Converts patterns described in terms of the macro's ports into scan patterns.
Make Target
A Mentor Graphics-defined name used in a Makefile. This name identifies a set of steps in a
given Mentor Graphics design flow. A target is an argument supplied to the UNIX make utility.
Memory BIST controller

A Mentor Graphics embedded test circuit that is used to implement a test for a memory or a
group of memories. Any number of memory BIST controllers can be inserted in a Top Module,
ELT Core Module, or a Block Module. The following types of memory BIST controllers can be
generated:
• NonProgrammable — A memory BIST controller that implements a limited number of
library algorithms. The algorithms are limited to the SMarch, SMarchCHKB,
SMarchCHKBci, SMarchCHKBcil, SMarchCHKBvcd, and ReadOnly. The
NonProgrammble controllers do not allow you to select an algorithm to run on specific
steps at the tester time.
• HardProgrammable — A memory BIST controller that implements one or more user-
defined algorithms that can be selected at tester time. The HardProgrammable
controllers do not allow you to define new algorithms at the tester time.
• SoftProgrammable — A memory BIST controller that implements user-defined
algorithms that can be programmed at the tester time.
Module
A partitioned portion of a chip design corresponding to a level in the HDL hierarchy. A module
can contain one or more sub-modules. Some modules have a special designation: Top Module,
Sub-Block, Block Module, and ELT Core Module.
Monitor
Term used to identify a directory being monitored for diagnosis data.

September 2016
Multicycle Path
A path that is defined such that a signal requires multiple clock cycles to propagate down the
path and be captured at the sink. The number of clock cycles required to propagate can be
defined for each multicycle path.
Multiple Detect
A technique that detects a fault multiple times in different ways, with the expectation to deliver
better detection of bridging and un-modeled faults. Also known as n-detect.
Multiple Input Signature Register (MISR)

The BIST circuitry used to capture results into a signature.
Multiprocessing
A general term that can refer either to distribution or multithreading, or to a combination of both.
Multithreading
The dividing up and simultaneous execution of processing tasks within one Process running on
one machine. This method minimizes memory use per Thread by sharing the design information
across all threads running on the same machine.
MUX-DFF
A style of scan cell using a multiplexer to select between system or shift data.
Path Delay
A fault model for at-speed testing that models combined delays through a known critical path.
Also known as delay testing.
Procedural Description Language (PDL)

The language in which IJTAG describes instructions to Tessent Shell on how to compute
patterns for the instrument. See also IEEE 1687-2014.
PDL Command Retargeter

A functionality that takes an instrument level PDL file or an interactively written set of PDL
commands, and computes how these PDL commands would look if called from a different
hierarchy level, usually the top level of the design described in ICL.
Periphery Flip-Flop
A flip-flop used to isolate a Block Module during an internal or external test mode of that block.
An input periphery flip-flop has at least one block module input in its fanin. An output periphery
flip-flop has at least one block module output or one input periphery flip-flop in its fanout. A
periphery flip-flop can be a functional flip-flop or a test-dedicated flip-flop.
Periphery Logic
Logic gates of an ELT core module located between the inputs/outputs and the first layer of
scannable flip-flops of that ELT core module. The periphery logic is tested during the external
test mode of that ELT core module.

September 2016
Periphery Scan Chain
A scan chain composed of Periphery Flip-Flops.
Physical Region
A portion of a chip or circuit corresponding to a Block Module that is laid out separately using a
Physical Design tool. It is also referred to as a physical block, layout region, or layout block.
Pin Sharing
Refers to functional pins shared with the Decompressor inputs and Compactor outputs.
Pipeline Stages (Channel)

Pipeline stages you insert outside the EDT logic, between top level pins/pads and Tessent
TestKompress channel inputs and outputs, to improve signal propagation time.
Pipeline Stages (Compactor)

Flip-flops (clocked by the leading edge of the Tessent TestKompress clock) that Tessent
TestKompress optionally inserts in the spacial compactor to improve the overall rate of data
transfer through the compactor logic.
PLL BIST Controller

A controller used to test a Phased-Locked Loop Sub-Block.
Post-Layout Netlist
A netlist obtained after the layout of a Block Module has been completed, including detailed
routing and timing optimization. Note that this netlist is usually flat, specifically, all levels of
hierarchy have been removed.
Process
The instance of the executable running on the master or slave host, regardless of the number of
Threads in use.
Processor
A resource that executes a Thread, which is added with the add_processors command or by
starting the tool.
Pseudo-Random Pattern Generator (PRPG)

The BIST circuitry used to generate random patterns.
Pseudo-Random Test
An approach that uses hardware to generate random (but repeatable) test patterns.
Pulse-in-capture clock
A clock signal that is pulsed in every cycle of the capture window.
Pulse-always Clock
A clock signal that is pulsed during every cycle (just like a synchronous free-running clock).

September 2016
Reduced Pin Count Testing (RPCT)
A test technique used for applying test patterns to a device through a subset of all the device pins.
Typically uses the JTAG interface and can be used to apply scan patterns with no impact on test
time or pattern count. Allows for use of low-cost testers with limited I/O interface.
Registration (for attributes)

Each design object has a list of characteristics, called attributes, attached to that object. For
example, all pins have an attribute that specifies its hierarchical name and its parent instance.
There are both pre-defined and user-defined attributes. The process for creating a new user-
defined attribute is called registration. The pre-defined attributes, unlike the user-defined
attributes, do not need to be registered.
Registered I/O
The practice of registering (i.e. adding DFFs) to the input/output signals of a block for the
purpose of synchronizing timing into and out of the block.
Retention
In the context of designs with multiple power domains, retention logic holds its state when it
either not powered or held at a standby voltage.
Ring Generator
A specialized form of an LFSR that produces pseudo-random data from inputs with continuous
stimulus. A ring generator is used in the Tessent TestKompress decompressor.
Runtime Programmable Algorithm

Also called Soft-Programmable. A runtime programmable algorithm () is a user-defined
algorithm that is defined using the ETVerify tool in the LV Flow after the memory BIST
controller generation. This algorithm might also be referred to as post-silicon
programmablealgorithm.
Sandia Controllability and Observability Analysis Program (SCOAP)

A method used to determine design testability; often used for scan or test point selection.
Scan
A technique for converting sequential design elements (i.e., flip-flops and latches) into control
and observe points for purposes of testing a design's logic.
Scan Cell
A single sequential element in a scan chain. Typical types include MUX-DFF, Clocked Scan and
LSSD.
Scan Chain
A connection of sequential elements converted into a shift register, which simplifies structural
testing by providing additional control and observe points to internal nodes within a design. Scan
chain operations consist of shifting in test data, capturing system data and shifting out system
responses. Scan chains form the basis for ATPG, EDT and Logic BIST.

September 2016
Scan Chain Family
A family of scan elements that can be created based on specific criteria such as a specified
instance, module, clock domain or power domain.
Scan Chain Masking

The mechanism whereby Tessent TestKompress records the actual measured value for each cell
in a specific scan chain in a compactor group, and changes the values to all Xs in all other chains
in the group, enabling the tool to observe the specific scan chain.
Scan Channel
A “virtual” scan chain that a chip incorporating EDT technology provides as the input/output
interface to a channel of a tester. A chip design may include more than one scan channel, based
upon the number of channels available on the ATE, that will be used to test the chip.
Scan Element
A library cell or lowest level model called a leaf cell. The library cell or leaf cell can be a single
or multi-bit scan element.
Scan Mode
A scan chain configuration that describes how the scan chains are stitched by Hierarchical Scan
Insertion.
Scan Model
A model used for a library cell to describe its properties to the Mentor Graphics analysis tools
(for example, ruleAnalyze). Library cells requiring scan models are primarily sequential cells,
such as flip-flops and latches, gates, and boolean functions that are not modeled as Verilog
primitives. Scan models for custom memories are created automatically by Embedded Memory
Test.
Scan Shell
See Graybox.
Sequential Elements
Refers to all elements in the design whose outputs change state as the result of a change to a
clock, set, or reset. Sequential elements include flip-flops, latches, RAMs and ROMs.
SerDes
Also known as SERDES. An acronym for a SERialyzer/DESerialyzer – typically a mixed-signal
PHY made of the two following blocks:
• TX: The transmitter serializes an input databus of width “N” clocked by a parallel clock
of frequency fTX; that is, it produces a bitstream (typically over a differential channel)
whose bitrate is N*fCLK.
• RX: The receiver accepts incoming serial data and converts it back into its parallel form,
while generating a recovered parallel clock from this incoming data.
When a TX sends data into a RX without bit errors, the RX should thus produce the same parallel
words and at the same frequency as what was clocked into the TX (although with some latency).

September 2016
Shared Isolation
Patented technique making use of functional flip-flops to provide scan isolation of a Block
Module during an internal or external test. This technique allows you to reduce significantly the
amount of test circuitry required to implement a hierarchical test approach and to enable a true
at-speed test of the periphery flip-flops made of functional flip-flops.
Shared Tessent TestKompress Pin

A decompressor input or compactor output that, rather than being a dedicated Tessent
TestKompress pin, is shared with a functional pin.
Segment Insertion Bit (SIB)

A recommended piece of DFT used in the IJTAG description of the access network; it is the
network that connects the top-level TAP, for example, to the instruments. A SIB is in essence a
scan chain switch. It has two scan input pins and one scan output pin.
Sim_gates
Simulation gates are the total count of gates used in the flattened model. They are constructed
from library primitives and netlist primitives and other gates created to improve simulation
accuracy and performance.
Soft Repair
The process of using BIST at power-up to determine a remapping of failing memory cells to
redundant rows or columns. See also hard repair.
Static Timing Analysis (STA)

STA is a method for validating that a gate-level netlist is free of timing errors, without having to
resort to lengthy simulations. Gate-level simulations are usually time-consuming (from a
simulator standpoint), especially if they include realistic delays (provided via a Standard Delay
Format file), that is “SDF file backannotation”. Additionally, their validity entirely depends on
the actual testbench (TB) being simulated and the surrounding circuit conditions it contains or
results. STA performs timing analysis by looking at every possible flop-to-flop path and reports
any possible timing path violating a single cycle timing, unless specifically declared as “false
path” (FP) or “multi-cycle path” (MCP).
STIL
IEEE 1450 Standard Test Interface Language. A test description language that provides an
interface between digital test generation tools and test equipment.
Stuck-At Fault Model

A fault model targeting defects that act as though a device node is stuck on or off, that is stuck at
a voltage level 1 (s-a-1) or voltage level 0 (s-a-0).
Sub-Block
A hierarchical sub-division within a Block Module which usually corresponds to cells of a
library, simple combinational/sequential cells, memories, pads, PLLs, SerDes blocks, etc.
Sometimes, a sub-block requires the creation of an specific model to enable the insertion of
appropriate embedded test for the sub-block. A sub-block cannot be ungrouped.

September 2016
SVF
Serial Vector Format, which is an IEEE 1149.1 standard, is a vector exchange format designed to
enable transfer of boundary scan vectors between tools. This format is controlled by boundary-
scan solution provider ASSET InterTech.
Standard Test Interface Language (STIL)

A recently IEEE-adopted standard (IEEE Std. 1450-1999) format for test patterns that is growing
in use.
Suspect
A circuit location (net or pin) and type of behavior at that location that the tool determines could
cause an observed symptom. There may be multiple suspects for one symptom.
Suspect Type
Suspects are typecast into categories (types) such as stuck-at, open, bridging, slow-to-rise, and so
on.
Symptom
A phenomenon that is causing test failures. A primary reason for using a diagnostic tool is to
isolate each symptom. Symptoms provide valuable clues that can help you identify a defect. As
part of the diagnosis process, Tessent Diagnosis groups fail information into one or more
independent symptoms (fail subsets) and assumes each such symptom is explainable by one
defect.
System-on-Chip (SoC)
An ASIC that is specially developed to meet the requirements of a given application in which the
objective is to integrate most functionality on a single chip, thereby realizing benefits in terms of
price, performance, and reliability. Examples of functions that are often integrated in an SoC are
microprocessors, memory, and interfaces.
Target Type
One of three Mentor Graphics-defined categories for a design module:
• Top — Causes the insertion of the Test Access Port (TAP) controller—with or without
boundary scan cells and with or without a top-level logicTest controller—to top module
of a chip. The integration tool is ETAssemble.
• Block — Causes the addition of scan chains or test controllers (except logicTest
controllers) or both in a block module. A Wrapper Test Access Port (WTAP) controller
is also added to the Block Module if any type of test controller is present.
• ELT Core — Causes the insertion of scan chains, a logicTest controller, and a Wrapper
Test Access Port (WTAP) controller in a Block Module. Embedded Test controllers for
sub-blocks such as memory, PLL, or ULTRA (for Tessent SerdesTest) are also inserted,
if applicable.

September 2016
Tessent Core Description (TCD) File
The core description file contains the information the tool needs to map the core-level patterns to
the next level of hierarchy during pattern retargeting. This includes information such as
description of the EDT hardware and scan chains.
Tessent Flow
The flexible flow provided within the Tessent Shell tool.
Tessent Shell Database (TSDB)

The Tessent Shell Database is a structured directory in which Tessent Shell stores and retrieves
data. Refer to the set_tsdb_output_directoryand open_tsdb commands for more information
about its content and usage.
Tessent TestKompress Logic

The hardware synthesized into a design to implement the EDT technology. This hardware
consists of two main components: A Decompressor and a Compactor.
Tessent TestKompress Patterns

The compressed patterns generated by Tessent TestKompress.
Test Access Mechanism (TAM)

A common term for logic that enables a test function to be accessed from a higher level interface.
Test Access Port (TAP)

Defined by the IEEE 1149.1 standard. A TAP is used to access test controllers/registers of a
circuit. Typically, a single TAP is present on the circuit but more than one can be used under
certain circumstances. A TAP is normally inserted in the circuit Top Module.
Test-Collared Sub-Block
A Sub-Block, such as memory, PLL, SerDes surrounded collar elements forming a test collar
around sub-blocks.
Test Coverage
Also known as coverage. A testability measure determined by the percentage of faults detected
by a pattern set divided by all testable faults.
Test Escape
Also known as escape. A defective device that passes through test as good. See Field Returns.
Test Failure
An ATE test result that does not equal the pre-defined expected result.
Test Points
Circuitry added to the design to increase controllability and/or observability during test.

September 2016
Testpoint
A small logic circuit inserted into a netlist (RTL or gate) to improve controllability or
observability of difficult-to-test gates/signals. There are two types of testpoints that can be
inserted in your design:
• ETChecker can be used to identify signals that need to be controlled in order to avoid
rule violations and signals that are otherwise unobservable. These signals are identified
with the lv.AddObservation and lv.InjectControl properties in ETChecker. Logic
described in RTL is automatically added to the RTL golden netlist. This type of
testpoints can be used with any circuit.
• The testpointAnalyze tool can be used to identify signals in a gate-level netlist requiring
additional controllability or observability in circuits that are random pattern resistant.
Thread
The smallest independent unit of a Process. A process can consist of multiple threads, all of
which share the same allocated memory and other resources on the same host.
Timing-Aware ATPG
An at-speed ATPG method that uses SDF timing information to activate and propagate faults.
Similar to transition fault ATPG, a slow-to-fall and slow-to-rise fault exists at each library IO
site. The ATPG process uses SDF such that targeted faults launch and capture between paths
with the largest delays possible. Timing-aware ATPG is more likely to detect small delay defects
than traditional transition patterns.
TLA
This term is used for latches where the defined clock (enable) off state activates the latch. As a
result, when clocks are off and the circuit is in a stable state, data will pass from the input to the
output of the latch as if it were a buffer. During the ATPG process, TLAs act as buffers.
Top Module
A chip is composed of a single top module that instantiates all other sub-modules. The top
module contains the Test Access Port (TAP) used to access all test resources of the circuit, like
boundary scan, logicTest controller, Memory BIST controller, etc. The Test Access Port (TAP)
controller can also be connected to Wrapper Test Access Port (WTAP) controllers embedded in
Block Modules or ELT Core Modules in the context of a hierarchical test strategy.
Transition Faults
A type of fault used in at-speed testing that models a gross delay at each gate terminal.
ULTRA Controller
Also known as UnLimited Time Resolution Analysis (ULTRA) controller. The technology and
principle on which Tessent PLLTest and Tessent SerdesTest are built upon. The ULTRA
controller performs statistical analysis on a signal of interest that has been under-sampled (that
is, multiply-sampled at a rate that is just slightly below the Nyquist frequency). For PLLTest,
those signals of interest may be the input and output(s) of the PLL; for a SerDes, it could be the
TX and RX clocks, the data bits, etc.

September 2016
Unified Power Format (UPF)
UPF (IEEE1801) describes features of a design that are employed to save power. It serves a
similar purpose to CPF. The three main attributes that are described are:
• Power domains and their power supplies
• Power control logic which includes level shifters, isolation logic, state retention logic as
well as power switch logic and associated control signals
• Power modes and transition conditions
Ungroup
An operation performed on a circuit description (RTL- or gate-level netlist) that consists of
removing levels of hierarchy. This operation can be performed by a synthesis or a layout tool.
Unwrapped Core
A module or core or block that does not contain or include any wrapper cells for the core.
User-Defined Fault Model (UDFM)
A custom fault model that enables the user to define specific sequences to target user-defined
faults. Custom faults can be defined at the library model level or between hierarchical instance
pins.
Waveform Generation Language (WGL)

An industry standard, IEEE-approved language that provides an interface between digital test
generation and ATE tools.
Wrapped Core
A module or core or block that contains or includes wrapper cells for the core. Wrapper cells
may be of type shared wrapper cells or dedicated wrapper cells.
Wrapper
One of more scan chains designed to isolate a block to facilitate hierarchical test. Wrappers
either use existing flops that are close to the block IO or add additional scan cells at the IO.
Wrapper Serial Port (WSP)

Provides access to wrappers used in hierarchical test. This term is used in the IEEE 1500
standard for embedded core test. A WSP is included within the WTAP used in the LV Flow.
Wrapper Test Access Port (WTAP)

Also called WrapperSerial Interface (WSI). Defined by the IEEE 1500 standard and inserted in
each block module. The WTAP allows you to distribute test control in a way that will reduce
routing congestion around the top module TAP and provide a fixed test interface for the block
module.
X Blocking
The X recorded by the tool in the pattern file in every position made unmeasurable as a result of
the occurrence of an X in the corresponding cell of a different scan chain in the same compactor
group.

September 2016
X-Bounding
Additional circuitry added to a design to stop unknown logic states from propagating to the
MISR circuitry.
Yield
The percent of functional units leaving a process. The lower the process yield, the higher the test
coverage must be to keep Defects Per Million (DPM) rates low.

September 2016
September 2016
Third-Party Information
For information about third-party software included with this release of Tessent products, refer to the Third-Party Software for
Tessent Products.
End-User License Agreement
The latest version of the End-User License Agreement is available on-line at:
www.mentor.com/eula
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collectively “Beta Code”), which may not be used without Mentor Graphics’ explicit authorization. Upon Mentor Graphics’
authorization, Mentor Graphics grants to Customer a temporary, nontransferable, nonexclusive license for experimental use to
test and evaluate the Beta Code without charge for a limited period of time specified by Mentor Graphics. Mentor Graphics may
choose, at its sole discretion, not to release Beta Code commercially in any form.
3.2. If Mentor Graphics authorizes Customer to use the Beta Code, Customer agrees to evaluate and test the Beta Code under normal
conditions as directed by Mentor Graphics. Customer will contact Mentor Graphics periodically during Customer’s use of the
Beta Code to discuss any malfunctions or suggested improvements. Upon completion of Customer’s evaluation and testing,
Customer will send to Mentor Graphics a written evaluation of the Beta Code, including its strengths, weaknesses and
recommended improvements.
3.3. Customer agrees to maintain Beta Code in confidence and shall restrict access to the Beta Code, including the methods and
concepts utilized therein, solely to those employees and Customer location(s) authorized by Mentor Graphics to perform beta
testing. Customer agrees that any written evaluations and all inventions, product improvements, modifications or developments
that Mentor Graphics conceived or made during or subsequent to this Agreement, including those based partly or wholly on
Customer’s feedback, will be the exclusive property of Mentor Graphics. Mentor Graphics will have exclusive rights, title and
interest in all such property. The provisions of this Subsection 3.3 shall survive termination of this Agreement.
4. RESTRICTIONS ON USE.
4.1. Customer may copy Software only as reasonably necessary to support the authorized use. Each copy must include all notices
and legends embedded in Software and affixed to its medium and container as received from Mentor Graphics. All copies shall
remain the property of Mentor Graphics or its licensors. Except for Embedded Software that has been embedded in executable
code form in Customer’s product(s), Customer shall maintain a record of the number and primary location of all copies of
Software, including copies merged with other software, and shall make those records available to Mentor Graphics upon
request. Customer shall not make Products available in any form to any person other than Customer’s employees and on-site
contractors, excluding Mentor Graphics competitors, whose job performance requires access and who are under obligations of
confidentiality. Customer shall take appropriate action to protect the confidentiality of Products and ensure that any person
permitted access does not disclose or use Products except as permitted by this Agreement. Customer shall give Mentor Graphics
written notice of any unauthorized disclosure or use of the Products as soon as Customer becomes aware of such unauthorized
disclosure or use. Customer acknowledges that Software provided hereunder may contain source code which is proprietary and
its confidentiality is of the highest importance and value to Mentor Graphics. Customer acknowledges that Mentor Graphics
may be seriously harmed if such source code is disclosed in violation of this Agreement. Except as otherwise permitted for
purposes of interoperability as specified by applicable and mandatory local law, Customer shall not reverse-assemble,
disassemble, reverse-compile, or reverse-engineer any Product, or in any way derive any source code from Software that is not
provided to Customer in source code form. Log files, data files, rule files and script files generated by or for the Software
(collectively “Files”), including without limitation files containing Standard Verification Rule Format (“SVRF”) and Tcl
Verification Format (“TVF”) which are Mentor Graphics’ trade secret and proprietary syntaxes for expressing process rules,
constitute or include confidential information of Mentor Graphics. Customer may share Files with third parties, excluding
Mentor Graphics competitors, provided that the confidentiality of such Files is protected by written agreement at least as well as
Customer protects other information of a similar nature or importance, but in any case with at least reasonable care. Customer
may use Files containing SVRF or TVF only with Mentor Graphics products. Under no circumstances shall Customer use
Products or Files or allow their use for the purpose of developing, enhancing or marketing any product that is in any way
competitive with Products, or disclose to any third party the results of, or information pertaining to, any benchmark.
4.2. If any Software or portions thereof are provided in source code form, Customer will use the source code only to correct software
errors and enhance or modify the Software for the authorized use, or as permitted for Embedded Software under separate
embedded software terms or an embedded software supplement. Customer shall not disclose or permit disclosure of source
code, in whole or in part, including any of its methods or concepts, to anyone except Customer’s employees or on-site
contractors, excluding Mentor Graphics competitors, with a need to know. Customer shall not copy or compile source code in
any manner except to support this authorized use.
4.3. Customer agrees that it will not subject any Product to any open source software (“OSS”) license that conflicts with this
Agreement or that does not otherwise apply to such Product.
4.4. Customer may not assign this Agreement or the rights and duties under it, or relocate, sublicense, or otherwise transfer the
Products, whether by operation of law or otherwise (“Attempted Transfer”), without Mentor Graphics’ prior written consent and
payment of Mentor Graphics’ then-current applicable relocation and/or transfer fees. Any Attempted Transfer without Mentor
Graphics’ prior written consent shall be a material breach of this Agreement and may, at Mentor Graphics’ option, result in the
immediate termination of the Agreement and/or the licenses granted under this Agreement. The terms of this Agreement,
including without limitation the licensing and assignment provisions, shall be binding upon Customer’s permitted successors in
interest and assigns.
4.5. The provisions of this Section 4 shall survive the termination of this Agreement.
5. SUPPORT SERVICES. To the extent Customer purchases support services, Mentor Graphics will provide Customer with updates and
technical support for the Products, at the Customer site(s) for which support is purchased, in accordance with Mentor Graphics’ then
current End-User Support Terms located at http://supportnet.mentor.com/supportterms.
6. OPEN SOURCE SOFTWARE. Products may contain OSS or code distributed under a proprietary third party license agreement, to
which additional rights or obligations (“Third Party Terms”) may apply. Please see the applicable Product documentation (including
license files, header files, read-me files or source code) for details. In the event of conflict between the terms of this Agreement
(including any addenda) and the Third Party Terms, the Third Party Terms will control solely with respect to the OSS or third party
code. The provisions of this Section 6 shall survive the termination of this Agreement.
7. LIMITED WARRANTY.
7.1. Mentor Graphics warrants that during the warranty period its standard, generally supported Products, when properly installed,
will substantially conform to the functional specifications set forth in the applicable user manual. Mentor Graphics does not
warrant that Products will meet Customer’s requirements or that operation of Products will be uninterrupted or error free. The
warranty period is 90 days starting on the 15th day after delivery or upon installation, whichever first occurs. Customer must
notify Mentor Graphics in writing of any nonconformity within the warranty period. For the avoidance of doubt, this warranty
applies only to the initial shipment of Software under an Order and does not renew or reset, for example, with the delivery of (a)
Software updates or (b) authorization codes or alternate Software under a transaction involving Software re-mix. This warranty
shall not be valid if Products have been subject to misuse, unauthorized modification, improper installation or Customer is not in
compliance with this Agreement. MENTOR GRAPHICS’ ENTIRE LIABILITY AND CUSTOMER’S EXCLUSIVE
REMEDY SHALL BE, AT MENTOR GRAPHICS’ OPTION, EITHER (A) REFUND OF THE PRICE PAID UPON
RETURN OF THE PRODUCTS TO MENTOR GRAPHICS OR (B) MODIFICATION OR REPLACEMENT OF THE
PRODUCTS THAT DO NOT MEET THIS LIMITED WARRANTY. MENTOR GRAPHICS MAKES NO WARRANTIES
WITH RESPECT TO: (A) SERVICES; (B) PRODUCTS PROVIDED AT NO CHARGE; OR (C) BETA CODE; ALL OF
WHICH ARE PROVIDED “AS IS.”
7.2. THE WARRANTIES SET FORTH IN THIS SECTION 7 ARE EXCLUSIVE. NEITHER MENTOR GRAPHICS NOR ITS
LICENSORS MAKE ANY OTHER WARRANTIES EXPRESS, IMPLIED OR STATUTORY, WITH RESPECT TO
PRODUCTS PROVIDED UNDER THIS AGREEMENT. MENTOR GRAPHICS AND ITS LICENSORS SPECIFICALLY
DISCLAIM ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NON-INFRINGEMENT OF INTELLECTUAL PROPERTY.
8. LIMITATION OF LIABILITY. TO THE EXTENT PERMITTED UNDER APPLICABLE LAW, IN NO EVENT SHALL
MENTOR GRAPHICS OR ITS LICENSORS BE LIABLE FOR INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
DAMAGES (INCLUDING LOST PROFITS OR SAVINGS) WHETHER BASED ON CONTRACT, TORT OR ANY OTHER
LEGAL THEORY, EVEN IF MENTOR GRAPHICS OR ITS LICENSORS HAVE BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES. IN NO EVENT SHALL MENTOR GRAPHICS’ OR ITS LICENSORS’ LIABILITY UNDER THIS
AGREEMENT EXCEED THE AMOUNT RECEIVED FROM CUSTOMER FOR THE HARDWARE, SOFTWARE LICENSE OR
SERVICE GIVING RISE TO THE CLAIM. IN THE CASE WHERE NO AMOUNT WAS PAID, MENTOR GRAPHICS AND ITS
LICENSORS SHALL HAVE NO LIABILITY FOR ANY DAMAGES WHATSOEVER. THE PROVISIONS OF THIS SECTION 8
SHALL SURVIVE THE TERMINATION OF THIS AGREEMENT.
9. THIRD PARTY CLAIMS.
9.1. Customer acknowledges that Mentor Graphics has no control over the testing of Customer’s products, or the specific
applications and use of Products. Mentor Graphics and its licensors shall not be liable for any claim or demand made against
Customer by any third party, except to the extent such claim is covered under Section 10.
9.2. In the event that a third party makes a claim against Mentor Graphics arising out of the use of Customer’s products, Mentor
Graphics will give Customer prompt notice of such claim. At Customer’s option and expense, Customer may take sole control
of the defense and any settlement of such claim. Customer WILL reimburse and hold harmless Mentor Graphics for any
LIABILITY, damages, settlement amounts, costs and expenses, including reasonable attorney’s fees, incurred by or awarded
against Mentor Graphics or its licensors in connection with such claims.
9.3. The provisions of this Section 9 shall survive any expiration or termination of this Agreement.
10. INFRINGEMENT.
10.1. Mentor Graphics will defend or settle, at its option and expense, any action brought against Customer in the United States,
Canada, Japan, or member state of the European Union which alleges that any standard, generally supported Product acquired
by Customer hereunder infringes a patent or copyright or misappropriates a trade secret in such jurisdiction. Mentor Graphics
will pay costs and damages finally awarded against Customer that are attributable to such action. Customer understands and
agrees that as conditions to Mentor Graphics’ obligations under this section Customer must: (a) notify Mentor Graphics
promptly in writing of the action; (b) provide Mentor Graphics all reasonable information and assistance to settle or defend the
action; and (c) grant Mentor Graphics sole authority and control of the defense or settlement of the action.
10.2. If a claim is made under Subsection 10.1 Mentor Graphics may, at its option and expense: (a) replace or modify the Product so
that it becomes noninfringing; (b) procure for Customer the right to continue using the Product; or (c) require the return of the
Product and refund to Customer any purchase price or license fee paid, less a reasonable allowance for use.
10.3. Mentor Graphics has no liability to Customer if the action is based upon: (a) the combination of Software or hardware with any
product not furnished by Mentor Graphics; (b) the modification of the Product other than by Mentor Graphics; (c) the use of
other than a current unaltered release of Software; (d) the use of the Product as part of an infringing process; (e) a product that
Customer makes, uses, or sells; (f) any Beta Code or Product provided at no charge; (g) any software provided by Mentor
Graphics’ licensors who do not provide such indemnification to Mentor Graphics’ customers; (h) OSS, except to the extent that
the infringement is directly caused by Mentor Graphics’ modifications to such OSS; or (i) infringement by Customer that is
deemed willful. In the case of (i), Customer shall reimburse Mentor Graphics for its reasonable attorney fees and other costs
related to the action.
10.4. THIS SECTION 10 IS SUBJECT TO SECTION 8 ABOVE AND STATES THE ENTIRE LIABILITY OF MENTOR
GRAPHICS AND ITS LICENSORS, AND CUSTOMER’S SOLE AND EXCLUSIVE REMEDY, FOR DEFENSE,
SETTLEMENT AND DAMAGES, WITH RESPECT TO ANY ALLEGED PATENT OR COPYRIGHT INFRINGEMENT
OR TRADE SECRET MISAPPROPRIATION BY ANY PRODUCT PROVIDED UNDER THIS AGREEMENT.
11. TERMINATION AND EFFECT OF TERMINATION.
11.1. If a Software license was provided for limited term use, such license will automatically terminate at the end of the authorized
term. Mentor Graphics may terminate this Agreement and/or any license granted under this Agreement immediately upon
written notice if Customer: (a) exceeds the scope of the license or otherwise fails to comply with the licensing or confidentiality
provisions of this Agreement, or (b) becomes insolvent, files a bankruptcy petition, institutes proceedings for liquidation or
winding up or enters into an agreement to assign its assets for the benefit of creditors. For any other material breach of any
provision of this Agreement, Mentor Graphics may terminate this Agreement and/or any license granted under this Agreement
upon 30 days written notice if Customer fails to cure the breach within the 30 day notice period. Termination of this Agreement
or any license granted hereunder will not affect Customer’s obligation to pay for Products shipped or licenses granted prior to
the termination, which amounts shall be payable immediately upon the date of termination.
11.2. Upon termination of this Agreement, the rights and obligations of the parties shall cease except as expressly set forth in this
Agreement. Upon termination of this Agreement and/or any license granted under this Agreement, Customer shall ensure that
all use of the affected Products ceases, and shall return hardware and either return to Mentor Graphics or destroy Software in
Customer’s possession, including all copies and documentation, and certify in writing to Mentor Graphics within ten business
days of the termination date that Customer no longer possesses any of the affected Products or copies of Software in any form.
12. EXPORT. The Products provided hereunder are subject to regulation by local laws and European Union (“E.U.”) and United States
(“U.S.”) government agencies, which prohibit export, re-export or diversion of certain products, information about the products, and
direct or indirect products thereof, to certain countries and certain persons. Customer agrees that it will not export or re-export Products
in any manner without first obtaining all necessary approval from appropriate local, E.U. and U.S. government agencies. If Customer
wishes to disclose any information to Mentor Graphics that is subject to any E.U., U.S. or other applicable export restrictions, including
without limitation the U.S. International Traffic in Arms Regulations (ITAR) or special controls under the Export Administration
Regulations (EAR), Customer will notify Mentor Graphics personnel, in advance of each instance of disclosure, that such information
is subject to such export restrictions.
13. U.S. GOVERNMENT LICENSE RIGHTS. Software was developed entirely at private expense. The parties agree that all Software is
commercial computer software within the meaning of the applicable acquisition regulations. Accordingly, pursuant to U.S. FAR 48
CFR 12.212 and DFAR 48 CFR 227.7202, use, duplication and disclosure of the Software by or for the U.S. government or a U.S.
government subcontractor is subject solely to the terms and conditions set forth in this Agreement, which shall supersede any
conflicting terms or conditions in any government order document, except for provisions which are contrary to applicable mandatory
federal laws.
14. THIRD PARTY BENEFICIARY. Mentor Graphics Corporation, Mentor Graphics (Ireland) Limited, Microsoft Corporation and
other licensors may be third party beneficiaries of this Agreement with the right to enforce the obligations set forth herein.
15. REVIEW OF LICENSE USAGE. Customer will monitor the access to and use of Software. With prior written notice and during
Customer’s normal business hours, Mentor Graphics may engage an internationally recognized accounting firm to review Customer’s
software monitoring system and records deemed relevant by the internationally recognized accounting firm to confirm Customer’s
compliance with the terms of this Agreement or U.S. or other local export laws. Such review may include FlexNet (or successor
product) report log files that Customer shall capture and provide at Mentor Graphics’ request. Customer shall make records available in
electronic format and shall fully cooperate with data gathering to support the license review. Mentor Graphics shall bear the expense of
any such review unless a material non-compliance is revealed. Mentor Graphics shall treat as confidential information all information
gained as a result of any request or review and shall only use or disclose such information as required by law or to enforce its rights
under this Agreement. The provisions of this Section 15 shall survive the termination of this Agreement.
16. CONTROLLING LAW, JURISDICTION AND DISPUTE RESOLUTION. The owners of certain Mentor Graphics intellectual
property licensed under this Agreement are located in Ireland and the U.S. To promote consistency around the world, disputes shall be
resolved as follows: excluding conflict of laws rules, this Agreement shall be governed by and construed under the laws of the State of
Oregon, U.S., if Customer is located in North or South America, and the laws of Ireland if Customer is located outside of North or
South America or Japan, and the laws of Japan if Customer is located in Japan. All disputes arising out of or in relation to this
Agreement shall be submitted to the exclusive jurisdiction of the courts of Portland, Oregon when the laws of Oregon apply, or Dublin,
Ireland when the laws of Ireland apply, or the Tokyo District Court when the laws of Japan apply. Notwithstanding the foregoing, all
disputes in Asia (excluding Japan) arising out of or in relation to this Agreement shall be resolved by arbitration in Singapore before a
single arbitrator to be appointed by the chairman of the Singapore International Arbitration Centre (“SIAC”) to be conducted in the
English language, in accordance with the Arbitration Rules of the SIAC in effect at the time of the dispute, which rules are deemed to be
incorporated by reference in this section. Nothing in this section shall restrict Mentor Graphics’ right to bring an action (including for
example a motion for injunctive relief) against Customer in the jurisdiction where Customer’s place of business is located. The United
Nations Convention on Contracts for the International Sale of Goods does not apply to this Agreement.
17. SEVERABILITY. If any provision of this Agreement is held by a court of competent jurisdiction to be void, invalid, unenforceable or
illegal, such provision shall be severed from this Agreement and the remaining provisions will remain in full force and effect.
18. MISCELLANEOUS. This Agreement contains the parties’ entire understanding relating to its subject matter and supersedes all prior
or contemporaneous agreements. Any translation of this Agreement is provided to comply with local legal requirements only. In the
event of a dispute between the English and any non-English versions, the English version of this Agreement shall govern to the extent
not prohibited by local law in the applicable jurisdiction. This Agreement may only be modified in writing, signed by an authorized
representative of each party. Waiver of terms or excuse of breach must be in writing and shall not constitute subsequent consent, waiver
or excuse.
Rev. 151102, Part No. 265968

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Tessent® Glossary

Software Version 2016.3

© 2009-2016 Mentor Graphics Corporation

Mentor Graphics Corporation

Send Feedback on Documentation: supportnet.mentor.com/doc_feedback_form

Application Specific Integrated Circuit (ASIC)

Automated Test Equipment (ATE)

Automatic Test Pattern Generator (ATPG)

Tessent® Glossary, v2016.3 3

Boundary Scan Design Language (BSDL)

Built-In-Repair Analysis (BIRA)

4 Tessent® Glossary, v2016.3

Built-In Self-Repair (BISR)

Tessent® Glossary, v2016.3 5

Clock Domain Base (CDB)

6 Tessent® Glossary, v2016.3

Comma Separated Values (CSV)

Common Power Format (CPF)

Tessent® Glossary, v2016.3 7

Current EDT Block

Defects Per Million (DPM)

Defective Parts Per Million (DPPM)

8 Tessent® Glossary, v2016.3

Distribution or Distributed Processing

Embedded Boundary Scan

Tessent® Glossary, v2016.3 9

Embedded Logic Test

ELT Core Module

10 Tessent® Glossary, v2016.3

Faulty Machine Simulation

First Compactor Stage

Tessent® Glossary, v2016.3 11

Functional ECO (Functional Engineering Change Order)

Good Machine Simulation

Hierarchical Integrated Flow

12 Tessent® Glossary, v2016.3

Hold Time Failure

Tessent® Glossary, v2016.3 13

Instrument Connectivity Language (ICL)

Internal Scan Chain

Internal JTAG (IJTAG)

Joint Test Action Group (JTAG)

14 Tessent® Glossary, v2016.3

Level Sensitive Scan Design (LSSD)

Tessent® Glossary, v2016.3 15

Linear Feedback Shift Register (LFSR)

Logic Built-In Self-Test (LBIST)

Low Pin Count Test (LPCT)

16 Tessent® Glossary, v2016.3

Memory BIST controller

Tessent® Glossary, v2016.3 17

Multiple Input Signature Register (MISR)

Procedural Description Language (PDL)

PDL Command Retargeter

18 Tessent® Glossary, v2016.3

Pipeline Stages (Channel)

Pipeline Stages (Compactor)

PLL BIST Controller