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Recommended For New Designs Refer T O Mp2333: High-Efficiency, 3A, 16V, 500Khz Synchronous, Step-Down Converter
Recommended For New Designs Refer T O Mp2333: High-Efficiency, 3A, 16V, 500Khz Synchronous, Step-Down Converter
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DESCRIPTION FEATURES
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The MP1475 is a high-frequency, synchronous, • Wide 4.5V-to-16V Operating Input Range
rectified, step-down, switch-mode converter • 80mΩ/30mΩ Low RDS(ON) Internal Power
with built-in power MOSFETs. It offers a very MOSFETs
compact solution to achieve a 3A continuous • High-Efficiency Synchronous Mode
output current with excellent load and line
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Operation
regulation over a wide input supply range. The • Fixed 500kHz Switching Frequency
MP1475 has synchronous mode operation for • Synchronizes from a 200kHz-to-2MHz
higher efficiency over the output current load External Clock
range. •
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Power-Save Mode at light load
Current-mode operation provides fast transient • Internal Soft-Start
•
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response and eases loop stabilization. Power Good Indicator
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Full protection features include over-current • OCP Protection and Hiccup
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• Thermal Shutdown
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protection and thermal shut down.
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Output Adjustable from 0.8V
The MP1475 requires a minimal number of • Available in an 8-pin TSOT-23 Package
readily-available standard external components,
and is available in a space-saving 8-pin APPLICATIONS
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All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Quality Assurance. “MPS” and “The
Future of Analog IC Technology” are Registered Trademarks of Monolithic
Power Systems, Inc.
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TYPICAL APPLICATION
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ORDERING INFORMATION
Part Number* Package Top Marking
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MP1475DJ TSOT-23-8 ADP
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* For Tape & Reel, add suffix –Z (e.g. MP1475DJ–Z);
For RoHS Compliant Packaging, add suffix –LF (e.g. MP1475DJ–LF–Z)
PACKAGE REFERENCE
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TOP VIEW
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PG 1 8 FB
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IN 2 7 VCC
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SW 3 6 EN/SYNC
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GND 4 5 BST
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VSW ....................................................................
Notes:
-0.3V (-5V for <10ns) to 17V (19V for <10ns) 1) Exceeding these ratings may damage the device.
VBST ...................................................... VSW+6V 2) About the details of EN pin’s ABS MAX rating, please refer to
All Other Pins................................ -0.3V to 6V (2) Page 9, Enable/SYNC control section.
(3) 3) The maximum allowable power dissipation is a function of the
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Continuous Power Dissipation (TA = +25°C) maximum junction temperature TJ (MAX), the junction-to-
..........................................................1.25W ambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
Junction Temperature.............................. 150°C any ambient temperature is calculated by PD (MAX) = (TJ
T
Lead Temperature ................................... 260°C (MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation will cause excessive die temperature, and the
Storage Temperature................. -65°C to 150°C regulator will go into thermal shutdown. Internal thermal
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operating conditions.
Output Voltage VOUT............... 0.8V to VIN x DMAX 5) Measured on JESD51-7, 4-layer PCB.
Operating Junction Temp. (TJ). -40°C to +125°C
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Parameter Symbol Condition Min Typ Max Units
Supply Current (Shutdown) IIN VEN = 0V 7 μA
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Supply Current (Quiescent) Iq VEN = 2V, VFB = 1V 0.6 1 mA
HS Switch-On Resistance HSRDS-ON VBST-SW =5V 80 mΩ
LS Switch-On Resistance LSRDS-ON VCC =5V 30 mΩ
Switch Leakage SW LKG VEN = 0V, VSW =12V 1 μA
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(6)
Current Limit ILIMIT Under 40% Duty Cycle 4.2 5 A
Oscillator Frequency fSW VFB=0.75V 430 500 570 kHz
Fold-Back Frequency fFB VFB<400mV 0.25 fSW
Maximum Duty Cycle DMAX VFB=700mV 90 95 %
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(6)
Minimum On Time τON_MIN 40 ns
Sync Frequency Range fSYNC 0.2 2 MHz
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Feedback Voltage VFB mV
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(7)
-40°C<TA<85°C 787 807 827
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Feedback Current IFB VFB=820mV 10 50 nA
EN Rising Threshold VEN_RISING 1.2 1.4 1.6 V
EN Falling Threshold VEN_FALLING 1.1 1.25 1.4 V
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VEN=2V 2 μA
EN Input Current IEN
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VEN=0 0 μA
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Threshold-Hysteresis
VCC Regulator VCC 5 V
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TYPICAL CHARACTERISTICS
VIN = 12V, VOUT = 3.3V, L=4.7μH, TA = 25°C, unless otherwise noted.
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VIN = 12V, VOUT = 3.3V, L=4.7μH, TA = 25°C, unless otherwise noted.
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VIN = 12V, VOUT = 3.3V, L=5.5μH, TA = 25°C, unless otherwise noted.
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PIN FUNCTIONS
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Package
Name Description
Pin #
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Power Good Output. The output of this pin is an open drain that goes high if the output
1 PG voltage exceeds 90% of the normal voltage. There is a 0.4ms delay between when
FB≥90% to when the PG pin goes high.
Supply Voltage. The IN pin supplies power for internal MOSFET and regulator. The
MP1475 operates from a +4.5V to +16V input rail. Requires a low-ESR, and low-
2 IN
inductance capacitor (C1) to decouple the input rail. Place the input capacitor very close to
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this pin and connect it with wide PCB traces and multiple vias to make the connection.
Switch Output. Connect this pin to the inductor and bootstrap capacitor. This pin is driven
up to VIN by the high-side switch during the PWM duty cycle ON-time. The inductor current
3 SW drives the SW pin negative during the OFF-time. The ON-resistance of the low-side switch
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and the internal body diode fixes the negative voltage. Connect using wide PCB traces
and multiple vias.
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System Ground. Reference ground of the regulated output voltage. PCB layout requires
4 GND
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extra care. For best results connect to GND with copper and vias.
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Bootstrap. Requires a capacitor connected between SW and BST pins is required to form
5 BST
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a floating supply across the high-side switch driver.
Enable. EN=high to enable the MP1475. Apply an external clock to change the switching
6 EN/SYNC
frequency. For automatic start-up, connect EN pin to VIN with an 100kΩ resistor.
Internal 5V LDO output. Powers the driver and control circuits are powered from this
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7 VCC
voltage. Decouple with a 0.1μF-0.22μF capacitor. Do not use a capacitor ≥0.22μF.
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Feedback. Connect to the tap of an external resistor divider from the output to GND to set
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the output voltage. The frequency fold-back comparator lowers the oscillator frequency
8 FB when the FB voltage is below 400mV to prevent current limit runaway during a short-circuit
fault condition. Place the resistor divider as close to the FB pin as possible. Avoid placing
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IN
+
-
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VCC RSEN
VCC Currrent Sense
Regulator
Amplifer
Bootstrap
Regulator BST
Oscillator HS
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Driver
+
SW
- Comparator
1pF On Time Control VCC
Current Limit
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Logic Control
50pF
Comparator
EN/SYNC Reference 400k
LS
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6.5V 1MEG
Driver
+
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+
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FB -
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- Error Amplifier GND
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PG + Ref
OPERATION
The MP1475 is a high-frequency, synchronous, The EN pin is clamped internally using a 6.5V
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rectified, step-down, switch-mode converter series-Zener-diode as shown in Figure 2.
with built-in power MOSFETs. It offers a very Connecting the EN input pin through a pullup
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compact solution that achieves a 3A continuous resistor to the voltage on the IN pin limits the
output current with excellent load and line EN input current to less than 100µA.
regulation over a wide input supply range. For example, with 12V connected to IN, RPULLUP
The MP1475 operates in a fixed-frequency, ≥ (12V – 6.5V) ÷ 100µA = 55kΩ.
peak-current–control mode to regulate the Connecting the EN pin is directly to a voltage
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output voltage. An internal clock initiates a source without any pullup resistor requires
PWM cycle. The integrated high-side power limiting the amplitude of the voltage source to
MOSFET turns on and remains on until the ≤6V to prevent damage to the Zener diode.
current reaches the value set by the COMP
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voltage. When the power switch is off, it
remains off until the next clock cycle starts. If,
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within 95% of one PWM period, the current in
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the power MOSFET does not reach the value
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set by the COMP value, the power MOSFET is
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forced to turn off. Figure 2: 6.5V Zener Diode Connection
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Internal Regulator
A 5V internal regulator powers most of the For external clock synchronization, connect a
internal circuitries. This regulator takes the VIN clock with a frequency range between 200kHz
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input and operates in the full VIN range. When and 2MHz 2ms after the output voltage is set:
VIN exceeds 5.0V, the output of the regulator is The internal clock rising edge will synchronize
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in full regulation. When VIN is less than 5.0V, with the external clock rising edge. Select an
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the output decreases, and the part requires a external clock signal with a pulse width less
0.1µF ceramic decoupling capacitor. than 1.7μs.
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between the two. This output current then MP1475 will power up. It shuts off when the
charges or discharges the internal VCC voltage drops below the UVLO falling
compensation network to form the COMP threshold voltage. This is non-latch protection.
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voltage, which controls the power MOSFET The MP1475 is disabled when the input voltage
current. The optimized internal compensation falls below 3.25V. If an application requires a
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network minimizes the external component higher under-voltage lockout (UVLO) threshold,
counts and simplifies the control loop design. use the EN pin as shown in Figure 3 to adjust
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Thermal Shutdown
Thermal shutdown prevents the chip from
operating at exceedingly high temperatures.
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When the silicon die reaches temperatures that
exceed 150°C, it shuts down the whole chip.
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When the temperature drops below its lower
threshold, typically 130°C, the chip is enabled
again.
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Internal Soft-Start floating power MOSFET driver. This floating
The soft-start prevents the converter output driver has its own UVLO protection. This
voltage from overshooting during startup. When UVLO’s rising threshold is 2.2V with a
the chip starts, the internal circuitry generates a hysteresis of 150mV. The bootstrap capacitor
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soft-start voltage (VSS) that ramps up from 0V to voltage is regulated internally by VIN through D1,
1.2V. When VSS is less than VREF, the error M1, R3, C4, L1 and C2 (Figure 4). If (VIN-VSW)
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amplifier uses VSS as the reference. When VSS exceeds 5V, U1 will regulate M1 to maintain a
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exceeds VREF, the error amplifier uses VREF as 5V BST voltage across C4. A 20Ω resistor
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the reference. The SS time is internally set to placed between SW and BST cap. is strongly
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1.2ms. recommended to reduce SW spike voltage.
Power Good Indicator D1
VIN
MP1475 has an open drain pin as the power-
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5V U1 R3
switches goes high with 0.4ms delay time. If VFB C4
goes below 85% of VREF, an internal MOSFET
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VOUT
pulls the PG pin down to ground. SW L1 C2
The internal circuit keeps the PG low once the
input supply exceeds 1.2V.
Figure 4: Internal Bootstrap Charging Circuit
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APPLICATION INFORMATION
Setting the Output Voltage Where ΔIL is the inductor ripple current.
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The external resistor divider sets the output
Choose the inductor ripple current to be
voltage (see Typical Application on page 1). The
approximately 30% of the maximum load current.
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feedback resistor R1 also sets the feedback loop
The maximum inductor peak current is:
bandwidth with the internal compensation
capacitor (see Typical Application on page 1). ΔIL
Choose R1 around 40kΩ. R2 is then given by: IL(MAX ) = ILOAD +
2
R1 Use a larger inductor for improved efficiency
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R2 = under light-load conditions—below 100mA.
VOUT
−1 Selecting the Input Capacitor
0.807V The input current to the step-down converter is
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The T-type network—as shown in Figure 5—is discontinuous, therefore requires a capacitor is to
highly recommended when VOUT is low. supply the AC current to the step-down converter
while maintaining the DC input voltage. Use low
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Cf
ESR capacitors for the best performance. Use
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ceramic capacitors with X5R or X7R dielectrics
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8 Rt R1
FB for best results because of their low ESR and
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VOUT
small temperature coefficients. For most
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applications, use a 22µF capacitor.
Since C1 absorbs the input switching current, it
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3.3 40.2 13 16 15 4.7 an RMS current rating greater than half of the
maximum load current.
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Use a1µH-to-10µH inductor with a DC current capacitors, add a small, high quality ceramic
rating of at least 25% percent higher than the capacitor (e.g. 0.1μF) placed as close to the IC
maximum load current for most applications. For as possible. When using ceramic capacitors,
highest efficiency, use an inductor with a DC make sure that they have enough capacitance to
resistance less than 15mΩ. For most designs, provide sufficient charge to prevent excessive
the inductance value can be derived from the voltage ripple at input. The input voltage ripple
following equation. caused by capacitance can be estimated as:
VOUT × (VIN − VOUT ) ILOAD V ⎛ V ⎞
L1 = ΔVIN = × OUT × ⎜ 1 − OUT ⎟
VIN × ΔIL × fOSC fS × C1 VIN ⎝ VIN ⎠
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ESR electrolytic capacitors. For best results, conditions:
use low ESR capacitors to keep the output
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z VOUT is 5V or 3.3V; and
voltage ripple low. The output voltage ripple can VOUT
be estimated as: z Duty cycle is high: D= >65%
VIN
VOUT ⎛ VOUT ⎞ ⎛ 1 ⎞ In these cases, add an external BST diode from
ΔVOUT = × ⎜1 − ⎟ × ⎜ RESR + ⎟
fS × L1 ⎝ VIN ⎠ ⎝ 8 × fS × C2 ⎠ the VCC pin to BST pin, as shown in Figure 6.
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Where L1 is the inductor value and RESR is the External BST Diode
IN4148
equivalent series resistance (ESR) value of the BST VCC
output capacitor. CBST
MP1475
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For ceramic capacitors, the capacitance
dominates the impedance at the switching SW
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frequency, and the capacitance causes the COUT
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majority of the output voltage ripple. For
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simplification, the output voltage ripple can be
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estimated as:
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Figure 6: Optional External Bootstrap Diode to
Enhance Efficiency
VOUT ⎛ V ⎞
ΔVOUT = × ⎜ 1 − OUT ⎟ The recommended external BST diode is
8 × fS × L1 × C2 ⎝
2
VIN ⎠
IN4148, and the BST capacitor value is 0.1µF
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VOUT ⎛ V ⎞
ΔVOUT = × ⎜ 1 − OUT ⎟ × RESR
fS × L1 ⎝ VIN ⎠
The characteristics of the output capacitor also
affect the stability of the regulation system. The
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operation especially for VCC capacitor and
input capacitor placement. For best results, VCC
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follow these guidelines: EN/SYNC
BST
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GND pin as close as possible. Make the
trace length of VCC pin-VCC capacitor
anode-VCC capacitor cathode-chip GND
pin as short as possible.
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GND
3. Place the ceramic input capacitor close to
IN and GND pins. Keep the connection of
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input capacitor and IN pin as short and
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wide as possible.
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Design Example
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4. Route SW, BST away from sensitive
analog areas such as FB. It’s not Below is a design example following the
recommended to route SW, BST trace application guidelines for the specifications:
under chip’s bottom side. Table 2: Design Example
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R6
R3
T
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R5
1
R4
C1
L1
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C1A
Vin
C2 Vout
C2A
GND
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Figure 7: 12VIN, 5V/3A Output
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Figure 10: 12VIN, 1.8V/3A Output
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PACKAGE INFORMATION
TSOT23-8
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See note 7
EXAMPLE
TOP MARK
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PIN 1 ID
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RECOMMENDED LAND PATTERN
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TOP VIEW
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SEE DETAIL''A''
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NOTE:
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FLASH OR PROTRUSION.
4) LEAD COPLANARITY(BOTTOM OF LEADS AFTER
FORMING) SHALL BE 0.10 MILLIMETERS MAX.
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NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.