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    Yopi
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    practicas VHD

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pdf or txt
    10 views19 pages

    Tecnologico Nacional Mexicano: Campus: Tuxtla Gutierres Chiapas

    Uploaded by

    Yopi

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pdf or txt
    of 19

    TECNOLOGICO NACIONAL

    MEXICANO

    CAMPUS: TUXTLA GUTIERRES CHIAPAS

    ALUMNO: PEREZ MORALES FREDY ANTONIO


    GRUPO: A5B
    INGENIERIA ELECTRONICA

    MATERIA: diseño de vhdl

    FECHA Y LUGAR: IXTAPA, CHIAPAS A 20 DE


    NOVIEMBRE DEL 2021
    PRACTICA 1
    |||||||
    _________________
    -| |-
    -| |-
    -| |-
    -| CYPRESS |-
    -| |-
    -| |- Warp VHDL Synthesis Compiler: Version 6.1 IR 28
    -| |- Copyright (C) 1991-2001 Cypress Semiconductor
    |_______________|
    |||||||

    ======================================================================
    Compiling: practica1.vhd
    Options: -yu -e10 -w100 -o2 -ygs -fP -v10 -dc16v8 -ppalce16v8-7pc -b practica1.vhd -u
    practica1.hie
    ======================================================================
    PLD Compiler Software: PLA2JED.EXE 31/03/2000 [v4.02 ] 6.1 IR 28

    DESIGN EQUATIONS (12:18:44)


    c=
    a(0) * a(1) * b(0) * b(1)
    + /a(0) * a(1) * /b(0) * b(1)
    + a(0) * /a(1) * b(0) * /b(1)
    + /a(0) * /a(1) * /b(0) * /b(1)

    Completed Successfully
    ----------------------------------------------------------------------------
    PLD Compiler Software: PLA2JED.EXE 31/03/2000 [v4.02 ] 6.1 IR 28

    PINOUT INFORMATION (12:18:44)

    Messages:
    Information: Checking for duplicate NODE logic.
    None.

    C16V8A
    __________________________________________
    b(1) =| 1| |20|* not used
    b(0) =| 2| |19|= c
    a(1) =| 3| |18|* not used
    a(0) =| 4| |17|* not used
    not used *| 5| |16|* not used
    not used *| 6| |15|* not used
    not used *| 7| |14|* not used
    not used *| 8| |13|* not used
    not used *| 9| |12|* not used
    not used *|10| |11|* not used
    __________________________________________

    Summary:
    Error Count = 0 Warning Count = 0

    Completed Successfully
    ----------------------------------------------------------------------------
    PLD Compiler Software: PLA2JED.EXE 31/03/2000 [v4.02 ] 6.1 IR 28

    RESOURCE UTILIZATION (12:18:44)

    Information: Macrocell Utilization.

    Description Used Max


    ______________________________________
    | Dedicated Inputs | 4 | 10 |
    | Output Macrocells | 1 | 2 |
    | I/O Macrocells | 0 | 6 |
    ______________________________________
    5 / 18 = 27 %

    Information: Output Logic Product Term Utilization.

    Node# Output Signal Name Used Max


    ________________________________________
    | 12 | Unused | 0 | 7 |
    | 13 | Unused | 0 | 7 |
    | 14 | Unused | 0 | 7 |
    | 15 | Unused | 0 | 7 |
    | 16 | Unused | 0 | 7 |
    | 17 | Unused | 0 | 7 |
    | 18 | Unused | 0 | 7 |
    | 19 | c | 4 | 7 |
    ________________________________________
    4 / 56 = 7 %

    Completed Successfully
    PRACTICA 2
    |||||||
    _________________
    -| |-
    -| |-
    -| |-
    -| CYPRESS |-
    -| |-
    -| |- Warp VHDL Synthesis Compiler: Version 6.1 IR 28
    -| |- Copyright (C) 1991-2001 Cypress Semiconductor
    |_______________|
    |||||||

    ======================================================================
    Compiling: practica2.vhd
    Options: -m -yu -e10 -w100 -o2 -ygs -fP -v10 -dc16v8 -ppalce16v8-7pc -b practica2.vhd -u
    practica2.hie
    ======================================================================

    ----------------------------------------------------------------------------
    PLD Compiler Software: PLA2JED.EXE 31/03/2000 [v4.02 ] 6.1 IR 28

    DESIGN EQUATIONS (12:45:13)

    /fl =
    /a * /b

    Completed Successfully
    ----------------------------------------------------------------------------
    PLD Compiler Software: PLA2JED.EXE 31/03/2000 [v4.02 ] 6.1 IR 28

    PINOUT INFORMATION (12:45:13)

    Messages:
    Information: Checking for duplicate NODE logic.
    None.

    C16V8A
    __________________________________________
    b =| 1| |20|* not used
    a =| 2| |19|= fl
    not used *| 3| |18|* not used
    not used *| 4| |17|* not used
    not used *| 5| |16|* not used
    not used *| 6| |15|* not used
    not used *| 7| |14|* not used
    not used *| 8| |13|* not used
    not used *| 9| |12|* not used
    not used *|10| |11|* not used
    __________________________________________

    Summary:
    Error Count = 0 Warning Count = 0

    Completed Successfully
    ----------------------------------------------------------------------------
    PLD Compiler Software: PLA2JED.EXE 31/03/2000 [v4.02 ] 6.1 IR 28

    RESOURCE UTILIZATION (12:45:13)

    Information: Macrocell Utilization.

    Description Used Max


    ______________________________________
    | Dedicated Inputs | 2 | 10 |
    | Output Macrocells | 1 | 2 |
    | I/O Macrocells | 0 | 6 |
    ______________________________________
    3 / 18 = 16 %

    Information: Output Logic Product Term Utilization.

    Node# Output Signal Name Used Max


    ________________________________________
    | 12 | Unused | 0 | 7 |
    | 13 | Unused | 0 | 7 |
    | 14 | Unused | 0 | 7 |
    | 15 | Unused | 0 | 7 |
    | 16 | Unused | 0 | 7 |
    | 17 | Unused | 0 | 7 |
    | 18 | Unused | 0 | 7 |
    | 19 | fl | 1 | 7 |
    ________________________________________
    1 / 56 = 1 %

    Completed Successfully
    PRACTICA 3
    |||||||
    _________________
    -| |-
    -| |-
    -| |-
    -| CYPRESS |-
    -| |-
    -| |- Warp VHDL Synthesis Compiler: Version 6.1 IR 28
    -| |- Copyright (C) 1991-2001 Cypress Semiconductor
    |_______________|
    |||||||

    ======================================================================
    Compiling: practica3.vhd
    Options: -m -yu -e10 -w100 -o2 -ygs -fP -v10 -dc16v8 -ppalce16v8-7pc -b practica3.vhd -u
    practica3.hie
    ======================================================================
    PLD Compiler Software: PLA2JED.EXE 31/03/2000 [v4.02 ] 6.1 IR 28

    DESIGN EQUATIONS (12:58:28)

    c=
    a(0) * a(1) * b(0) * b(1)
    + /a(0) * a(1) * /b(0) * b(1)
    + a(0) * /a(1) * b(0) * /b(1)
    + /a(0) * /a(1) * /b(0) * /b(1)

    Completed Successfully
    ----------------------------------------------------------------------------
    PLD Compiler Software: PLA2JED.EXE 31/03/2000 [v4.02 ] 6.1 IR 28

    PINOUT INFORMATION (12:58:28)

    Messages:
    Information: Checking for duplicate NODE logic.
    None.

    C16V8A
    __________________________________________
    b(1) =| 1| |20|* not used
    b(0) =| 2| |19|= c
    a(1) =| 3| |18|* not used
    a(0) =| 4| |17|* not used
    not used *| 5| |16|* not used
    not used *| 6| |15|* not used
    not used *| 7| |14|* not used
    not used *| 8| |13|* not used
    not used *| 9| |12|* not used
    not used *|10| |11|* not used
    __________________________________________
    Summary:
    Error Count = 0 Warning Count = 0

    Completed Successfully
    ----------------------------------------------------------------------------
    PLD Compiler Software: PLA2JED.EXE 31/03/2000 [v4.02 ] 6.1 IR 28

    RESOURCE UTILIZATION (12:58:28)

    Information: Macrocell Utilization.

    Description Used Max


    ______________________________________
    | Dedicated Inputs | 4 | 10 |
    | Output Macrocells | 1 | 2 |
    | I/O Macrocells | 0 | 6 |
    ______________________________________
    5 / 18 = 27 %

    Information: Output Logic Product Term Utilization.

    Node# Output Signal Name Used Max


    ________________________________________
    | 12 | Unused | 0 | 7 |
    | 13 | Unused | 0 | 7 |
    | 14 | Unused | 0 | 7 |
    | 15 | Unused | 0 | 7 |
    | 16 | Unused | 0 | 7 |
    | 17 | Unused | 0 | 7 |
    | 18 | Unused | 0 | 7 |
    | 19 | c | 4 | 7 |
    ________________________________________
    4 / 56 = 7 %

    Completed Successfully
    PRACTICA 4
    |||||||
    _________________
    -| |-
    -| |-
    -| |-
    -| CYPRESS |-
    -| |-
    -| |- Warp VHDL Synthesis Compiler: Version 6.1 IR 28
    -| |- Copyright (C) 1991-2001 Cypress Semiconductor
    |_______________|
    |||||||

    ======================================================================
    Compiling: practica4.vhd
    Options: -m -yu -e10 -w100 -o2 -ygs -fP -v10 -dc16v8 -ppalce16v8-7pc -b practica4.vhd -u
    practica4.hie
    ----------------------------------------------------------------------------
    PLD Compiler Software: PLA2JED.EXE 31/03/2000 [v4.02 ] 6.1 IR 28

    DESIGN EQUATIONS (13:18:55)

    f=
    /a * b

    Completed Successfully
    ----------------------------------------------------------------------------
    PLD Compiler Software: PLA2JED.EXE 31/03/2000 [v4.02 ] 6.1 IR 28

    PINOUT INFORMATION (13:18:55)

    Messages:
    Information: Checking for duplicate NODE logic.
    None.

    C16V8A
    __________________________________________
    b =| 1| |20|* not used
    a =| 2| |19|= f
    not used *| 3| |18|* not used
    not used *| 4| |17|* not used
    not used *| 5| |16|* not used
    not used *| 6| |15|* not used
    not used *| 7| |14|* not used
    not used *| 8| |13|* not used
    not used *| 9| |12|* not used
    not used *|10| |11|* not used
    __________________________________________
    Summary:
    Error Count = 0 Warning Count = 0

    Completed Successfully
    ----------------------------------------------------------------------------
    PLD Compiler Software: PLA2JED.EXE 31/03/2000 [v4.02 ] 6.1 IR 28

    RESOURCE UTILIZATION (13:18:55)

    Information: Macrocell Utilization.

    Description Used Max


    ______________________________________
    | Dedicated Inputs | 2 | 10 |
    | Output Macrocells | 1 | 2 |
    | I/O Macrocells | 0 | 6 |
    ______________________________________
    3 / 18 = 16 %

    Information: Output Logic Product Term Utilization.

    Node# Output Signal Name Used Max


    ________________________________________
    | 12 | Unused | 0 | 7 |
    | 13 | Unused | 0 | 7 |
    | 14 | Unused | 0 | 7 |
    | 15 | Unused | 0 | 7 |
    | 16 | Unused | 0 | 7 |
    | 17 | Unused | 0 | 7 |
    | 18 | Unused | 0 | 7 |
    | 19 | f | 1 | 7 |
    ________________________________________
    1 / 56 = 1 %

    Completed Successfully
    ----------------------------------------------------------------------------
    PRACTICA 5
    |||||||
    _________________
    -| |-
    -| |-
    -| |-
    -| CYPRESS |-
    -| |-
    -| |- Warp VHDL Synthesis Compiler: Version 6.1 IR 28
    -| |- Copyright (C) 1991-2001 Cypress Semiconductor
    |_______________|
    |||||||

    ======================================================================
    Compiling: practica4.vhd
    Options: -m -yu -e10 -w100 -o2 -ygs -fP -v10 -dc16v8 -ppalce16v8-7pc -b practica4.vhd -u
    practica4.hie
    ----------------------------------------------------------------------------
    PLD Compiler Software: PLA2JED.EXE 31/03/2000 [v4.02 ] 6.1 IR 28

    DESIGN EQUATIONS (13:18:55)

    f=
    /a * b

    Completed Successfully
    ----------------------------------------------------------------------------
    PLD Compiler Software: PLA2JED.EXE 31/03/2000 [v4.02 ] 6.1 IR 28

    PINOUT INFORMATION (13:18:55)

    Messages:
    Information: Checking for duplicate NODE logic.
    None.

    C16V8A
    __________________________________________
    b =| 1| |20|* not used
    a =| 2| |19|= f
    not used *| 3| |18|* not used
    not used *| 4| |17|* not used
    not used *| 5| |16|* not used
    not used *| 6| |15|* not used
    not used *| 7| |14|* not used
    not used *| 8| |13|* not used
    not used *| 9| |12|* not used
    not used *|10| |11|* not used
    __________________________________________
    Summary:
    Error Count = 0 Warning Count = 0

    Completed Successfully
    ----------------------------------------------------------------------------
    PLD Compiler Software: PLA2JED.EXE 31/03/2000 [v4.02 ] 6.1 IR 28

    RESOURCE UTILIZATION (13:18:55)

    Information: Macrocell Utilization.

    Description Used Max


    ______________________________________
    | Dedicated Inputs | 2 | 10 |
    | Output Macrocells | 1 | 2 |
    | I/O Macrocells | 0 | 6 |
    ______________________________________
    3 / 18 = 16 %

    Information: Output Logic Product Term Utilization.

    Node# Output Signal Name Used Max


    ________________________________________
    | 12 | Unused | 0 | 7 |
    | 13 | Unused | 0 | 7 |
    | 14 | Unused | 0 | 7 |
    | 15 | Unused | 0 | 7 |
    | 16 | Unused | 0 | 7 |
    | 17 | Unused | 0 | 7 |
    | 18 | Unused | 0 | 7 |
    | 19 | f | 1 | 7 |
    ________________________________________
    1 / 56 = 1 %

    Completed Successfully
    PRACTICA 6
    |||||||
    _________________
    -| |-
    -| |-
    -| |-
    -| CYPRESS |-
    -| |-
    -| |- Warp VHDL Synthesis Compiler: Version 6.1 IR 28
    -| |- Copyright (C) 1991-2001 Cypress Semiconductor
    |_______________|
    |||||||

    ======================================================================
    Compiling: practica5.vhd
    Options: -m -yu -e10 -w100 -o2 -ygs -fP -v10 -dc16v8 -ppalce16v8-7pc -b practica5.vhd -u
    practica5.hie
    ----------------------------------------------------------------------------
    PLD Compiler Software: PLA2JED.EXE 31/03/2000 [v4.02 ] 6.1 IR 28

    DESIGN EQUATIONS (14:04:13)

    f=
    b*c
    + /a * /b

    Completed Successfully
    ----------------------------------------------------------------------------
    PLD Compiler Software: PLA2JED.EXE 31/03/2000 [v4.02 ] 6.1 IR 28

    PINOUT INFORMATION (14:04:13)

    Messages:
    Information: Checking for duplicate NODE logic.
    None.

    C16V8A
    __________________________________________
    c =| 1| |20|* not used
    b =| 2| |19|= f
    a =| 3| |18|* not used
    not used *| 4| |17|* not used
    not used *| 5| |16|* not used
    not used *| 6| |15|* not used
    not used *| 7| |14|* not used
    not used *| 8| |13|* not used
    not used *| 9| |12|* not used
    not used *|10| |11|* not used
    __________________________________________

    Summary:
    Error Count = 0 Warning Count = 0

    Completed Successfully
    ----------------------------------------------------------------------------
    PLD Compiler Software: PLA2JED.EXE 31/03/2000 [v4.02 ] 6.1 IR 28

    RESOURCE UTILIZATION (14:04:13)

    Information: Macrocell Utilization.

    Description Used Max


    ______________________________________
    | Dedicated Inputs | 3 | 10 |
    | Output Macrocells | 1 | 2 |
    | I/O Macrocells | 0 | 6 |
    ______________________________________
    4 / 18 = 22 %

    Information: Output Logic Product Term Utilization.

    Node# Output Signal Name Used Max


    ________________________________________
    | 12 | Unused | 0 | 7 |
    | 13 | Unused | 0 | 7 |
    | 14 | Unused | 0 | 7 |
    | 15 | Unused | 0 | 7 |
    | 16 | Unused | 0 | 7 |
    | 17 | Unused | 0 | 7 |
    | 18 | Unused | 0 | 7 |
    | 19 | f | 2 | 7 |
    ________________________________________
    2 / 56 = 3 %

    Completed Successfully

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