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Weighted Random Patterns For BIST Generated in Cel
Weighted Random Patterns For BIST Generated in Cel
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Ondrej Novak
Technical University of Liberec
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Ondrej Novak
Technical University Liberec, Hálkova 6, 461 17 Liberec I, Czech Republic
e-mail: ondrej.novak@vslib.cz
Graph 1: Weight rates of 23 bit LFSR with a primitive characteristic polynomial. The LFSR output was serially fed
to the scan chain of the length 683 bits.
70000
60000
50000
40000
30000
20000
10000
0
0 50 100 150 200 250 300 350 400 450 500 550 600 650
Graph 2: Weight rates of the 683 bit CA which generates code patterns.
20000
15000
10000
5000
0
0 50 10 0 1 50 200 250 3 00 350 400 4 50 500 550 6 00 650
Graph 3. Weight rates of the 683 bit CA which generated non code patterns.
250000
200000
150000
100000
50000
0
0 50 100 150 200 250 300 350 400 450 500 550 600 650
Graph 4. Weight rates of the 683 bit CA which generated non code patterns. The seed was different from that one in
the Graph 3.
D flip-flop with set or reset – 180µm x 106 µm
T flip-flop with set – 170µm x 106 µm
100000
T flip-flop with reset – 190µm x 106 µm
XOR gate – 80µm x 106 µm.
10000 If we compare the solution of T flip-flop CA with
asynchronous set from Fig. 2 with the simple chain formed
1000 by D flip-flops with set or reset we can see that the used
chip area will be similar. If we compare the solution of T
100 flip-flop CA with the D flip flop CA we can see that we
use only about 65 % of silicon for the flip-flops and gates,
we also spare some area because of simpler routing.
10
4. Results Obtained
1
We have chosen ISCAS 85 and ISCAS 89 benchmark
0,3 0,4 0,5 0,6
circuits with a significant number of random pattern
resistant faults. The internal flip-flops were considered to
be CUT inputs. We checked the number of non detected
Graph 5: 17 bit CA. Number of CA sequences (Y faults both for a 32 bit LFSR with a primitive polynomial
axis) with given weight (X axis). and for the CA. The polynomial of the 32 bit LFSR was
randomly chosen from the list of primitive polynomials.
The seed of the CA was chosen in such a way that the
weight rates of randomly chosen code and non code
sequences were estimated. After getting pattern sequences
Test/Shift
with different weight rates the fault coverage of the
0 “promising” test sequences was verified. For every circuit
1 CUT
we have done 8 experiments with different LFSR
sequences and 8 experiments with CA sequences. The best
... ... results are given in Tab. 1.
Seeds T T T T T T cube 32 bit WRP CA
circuit LFSR
Memory size [7]
input part of scan output part of
chain (n bits) scan chain
s 641 54 12 1 7
Fig. 3. s 713 54 11 0 7
Let us suppose that the CUT is designed in accordance s 820 23 9 4 6
with the Scan Design methodology with modified
Boundary Scan cells in such a way that D flip-flops in the s 832 23 17 4 5
scan chain are replaced by T flip-flops. The testing starts s 953 45 10 1 3
after reset and seeding the CA from the memory. At each
clock cycle the CA generates a new pattern, and the CUT s 1238 32 10 13 11
responds are compacted in the output part of the chain.
After performing a given number of test steps the s 5378 214 38 28 27
deterministic test patterns are shifted into the chain and s1196 32 17 18 11
the CUT responses are compacted in the output part of the
chain. We have to keep in mind that the seeds which are s 13207 700 624 196 472
stored in the memory have to be modified for both parts
of testing in such a way that after shifting into the scan s 9234 247 648 193 602
chain the desired test cube would be present at the CUT c 2670 157 304 6 292
inputs.
c 7552 206 324 93 130
3. Hardware overhead
Table 1. Comparison of the numbers of faults which
We have designed the CA in MIETEC 2.4 µm CMOS remain undetected after 10 000 test patterns
technology. In this technology we have the following generated in 32-bit LFSR, by WRP method and by a
sizes of the flip-flops: CA .
In the table we compare the numbers of undetected coverage of the benchmark circuits. The research was in
faults with WRP fault coverage [7].The experiments done part supported by the research grants of the Czech Grant
with the ISCAS benchmark circuits showed that in some Agency GACR 102/98/1003 and of the Ministry of
cases we obtain better fault coverage for CA then for Education, Youth and Sport VS 96006.
LFSR, in some cases we obtain similar results. Because of
the lower hardware overhead the CA solution is
advantageous. If we compare the proposed solution with References:
the weighted random patterns with global weights [7] we
[1] Bardell, P. – McAnney, W. H.- SAVIR, J.: Built-
can see that the CA gives worse results. The hardware
overhead which is necessary for generating test patterns In Test for VLSI. New York: Wiley-Interscience,
with a priori given global weights is much higher than for 1987
the CA solution and thus the CA solution could be used in [2] CHAUDHURI, P.P. et al.: Additive Cellular
the cases in which the size of hardware overhead is Automata Theory and Applications Volume I.
crucial. IEEE Computer Society Press, 1997, 340 pp.
[3] DAEHN, W. – MUCHA, J.: Hardware test pattern
generators for built-in test. Proc. of IEEE
4. Conclusion
ITC,1981, pp. 110-113
A linear cellular automaton which can be used as a
[4] KOENEMANN, B.: LFSR – coded test patterns
TPG for BIST was designed. Its main features are its
for scan designs. Proc. Europ. Test Conf., Munich
simple structure and high fault coverage. The simplicity
, Germany, 1991, pp. 237-242
of the structure is due to the existence of only one
feedback with no XOR. The CA can be implemented in [5] HELLEBRAND, S. - RAJSKI, J.- TARNICK, S.-
the CUT by replacing the D flip flops in the scan chain VENKATARAMAN, S. - COURTOIS, B.: Built-
with the T flip/flops and by adding a feedback from the In Test for Circuits with Scan Based on Reseeding
last to the first flip-flop. The properties of the generated of Multiple-Polynomial Linear Feedback Shift
patterns depend on the seed of the CA. No additional Registers. IEEE Trans. on Comp.,vol. 44, No. 2,
hardware changes have to be done when we want to February 1995, pp. 223-233
change the rate of weights in generated patterns.
[6] Hlawiczka, A.: D or T Flip-Flop Based Linear
We compared the properties of the CA with the Registers. Archives of Control Sciences, vol. 4.,
properties of a 32 bit LFSR which is usually used for XXXVII, 1992, pp. 578-587
pseudorandom test pattern generation.
The CA has the following advantages: [7] KUNZMANN, A. : Efficient Random Testing with
Global Weights. Proc. of IEEE EURO-DAC `96
• no hardware overhead, the whole TPG can be built
by converting the existing scan chain
[8] McCLUSKEY, E.J.: Built-in self-test techniques.
• depending on the seed the CA can generate
IEEE Design & Test of Comput., Vol. 2., April
weighted pseudorandom test sets with different
1985, pp. 21-28
rates of weights
• the fault coverage for ISCAS benchmark circuits [9] WANG, L.T. - McCLUSKEY, E.J.: Condensed linear
is better than it is for an external LFSR feedback shift register (LFSR) testing - A
Disadvantages: pseudoexhaustive test technique. IEEE Trans. on
• all flip-flops have to be set or reset-able, a seed for Comp. Vol. C-35, Apr. 1986, pp. 367-370
the CA has to be calculated in more complex
[10] WUNDERLICH, H. J. : Self Test Using
manner than for the LFSR
Unequiprobable Random Patterns. Proc. IEEE 17
• the patterns are generated in the scan chain and FTCS, Pittsburgh 1987, pp.236-244
thus the CUT responses must not influence the
flip/flops in the input part of the chain during the
test.
The TPG can be advantageously used in mixed mode
testing where we generate a given number of patterns and
after it we exercise the circuit with deterministic test
patterns which are stored in a memory.
Acknowledgment
The author wishes to thank H.-J. Wunderlich and S.
Hellebrand for their help with the estimation of fault