Isolated and Bidirectional two-stage DC/AC
2021 IEEE 12th International Symposium on Power Electronics for Distributed Generation Systems (PEDG) | 978-1-6654-0465-5/21/$31.00 ©2021 IEEE | DOI: 10.1109/PEDG51384.2021.9494273
converter with grid-forming virtual inertia and high
ripple on the DC bus for Single-Phase Grid
applications
Alvaro Zarate José Carlos U. Peña
Universidad Nacional de Ingeniería Universidad Nacional de Ingeniería
Lima, Perú
azarates@uni.pe jugazp@uni.pe
Abstract— The increasing utilization of electronic converters
to interface distributed energy resources (energy storage units and
renewable energies) with the grid, has decreased the inertial
spinning reserves of the power system. In this context, an isolated
and bidirectional two-stage DC-AC converter with grid-forming
virtual inertia capability and film capacitor on the DC-Link is
presented. The proposed converter allows to interface energy
storage units (ESU) with the single-phase grid. The two-stage DC-
AC converter is composed of a dual active bridge series resonant
(DABSR) DC-DC converter cascaded with a single-phase voltage
source inverter (VSI), linked by a film capacitor. In the proposed
control strategy, the DABSR controls the DC-Link voltage
allowing the power decoupling on the DC-side while the VSI is
controlled to emulate a virtual synchronous machine (VSM) when
the ESU are connected to the grid. Therefore, the proposed
converter has the following advantages: (1) high durability with
reduced volume due to film capacitor instead of electrolytic
capacitor on the DC-Bus, (2) high efficiency due to ZVS in the DC-
DC converter and, (3) virtual inertia provided by VSI controlled
as a VSM, increasing inertial energy reserves in the grid. The
converter functionality and control strategy are validated by
simulation of a 3.3kW system.
Keywords—Virtual Inertia, virtual synchronous machine
(VSM), grid forming, DABSR DC-DC converter, two-stage DC/AC
converter, high ripple, high durability, single-phase grid.
I. INTRODUCTION
The frequency is a key factor in electric power systems, and
its stability is strongly determined by the inertial reserves. The
increase of energy sources connected through electronic
converters reduces these inertial reserves. Therefore, there have
been several proposals to provide synthetic inertia by inverters,
called virtual inertia (VI). These methods could be classified in
two types, according to the control strategy of the VSI: the grid
following VI methods and the grid forming VI methods [1]. The
grid following VI methods depend on a PLL with high accuracy
to detect the frequency variations which is a limitation for
implementation [2]. Instead, the grid forming methods allow the
emulation of a synchronous machine by controlling the output
AC voltage [3]. Therefore, these methods are known as Virtual
Synchronous Machines (VSM) or Virtual Synchronous
Generators. In [4], single-phase VSM is introduced, where the
swing equation is embedded in the control strategy of a
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Damián Sal y Rosas
Universidad Nacional de Ingeniería
Lima, Perú Lima, Perú
dsalyrosas@uni.edu.pe
bidirectional inverter. Although, this study does not take into
account the DC-Link voltage control. In [5], a single-phase
inverter with inertia emulation is introduced and the DC-Link is
controlled by a DC-DC stage composed by boost converters.
However, the authors do not address the issue of the low lifetime
DC-Link electrolytic capacitor [6] and the limited gain of boost
converters. Indeed, different solutions have been proposed to
replace the electrolytic capacitor by film capacitor on the DC-
Link to increase the converter lifetime [7]. The typical solution
is to use a film capacitor on the DC-Link allowing a high ripple
[8]. However, most studies found in the literature are focused
on grid following DC-AC converter without VSM. In fact, no
work has proposed a single-phase VSM with high ripple on the
DC-Link.
A grid forming two-stage isolated and bidirectional DC-AC
converter with high ripple on the DC-Link is proposed in [9],
[10]. The authors propose a Dual Active Bridge series-resonant
(DABSR) DC-DC converter linked with a single-phase voltage
source inverter (VSI) by a film capacitor on the DC-Link.
However, the authors do not implement a VSM in the VSI
control strategy.
This paper proposes a control strategy to implement a single-
phase VSM in a two-stage isolated and bidirectional DC-AC
converter with high voltage ripple on the DC-Link. The
proposed control strategy is implemented in the same two-stage
DC-AC converter as proposed in [9], [10]. Therefore, the
proposed control strategy has the following advantages: (1) the
time-variant single-phase power is decoupled by the DC-DC
DABSR converter handling high voltage ripple on the DC-Link,
allowing to replace electrolytic capacitors by film capacitors, (2)
a single-phase grid forming VSM is implemented in the VSI
control strategy.
An overview of the proposed converter and control strategy
is presented in the following section. The control methods for
DC-DC and single-phase DC-AC converters are exposed in
Section III. Computational simulation results for a 3.3kW
system are presented in Section IV.
II. CONVERTER CONFIGURATION
The two-stage DC-AC converter scheme and the proposed
control strategy are shown in Fig. 1. From right to left it is shown

+& computed by (11)
+ '-
/ BC*6
1∶*
2 2&:
Power
%=
Source
(ESU)
' ;< '&;<
5 2-
5 computed by (9)
/&0
Fig. 1. Power circuit structure and DC-DC control.
the energy storage unit (ESU), the DABSR DC-DC converter,
the DC-Link film capacitor, the grid forming VSI, the LC filter
and the grid with its impedance.
The ESU could be super-capacitor or battery banks, or any
distributed energy source capable of release or absorb inertial
energy when a frequency event occurs, the choice of an specific
ESU depends on dynamics of power fluctuation that will be
covered, as shown in [5].
The power decoupling and the DC-Link average voltage
control is performed by the DABSR converter. Therefore, in a
frequency event, the DABSR manages the release or absorption
of power from the ESU according to the current required in the
DC-Link, in order to stabilize the VSM frequency to its nominal
value.
The incoming or outgoing power on the DC bus is set by the
VSM through the required DC current, where the synchronous
machine dynamics are emulated implementing the swing
equation in a functional block of the control system. Droop
control is also implemented for active and reactive power
control blocks, and a virtual stator impedance block to ensure
stable operation in case of direct parallel operation of multiple
VSM units [4].
The output LC filter to interface with the grid, is designed to
filter the high frequency ripple generated by the SPWM
modulation and to lead with the reactive power, reducing
conduction losses in the VSI switches [11].
The VSM control was designed in per unit (p.u.) quantities,
while absolutes quantities are utilized for DC-DC control
design. The base power for VSM design is 3.3 KVA, while
nominal active power for DABSR converter design is 3.3 KW.
III. CONTROLLERS DESIGN
This section discusses the design of the different control
schemes.
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2&:
>? , @=? >A , @A
%&
% %&
,
'- '&
.
6789 % , %& , '&
3 4
Virtual
Notch Inertia
Filter
1/
A. VSM Control Design
This control strategy has three important parts: The nested
voltage and current control loops, the power control blocks and
the synchronization control loop.
1) Nested Voltage and Current control loops
The main structure of these control loops is explained in [4].
The control model for that system has been elaborated, and it is
shown in Fig. 2. It can be seen that plants for the controllers are
the PWM signal generator, the LC filter and the grid impedance.
The inner current loop controller is tuned according to the
Modulus Optimum method, meanwhile the outer voltage loop
controller is tuned by means to the Symmetrical Optimum
method. According to [12], applied for the nested PR controllers
designed in p.u, the controllers gains are (1) and (2).
, (1)
,
(2)
inductor, and Td Tsw /2 the average time delay of the converter,
In (1), Tl1 l1 /(rl1 ωb ) represents time constant of the filter
where l1 and rl1 are the p.u. values of the resistance and
ωb is 2π 60 rad/sec . In (2), Tc = c / ωb represents the time
inductance of the filter inductor, and the base angular frequency
constant of the capacitor filter, and Teq the equivalent time delay
of the current closed-loop transfer function, where c is the p.u.
value of the filter capacitance. While the recommended value for
a is three.
The switching frequency is increased with respect to [4] to
reduce the size of the reactive components. From Fig. 2, it can
the effects of %& and '& , in the voltage and current control loops
be seen that feedforward elements are required to compensate
respectively. Then, a second order low pass filter is added to
compensate the 75% disturbance effects of the first and third
harmonics in the output current io , as shown in Fig. 2.
 Fig. 2. Per unit voltage and current control model.
2) Power control
The power control algorithm is also based on [4]. Some
modifications are done, among them the operation of the swing
equation implemented in the active power control block, on the
premise that the derivative of a signal is equal to the derivative
of the fundamental AC component, the derivative component
applies over ΔωVSM instead of ωVSM [7], in order to have a small
signal control. Such modification is achieved by adding one unit
as shown in Fig. 3, while the mathematical equivalence is shown
in (3).
DEFGH DIEFGH ≅ D7EFGH . 19
≅ LM& . M& . - OEFGH .E
PA QR
? ∗
(3)
K
The Boolean signal EnVI enables the reference for the
voltage and current control loops and commands the transition
from grid following to grid forming operation. The scaled phase
difference signal Δω , shown in Fig. 4, is added for
synchronization process, further details will be provided in the
following subsection.
3) Synchronization Process
In order to avoid high currents during initialization or
reconnection, a synchronization strategy is required. To achieve
this goal, grid voltage vg and output voltage vo are sensed and
introduced to a fast response PLL [13], to obtain their phases.
As seen in Fig. 4, the phase difference multiplied by a
proportional constant produces the scaled phase difference,
Fig. 3. Power Control structure for the single-phase VSM and initialization signals.
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ΔωVSM , that enters to the active power controller by subtracting
from the reference angular frequency ω* , as in [14] and [15].
The synchronization algorithm will not be explained in all
its extent in this paper, but only the final part of the process,
where Boolean EnVI signal enables or disables the power
control loop.
The transition from grid following to grid forming is done
when the phase difference is close to zero. Before the transition
EnVI signal is logic ‘1’, which means that virtual inertia is
decoupled and PR voltage controller follows the grid voltage, all
the integrators of power control block are disabled to avoid its
saturation and active power reference is set to zero, as presented
in Fig. 3.
Then S*2/ signal changes to ‘0’ whenever Δω ≈ 0 ,
disconnecting the grid reference and connecting the voltage
reference to the signal from the power controller, and enabling
the integrators, thereby the VSM starts synchronized with the
grid phase, and the transition is smooth.
B. DC-DC converter and DC-Link voltage Control
The DABSR DC-DC converter manages the release or
absorption of power from the ESU through a phase shift control,
while the DC-link voltage ripple is handled by duty ratio control.
To analyze the DABSR converter the variables are presented
in Fig. 1. An equivalent circuit for the tank circuit, considering
only fundamental components of square voltages waveforms, is
presented in Fig. 5.
 ' <;,? 2 sin7Ex 89 ;
w

v
[

'&<;,? y'- sin L Y Rz sin7Ex 8 . 59

w X (10)
[

Fig. 4. Synnchronization loop, active only during synchronization period.
Considering the ripple at twice the single-phase grid
The modulated voltages vihf and vohf and the respective duty
ratios are shown in Fig. 6. The volts-seconds steady state
constraint leads to (11) and (12). Where Vom defines the value
of duty ratio αo . While, to achieve a constant Vi a 50% duty
cycle is required, according to (13).

sin`? L R
XY 7{9 FYi
frequency, according to [16], [17], the average DC output
7{9
current (see Fig.1), in a switching period, is given by (4) (11)

〈%&- 〉 /&0 sin L Y R

X
2&: '- 789 sin L R
(4) XY 7{9
(12)

The variable /&0 is the phase shift current component X] 7{9 [

(13)
defined in (5) and (6). Where, Vom is the minimum value of the
A PI controller with 20|} cut-off frequency cascaded with
DC-link voltage. In addition, the quality factor Q of the resonant
tank is defined in (7).
a Notch Filter controls the average DC-Link voltage by means
/&0 sin 5
Z \F] of the phase shift angle φ, as shown in Fig. 1, while the duty ratio
[ ^7_`?/_9
(5)
αo is time-variant and Vom is a constant value. The
implementation of the DABSR DC-DC converter control
a bc ; e ;E ;*
3 = fg ? FYi scheme according to the equations presented in this section is
f3 h=3 c3 F]
(6)
3 shown in Fig. 1.

j
^ ^ IV. SIMULATION RESULTS
kl mn p]
(7)
The main parameters for simulation validations are
o q
presented in Table I.
Where, P is the nominal active power. Then, (5) could be
TABLE I. MAIN PARAMETERS OF THE DABSR AND GRID FORMING VSI
presented in a compact form as (8).

/&0 sin 5 r sin 5

Z \F]
DABSR parameters Value VSI parameter Value

[ ^7_`?/_9
(8) 220V,
Nominal Power 3.3KW Grid voltage
60Hz
Nominal ESU voltage 96V DC-link capacitance 240uF
Then, by rearranging terms of (5), the phase-shift angle is
Resonant inductance VSI switching
computed by (9). (Lr )
230uH
frequency
20KHz

5 sin`? L YtR
s 7Cr 9 voltage (〈vdc 〉)
Resonant capacitance Average DC-link
15nF 450V
u
(9)
DABSR switching Minimum DC-link
96KHz 380V
frequency (fx ) voltage (Vom )
The component Ioφ can be obtained as the control signal of

While the parameter r is calculated from the circuit elements,

the average DC-link voltage controller, as shown in Fig. 1.
The resonant components reported in Table I are elaborated
for validation of grid connected and islanded operation modes,
according to (6) and (8). Moreover, to deal with the DC voltage and for power variation tests in ESU discharging or charging
ripple at twice the grid frequency, the duty ratio control strategy mode.
presented in [18] is adopted. Therefore, only the fundamental
components at the switching frequency are considered, then the
AC voltages at the active bridges are defined in (10).

,2%
•
Ex 8 0 Ex 8
0 ~ 2~ ~ 2~

.2%

Fig. 5. Equivalent circuit for steady-state analysis. Fig. 6. Modulated voltages for the DABSR converter.

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A. Synchronization Process B. Power reference changes and load events
For the system presented in Fig. 1, with the synchronization These simulations consider a VSM already synchronized
control strategy presented in Fig. 3 and Fig. 4, the signals and connected to grid. Power step changes and load connection
involved in the processes of reconnection and disconnection of are tested, also main DC control signals are presented.
the VSM to the grid are shown in Fig. 7.
In Fig. 9, the VSM is set in a power injection operation
Two transitions are presented in Fig. 7: first the transition mode. Fig. 9a shows that the VSM starts with zero power
from islanded mode to grid connected mode at t = 0.8s, and the reference, at t = 0s a step up of 0.8 p.u. in power reference occur;
reverse transition, i.e., from grid-connected to islanded so, according to the VSM dynamics, the output active power is
operation mode, at t = 1.2s, controlled by signal conm illustrated set to that value. Then, at t = 0.75s, a second step up occurs,
in Fig. 7c. It can also be seen that signal EnVI, is enabled from t setting the output active power to its rated value (1 p.u.). Finally,
= 0.8s to t = 1.2s, during this period the power control is enabled, at t = 2s an additional load is connected at the point of
and so, the average output active power follows the active power connection with the grid, causing a temporary power-frequency
reference as presented in Fig. 7a; otherwise, output active power imbalance, then the VSM releases inertial energy in response to
is determined by load, in this case 0.2 p.u. The scaled phase this frequency event. The corresponding values of the
difference signal is shown in Fig. 7b, this signal is enabled only fluctuations in VSM frequency are presented in Fig. 9b. The
during the synchronization process, from t = 0.1s to t = 0.8s. In high frequency tank current during the whole process is
order to streamline the simulation process, kθ = 0.4 is chosen, presented in Fig. 9c, constant amplitude of current waveform
but for experimental validations it is advisable to choose much verifies the power decoupling. High frequency AC voltages,
smaller values, in order to avoid strong variations in VSM produced by actives bridges, and tank current are presented in
frequency when initializing synchronization. Fig. 10. It is noticeable that all switches are in ZVS operation.
Moreover, it is possible to see the duty ratio modulation on the
Fig. 8a shows the VSM output voltage and the grid voltage output active bridge, according to (11).
in p.u. during the entire process. It is noticeable that, for second
transition there is no changes in vo . While, for first transition, the Bidirectional power flow is also tested. Per unit active power
view is expanded from t = 0.05s to t = 0.4s in Fig. 8b, in order waveforms are presented in Fig. 11a, setting the power reference
to visualize the phase lag of vo due to the inner active power to 0.5 p.u. at t = 0s, and then setting the power reference to -0.5
control configuration, which may start with random phase shift p.u., changing from power injection from the ESU, to charging
with respect to the grid, as shown in the simulation. the ESU from the grid. While respective VSM frequency
fluctuations are illustrated in Fig. 11b. The DC-link voltage is
poavg poref
shown in Fig. 11c, with a magnification to visualize the 120Hz
0.5 oscillation. The ripple magnitude depends on the film
0.4
0.3
capacitance, and the gains of the PI controller. Finally, Fig. 11d
0.2 illustrates the DC current provided by the ESU. Note that, with
0.1
0
the proposed control strategy, the low frequency ripple in the
0 0.1 0.8 1.2 1.5
Dw (a)
0.5 1.2
1
0 0.8
0.6
-0.5
0.4
0.2
-1
0
-1.5 -0.2
0 1.5 0 0.75 1.5 2
conm EnVI (b) w_vsm w_vsm_ref (a)
1 1.004
0.8 1.003
0.6 1.002
0.4 1.001
0.2 1
0 0.999
0 0.1 0.5 (c) 0.8 1 1.2 1.5 0
iohf
0.5
(b) 1 1.5 2

30
20
Fig. 7. Signals involved in transitions between islanded and grid-connected. 10
0
-10
-20
-30
0 0.5 1 1.5 2
(c)

Fig. 9. Simulation results for power tests in power injection operation mode.
(a)
600
400
200
0
-200
-400
-600
(b) 0.49997 0.49998 0.49999 0.5
Time (s)

Fig. 8. Grid voltage and VSM output voltage waveforms in transitions. Fig. 10. High frequency DABSR signals

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