KOMBOLCHA INSTITUTE OF TECHNOLOGY

FACULITY OF ELECTRICAL AND COMPUTER ENGINEERING

DEPARTMENT OF COMPUTER ENGINEERING

ADVANCED VLSI ASSIGNMEMT I

Group Name Id
1. BELAY GAWCHO SGSR/0005/11
2. KALEAB TEGAYE SGRR/0002/11
2. GETACHW GIRMA SGSR/0007/11

Submitted TO: Dr. Kinde

Submitted Date: 02/26/2012

1 a) briefly distinguish between abstraction and hierarchy in the context of the VLSI
Design process

The VLSI Design Process

The Design Process: An iterative process that refines an "idea" to a manufacturable device
through at least five levels of design abstraction.
Abstraction: A very effective means of dealing with design complexity.
 Creating a model at a higher level of abstraction involves
replacing detail at the lower level with simplifications.
 Simulation: - The functional behavior of the design (or a
parameter such as power) is determined by applying a set of
excitation vectors to a circuit model
Hierarchy and Abstraction
 Moore's Law: Integration density doubles every 24 months.
 For example, Microprocessors:
 The million transistor/chip barrier crossed in `88 with the 486
 Impact of this revolution on design:
 Hand crafting not possible anymore (as was done for the 4004).
 Hierarchy is used in the design of the Pentium.
 The processor is a collection of modules each composed of cells.
 Re-use of cells reduces design effort and increases the chance of a first-time right
implementation.
  The use of hierarchy is a key ingredient to the success of the digital circuit.
 Reason why large analog designs never caught on.
Hierarchy and Abstraction
 Abstraction is also possible in digital designs.
 And difficult to apply effectively to analog designs.
 Critical element in dealing with complexity.
 A multiplier, for example, can be designed and treated like a black box.
 The performance of the multiplier is only marginally influenced by the way it is used
in a larger system
 This divide and conquer (hierarchical) approach allows the designer to deal with a much
smaller number of well characterized modules (or abstractions).
 Abstraction levels:
 Physical level: Rectangles, design rules.
 Circuit level: Transistors, R and C, analog voltage/current values.
 Switch level: Transistors, R and C, multi-valued logic.
 Logic level: Boolean logic gates, binary valued logic.
 Register Transfer Level: Adders, data paths, binary valued words.
 Functional level: Processors, programs and data structures.
Hierarchy and Abstraction
 Entire CAD design frameworks are based on this design philosophy.
 These have made it possible to achieve current design complexity
 Design tools include:
 Simulation at various complexity levels.
 Design verification.
 Layout generation.
 Design synthesis.
 Standard cells are a popular design style that makes layout generation easy.
 Layouts of basic gates such as AND, OR, NAND, NOR, and NOT as well as
arithmetic and memory modules are provided as input.

 These cells are designed with similar characteristics, such as constant height, and
can be manipulated easily to generate a layout.

The VLSI Testing Process

  A process applied to hardware devices whose goal is to determine if the device is free of
fabrication defects that would otherwise cause the device to violate
its functional or parametric specifications.


 It is applied to every device and therefore needs to be simple and fast.

 For logic test, we are done as soon as we observe the first error.

 However, we may be interested in locating the fault as well, for chip or process
debug.
 The objective of diagnosis is to determine the location of the
fault.
 It requires more tests.

Parametric tests
 Based on the analysis of a continuous circuit parameter, in contrast to
functional test which analyzes logic signals.
 
Parametric tests
 Check a number of continuous circuit variables such as noise margins,
propagation delay, maximum clock frequencies, steady-state current, and transient
signal behavior.

 These parameters are usually checked under a number of different temperatures

and supply voltages.

Note that the stimulus is digital, but the analysis of the output is performed on
an analog value or waveform.
The Testing Process
  When Device Under Test (DUT) is digital logic device, the stimuli are
called test patterns or test vectors.

 A device test consists of applying the test patterns one at a time (by a tester) to
the Primary Inputs of the DUT.

 The test patterns are defined in a test program that describes the waveforms to
be applied, the voltage levels and the clock frequency.

 A new part is automatically fed to the tester and a probe card or DUT board is
used to connect the inputs and outputs of the tester to the pins of the die or
package.
(b) Briefly explain why it is tractable (and popular) to automate the process of physical design
using standard cell libraries, i.e, what characteristics of standard cell make it easier?
Ans: -
i) Circuit design characteristics:
The functionality and the electrical characteristics of each cell is tested, analyzed, and specified.
In general, a test chip is manufactured and the performance of the each cell is analyzed from
silicon. In some cases, only a process characterization step is completed to generate simulation
models of the transistor characteristics, and library characterization tools use these models to create
the simulation views of each cell. Multiple drive strengths for each cell type are created. In
addition, the different drive strengths are multiples of a base or minimum size.
ii) Characteristics related to the shape of the cells
During the layout design of the cells, the cells are built using a predefined template that will ensure
that all the requirements are met. The template includes the height of the cell, the placement of
wells, N-transistors, and P-transistors, and guidelines to follow so that the cell can be flipped
vertically or horizontally and can be placed beside all other cells without creating errors such as
DRC violations. Cells are rectangular. Cells for specific rows or chip areas are all the same height.
a library may contain multiple sets of cells. For example, different cells will be used for logic, data
path, and I/O areas. Every cell length is rounded up to a multiple of a
coarse grid. This grid is determined by either of the following: A specific design rule (such as the
minimum well width) A desire to make placement easier and faster (using a coarse grid reduces the
number of possible placement coordinates, thus accelerating the placement process).
The power supply lines have a predefined width and position for the entire library the width of the
supply over the cell length is always consistent.

iii) Characteristics related to the interface of the cells

All the input and output ports have a predefined type, layer, position, size, and interface points.
These characteristics are determined based on the placer and/or router to be used to implement the
design. The ports are targets for the router and should be optimized with the router in mind for best
results. An example of this would be that routing can be made faster and easier by using a signal
pitch that is defined on a coarse grid. Routing tools will use fewer computing resources if a coarse
grid is used because the arithmetic required of the tool is simplified. The interface of the cells can
be designed to share certain connections. Examples would be source connections of transistors that
are connected to power supplies. Alternatively, common substrate and tub contacts can be shared
between cells. All non-shared polygons have to be spaced from the boundary of the cell by a value
equal to one-half of the layer spacing design rule. This ensures that abutting cells will be correct by
construction.

(c) Discuss the quality metrics of digital design.

Ans:
Fundamental Design Metrics

1. Functionality
2. Cost
2.1. NRE (fixed) costs - design effort
 Fixed cost to produce the design
- design effort
- design verification effort
- mask generation
 Influenced by the design complexity and designer productivity
 More pronounced for small volume products
2.2. RE (variable) costs - cost of material, parts, assembly, test
 Recurring costs – proportional to product volume
 silicon processing, material - also proportional to chip area
 assembly (packaging)
 Test:
3. Reliability and robustness
3.1 Noise margins
 Noise – unwanted variations of voltages and currents at the logic nodes
 From two wires placed side by side there are two types of coupling
1. capacitive coupling - voltage change on one wire can influence
signal on the neighboring wire - cross talk

2. inductive coupling - current change on one wire can influence

signal on the neighboring wire

3. From noise on the power and ground supply rails: can influence
signal levels in the gate
 3.2 Noise immunity
4. Performance/Power
4.1. Speed (delay)
 Propagation delay and the power consumption of a gate are related
 Propagation delay is (mostly) determined by the speed at which a given amount of
energy can be stored on the gate capacitors
 the faster the energy transfer (higher power dissipation) the faster the gate
 For a given technology and gate topology, the product of the power consumption
and the propagation delay is a constant
 Power-delay product (PDP) – energy consumed by the gate per switching
event.
 An ideal gate is one that is fast and consumes little energy, so the ultimate quality
metric is:
Energy-delay product (EDP) = power-delay 2
4.2. Power consumption; energy
5. Time-to-market

2. (a) Give three examples of noise sources (unwanted variations in voltage and current) in digital
circuits.

ANS:
1. capacitive coupling - voltage change on one wire can influence signal on the
neighboring wire - cross talk

2. Inductive coupling - current change on one wire can influence signal on the
neighboring wire

3. From noise on the power and ground supply rails: can influence signal levels in
the gate
(b) Plot the typical voltage transfer characteristics of CMOS inverter with supply voltage of 2.5 V.
Label VOH,VOL,VIL, VIH and VM in the voltage transfer curve (approximately).

ANS:
(c) Express the noise margins NML (noise margin low) and NMH (noise margin high)
in terms VOH,VOL,VIH, and VIH.
(d) Distinguish between static and dynamic power consumption in digital circuits.

ANS:
In modern low power. high performance microprocessors, static power is usually defined as the
power consumed by the device when it is in quiescent mode, usually implemented as some kind of
sleep mode, and dynamic power is the additional power consumed when the device is in operation.

At the CMOS circuit level, whether it be an NAND, NOR, Latch, etc. these circuits are designed
theoretically to not consume any power if their inputs are not switching (or in the case of a latch, if
there is no clock input Page on toggling. In reality, all FET transistors leak current between the
source and drain (if there is a voltage potential across the source drain) even if the gate voltage is in
the off position. This current is called sub threshold current and used to be insignificant. However,
as devices have become smaller and smaller and operating voltages have not scaled down with
technology scaling (due to problems scaling the threshold voltage), this sub threshold voltage is
becoming an increasingly important component of the total power of a chip. This becomes
especially true in devices that have millions of these simultaneously leaky circuits, even if the
device is not doing anything. Early power managed devices (like microprocessors) were able to
control power consumption in sleep modes by simply slowing or stopping the clock (known as
clock gating) but as static power consumption has increased, it has become more important to
consider techniques such as voltage islands on chips where the voltage to large portions of a chip
can be shut off (or reduced) to reduce the static leakage currents.

The dynamic power is the power associated with switching. To a first order approximation, in any
CMOS circuit like those described above, the output of the circuit (NAND, NOR, etc.) is connected
to a wire that is usually connected to the input of other circuits. This wire and inputs to other
circuits (which are usually gate electrodes) can be modeled as capacitive loads to the circuit. When
the circuit has to switch from a high voltage to a low voltage (or vice versa) then this capacitance
has to be charged or discharged. This takes a certain amount of energy and if you repeat this
billions of times every second, it becomes a continuous or AC power. As the other respondent
mentioned, there can also exist in circuits an intermediate position where in the process of
switching, there can appear a direct path in the circuit between voltage and ground which can cause
a switching current that is resistive and therefore different than the capacitive power just
described. This resistive current can be managed somewhat with good device and circuit design
and non-overlapping clocks in latch design, but this power may also be considered a dynamic
power as it only occurs when circuits are switching.

3. Implement the following logic function in conventional CMOS.

F = A(B + C) + DE ¯
(a) If there are more one possible implementations, do the one that imposes less capacitive load at
the output, i.e, faster.

(b) Size the transistors such that the logic gate is equivalent (in resistance and current)
to a unit inverter (i.e WL pp= 2 and WnLn = 1). If there are more than one way of
sizing, do the one that results in a faster circuit.
4. Sequential circuits
(a) draw the transistor-level circuit diagram of a positive-edge-triggered register using transmission
gates and CMOS inverters. The inputs are D and CLK, and the output is Q. The circuit diagram
MUST show all transistors. You may start with multiplexer-based diagram, and then convert to
transistor-level circuits.
(b) Given the propagation delay of an inverter is ttp-inv = 15ps, and the propagation delay of the
transmission gate is ttp-tx = 25ps. Also assume that contamination delay is 0. Calculate the setup
time, propagation delay and hold time of the register in (a).

Anser:
Given: ttp−tx = 25ps, ttp−inv = 15ps, tcd=0ps

Required: tst=?, tpd=?,

tht=?

Solution: -
Setup time(tst): The set-up time is the time before the rising edge of the clock that the input data
D must become valid. Setup time is for the transmission gate multiplexer-based register, the
input D has to propagate through I1, T1, I3 and I2 before the rising edge of the clock. Therefore

tst= 3 *tpd_inv + tpd_tx = 3*15ps+25ps= 70ps

Propagation delay(tpd): The propagation delay is the time for the value of QM to propagate to the
output Q.

tpd = tpd_tx + tpd_inv = 15ps+25ps= 40ps

Hold time(tht): The hold time represents the time that the input must be held stable after the rising
edge of the clock. In this case, the transmission gate T1 turns off when clock goes high and
therefore any changes in the D-input after clock going high are not seen by the input. Therefore,
the hold time is 0.
(c) Draw also the transistor level circuit diagram of master-slave register based on
NMOS-only pass transistors and CMOS inverters.
(d) Compare the designs in (a) and (c) in terms of the number of transistors and
robustness.

Ans
 in terms of the number of transistors the design in (a) are better than the design in
(c), because the number of transistor at (a) ten, the number transistor at (c) twelves.
 In terms of robustness
 Edge triggered latch(register) is called flip flop. In designing of positive edge
triggered register can reduce the number of transistor from 16 to 12 by replacing
transmission gate and cmos inverter based design by nmos only pass transistor and
cmos inverter based design.

 Single transmission gate D flipflop input must over drive feedback signal and must
use weak feedback inverter. It is usefull when chip area is critical but input
signal must be strong. Pass gate of D flpflop replace transmission gate with nmos
pass gate very common in VLSI circuit design.

5. Arithmetic Circuits.
(a) Sketch the block diagram and logic-gate level diagram of a 4-bit ripple carry adder
(use four single-bit adders). Only use inverters, two-input AND, OR and XOR
gates. Do not use any multi-input logic gates.

Circuit diagram of a 4-bit ripple carry adder

(b) Calculate the delay of the critical path, if the gate delays are ti = 15ps (for inverter),
ta = 25ps (for AND), to = 30ps (for OR) and tx = 40ps (for XOR) gates.

Answer:
In ripple carry adder carry from the last bit is available after 2n gate delay whereas sum is after

2n-1 gate delay and the critical path propagation gate delay is 2n+1(tpg= 2n+1=2*4+1=9).
tcarry(tAO)= 2n*tand + n*tor =2*4tand+4*tor = 8*25ps+ 4*30ps= 320ps

tsum(txor)=2n* txor = 2*4*40ps = 320ps

tadder= (N-1) tcarry + tsum = 3*320ps + 320ps= 1280ps , is propagation delay of ripple carry adder

The critical path propagation delay of ripple carry adder(tripple) is

tripple= tpg +(N-1) tAO + txor , tpg is 1 bit propagate/ generate

tripple= 9 + (4-1)320ps + 320 ps = 1289ps

(c) Propose, at least one method, which can be used to reduce the delay of the critical
path.
(d) Count the number of transistors if conventional CMOS circuit is used to implement
the logic gates.
Answer: Techniques used to reduce the delay of the critical path:

Remove the output inverters and alternate positive and negative logic to reduce
delay and transistor count to 24.

Feed the carry-in signal (C) to the inner inputs so the internal capacitance is
already discharged.

Make all transistors in the sum logic whose gate signals are connected to the
carry- in and carry logic minimum size (1 unit, e.g., 4 X 12 X). This minimizes
the branching effort on the critical path. Keep routing on this signal as short as
possible to reduce interconnect capacitance.

Determine widths of series transistors by logical effort and simulation. Build an

asymmetric gate that reduces the logical effort from C to Cout at the expense of
effort to S.

Use relatively large transistors on the critical path so that stray wiring capacitance
is a small fraction of the overall capacitance.

6. VLSI Design Flow and CAD Tools.

(a) Sketch the block diagram of standard cell based digital ASIC design flow and give
brief descriptions of each step (from design capture to tape out).
 ASICs stands for Application Specific Integrated Circuits, and refer to semiconductor solutions
design for a particular application, as opposed to other solutions like Field Programmable Gate
Arrays (FPGAs) which can be programmed multiple times to perform a different function.
ASIC is also sometimes referred to as SoC (System on Chip). ASIC design flow starting from
ASIC design specification to design tape-out for manufacturing in the foundry, and highlight
important decisions and activities that each step entails
ASIC Specification: The first step in ASIC design flow is defining the specifications of the
product before we embark on designing it. This phase typically involves market surveys with
potential customers to figure out the needs and talking to the technology experts to gauge the
future trends. Developing a thorough and correct specification usually sets a solid foundation for
the ASIC design. The technical specifications need refinement of the technical requirements over
time, but it’s important to cover the information in an unambiguous manner.
ASIC Architecture: After pruning the specifications, it’s now time to partition the entire ASIC
or SOC’s functionality into multiple functional blocks. A good architecture focuses on gleaning
the best performance of the ASIC chip, while minimizing the hardware resources which directly
helps in keeping the overall cost of the chip within the allocated budget. During this phase,
architects define the relationship between various functional blocks and allocate time budget to
each block. The divide between hardware and software blocks is also a critical part of this phase
of the ASIC design. Design is captured in a high level programming language like C++ or
System C.
Logic Design and Verification: This step refers to the frontend part of the ASIC design flow
and involves coding the data flow of each functional block in a hardware description language
like Verilog, VHDL or System Verilog. The interactions between the functional blocks is also
coded. Logic Design usually comprises of:

Combinational Logic: Combinational logic usually refers to Boolean combinatorial gates like the
OR, AND, NAND, NOR etc. Sequential Elements: Sequential elements play a critical role in
interfacing between different combinational logic clouds performing different functions by
storing their output temporarily. Finite State Machines (FSMs): These are higher abstraction of a
sequential logic which can be implemented both in hardware and software. FSMs model
response of a digital machine to a set of inputs to produce deterministic set of outputs, and serves
as an important building block for logic designers.

Arithmetic Logic Blocks: Arithmetic computations form the heart of the computing logic, and
usually is the bottleneck for performance in high performance CPU cores. Arithmetic
computation includes addition, subtraction, multiplication and division

Data-path Design: In addition to coding combinations of above elements, Hardware Description

Languages (HDLs) can model data path design in an abstract manner like a programming
language which can be interpreted by EDA tools correctly. These could be multiplexing,
decoding, case statements etc.

Physical Design: This refers to the backend design cycle. If there’s just one aspect that
distinguishes the backend design from frontend design, then it would be- delay. Frontend design,
while being cognizant of the logic delays and speed, largely ignores it for majority part of the
RTL coding and verification. While, on the other hand, physical design sees real delay right from
the very beginning.Physical design flow is further sub-divided into the following:

Synthesis: Synthesis reads in the RTL code (.v or .sv files) along with physical libraries of the
standard cells that may contain- delay information (.lib files), physical dimensions and metal
layer information within the cell (.lef files) and other constraint files to convert the behavioral or
dataflow code into real physical standard cell gates. Note that there are many possible
implementations for 2:1 Multiplexer, and Synthesis is responsible to do an educated trade-off
with performance, power and area to come up with the best implementation considering these
constraints.

Floor planning: Floor planning step formalizes and refines the floorplan that was first
conjured up during the architecture planning step. In this step, the entire die area is divided into
physical partitions, and their shapes are molded while keeping in mind the area requirements, the
flow of top level data and control buses, possibility of any future growth. Pins and ports are
assigned a rough location, which can further be refined depending on the Place and Route results.
This is usually the most critical step in physical design cycle, and requires multiple iterations.
Any additional time spent here is worth it considering its long lasting implications on routing
congestion, cell density, timing QoR and DRCs.A robust power grid delivery- which addresses
static and dynamic IR drop is also a critical function of the floor planning step.
 Placement: During placement, all standard cells are placed in legal locations on site rows. The
aim of this step is to minimize the wire length, while ensuring optimal placement that will help
faster timing convergence.
Clock Tree Synthesis: Till now, clock network was ideal. During clock tree synthesis, clocks
are propagated and the clock tree is synthesized using clock buffers. The major goals of this step
is to achieve optimal clock latency while minimizing clock skew. There are many proposed
algorithms to design an optimal clock tree- H Tree, Steiner Tree etc.
Detail Routing: With all instances placed and clocks routed, now it’s time to route the signal
nets. Modern process supports 10-12 metal layer stack, with M0-M1 reserved for standard cell
routing. Aim of detail routing is to ensure minimum detours because these may have
implications on timing, and to ensure minimum DRC (Design Rule Check) violations like opens,
shorts etc. This step performs multiple search and repair loops (10-20) to keep the overall DRC
count low.

Physical and Timing Verification: While logic verification ensures correct functionality,
physical verification ensures correct layout. There’s been an increase in Physical Verification
checks which includes- DRC (Design Rule Checks), LVS (Layout versus Schematic), Electro
migration, Electro-static discharge violations (ESD), Antenna violations, Pattern Match (PM)
violations, Shorts, Opens, Floating nets etc. It is important to track these violations in parallel
with the Place and Route flow to avoid any surprises just days before tape-out.
Timing Verification verifies that the chip runs at the specified frequency by ensuring setup and
hold is met for all timing paths in the design

(b) Discuss about the Alliance VLSI CAD tools which can be used in each step of the
design flow.

Ans: - Alliance CAD System is a free set of EDA tools and portable cell libraries for VLSI
design. It covers the design flow from VHDL up to layout. It includes VHDL simulator, RTL
synthesis, place and route, netlist extractor, DRC. It is open source and free to use. It was
developed in the 90th and is no longer active developed. Especially tools have a graphical
user interface are outdated. However, it still includes some good command line tools and is the
only free open source synthesis tool existing.
The design flow of Vlsi design flow
CAD Tools used for VLSI design flow are listed below
Behavioral and RTL Simulation - Questasim (Mentor Graphics)

• Device and Circuit Level Simulation – Tanner EDA (Mentor Graphics: S-Edit, T-Spice and W-
Edit)
• Layout Design – Tanner EDA (Mentor Graphics: L-Edit)
• Design Verification: Tanner EDA (Mentor Graphics: LVS)

• SPICE OPUS – free Analog Circuit Simulation • Alliance --A Free VLSI/CAD System (Linux) •
Open-Source digital Design flow.
• Qflow: An Open-Source Digital Synthesis Flow (Linux)