Microcontroller 32-bit

ARM Architecture
DENNY H.T. NUGROHO, M.T.
WEEK 4
uC Vs uP ?

-Microprosesor ?
- Intel core i3,5,7.
- Intel 4004

-Microcontroller ?
- Atmega
- ARM
Arm History

• Acorn Computers first developed the Acorn RISC Machine

architecture 1980 (ARM1)
• first ARM-based products were coprocessor modules for
the BBC Micro series of computers.
• 1983  The 6502's memory access architecture had let
developers produce fast machines without costly direct
memory access (DMA) hardware. (ARM2)
• 1992 ARM6  Apple used the ARM6-based ARM610 as the
basis for their Apple Newton PDA.
ARM Block Diagram
ARM Block Diagram
1. JTAG (Joint Test Action Group) is an industry standard for
verifying designs and testing printed circuit boards after
manufacture. JTAG implements standards for on-chip
instrumentation in electronic design automation (EDA) as a
complementary tool to digital simulation.
2. Bus data (AHB & APB)
◦ Advanced High-performance Bus (AHB) is a bus protocol
introduced in Advanced Microcontroller Bus Architecture
version 2 published by ARM Ltd company. large bus-widths
(64/128/256/512/1024 bit). A simple transaction on the AHB
consists of an address phase and a subsequent data phase
(without wait states: only two bus-cycles)
ARM Block Diagram
2. Bus data (AHB & APB).
◦ Advanced Peripheral Bus (APB) is designed for low bandwidth
control accesses, for example register interfaces on system
peripherals. This bus has an address and data phase similar to
AHB, but a much reduced, low complexity signal list (for
example no bursts).
3. Memory
◦ EBI
◦ SRAM
◦ Flash
ARM Block Diagram
4. Peripheral
◦ Ethernet MAC
◦ CAN
◦ USART
◦ USB Device
◦ SPI
◦ PWM Ctrl
◦ TWI
◦ Synchro Serial Ctrl
◦ ADC
◦ Timer/Counter
ARM Block Diagram
5. System Controller
◦ Advance Interrupt Ctrl
◦ Power Mng Ctrl
◦ PLL
◦ Osc
◦ RC Osc
◦ Brownout Detect
◦ Power On Reset
◦ Prog. Int. Timer
◦ Watchdog Timer
◦ Real Time Timer
◦ Debug Unit
◦ PID Ctrl
List of ARM microarchitectures
STM32F103
Family
STM32F103 Family
Features
o ARM® 32-bit Cortex®-M3 CPU Core
o 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone
2.1) performance at 0 wait state memory access.
o Single-cycle multiplication and hardware division.
o Memories
o 64 or 128 Kbytes of Flash memory
o 20 Kbytes of SRAM
Features
o Clock, reset and supply management
o 2.0 to 3.6 V application supply and I/Os
o POR, PDR, and programmable voltage detector (PVD)
o 4-to-16 MHz crystal oscillator
o Internal 8 MHz factory-trimmed RC
o Internal 40 kHz RC
o PLL for CPU clock
o 32 kHz oscillator for RTC with calibration
o Low-power
o Sleep, Stop and Standby modes.
o VBAT supply for RTC and backup registers.
Features
o 2 x 12-bit, 1 μs A/D converters (up to 16 channels)
oConversion range: 0 to 3.6 V
oDual-sample and hold capability
oTemperature sensor
o DMA
o7-channel DMA controller
oPeripherals supported: timers, ADC, SPIs, I2Cs and USARTs
o Up to 80 fast I/O ports
o26/37/51/80 I/Os, all mappable on 16 external interrupt
vectors and almost all 5 V-tolerant
Features
o Debug mode
oSerial wire debug (SWD) & JTAG interfaces
o 7 timers
oThree 16-bit timers, each with up to 4 IC/OC/PWM or pulse
counter and quadrature (incremental) encoder input.
o16-bit, motor control PWM timer with dead-time generation
and emergency stop.
o2 watchdog timers (Independent and Window)
oSysTick timer 24-bit downcounter
Features
o Up to 9 communication interfaces
oUp to 2 x I2C interfaces
oUp to 3 USARTs
oUp to 2 SPIs (18 Mbit/s)
oCAN interface
oUSB 2.0 full-speed interface
o CRC calculation unit, 96-bit unique ID
Device overview
Overview STM32F103 Fam.
1. ARM® Cortex®-M3 core with embedded Flash and SRAM
- latest generation of ARM processors for embedded systems
- developed to provide a low-cost platform
- low-power consumption
- outstanding computational performance and an advanced
system response to interrupts
- code-efficiency, the memory size usually associated with 8- and
16-bit devices.
- 64 or 128 Kbytes of embedded Flash is available for storing
programs and data.
- Twenty Kbytes of embedded SRAM accessed (read/write) at
CPU clock speed with 0 wait states.
Overview STM32F103 Fam.
2. CRC (cyclic redundancy check) calculation unit
- is used to get a CRC code from a 32-bit data word and a
fixed generator polynomial.
- CRC-based techniques are used to verify data transmission
or storage integrity.
- The CRC calculation unit helps compute a signature of the
software during runtime, to be compared with a reference
signature generated at link-time and stored at a given
memory location.
Overview STM32F103 Fam.
3. Nested vectored interrupt controller (NVIC)
- a nested vectored interrupt controller able to handle up to
43 maskable interrupt channels and 16 priority levels.
- This hardware block provides flexible interrupt
management features with minimal interrupt latency.
Overview STM32F103 Fam.
4. External interrupt/event controller (EXTI)
- The external interrupt/event controller consists of 19 edge
detector lines used to generate interrupt/event requests.
- Each line can be independently configured to select the
trigger event (rising edge, falling edge, both) and can be
masked independently.
- The EXTI can detect an external line with a pulse width
shorter than the Internal APB2 clock period.
Overview STM32F103 Fam.
5. Clocks and startup
- System clock selection is performed on startup, however the
internal RC 8 MHz oscillator is selected as default CPU clock on
reset.
- An external 4-16 MHz clock can be selected, in which case it is
monitored for failure.
- Several prescalers allow the configuration of the AHB frequency,
the high-speed APB (APB2) and the low-speed APB (APB1)
domains.
- The maximum frequency of the AHB and the high-speed APB
domains is 72 MHz.
- The maximum allowed frequency of the low-speed APB domain
is 36 MHz.
Overview STM32F103 Fam.
6. Boot modes
At startup, boot pins are used to select one of three boot
options:
• Boot from User Flash
• Boot from System Memory
• Boot from embedded SRAM
The boot loader is located in System Memory. It is used to
reprogram the Flash memory by using USART1. For further
details please refer to AN2606.
Overview STM32F103 Fam.
7. Power supply schemes
- VDD = 2.0 to 3.6 V: external power supply for I/Os and the
internal regulator. Provided externally through VDD pins.
- VSSA, VDDA = 2.0 to 3.6 V: external analog power supplies
for ADC, reset blocks, RCs and PLL (minimum voltage to be
applied to VDDA is 2.4 V when the ADC is used). VDDA and
VSSA must be connected to VDD and VSS, respectively.
- VBAT = 1.8 to 3.6 V: power supply for RTC, external clock
32 kHz oscillator and backup registers (through power
switch) when VDD is not present.
Overview STM32F103 Fam.
8. Power supply supervisor
- The device has an integrated power-on reset
(POR)/power-down reset (PDR) circuitry. It is always active,
and ensures proper operation starting from/down to 2 V.
- The device remains in reset mode when VDD is below a
specified threshold, VPOR/PDR, without the need for an
external reset circuit.
- The device features an embedded programmable voltage
detector (PVD) that monitors the VDD/VDDA power supply
and compares it to the VPVD threshold.
- The PVD is enabled by software.
Overview STM32F103 Fam.
9. Voltage regulator
The regulator has three operation modes: main (MR), low-
power (LPR) and power down.
• MR is used in the nominal regulation mode (Run)
• LPR is used in the Stop mode
• Power down is used in Standby mode: the regulator
output is in high impedance: the kernel circuitry is powered
down, inducing zero consumption (but the contents of the
registers and SRAM are lost)
 Overview STM32F103 Fam.
10. Low-power modes
• Sleep mode In Sleep mode, only the CPU is stopped. All peripherals
continue to operate and can wake up the CPU when an
interrupt/event occurs.
• Stop mode The Stop mode achieves the lowest power
consumption while retaining the content of SRAM and registers. All
clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the
HSE crystal oscillators are disabled. The voltage regulator can also be
put either in normal or in low-power mode. The device can be
woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output, the RTC
alarm or the USB wakeup.
 Overview STM32F103 Fam.
10. Low-power modes
• Standby mode The Standby mode is used to achieve the lowest
power consumption. The internal voltage regulator is switched off so
that the entire 1.8 V domain is powered off. The PLL, the HSI RC and
the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for
registers in the Backup domain and Standby circuitry. The device
exits Standby mode when an external reset (NRST pin), an IWDG
reset, a rising edge on the WKUP pin, or an RTC alarm occurs.
Overview STM32F103 Fam.
11. DMA
- The flexible 7-channel general-purpose DMA is able to
manage memory-to-memory, peripheral-to-memory and
memory-to-peripheral transfers.
- Each channel is connected to dedicated hardware DMA
requests, with support for software trigger on each channel.
Configuration is made by software and transfer sizes
between source and destination are independent.
- The DMA can be used with the main peripherals: SPI, I2C,
USART, general-purpose and advanced-control timers TIMx
and ADC.
Overview STM32F103 Fam.
12. RTC (real-time clock) and backup registers
-The RTC and the backup registers are supplied through a
switch that takes power either on VDD supply when present
or through the VBAT pin. The backup registers are ten 16-bit
registers used to store 20 bytes of user application data
when VDD power is not present.
-- The real-time clock provides a set of continuously running
counters which can be used with suitable software to
provide a clock calendar function, and provides an alarm
interrupt and a periodic interrupt.
Overview STM32F103 Fam.
13. Timers and watchdogs
-advanced-control timer (TIM1)
-three general-purpose timers (TIM2, TIM3, TIM4)
-two watchdog timers
-SysTick timer.
Overview STM32F103 Fam.
14. GPIOs (general-purpose inputs/outputs)
-Each of the GPIO pins can be configured by software as
output (push-pull or open-drain), as input (with or without
pull-up or pull-down) or as peripheral alternate function.
-Most of the GPIO pins are shared with digital or analog
alternate functions.
-I/Os on APB2 with up to 18 MHz toggling speed.
Overview STM32F103 Fam.
15. ADC (analog-to-digital converter)
-Two 12-bit analog-to-digital converters are embedded into
STM32F103xx performance line devices and each ADC
shares up to 16 external channels, performing conversions
in single-shot or scan modes.
Additional logic functions embedded in the ADC interface
allow:
• Simultaneous sample and hold
• Interleaved sample and hold
• Single shunt
The ADC can be served by the DMA controller.
Overview STM32F103 Fam.
16. Peripheral
-I2C
-USART
-SPI
-CAN
-USB
Overview STM32F103 Fam.
17. Temperature sensor
The temperature sensor has to generate a voltage that varies
linearly with temperature. The conversion range is between
2 V < VDDA < 3.6 V. The temperature sensor is internally
connected to the ADC12_IN16 input channel which is used
to convert the sensor output voltage into a digital value.
Block Diagram STM32F103C8xx
Sekian..