VLSI Testing and

Testability

Combinational ATPG - 1

Dr. S. Sivanantham
School of Electronics Engineering
VIT University
Vellore 632014
INIDA
VLSI Testing and Testability
 Summary of last courses
In the previous lectures we have seen:
• the necessity to test VLSI systems, and related costs/benefit
analysis
• how faults are modeled
• how faults are simulated
• how the quality of testing is measured

Let us now focus on how test vector patterns are generated

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 Course outline

• Structural vs. functional test
• Scan design First, we have to study
• Search space abstractions
 a number of useful
concepts
•
•
Five values algebra
Path sensitization 

• Combinational ATPG algorithm
– D-algorithm


In a second phase, we
will study actual
algorithms

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 Functional test
Computational burden of functionally testing a 64-bit adder

A B Carry-in
64 64 1

+
64 1

Sum Carry-out

• the adder has 129 inputs and 65 outputs

• in order to completely exercise its functionality, we need 2129 input patterns,

generating 265 output patterns

• using a 1GHz ATE, this takes 2.15x 1022 years, roughly

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 Structural test (1)
Structural representation of a 1-bit full-adder

A
B
Sum generation of sum
Carry-in

Carry-out generation of
carry

16 stuck-at fault locations

… to be repeated 64x for a 64-bit adder

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 Structural test (2)
Computational burden of structurally testing a 64-bit adder (approximate !)

• the total structural fault list has 64 x 16 = 1024 faults

• thus, 1024 vectors are needed for a full structural test

• using a 1GHz ATE, this takes 1.024 x 10-7 s

The functional and structural examples achieve the exact same fault coverage

In practice:
• a subset covering <75% faults is provided by the designer as functional
test-patterns
• ATPG is applied to supplement and raise the coverage to >98% stuck-at
fault coverage

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 ATPG
Automatic Test-Pattern Generator (ATPG) algorithm:

• inject a fault into a circuit

• activate the fault, and cause its effects to propagate to a circuit primary
output

• if the circuit output is different from what would be expected from a fault-
free circuit, then the fault can be detected

But also:

• detect redundant or unnecessary circuit logic

• prove whether one circuit implementation matched another circuit

implementation

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 Search space abstractions
A logic circuit is represented as binary tree representation of the AND gate
direct acyclic graph with a root and cj
vertex v
One only path leads from a vertex to x2
the root
0 1
Only two decisions are possible from
a node x1 x1
0 1 0 1
This is a binary decision tree
0 0 0 1

“backtracking”
The tree represents all possibilities for input patterns x1 and x2
The leaf nodes represent the good machine output for the selected inputs

All ATPG algorithms search a similar tree to find test-patterns

• each node of the tree represents a decision variable
• when a conflict or no solution is found, the algorithm dictates reversing
previous decision: backtrack
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 Search space abstractions (2)
The Binary decision diagram (BDD) is
obtained by reducing the decision tree
It represents the optimal form of a switching cj
function
x2

1
Any switching function can be described 0
x1
by a BDD
0 1

0 1
In order to read the diagram:
• start from root node (top) binary decision diagram
• the product of all visited nodes forms representation of the circuit
the maxterms/minterms
• the output value is read at the leaf

e.g. rightmost path: x1 · x2 = 1

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 ATPG
The automatic test pattern generation makes use of these search space
abstractions

An internal representation of explored, infeasible, tree is being kept in

memory

cj
x2
Searched and Infeasible
0 1 Unexplored

x1 x1
0 1 0 1

0 0 0 1

Present Assignment

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 Roth’s 5-valued algebra
In order to proceed ATPG in one single pass of the algorithm, a high-order
algebra representing both the good and failing machine simultaneously is
presented

D 1 in true circuit, 0 in faulty circuit 1 1 in both true and faulty circuit

D 0 in true circuit, 1 in faulty circuit 0 0 in both true and faulty circuit

X unknown value in either true or

faulty circuit
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 Forward implication
A forward implication results when the inputs to a logic gate are sufficiently
labeled so that the output can be uniquely determined

D three examples
D
1
AND gate forward implication
table

D D
0

D D
0

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 Backward implication
The backward implication is the unique determination of all gate inputs
when the gate output and some of the inputs are given

three examples
1 1
1
Used by the ATPG in the
justification step, as
D D backtracing procedure, where
given an output objective, the
0 input conditions are traced in a
backward pass

D D
backtracking  backtracing
0

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 Fault cone and D-frontier
1 1
0 Fault Cone

s-a-1 1
D D x D-Frontier

x
0 0

Fault cone set of hardware that can be reached while performing a forward
tracing, starting at the fault site
D-frontier set of gates closest to POs with D or D at the input and X at the
output

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 Path sensitization method
Preferred ATPG method, consisting of three steps

1. fault sensitization a fault is activated by forcing the signal driving it to the

opposite value from the fault

1. fault propagation the fault effect is propagated to a PO (primary output)

1. line justification internal signal assignments previously made to sensitize

or propagate are justified by setting PIs (primary inputs) of the circuit

A conflict may arise when an assignment contradicts with a previously made

assignment

Backtrack is then needed, where a previously made assignment is discarded,

and an alternate assignment selected

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Circuit example for path sensitization
(1)
1 f
s-a-0
D z
a
c
g b

Path sensitization of this circuit will demonstrate conflict, and backtrack.

Step1: assuming the second input s-a-0, fault activation requires that this
node be controlled to logic 1, thus causing a D downstream of the fault

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 Circuit example for path sensitization
(2)
0
1 f
s-a-0 0 0
D D
z
a D D
c
g b
1

Step2: fault propagation, decision path scenario is a-b-c-z

– all off-path values must be non-controlling, i.e. g=1, f=0
– indeed, D-bar shows up at the output
Step3: justification
– backtracing f=0 requires that both inputs of the OR gate be at logic 0
– this creates a conflict since the nodes downstream of the fault should be at D
– backtracking is needed

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 Circuit example for path sensitization
(3)
0 D
1 f
s-a-0 D
D 1
z
a D D
c
g b
1

Step2: backtracking, we try simultaneous propagation through paths a-b-c-z

and f-z
– this solution must be abandoned as the fault does not propagate to a PO
– the D-frontier is said to disappear

– backtrack, again …

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 Circuit example for path sensitization
(4)
0 D
1 f
s-a-0 D
D
1 z
a 0
0 c
g b

Step2: backtracking, we try path f-z

– D propagates through the first OR if the other input is set to logic 0
– c=0, which allows successful propagation of D to z
Step3: justifying
– a=1 causes c=0
– this creates a conflict again,
– backtracking is needed, again

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 Circuit example for path sensitization
(5)
0 0 D
1 f
s-a-0 D
D
z
a 0
c
g b
0 0
x

Step3: justifying
– g=0 causes c=0
– no conflict remains, the vector is discovered as 010x

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 Circuit example for path sensitization
(6)
A=0
B=1 f
s-a-0
Z=D
z
a
c
g b
C=0
E=x

So, what have we achieved so far … ?

remember that we do not have access to probe or control any of the

internal nodes while doing the test measurement

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 Circuit example for path sensitization
(7)
In conclusion

The test for the s-a-0 fault is vector ABCD=010x, and produces output

• Z=1 in the good machine, and

• Z=0 in the failing machine

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 So, what do we do now ?
The path sensitization method works fine …

… however, a number of extra steps must be taken in order to

to have an algorithm that can be processed by a machine

VLSI Testing and Testability