VLSI Testing and

Testability

Testability Measures –
Combinational Circuits
Dr. S. Sivanantham
School of Electronics Engineering
VIT University
Vellore 632014
INIDA
VLSI Testing and Testability
Layered controllability example
CC0, CC1

1,1 2,2 d
a
3,5
z
1,1
b 3,2
c e
1,1

CC0(a) = CC1(a) = CC0(b) = CC1(b) = CC0(c) = CC1(c) = 1

CC0(d) = CC1(d) = 1+1 = 2

CC0(e) = 1 + 1 + 1 = 3 CC1(e) = min{1, 1} + 1 = 2

CC0(z) = min{2, 3} + 1 = 3 CC1(z) = 2 + 2 + 1 = 5

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 Observability measuring method
Algorithm steps

initialization step: set observability of PO to 0, and of internal nodes

and PIs to infinity

1. start from PO moving backwards towards PIs

1. propagate through to primary inputs, and add 1 for each logic layer; for
each gate, calculate the observability of all inputs

1. assess the difficulty of placing other PIs into values that allow the
observed PI value to propagate to PO

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 Detailed observability example
Observability of a Boolean gate input

CO(a)
CC1(a)
CO(z) = 0 CC0(a)
a CO(z)
CO(a) = CO(z) + CC1(b) + 1 z
b
CO(b) = CO(z) + CC1(a) + 1 CO(b)
CC1(b)
CC0(b)

same concept, using words:

the effort I must produce in order observe the input of a logic gate is
equal to the effort needed to observe the output plus one, augmented
with the effort needed to place all other inputs in a non-controlling state,
allowing the observed node state propagating through

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Combinational observability rules (1)

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Combinational observability rules (2)

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 Reconvergence issue
SCOAP may perform poorly in presence of reconvergent signals

1. low testability value may remain undetected

1,1 2,2 s-a-0

a
z

3,4

2. SCOAP does not detect signal independency

1,1 2,2 1,1 3,3

a z a z

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How reconvergent topologies are handled
(1)
SCOAP forward processing of controllabilities
format: CC0, CC1
1,1 3,2
a

1,1 2,6
b z
1,1
1,1
c
3,2

SCOAP backward processing of observabilities

format: CC0, CC1 (CO)

1,1 (6) 3,2 (4)

a

1,1 (5) 1,1(6) 2,6 (0)

b z
1,1(6) 1,1 (5)
1,1 (6)
c
3,2 (4)

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How reconvergent topologies are handled
(2)
Controllability issue
4
format: CC0, CC1
Consequently, and only for the
purpose of this calculation, we
may change both OR output 5
controllabilities to 1 from 2 into 1 Eventually,

1,1 3,2 1
CC1(z) = 1 + 1 + 1 + 1 = 4

a
2,6
1,1 2,4
b z
1,1
1,1
c
3,2 1
2 1

Line be is connected to the In order to control z to 1, all three

inputs of three gates; however 3 inputs of the OR gate must be at
the effort needed to control b to 1, specifically this one
We take the effort of controlling b
logic 1 should be taken into
to logic 1 into account here
account once only

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How reconvergent topologies are handled
(3)
Observability issue
format: CC0, CC1 (CO[0], CO[1])

1,1 (inf,6) 3,2 (inf,4)

a

1,1 (5) 1,1(inf,6) 2,6 (0)

b z
1,1(inf,6) 1,1 (5)

c
1,1 (inf,6) 3,2 (inf,4) In order to control a logic 0 on
this node, all other AND inputs
must be set to logic 1, which
prevents setting this node to
logic 0; thus CO[0] = infinity

Here the correct controllability values have not been considered during backwards observability processing

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