VLSI Testing and Testability

Fault Simulation - II

Dr. S. Sivanantham
School of Electronics Engineering
VIT University
Vellore 632014
INIDA
VLSI Testing and Testability
 Parallel Fault Simulation

 Good and faulty ckts, say ‘W’ are simulated together

 A set of ‘F’ faults require [F/W] passes

 Compiled-code method; best with two-states (0,1)

 Exploits inherent bit-parallelism of logic operations on computer
words
 Storage: one word per line for two-state simulation
 Multi-pass simulation: Each pass simulates w-1 new faults, where w is
the machine word length
 Speed up over serial method ~ w-1
 Not suitable for circuits with timing-critical and non-Boolean logic

VLSI Testing and Testability

 Parallel fault simulation (1)
• Modern computer process 32-bit or 64-bit operands in one pass; this
wide word size is used to store several copies of a signal and process
all in one parallel pass

• … under following assumptions ….

– the circuit consists of only logic gates, with unit delays
– only stuck-at faults are simulated
all signals assuming
– Rx Ry values either 1Thisoronly0bit used in serial simulation
driving signal All w-bits (8 bits here) used in parallel
simulation where 1 bit stores the true
AND

value (dark bit)

ALU

Rx

VLSI Testing and Testability

 Parallel fault simulation (2)
• Multi-pass simulation
Each pass simulates w-1 new faults, where w is the machine word
length (16-bit, 32-bit, …)

• Speed up over the serial method ~ w-1

one bit-position is reserved for the signal value of the
fault-free circuit

• Not suitable for non-Boolean logic

VLSI Testing and Testability

 Parallel simulation example (1)
• Two single stuck-at faults are injected into the circuit in next slide
c s-a-0, and f s-a-1

• The word length considered is w=3, i.e. all signals in a particular node are
expressed in a three-bit format where
– bit-0 is the signal value of the fault-free circuit
– bit-1 is the signal value of the circuit assuming c s-a-1
– bit-2 is the signal value of the circuit assuming f s-a-0

• All bits forming a 3-bit word are updated simultaneously, according to the
logical function to be processed

• All faults causing word bits of value at the circuit output that differ from the
fault free circuit are declare detected
VLSI Testing and Testability
Parallel simulation example (2)
Bit 0: fault-free circuit
Bit 1: circuit with c s-a-1
Bit 2: circuit with f s-a-0
f s-a-0 can not be detected
using this specific vector
c s-a-1 detected

0 0 0
0 1 0
a
s-a-1
b e
c
0 0 0 0 1 0 0 1 0

d f s-a-0

1 1 1 1 1 0

VLSI Testing and Testability

 Actual implementation in the
simulator
• Faults are modeled by superimposing logic gates into the circuit
– s-a-0  AND2 gate (2-input AND gate)
all other input bits set to 1, except a 0 at the bit-location of
the fault
– s-a-1  OR2 gate
0 0 all
0 other input bits set to 0,
0 except
1 0 a 1 at the bit-location
a of the fault
s-a-1
b e
c
0 0 0 0 1 0 0 1 0

g
0 1 0 1 1 1
d f
1 1 0

s-a-0
1 1 0

VLSI Testing and Testability

 Parallel Fault Sim. Example

Bit 0: fault-free circuit

Bit 1: circuit with c s-a-0
Bit 2: circuit with f s-a-1

1 1 1
c s-a-0 detected
a 1 0 1
1 1 1 1 0 1
b e
1 0 1
c s-a-0 g
0 0 0

d f s-a-1 0 0 1

VLSI Testing and Testability