Computer Logic Design

Fall 2006 Semester

Sessional 1 Solution
Total Marks: 50

Course Instructors:
Usman Khalid / Azhar Rauf
Problem 1: Points: 6
Given the following binary circuit plot the value of X on the timing
diagram

A
B
C
D
E

Solution:
As
Therefore

X = (A’B’+ C) (D+E’)
X = A’B’D + A’B’E’ + CD + CE’
So whenever any one of the product terms is high X goes high
 A B C D E X Reason
0 0 1 1 1 1 CD is high
1 1 1 0 1 0
0 0 1 1 0 1 DE’ and CD is high
1 0 0 0 1 0
0 0 0 0 0 1 A’B’E’ is high
1 1 1 1 0 1 CD and DE’ is high
0 0 0 1 1 1 A’B’D is high

So the waveform is:

X
Problem 2: Points: 12
Given the following Boolean function that spans five dimensions
F(A,B,C,D,E) = AC’ + ACE+ ACE’ + A’CD’+ A’D’E’

a. Implement function F using logic gates

b. Convert the circuit obtained in part a. to equivalent NOR Gate
Circuitry
c. Optimize the number of gates using any logic reduction
technique

Solution:
a. Implement function F using logic gates
F = AC’ + ACE+ ACE’ + A’CD’+ A’D’E’
b. Convert the circuit obtained in part a. to equivalent NOR Gate
Circuitry
F = (((A’+C)’+ (A’+C’+E’)’ +(A’+C’+E)’ + (A+C’+D)’+ (A+D+E)’)’)’

c. Optimize the number of gates using any logic reduction technique

i. Using Boolean algebra

F = AC’ + ACE+ ACE’ + A’CD’+ A’D’E’
F = AC’ + AC (E +E’) + A’CD’ + A’D’E’
As E + E’ = 1
F = AC’ + AC +A’CD’ + A’D’E’
F = A(C+C’) +A’CD’ + A’D’E’
F = A +A’CD’+ A’D’E’
F = A + A’(CD’ +D’E’)
As X+YZ = (X+Y)(X+Z) hence
F = (A + A’)(A + CD’ +D’E’)
Hence
F = A + CD’ +D’E’

ii. Using Karnaugh Map

Since B is not included in the function so a four variable Karnaugh
Map is required

Optimization

This implies
F = A + CD’ + D’E’
Problem 3: Points: 10
Design a combinational circuit with three inputs x, y and z and three
outputs A, B and C. When the binary input is 0,1,2 or 3, the binary
output is one greater than the input, When the binary input is 4,5,6 or
7, the binary output is one less than the input.

Solution:
Inputs Outputs
X Y Z A B C
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 0 1 1
1 0 1 1 0 0
1 1 0 1 0 1
1 1 1 1 1 0

For A

A = XZ + YZ + XY
For B

B = X’Y’Z + X’YZ’ + XY’Z’ + XYZ

= X xor Y xor Z

For C

C = Z’
Problem 4: Points: 6
a. Convert the even parity number 100110100 where parity is
attached to the most significant bit to a BCD

b. Design a 3-bit odd/even parity generator circuit with a control bit

such that when a control bit is one even parity circuit is
activated otherwise the odd parity circuit is active.

Solution:
a. Convert the even parity number 100110100 where parity is
attached to the most significant bit to a BCD

100110100
After removing the parity bit we are left with
00110100

Weights 128 64 32 16 8 4 2 1
Binary 0 0 1 1 0 1 0 0
Decimal 32+16+4 = 52
BCD 0 1 0 1 0 0 1 0

b. Design a 3-bit odd/even parity generator circuit with a control bit

such that when a control bit is one even parity circuit is activated
otherwise the odd parity circuit is active.
Problem 5: Points: 6
Optimize the given Truth Table using K-map for minimized POS
where ‘X’ denotes the ‘Don’t Care inputs’

J K L M F
0 0 0 0 X
0 0 0 1 0
0 0 1 0 1
0 0 1 1 X
0 1 0 0 X
0 1 0 1 1
0 1 1 0 0
0 1 1 1 X
1 0 0 0 X
1 0 0 1 X
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
Solution:

F = (K’ +M)(K + M’)

Problem 6: Points: 10
a. Derive equations for full and half adders
b. Show how full adder may be implemented using two half
adders.

Solution:
a. Derive equations for full and half adders
Half Adder: (without any carry in)
A B Cout Sum
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
This implies
Sum = A xor B
Cout = AB

Full Adder: (with Carry in)

Cin A B Cout Sum
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

This implies

Sum = A xor B xor C

For Cout

Cout = AB + CinA’B + CinAB’

Cout = AB + Cin(A’B + AB’)
Cout = AB + Cin(A xor B)

b. Show how full adder may be implemented using two half adders.

Comparing full adder and half adder equations

Sum = A xor B Sum = A xor B xor C

Cout = AB Cout = AB + Cin(A xor B)

This implies