ARM Architecture

The ARM Architecture
The ARM Architecture
www.pantechsolutions.net
Agenda
g
• Introduction to ARM Ltd
Introduction to ARM Ltd
• Programmers Model
Programmers Model
• Instruction Set
• System Design
• Development Tools
ARM Ltd.,,
• Founded in 1990
Founded in 1990
– Spun out of Acorn Computers
• Designs the ARM range of RISC processor
• Licenses ARM core for Design Partners
Licenses ARM core for Design Partners
– ARM does not fabricate Silicon on own
• Develops technology to assist with ARM Arch.
– Software Tools
– Boards | Debug Hardware | Peripherals
– Application Software | Bus Architecture
IP – Intellectual Property
p y
• ARM provides hard and soft views to licensees
ARM provides hard and soft views to licensees
– RTL and Synthesis Overflow
– GDSII Layout
GDSII L t
• Licensees have the right to use hard or soft views
g
of the IP
– Soft views include gate level net‐list
– Hard view are DSMs
• OEMs must use Hard Views
– To protect ARM IP
To protect ARM IP
ARM Overview
Silicon
IP Core
Manufacturer
RTL / GDSII
NXP | Atmel |
Layout
y
SAMSUNG | INTEL
SAMSUNG | INTEL
Development IAR
Tools KEIL
IDE/Debugger Realview…
ICE
ARM Overview
• Shipped in excess of 10 billion units since 1990.
Shipped in excess of 10 billion units since 1990
• Over 1300 new chip designs with ARM IP in 2007
p g
• Licensed by majority of world’s leading
Semiconductor manufacturers
• At least 90 processors are shipped every second.
• isuppli
i li predicts over 5 billion chips/year will
di 5 billi hi / ill
ship in 2011
ship in 2011.
Markets
The FIVE key markets are:
Embedded Enterprise Home Mobile Emerging

Solutions Solutions Solutions Solutions Applications
• Smart
Smart Cards
Cards • Flash Cards
Flash Cards • Still Cameras
Still Cameras • Bluetooth
Bluetooth • Gaming
• Automotive • Hard Disks • Digital TV • PDA • Robot
• Dashboard • Printers • Set Top Box • Smart Phone • And much
Controls more….
90 % of the mobile handsets
use ARM Technology
Processor Licensee
• ARM licenses its microprocessor IP to majority of
ARM licenses its microprocessor IP to majority of
the semiconductor companies.
p
Familyy Licenses
CortexTM 47
ARM11TM 66
ARM9TM 247
ARM7TM 155
Whyy ARM ?
• Built in architecture extensions
– THUMB®2 ‐ Greatly improved code density
THUMB®2 G tl i d d d it
– DSP ‐ Signal process directly in the RISC core
– J ll ®
Jazelle® ‐ J
Java acceleration
l i
– Trustzone™ ‐ Maximum Security Environment
• Core Performance
• Tools of Choice
• Wide Support
Wid S t
• Low Power Consumption
Low Power Consumption
Architecture Extensions
• Improved Code Density
Improved Code Density
• Improved Performance
Improved Performance
• Power Efficiencyy
Architecture Extensions…
• The TrustZone
The TrustZone®
– Provide a Trusted Execution Environment (TEE)
– Consistent programming model across platforms and
applications
– Hardware backed security environment
Architecture Extensions…
• Jazelle
Jazelle®
– Technology to enable Jazelle H/w in any existing JVM
– Full featured multi‐tasking Java Virtual Machine JVM
– Enables acceleration of execution environments
Apple iPhone
www.pantechsolutions.net Key Design Win for NXP ARM
12 Logic
12 Logic 5$ – 6 $
5$ 6$
LPC2211 PMU
Parts content
2007
• 4 ‐ 5 Mega Units 2008
• 10 Mega Units
Significant Design-
Design-Win
www.pantechsolutions.net Americas:
Q4 2006
Significance Used LPC900 MCUs to beat Automation Bank machine can
be chosen as world platform by
Microchip on high volume
consumer product
consumer product
Diebold.
Customer Diebold ‐ Procomp
MMS DW LPC2144FBD64‐S Provides stronger security

Product system in this kind of product
product.
Other
NXP/MMS
part types
End Product Automation Bank Machine
Application Baking
Quantity 50k units
(EAU)
V l (3yr/5yr
Value (3 /5 $1 00 mil (3yr)
$1.00 mil (3yr)
auto)
NXP NXP MCU is most competitive package product Sales Marcelo Gonçalves
solution
Competitive
Competitive Engineer
Advantage
ARM Partnership
p Model
ARM7 Familyy
• ARM7 Family Includes…
ARM7 Family Includes
ARM7TDMI ARM7EJ‐S
• T ‐ Thumb® instruction set • E – DSP Extension
• D ‐ Debug extension • J – Jazelle®, Java Extension
• M‐Enhanced multiplier (32x8) • S – Synthesizable
• I‐Embedded ICE
ARM7TDMI‐S (ARM v4T) ARM720T
• T
T ‐ Thumb
Thumb® instruction set
instruction set • T
T – Thumb
• D ‐ Debug extension • Uses ARM7TDMI‐S CPU
• M‐Enhanced multiplier (32x8) • MMU Included
• I‐Embedded ICE
• S –
S Synthesizable Macro
S h i bl
End Products
Agenda
g
Programmers Model
• Instruction Set
• System Design
Bus Width
• ARM7 is a 32‐bit architecture
ARM7 is a 32‐bit architecture
• Data Paths and Instructions (ARM) are 32 bits wide
( )
• Von‐Neumann Architecture
– Instructions and Data use
same bus
• Thumb Mode
– Subset of 16‐bit instructions
S b t f 16 bit i t ti
– Code density optimization
Data and Instruction
• DATA when used in ARM
DATA when used in ARM
– Byte : 8 bits
– Half Word : 16 bits (2 Bytes)
– Word : 32 bits (4 Bytes)
• Instruction Set of most ARMs
– 32 bits ARM Instruction Set
– 16 bits Thumb Instruction Set
Processor Modes
• Unprivileged Mode
User • Most tasks run on this mode
FIQ • Entered when a high priority Interrupt is occurred
IRQ • Entered when a low priority interrupt (normal) is
occurred
• Entered on Reset
E t d R t
Supervisory • Entered on Software Interrupt
Abort • To handle memory access violations
T h dl i l ti
Undefined • To handle un‐defined instructions
System
y • Privileged mode using the same registers as user mode
The ARM Register
g Set
Current Visible Registers
Current Visible Registers
r0
Abort
Undef
SVC
IRQ
FIQ
User Mode
Mode
Mode
Mode r1
r2
r3 Banked out Registers
r4
r5
r6 User FIQ IRQ SVC Undef Abort
r7
r8 r8 r8
r9 r9 r9
r10 r10 r10
r11 r11 r11
r12 r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)
cpsr
spsr spsr spsr spsr spsr spsr
Register
g Organization
g Summary
y
User FIQ IRQ SVC Undef Abort
r0
r1
User
r2 mode
r3 r0-r7,
r4 r15, User User User User
r5 and mode mode mode mode Thumb state
cpsr r0-r12, r0-r12, r0-r12, r0-r12, Low registers
r6
r15, r15, r15, r15,
r7 and and and and
r8
8 r8
8 cpsr cpsr cpsr cpsr
r9 r9
r10 r10 Thumb state
r11 r11 High registers
r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)
cpsr
spsr spsr spsr spsr spsr
Note: System mode uses the User mode register set

The Registers
g
• ARM has 37 registers all of which are 32 bits long
– 1 dedicated Program Counter
– 1 dedicated Current Program Status Register (CPSR)
– 5 dedicated Saved Program Status Register (SPSR)
5 dedicated Saved Program Status Register (SPSR)
– 30 General Purpose Register
• The current processor mode governs the access of register banks
p g g
– A particular set of r0‐r12 registers
– A particular r13 (stack pointer) and r14 (link register, LR)
– The program counter (PC)
The program counter (PC)
– The current program status register (CPSR)
• Privileged Mode can access
Privileged Mode can access
– A particular SPSR (Saved Program Status Register)
Program Status Registers
31 28 27 24 23 16 15 8 7 6 5 4 0
N Z C V Q J U n d e f i n e d I F T mode
f s x c
• Condition code flags • Interrupt Disable bits.
p
– N = Negative result from ALU
– Z = Zero result from ALU – I = 1: Disables the IRQ.
– C = ALU operation Carried out – F = 1: Disables the FIQ.
– V = ALU operation overflowed
V = ALU operation overflowed
• T Bit
• Sticky Overflow flag ‐ Q flag
– Architecture xT only
Architecture 5TE/J only
– Architecture 5TE/J only
– T = 0: Processor in ARM state
– Indicates if saturation has
occurred – T = 1: Processor in Thumb
state
• J bit
– Architecture 5TEJ only • Mode bits
– J = 1: Processor in Jazelle
J = 1: Processor in Jazelle – Specify the processor mode
Specify the processor mode
state
Program
g Counter ((r15))
• When the processor is executing in ARM state:
– All
All instructions are 32 bits wide
i t ti 32 bit id
– All instructions must be word aligned
– Therefore the pc
p value is stored in bits [31:2] with bits [1:0]
[ ] [ ]
undefined (as instruction cannot be halfword or byte aligned).
• When the processor is executing in Thumb state:

When the processor is executing in Thumb state:
– All instructions are 16 bits wide
– All instructions must be halfword aligned
– Therefore the pc value is stored in bits [31:1] with bit [0]
undefined (as instruction cannot be byte aligned).
• When the processor is executing in Jazelle state:
– All instructions are 8 bits wide
– Processor performs a word access to read 4 instructions at once
Processor performs a ord access to read 4 instr ctions at once
Exception
p Handling
g
• When an exception occurs, the ARM:
– Copies CPSR into SPSR_<mode>
– Sets appropriate CPSR bits
• Change to ARM state 0x1C FIQ
• Change to exception mode 0x18 IRQ
• Disable interrupts (if appropriate)
p ( pp p ) 0x14 (Reserved)
0x10 Data Abort
– Stores the return address in LR_<mode>
0x0C Prefetch Abort
– Sets PC to vector address 0x08 Software Interrupt
• To return, exception handler needs to: 0x04 Undefined Instruction

0x00 Reset
– Restore CPSR from SPSR_<mode>
Vector Table
– Restore PC from LR_<mode> Vector table can be at
This can only be done in ARM state. 0xFFFF0000 on ARM720T
and on ARM9/10 family y devices
Development
p of ARM Architecture
Improved
Halfword 5 TE Jazelle
and signed
4 ARM/Thumb
Interworking Java bytecode 5 TEJ
1 halfword / C LZ execution
byte support
System SA-110 Saturated maths ARM9EJ-S ARM926EJ-S
2 mode
py
DSP multiply-
SA 1110
SA-1110 ARM7EJ S
ARM7EJ-S ARM1026EJ S
ARM1026EJ-S
accumulate
instructions
3 ARM1020E SIMD Instructions
Thumb
instruction 4T Multi-processing
6
set XScale
Early ARM V6 Memory
architectures architecture (VMSA)
ARM7TDMI ARM9TDMI ARM9E S
ARM9E-S
Unaligned data
ARM720T ARM940T ARM966E-S support ARM1136EJ-S
Agenda
g
Programmers Model
• Instruction Set
• System Design
ARM7 TDMI - S
• The ARM7TDMI‐S is based on ARM7 Core
The ARM7TDMI S is based on ARM7 Core
– 3 Stage Pipeline
– Von‐Neumann Architecture
– CPI ~ 1.9
• T – Thumb instruction Sets
• D – includes debug extensions
• M – Enhanced Multipliers
• I – Core has Embedded ICE logic extensions
• S – Fully Synthesizable soft IP
Instruction Pipeline
p
• The ARM7TDMI
The ARM7TDMI‐SS core uses a pipeline
core uses a pipeline
– Increase the speed of the flow of instructions
– Enables several operations to take place
E bl l ti t t k l
simultaneously
– Program Counter (PC) points to instruction being
Program Counter (PC) points to instruction being
fetched rather than that being executed
• During normal pipelined operation
l l d
– An instruction x is executed
– Instruction (x‐1) is being decoded
– Instructino (x‐2) is being fetched
3-Stage Instruction Pipeline
ARM Thumb
PC PC Fetch Instruction Fetched from Memoryy
Thumb only: Thumb instruction
Thumb only: Thumb instruction
PC ‐ 4 PC ‐ 2 Decode decompressed to ARM instruction
Instruction decoded
PC ‐ 8 PC ‐ 4 Execute Registers read from Register Bank,

Shift and ALU operations performed,
Registers written back to Register Bank
Optimal Pipelining
• In this example it takes 6 clock cycles to execute 6 instructions
• All operations are on registers (single cycle instructions)

All operations are on registers (single cycle instructions)
• Clock cycles per instruction (CPI) = 1
ADD Fetch Decode Execute

SUB Fetch Decode Execute
MOV Fetch Decode Execute
AND Fetch Decode Execute
ORR Fetch Decode Execute
EOR Fetch Decode Execute
CMP Fetch Decode
RSB Fetch
1 2 3 4 5 6 7 8
y
Cycle
Branch Pipeline Example
• Branches break the pipeline
• Example in ARM state
BL 0x8000 Fetch Decode Execute Linkret Adjust

X 0x8004 Fetch Decode
X 0x8008 Fetch
ADD 0x8FEC Fetch Decode Execute
SUB 0x8FF0 Fetch Decode Execute
MOV 0x8FF4 Fetch Decode
AND 0x8FF8 Fetch
1 2 3 4 5 6 7
Cycle
Instruction Set
• All instructions are 32‐bits long
All instructions are 32 bits long
• Many instructions execute in a single cycle
• Instructions are conditionally executed
• ARM is a load / store architecture
ARM is a load / store architecture
– via registers => RISC
• Load or store multiple registers in a single instruction
using <register list>
Conditional Execution
Mnemonic Description
EQ Equal
NE Not equal
CS / HS Carry Set / Unsigned higher or same
CC / LO Carry Clear / Unsigned lower
MI Negative
PL Positive or zero
VS Overflow
VC No overflow
HI Unsigned higher
LS Unsigned lower or same
GE Signed greater than or equal
LT Signed less than
GT Signed greater than
LE Signed less than or equal
AL Always (normally omitted)
Thumb Instruction Set ((1))
• Instruction Types
– Branch
• Unconditional ± 2KBytes
• Conditional ± 256Bytes
• Branch with Link y
± 4MBytes ((2 Instructions!))
• Branch and exchange change to ARM state if Rm[0] = 0
• Branch and exchange with Link
Branch and exchange with Link
– Data Processing
• Subset of ARM data processing instructions
Subset of ARM data processing instructions
• Not conditionally executed (but some update flags)
ARM and Thumb Interworking
g
• Switch between ARM state and Thumb state using BX instruction
– In ARM state:
In ARM state BX<condition> Rn
BX<condition> Rn
– In Thumb state: BX Rn
31 1 0
Rn
n: 0-15
0 15
ARM / Thumb selection

0: ARM state
BX 1: Thumb state
31 1 0
Destination
address 0
Agenda
g
Programmers Model
• Instruction Set
• System Design
Example
p ARM based System
y
RAM ARM core
16 bit wide
Interrupt I / O
Peripherals
Controller
ROM
8 bit wide RAM
32 bit wide
• Advanced Microcontroller Bus Architecture
Ad d Mi t ll B A hit t
– on‐chip interconnect
p
– established, open specification
– framework for SoC designs
– enabler for IP reuse
enabler for IP reuse
– ‘digital glue’ that binds IP cores together
Example
p AMBA System
y
ARM core
Keypad
UART
High‐
bandwidth AHB APB APB Timer
M
Memory Bridge
Interface
Display
RTC
High‐bandwidth on‐ DMA Bus
chip RAM
h M t
Master
I/O
AHB and APB / VPB
• Advanced High‐Performance Bus
– high‐performance
high performance
– pipelined
– fully‐synchronous backplane
f ll h b k l
– multiple bus masters
• Advanced Peripheral Bus / VLSI Peripheral Bus
– low‐power
– non‐pipelined
– simple interface
p
– wait support (VPB)
Agenda
g
Programmers Model
• Instruction Set
• System Design
The RealView Product Families
Compilation Tools Debug Tools Platforms

ARM Developer Suite (ADS) – AXD (part of ADS) ARMulator (part of ADS)
Compilers (C/C++ ARM & Thumb), Trace Debug Tools Integrator™ Family
Li k & Utilities
Linker Utiliti
Multi-ICE
Multi-Trace
RealView Compilation Tools (RVCT) RealView Debugger (RVD) RealView ARMulator ISS (RVISS)
RealView ICE (RVI)
RealView Trace (RVT)
ARM Debug
g Architecture
Ethernet
Debugger (+ optional
trace tools)
JTAG port Trace Port

• EmbeddedICE Logic
– Provides breakpoints and processor/system access
TAP
• JTAG interface (ICE) controller
– Converts debugger commands to JTAG signals
Converts debugger commands to JTAG signals ETM
• Embedded trace Macrocell (ETM) EmbeddedICE
– Compresses real‐time instruction and data access Logic
trace
– Contains ICE features (trigger & filter logic)
• Trace port analyzer (TPA) ARM
core
– Captures trace in a deep buffer
References
• www.arm.com
www arm com
• http://www.arm.com/markets/
• http://in.youtube.com/watch?v=4VRtujwa_b8
p // y / j _
– ARM Webinars | ARM Video Search
• http://infocenter.arm.com/help/index.jsp?topic=/
com arm doc set appnotes/
com.arm.doc.set.appnotes/
References
Questions ?

ARM Architecture

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ARM Architecture

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The ARM Architecture

The ARM Architecture

Embedded Enterprise Home Mobile Emerging

MMS DW LPC2144FBD64‐S Provides stronger security

Note: System mode uses the User mode register set

• When the processor is executing in Thumb state:

• To return, exception handler needs to: 0x04 Undefined Instruction

PC ‐ 8 PC ‐ 4 Execute Registers read from Register Bank,

• All operations are on registers (single cycle instructions)

ADD Fetch Decode Execute

BL 0x8000 Fetch Decode Execute Linkret Adjust

ARM / Thumb selection

Compilation Tools Debug Tools Platforms

JTAG port Trace Port

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