AN43 M.2 Pinout Descriptions and Reference Designs

Application Note
congatec Application Note
Affected Products All products
Subject M.2™ Pinout Descriptions and Reference Designs
Confidential/Public Public
Author SDA
Copyright © 2020 congatec AG AN43 M.2 Pinout Descriptions and Reference Designs 1/14
Printed versions of this document are not under revision control
Application Note
Revision History
Revision Date (yyyy-mm-dd) Author Changes
1.0 2020-01-28 SDA First release
Application Note
Preface
This application note provides the pinout description, reference design and design notes
for each of the three M.2™ sockets commonly implemented on embedded systems
(Socket 1 – Key E, Socket 2 – Key B, and Socket 3 – Key M).
Disclaimer
The information contained within this Application Note, including but not limited to any
product specification, is subject to change without notice.
congatec AG provides no warranty with regard to this Application Note or any other
information contained herein and hereby expressly disclaims any implied warranties of
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information contained herein or the use thereof.
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Application Note
Symbols
The following are symbols used in this application note.
Note
Notes call attention to important information that should be observed.
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Cautions warn the user about how to prevent damage to hardware or loss of data.
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Application Note
1 Introduction
This application note provides the pinout description, reference design, and design notes
for three M.2™ sockets and respective interfaces commonly used on embedded systems:
• Socket 1 – Key E (Section 2 of this application note)
• Socket 2 – Key B (Section 3 of this application note)
• Socket 3 – Key M (Section 4 of this application note)
Additional information is provided for sockets with configuration pins.
For information about less commonly used sockets and respective interfaces (e.g. SDIO,
I2S, UART), refer to the PCI Express M.2 Specification available for purchase from PCI-SIG
(https://pcisig.com).
Note
The content of this application note is based on the PCI Express M.2 Specification
Revision 3.0, Version 1.2.
Application Note
2 Socket 1 – Key E
2.1 Pinout Description
74 3.3V GND 75
72 3.3V RESERVED/REFCLKn1 73
70 UIM_POWER_SRC/GPIO_1/PEWAKE1# RESERVED/REFCLKp1 71
68 UIM_POWER_SNK/CLKREQ1# GND 69
66 UIM_SWP/PERST1# RESERVED/PERn1 67
64 RESERVED RESERVED/PERp1 65
62 ALERT# (I)(0/1.8 V) GND 63
60 I2C_CLK (O)(0/1.8 V) RESERVED/PETn1 61
58 I2C_DATA (I/O)(0/1.8 V) RESERVED/PETp1 59
56 W_DISABLE1# (O)(0/3.3V) GND 57
54 W_DISABLE2# (O)(0/3.3V) PEWAKE0# (I/O)(0/3.3V) 55
52 PERST0# (O)(0/3.3V) CLKREQ0# (I/O)(0/3.3V) 53
50 SUSCLK(32kHz) (O)(0/3.3V) GND 51
48 COEX_TXD (O)(0/1.8V) REFCLKn0 49
46 COEX_RXD (I)(0/1.8V) REFCLKp0 47
44 COEX3 (I/O)(0/1.8V) GND 45
42 VENDOR DEFINED PERn0 43
40 VENDOR DEFINED PERp0 41
38 VENDOR DEFINED GND 39
36 UART RTS (O)(0/1.8V) PETn0 37
34 UART CTS (I)(0/1.8V) PETp0 35
32 UART TXD (O)(0/1.8V) GND 33
Key E Key E
Key E Key E
Key E Key E
Key E Key E
Key E SDIO RESET#/TX_BLANKING (O)(0/1.8V) 23
22 UART RXD (I)(0/1.8V) SDIO WAKE# (I)(0/1.8V) 21
20 UART WAKE# (I)(0/3.3V) SDIO DATA3(I/O)(0/1.8V) 19
18 GND SDIO DATA2(I/O)(0/1.8V) 17
16 LED_2# (I)(OD) SDIO DATA1(I/O)(0/1.8V) 15
14 PCM_OUT/I2S SD_OUT (O)(0/1.8V) SDIO DATA0(I/O)(0/1.8V) 13
12 PCM_IN/I2S SD_IN (I)(0/1.8V) SDIO CMD(I/O)(0/1.8V) 11
10 PCM_SYNC/I2S WS (I/O)(0/1.8V) SDIO CLK/SYSCLK (O)(0/1.8V) 9
8 PCM_CLK/I2S SCK (I/O)(0/1.8V) GND 7
6 LED_1# (I)(OD) USB_D- 5
4 3.3V USB_D+ 3
2 3.3V GND 1
Application Note
2.2 Reference Design

+V3.3
FB1 X11
FBD90R0A28S05D_HF C1 C2 C3
4 3 2 C100nS02V16X C10uS03V10X C22uS05V6X
USB+ USB+_CM 3 VCC_3P3 4
M.2 Slot 1 - SDIO Pinout
1 2 USB-_CM 5 USB_D+ Key E VCC_3P3 72
USB- USB_D- VCC_3P3 74
VCC_3P3
PCIE_CLK+ 47 62 ALERT#_1V8
PCIE_CLK+ PCIE_CLK- 49 PCIE_REFCLK+ ALERT#_1P8 60 I2C_CLK_1V8 ALERT#_1V8
SM B
PCIE_CLK- PCIE_REFCLK- I2C_CLK_1P8 58 I2C_DAT_1V8 I2C_CLK_1V8
PCIE_RX+ 41 I2C_DAT_1P8 I2C_DAT_1V8
PCIE_RX+ PCIE_RX- 43 PCIE_RX0+
PCIE_RX- PCIE_RX0- 71
PC Ie0
PCIE_TX+ 35 RSVD/PCIE_REFCLK1+ 73
PCIE_TX+ PCIE_TX- 37 PCIE_TX0+ RSVD/PCIE_REFCLK1-
PCIE_TX- PCIE_TX0- 65
PC Ie1
PCIE_WAKE# 55 RSVD/PCIE_RX1+ 67
PCIE_WAKE# CLKREQ# 53 PEWAKE0#_3P3 RSVD/PCIE_RX1-
CLKREQ# PCIE_RST# 52 CLKREQ0#_3P3 59
PCIE_RST# PERST0#_3P3 RSVD/PCIE_TX1+ 61
RSVD/PCIE_TX1-
SDIO_CLK_1V8* 9
SDIO_CLK_1V8* SDIO_CMD_1V8* 11 SDIO_CLK_1P8 68
SDIO_CMD_1V8* SDIO_D0_1V8* 13 SDIO_CMD_1P8 UIM_PWR_SNK/CLKREQ1# 66
U IM
SDIO_D0_1V8* SDIO_D1_1V8* 15 SDIO_DAT0_1P8 UIM_SWP/PERST1# 70

SDIO_D1_1V8* SDIO_D2_1V8* 17 SDIO_DAT1_1P8 UIM_PWR_SRC/GPIO1/PEWAKE1#
SD IO
SDIO_D2_1V8* SDIO_D3_1V8* 19 SDIO_DAT2_1P8

SDIO_D3_1V8* SDIO RESET#_PWREN_1V8* 23 SDIO_DAT3_1P8 44 +V3.3
SDIO RESET#_PWREN_1V8* SDIO_WAKE#_1V8** 21 SDIO_RESET#_1P8 COEX3_1P8 46
SDIO_WAKE#_1V8** SDIO_WAKE#_1P8 COEX2_1P8 48 D1 DLED0603Y EL R1 R1%220RS02
COEX1_1P8 50
C OM M
I2S_CLK_1V8* 8 SUSCLK_3P3 16 D2 DLED0603Y EL R2 R1%220RS02

I2S_CLK_1V8* I2S_LRCLK_1V8* 10 PCM_CLK/I2S_SCK_1P8 LED2#_OD 6
I2S_LRCLK_1V8* I2S_SDIN_1V8* 12 PCM_SY NC/I2S_WS_1P8 LED1#_OD 54 M1
I2S
I2S_SDIN_1V8* I2S_SDOUT_1V8* 14 PCM_IN/I2S_SDI_1P8 W_DISABLE2#_3P3 56

I2S_SDOUT_1V8* PCM_OUT/I2S_SDO_1P8 W_DISABLE1#_3P3 1 ON 4
1
UART_TX_1V8 32 1 2 3
DCDS2C05GTA
DCDS2C05GTA
UART_TX_1V8 UART_RX_1V8 22 UART_TXD_1P8 GND 7 2
UART_RX_1V8 UART_RTS_1V8 36 UART_RXD_1P8 GND 18
U AR T
UART_RTS_1V8 UART_CTS_1V8 34 UART_RTS_1P8 GND 33

UART_CTS_1V8 UART_WAKE#_3V3** 20 UART_CTS_1P8 GND 39 MDIPSW2_IT
D13
D14
UART_WAKE#_3V3** UART_WAKE#_3P3 GND 45
GND 51
64 GND 57
42 RSVD GND 63
40 VENDOR_DEF3 GND 69
38 VENDOR_DEF2 GND 75
VENDOR_DEF1 GND
XPCIE_M2_4MM2_E_3030
Figure 1: Socket 1 - Key E Reference Design
2.3 Design Notes

The reference design above (Figure 1) shows an M.2 Socket 1 – Key E used for connectivity
applications. M.2 WiFi/Bluetooth expansion cards are usually connected via PCIe and USB.
Other buses (e.g. SDIO and I2S) may not be supported by the COM.
The AC coupling capacitors are placed on the COM for the PCIE_TX+/- signals and for the
PCIE_RX+/- signals on the M.2 expansion card. Therefore, it is not required to place AC
coupling capacitors on the carrier board.
The M.2 clock request signal (CLKREQ#) enables the PCIe reference clock and should be
connected to the output enable pin of the PCIe clock buffer. As the CLKREQ# signal is an
active low, open drain output of the M.2 expansion card, a pull-up resistor is required on
the carrier board.
Application Note
3 Socket 2 – Key B
74 3.3 V/VBAT CONFIG_2 75
72 3.3 V/VBAT GND 73
70 3.3 V/VBAT GND 71
68 SUSCLK(32kHz) (O)(0/3.3V) CONFIG_1 69
66 SIM DETECT (O) RESET# (O)(0/1.8V) 67
64 COEX_RXD (I)(0/1.8V) ANTCTL3 (I)(0/1.8V) 65
62 COEX_TXD (O)(0/1.8V) ANTCTL2 (I)(0/1.8V) 63
60 COEX3 (I/O)(0/1.8V) ANTCTL1 (I)(0/1.8V) 61
58 NC ANTCTL0 (I)(0/1.8V) 59
56 NC GND 57
54 PEWAKE# (I/O)(0/3.3V) REFCLKp 55
52 CLKREQ# (I/O)(0/3.3V) REFCLKn 53
50 PERST# (O)(0/3.3V) GND 51
48 GPIO_4 (I/O)(0/1.8V) PETp0/SATA-A+ 49
46 GPIO_3 (I/O)(0/1.8V) PETn0/SATA-A- 47
44 GPIO_2 (I/O)/ALERT# (I)/(0/1.8V) GND 45
42 GPIO_1 (I/O)/SMB_DATA (I/O)/(0/1.8V) PERp0/SATA-B- 43
40 GPIO_0 (I/O)/SMB_CLK (I/O)/(0/1.8V) PERn0/SATA-B+ 41
38 DEVSLP (O) GND 39
36 UIM-PWR (I) PETp1/USB3.1-Tx+/SSIC-TxP 37
34 UIM-DATA (I/O) PETn1/USB3.1-Tx-/SSIC-TxN 35
32 UIM-CLK (I) GND 33
30 UIM-RESET (I) PERp1/USB3.1-Rx+/SSIC-RxP 31
28 GPIO_8 (I/O) (0/1.8V) PERn1/USB3.1-Rx-/SSIC-RxN 29
26 GPIO_10 (I/O) (0/1.8V) GND 27
24 GPIO_7 (I/O) (0/1.8V) DPR (O) (0/1.8V) 25
22 GPIO_6 (I/O)(0/1.8V) GPIO_11 (I/O) (0/1.8V) 23
20 GPIO_5 (I/O)(0/1.8V) CONFIG_0 21
Key B Key B
Key B Key B
Key B Key B
Key B Key B
Key B GND 11
10 GPIO_9/DAS/DSS (I/O)/LED_1# (I)(0/3.3V) USB_D- 9
8 W_DISABLE1# (O)(0/3.3V) USB_D+ 7
6 FULL_CARD_POWER_OFF# (O)(0/1.8V or 3.3V) GND 5
4 3.3 V GND 3
2 3.3 V CONFIG_3 1
Application Note
3.1.1 Host Interface Configuration

The four CONFIG_X pins select the intended host interface. The system shall read all four
configuration pins to identify the selected pinout configuration. The system shall pull-up
these configuration pins to an appropriate power rail so the configuration pins can be
read even if the M.2 expansion card is not powered.
The table below shows how the CONFIG_X pins are connected on the M.2 expansion card
to select the required host interface:
CONFIG_0 CONFIG_1 CONFIG_2 CONFIG_3 Host Interface
(Pin 21) (Pin 69) (Pin 75) (Pin 1)
0 0 0 0 SSD - SATA
0 1 0 0 SSD - PCIe
0 0 1 0 WWAN – PCIe (Port Configuration 0*)
0 0 0 1 WWAN – PCIe, USB3.1 Gen1 (Port
Configuration 0*)
Configuration 1*)
Configuration 2*)
Configuration 3*)
1 0 0 0 WWAN – SSIC (Port Configuration 0*)
1 0 1 1 WWAN – PCIe, USB3.1 Gen1 (vendor
defined)
1 1 1 1 No Add-in Card Present
Note
* Refer to the PCI Express M.2 Specification for different port configurations.
Application Note

VCC3V3
FB2
FB220R2A2S03
FB1
FBD90R0A33S05D
USB+ 4 3 X1
USB+ 7 2
USB+_CM VCC3V3 C344 C10uS03V16X
USB- 1 2 USB-_CM 9 USB_D+ M.2 Slot B VCC_3p3 4 C345 C10uS03V16X
USB- USB_D- VCC_3p3 70
Platform Pinout C346 C100nS02V16X
VCC_3p3 72 C347 C10nS02V10X
PCIE_CLK+ 55 VCC_3p3 74 C348 C10nS02V10X
PCIE_CLK+ 53 REFCLKp VCC_3p3
PCIE_CLK-
PCIE_CLK- REFCLKn
PCIE0_TX+_SATA0_TX+ 49 64
PCIE0_TX+_SATA0_TX+ 47 PETp0/SATA_A+ COEX1_1p8 62
PCIE0_TX-_SATA0_TX-
PCIE0_TX-_SATA0_TX- PETn0/SATA_A- COEX2_1p8 60
PCIE0_RX+_SATA0_RX- 43 COEX3_1p8
PCIE0_RX+_SATA0_RX- PCIE0_RX-_SATA0_RX+ 41 PERp0/SATA_B-
PCIE0_RX-_SATA0_RX+ PERn0/SATA_B+ 59
ANTCTL0_1p8 61
PCIE1_TX+ 37 ANTCTL1_1p8 63
PCIE1_TX+ 35 PETp1/USB30_TX+/SSIC_TX+ ANTCTL2_1p8 65
PCIE1_TX-
PCIE1_TX- PETn1/USB30_TX-/SSIC_TX- ANTCTL3_1p8
PCIE1_RX+ 31
PCIE1_RX+ PCIE1_RX- 29 PERp1/USB30_RX+/SSIC_RX+ 36
PCIE1_RX- PERn1/USB30_RX-/SSIC_RX- UIM_PWR 34
UIM_DATA 32
PCIE_WAKE# 54 UIM_CLK 30
PCIE_WAKE# CLKREQ# 52 PEWAKE#_3p3 UIM_RESET VCC3V3
CLKREQ# PCIE_RST# 50 CLKREQ#_3p3 66
PCIE_RST# PERST#_3p3 SIM_DETECT_1p8
67 25 R1
RESET#_1p8 DPR_1p8 R1%10k0S02
40 21 CONFIG_1 = L --> SATA
42 GPIO0_(GNSS_SCL/SIM_DET2)_1p8 CONFIG_0 69 CONFIG_1
44 GPIO1_(GNSS_SDA/UIM_DAT2)_1p8 CONFIG_1 75 CONFIG_1 CONFIG_1 = H --> PCIe
46 GPIO2_(GNSS_IRQ/UIM_CLK2)_1p8 CONFIG_2 1
48 GPIO3_(SY SCLK/GNSS_0/UIM_RST2)_1p8 CONFIG_3
20 GPIO4_(TX_BLK/GNSS_1/UIM_PWR2)_1p8
22 GPIO5_(AUDIO0/RFU)_1p8 56
24 GPIO6_(AUDIO1/RFU)_1p8 MFG_DAT 58
28 GPIO7_(AUDIO2/RFU)_1p8 MFG_CLK
10 GPIO8_(AUDIO3/RFU)_1p8 M1
26 GPIO9_(LED1#/DAS_DSS#)_3p3 M1 M2
23 GPIO10_(W_DISABLE_2#)_1p8 M2
GPIO11_(WoWWAN#)_1p8 3
GND 5
8 GND 11
W_DISABLE_1#_3p3 GND 27
6 GND 33
FULL_CARD_PWROFF#_1p8/3p3 GND 39
38 GND 45
DEVSLP_3p3 GND 51
68 GND 57
SUSCLK_3p3 GND 71
GND 73
GND
XPCIE_M2_4MM2_B
VCC3V3
C1 C2 C3
C100nS02V16X C100nS02V16X C100nS02V16X
U1
10
UPI3DBS12212A_TQFN20
1
6 VDD
VDD
VDD
19 SATA0_TX+
B0+ 18 SATA0_TX- SATA0_TX+
PCIE0_TX+_SATA0_TX+ 3 B0- SATA0_TX-
PCIE0_TX+_SATA0_TX+ PCIE0_TX-_SATA0_TX- 4 A0+ 17 SATA0_RX-
PCIE0_TX-_SATA0_TX- A0- B1+ 16 SATA0_RX+ SATA0_RX-
B1- SATA0_RX+
PCIE0_RX+_SATA0_RX- 7
PCIE0_RX+_SATA0_RX- 8 A1+ 15
PCIE0_RX-_SATA0_RX+ PCIe0_TX+
PCIE0_RX-_SATA0_RX+ A1- C0+ 14 PCIe0_TX+
PCIe0_TX-
C0- PCIe0_TX-
13 PCIe0_RX+
9 SEL- L: A=B C1+ 12 PCIe0_RX+
PCIe0_RX-
CONFIG_1 2 SEL SEL- H: A=C C1- PCIe0_RX-
PD
SEL = L --> A to B
GND
GND
GND
PAD
SEL = H --> A to C
5
11
20
21
Figure 2: Socket 2 - Key B Reference Design
Application Note
3.3 Design Notes

The reference design above (Figure 2) shows an M.2 Socket 2 – Key B used to connect
PCIe or SATA based storage devices.
CONFIG_1 pin enables the appropriate host interface:
• CONFIG_1 low enables SATA
• CONFIG_1 high enables PCIe
The second PCIe lane enables support for PCIe x2 devices like Intel Optane memory. For
PCIe x2 support, the PCIe lanes must be configured to a PCIe x2 link.
Note
As the CONFIG_1 signal is not connected on the M.2 expansion card when PCIe is
enabled, a pull-up resistor is required on the carrier board.
If the M.2 socket is used for a SATA based storage device, pin 43 must be connected
to the negative signal of the differential pair used for SATA Rx.
If the M.2 socket is used for a PCIe based storage device, pin 43 must be connected
to the positive signal of the differential pair used for PCIe Rx.
Application Note
4 Socket 3 – Key M
74 3.3 V GND 75
72 3.3 V GND 73
70 3.3 V GND 71
68 SUSCLK (O)(0/3.3V) PEDET 69
Key M NC 67
Key M Key M
Key M Key M
Key M Key M
Key M Key M
58 NC GND 57
56 NC REFCLKp 55
54 PEWAKE# (I/O)(0/3.3V) or NC REFCLKn 53
52 CLKREQ# (I/O)(0/3.3V) or NC GND 51
50 PERST# (O)(0/3.3V) or NC PETp0/SATA-A+ 49
48 NC PETn0/SATA-A- 47
46 NC GND 45
44 ALERT# (I) (0/1.8V) PERp0/SATA-B- 43
42 SMB_DATA (I/O) (0/1.8V) PERn0/SATA-B+ 41
40 SMB_CLK (I/O)(0/1.8V) GND 39
38 DEVSLP (O) PETp1 37
36 NC PETn1 35
34 NC GND 33
32 NC PERp1 31
30 NC PERn1 29
28 NC GND 27
26 NC PETp2 25
24 NC PETn2 23
22 NC GND 21
20 NC PERp2 19
18 3.3 V PERn2 17
16 3.3 V GND 15
14 3.3 V PETp3 13
12 3.3 V PETn3 11
10 DAS/DSS (I/O)/LED_1# (I)(0/3.3V) GND 9
8 NC PERp3 7
6 NC PERn3 5
4 3.3 V GND 3
2 3.3 V GND 1
Application Note

X40 VCC3V3 C317 C10uS03V16X
1
M.2 socket 3 2
C320 C1u0S02V25X
C322 C10nS02V10X
3 GND 3.3V 4 C324 C10nS02V10X
PCIE3_RX- 5 GND 3.3V 6
PCIE3_RX- PCIE3_RX+ 7 PERN3 NC2 8
PCIE3_RX+ 9 PERP3 NC3 10 LED1#_OD
PCIE3_TX- 11 GND DAS/DSS# 12 LED1#_OD
PCIE3_TX- 13 PETN3 3.3V 14
PCIE3_TX+
PCIE3_TX+ 15 PETP3 3.3V 16
PCIE2_RX- 17 GND 3.3V 18 C318 C10uS03V16X
PCIE2_RX- PCIE2_RX+ 19 PERN2 3.3V 20 C327 C100nS02V16X
PCIE2_RX+ 21 PERP2 NC4 22 C328 C10nS02V10X
PCIE2_TX- 23 GND NC5 24
PCIE2_TX- 25 PETN2 NC6 26
PCIE2_TX+
PCIE2_TX+ 27 PETP2 NC7 28
PCIE1_RX- 29 GND NC8 30
PCIE1_RX- PCIE1_RX+ 31 PERN1 NC9 32
PCIE1_RX+ 33 PERP1 NC10 34
PCIE1_TX- 35 GND NC11 36
PCIE1_TX- 37 PETN1 NC12 38
PCIE1_TX+ SATA_DEVSLP#
PCIE1_TX+ 39 PETP1 DEVSLP 40 SATA_DEVSLP#
PCIE0_RX-_SATA0_RX+ 41 GND NC13 42
PCIE0_RX-_SATA0_RX+ PERN0/SATA_B+ NC14 NC if not used
PCIE0_RX+_SATA0_RX- 43 44
PCIE0_RX+_SATA0_RX- 45 PERP0/SATA_B- NC15 46
PCIE0_TX-_SATA0_TX- 47 GND NC16 48
PCIE0_TX-_SATA0_TX- 49 PETN0/SATA_A- NC17 50
PCIE0_TX+_SATA0_TX+ PCIE_RST#
VCC3V3 PCIE0_TX+_SATA0_TX+ 51 PETP0/SATA_A+ PERST#/NC 52 PCIE_RST# (CB_RESET#)
CLKREQ#
53 GND CLKREQ#/NC 54 CLKREQ#
PCIE_CLK- WAKE#
PCIE_CLK- 55 REFCLKN PEWAKE#/NC 56 WAKE#
PCIE_CLK+
PCIE_CLK+ 57 REFCLKP NC18 58
R571 GND NC19
R1%10k0S02 KEY M
67 68 C337 C10uS03V16X
PEDET 69 NC1 (32K)SUSCLK 70 C339 C1u0S02V25X
PEDET 71 PEDET 3.3V 72 C341 C10nS02V10X
73 GND 3.3V 74 C343 C10nS02V10X
PEDET = L --> SATA GND 3.3V
75
PEDET = NC --> PCIe GND
XPCIE_M2_4MM2_2280_M
VCC3V3
C349 C350 C351

C100nS02V16X C100nS02V16X C100nS02V16X
U1
10
UPI3DBS12212A_TQFN20
1
6 VDD
VDD
VDD
19 SATA0_TX+
B0+ 18 SATA0_TX- SATA0_TX+
PCIE0_TX+_SATA0_TX+ 3 B0- SATA0_TX-
PCIE0_TX+_SATA0_TX+ PCIE0_TX-_SATA0_TX- 4 A0+ 17 SATA0_RX-
PCIE0_TX-_SATA0_TX- A0- B1+ 16 SATA0_RX+ SATA0_RX-
B1- SATA0_RX+
PCIE0_RX+_SATA0_RX- 7
PCIE0_RX+_SATA0_RX- 8 A1+ 15
PCIE0_RX-_SATA0_RX+ PCIe0_TX+
PCIE0_RX-_SATA0_RX+ A1- C0+ 14 PCIe0_TX+
PCIe0_TX-
C0- PCIe0_TX-
13 PCIe0_RX+
9 SEL- L: A=B C1+ 12 PCIe0_RX+
PEDET PCIe0_RX-
PEDET 2 SEL SEL- H: A=C C1- PCIe0_RX-
PD
SEL = L --> A to B
GND
GND
GND
PAD
SEL = H --> A to C
5
11
20
21
Figure 3: Socket 3 - Key M Reference Design
Application Note
4.3 Design Notes

The reference design above (Figure 3) shows an M.2 Socket 3 – Key M used to connect
PCIe or SATA based storage devices.
The PEDET signal enables the appropriate host interface. The M.2 expansion card connects
the PEDET signal accordingly:
• PEDET low enables SATA (M.2 expansion card connects PEDET signal to GND)
• PEDET high enables PCIe (PEDET signal not connected on M.2 expansion card)
For maximum bandwidth, combine the four PCIe lanes to a x4 link.
Note
As the PEDET signal is not connected on the M.2 expansion card when PCIe is enabled,
a pull-up resistor is required on the carrier board.
If the M.2 socket is used for a SATA based storage device, pin 43 must be connected
to the negative signal of the differential pair used for SATA Rx.
If the M.2 socket is used for a PCIe based storage device, pin 43 must be connected
to the positive signal of the differential pair used for PCIe Rx.

AN43 M.2 Pinout Descriptions and Reference Designs

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AN43 M.2 Pinout Descriptions and Reference Designs

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Application Note

congatec Application Note

Affected Products All products

Subject M.2™ Pinout Descriptions and Reference Designs

1.0 2020-01-28 SDA First release

Electrostatic Sensitive Device

Notes call attention to important information that should be observed.

62 ALERT# (I)(0/1.8 V) GND 63

60 I2C_CLK (O)(0/1.8 V) RESERVED/PETn1 61

58 I2C_DATA (I/O)(0/1.8 V) RESERVED/PETp1 59

56 W_DISABLE1# (O)(0/3.3V) GND 57

54 W_DISABLE2# (O)(0/3.3V) PEWAKE0# (I/O)(0/3.3V) 55

52 PERST0# (O)(0/3.3V) CLKREQ0# (I/O)(0/3.3V) 53

50 SUSCLK(32kHz) (O)(0/3.3V) GND 51

48 COEX_TXD (O)(0/1.8V) REFCLKn0 49

46 COEX_RXD (I)(0/1.8V) REFCLKp0 47

44 COEX3 (I/O)(0/1.8V) GND 45

42 VENDOR DEFINED PERn0 43

40 VENDOR DEFINED PERp0 41

38 VENDOR DEFINED GND 39

36 UART RTS (O)(0/1.8V) PETn0 37

34 UART CTS (I)(0/1.8V) PETp0 35

32 UART TXD (O)(0/1.8V) GND 33

22 UART RXD (I)(0/1.8V) SDIO WAKE# (I)(0/1.8V) 21

20 UART WAKE# (I)(0/3.3V) SDIO DATA3(I/O)(0/1.8V) 19

18 GND SDIO DATA2(I/O)(0/1.8V) 17

16 LED_2# (I)(OD) SDIO DATA1(I/O)(0/1.8V) 15

14 PCM_OUT/I2S SD_OUT (O)(0/1.8V) SDIO DATA0(I/O)(0/1.8V) 13

12 PCM_IN/I2S SD_IN (I)(0/1.8V) SDIO CMD(I/O)(0/1.8V) 11

10 PCM_SYNC/I2S WS (I/O)(0/1.8V) SDIO CLK/SYSCLK (O)(0/1.8V) 9

8 PCM_CLK/I2S SCK (I/O)(0/1.8V) GND 7

6 LED_1# (I)(OD) USB_D- 5

2.2 Reference Design

SDIO_D0_1V8* SDIO_D1_1V8* 15 SDIO_DAT0_1P8 UIM_SWP/PERST1# 70

SDIO_D2_1V8* SDIO_D3_1V8* 19 SDIO_DAT2_1P8

I2S_CLK_1V8* 8 SUSCLK_3P3 16 D2 DLED0603Y EL R2 R1%220RS02

I2S_SDIN_1V8* I2S_SDOUT_1V8* 14 PCM_IN/I2S_SDI_1P8 W_DISABLE2#_3P3 56

UART_RTS_1V8 UART_CTS_1V8 34 UART_RTS_1P8 GND 33

Figure 1: Socket 1 - Key E Reference Design

2.3 Design Notes

72 3.3 V/VBAT GND 73

70 3.3 V/VBAT GND 71

68 SUSCLK(32kHz) (O)(0/3.3V) CONFIG_1 69

66 SIM DETECT (O) RESET# (O)(0/1.8V) 67

64 COEX_RXD (I)(0/1.8V) ANTCTL3 (I)(0/1.8V) 65

62 COEX_TXD (O)(0/1.8V) ANTCTL2 (I)(0/1.8V) 63

60 COEX3 (I/O)(0/1.8V) ANTCTL1 (I)(0/1.8V) 61

54 PEWAKE# (I/O)(0/3.3V) REFCLKp 55

52 CLKREQ# (I/O)(0/3.3V) REFCLKn 53

50 PERST# (O)(0/3.3V) GND 51

48 GPIO_4 (I/O)(0/1.8V) PETp0/SATA-A+ 49

46 GPIO_3 (I/O)(0/1.8V) PETn0/SATA-A- 47

44 GPIO_2 (I/O)/ALERT# (I)/(0/1.8V) GND 45

42 GPIO_1 (I/O)/SMB_DATA (I/O)/(0/1.8V) PERp0/SATA-B- 43

40 GPIO_0 (I/O)/SMB_CLK (I/O)/(0/1.8V) PERn0/SATA-B+ 41

38 DEVSLP (O) GND 39

36 UIM-PWR (I) PETp1/USB3.1-Tx+/SSIC-TxP 37

34 UIM-DATA (I/O) PETn1/USB3.1-Tx-/SSIC-TxN 35