Introduction to ModelSim:

Installation and Simulating a Decoder

Installation

1. Download ModelSim PE Student Edition (registration required):

https://www.mentor.com/company/higher_ed/modelsim-student-edition
2. If you have disabled Internet Explorer (Windows 8/Windows 10) make sure that you re-enable it for the
installation.
3. After installation a window will open up in Internet Explorer so that you can get a license. This is
required to complete the installation.
4. If you have any issues during the installation process you can try some of the solutions discussed here:
https://groups.google.com/forum/#!topic/modelsim-pe-student-edition/EsR_sN-uzQo

Simulation

1. Before you can run a simulation you must first create a new project (​File > New Project​). Complete the
dialogue by giving it a name and library location (“work” is the default) and then create a new
SystemVerilog source.
2. In this example a new project was created with a single source file named “Decoder.sv”. The source
code creates a Decoder just like the one we created for Lab3.
Write click on the Decoder.sv file on the right, and select compile all. Your status should have a green check
mark just like the following.
In the main menu go to (Simulation -> start simulation)

Pick the file you would like to simulate, in our case that will be Decoder.sv.
Now your screen should look something like this.
3. In order to simulate the project all “Objects” must be added to the wave simulator by highlighting them,
right clicking, and adding them to it.
4. Input can be simulated directly by right clicking the signal in the wave window and selecting “Force…”.
Enter the value you would like to see as ‘data’ the input for this system verilog file.

5. Simulate the program for 100ns by pressing the green button under “Window” on the toolbar. Verify that
the waveform behaves as expected

You should the changes directly on the wave screen when you press run, you can also change the input again
 As we see we have input with the state of the output shown on the waveform.

Source Code

 
 
 
module Dcoder( 
input logic [3:0] data, //the number to show 
output logic [6:0] segments // 7 segs 
); 
 
always_comb  //comb logic 
case( data ) // 7​bABCDEFG 
0: segments = 7'b0000001; 
1: segments = 7'b1001111; 
2: segments = 7'b0010010; 
3: segments = 7'b0000110; 
4: segments = 7'b1001100; 
5: segments = 7'b0100100; 
6: segments = 7'b0100000; 
7: segments = 7'b0001111; 
8: segments = 7'b0000000; 
9: segments = 7'b0001100; 
default:segments = 7'b1111111; 
endcase 
endmodule