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    1. The document provides solutions to problems from a sample final exam, including FSM design, timing methodology calculations, Moore machine characteristics, state minimization, and fault testing. 2. For timing methodology, it calculates clock period based on timing parameters like setup time and propagation delays. 3. For Moore machine problems, it determines the range of possible states, inputs, outputs, and transitions based on the number of flip-flops and input/output bits.

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    1. The document provides solutions to problems from a sample final exam, including FSM design, timing methodology calculations, Moore machine characteristics, state minimization, and fault testing. 2. For timing methodology, it calculates clock period based on timing parameters like setup time and propagation delays. 3. For Moore machine problems, it determines the range of possible states, inputs, outputs, and transitions based on the number of flip-flops and input/output bits.

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    12 views4 pages

    Sample Final1 Solns Upd

    Uploaded by

    sal
    1. The document provides solutions to problems from a sample final exam, including FSM design, timing methodology calculations, Moore machine characteristics, state minimization, and fault testing. 2. For timing methodology, it calculates clock period based on timing parameters like setup time and propagation delays. 3. For Moore machine problems, it determines the range of possible states, inputs, outputs, and transitions based on the number of flip-flops and input/output bits.

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    © All Rights Reserved
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    of 4

    Solutions to Sample Final 1

    1. FSM Design

    2. Timing Methodology
    Tskew = 5ns
    Max( Tp,FF ) = 40ns
    Max( Tp,Logic ) = 20×2=40ns (NAND-NAND Implementation)
    TSU = 20ns
    Tclk = 1.1(T2-1 + T1-2 + Tgap1 + Tgap2 ) =
    1.1(2TP,FF+TP,Logic+2Tsu+2Tskew)
    = 1.1 (80 ns + 40 ns + 40 ns + 10 ns) = 177 ns
    Assume Φ 1 is the clock for the slave and Φ 2 for the master FFs
    TΦ1 −Φ 2 = margin[max(Tp,FF ) + TSU + TSkew + max( Tp,Logic )]
    = 1.1[40+20+5+40]
    = 115.5 ns
    TΦ 2 −Φ1 = margin[max(Tp,FF ) + TSU + TSkew ] < TΦ1 −Φ 2
    For Symmetric clock design, TΦ1 −Φ 2 and TΦ 2 −Φ1 have to be equal, so TΦ 2 −Φ1 =115.5ns
    TCLK1 = 2 max(TΦ1 −Φ 2 , TΦ 2 − Φ1 ) =2 TΦ1 −Φ 2 =2*115.5 = 231 ns

    3. Moore Machine
    (a) 2 N FF −1 < Ns ≤ 2 N FF
    N FF = 4
    The minimum number of states in the state-transition diagram is 2 3 + 1 = 9 .
    The maximum number of states in the state-transition diagram is 2 4 = 16 .

    (b) 3 input bits


    The minimum number of Transition arrows starting at a particular state is 1.
    The maximum number of Transition arrows starting at a particular state is 2 3 = 8 .

    (c) The minimum number of Transition arrows that can end at a particular state is
    1, because no state is isolated.
    All possible transition arrows are 16 (# of max states)× 8 (# of max input) =
    128. And since no state is isolated, every state needs at least 1 input. So the
    maximum number of transition arrow that can end at a particular state is 16× 8-
    15 =113.

    (d) 7 output bits


    The minimum number of different binary patterns that can be displayed on the
    outputs is 2, otherwise if only 1 output, the machine does not do anything useful.
    Since this is a Moore machine, one output is associated with each state. The
    max # of different output = min( 2 7 , max # of states) = ( 2 7 , 16) = 16.

    4. State Minimization
    X

    0 1
    S0 S1/0 S4/0
    S1 S2/0 S1/0
    S2 S1/0 S6/0
    S3 S1/0 S3/0
    S4 S5/0 S4/0
    S5 S2/0 S1/0
    S6 S5/0 S3/1
    S1 S1 S2
    S1 S4
    S2 S4 S6
    S1 S6
    S3 S4 S3 S3 S6
    S1 S2
    S4 S1 S5 S1 S5 S1 S5
    S2 S5
    S4 S6
    S5 S1 S4 S1 S2 S1 S2 S1 S4
    S1 S2 S1 S6 S1 S3 S2 S5
    S6 X
    X X X X X
    S0 S1 S2 S3 S4 S5

    From above table, we get the reduced state as following,

    (S0S3S4) (S1S5)(S2) (S6)


    A’ B’ C’ D’

    0 1
    A’ B’/0 A’/0
    B’ C’/0 B’/0
    C’ B’/0 D’/0
    D’ B’/0 A’/1

    0/0 1/0
    A’ B’
    1/0

    0/0 0/0
    1/1
    0/0

    1/0
    D’ C’
    5. Testing

    F p/d = f p/d ⊕ f = 0
    F p / d represents all tests for fault p/d
    a). F p / d = 0. No test is available for the fault f p / d . f p / d is untestable
    b). F p / d = 1. Any input combination can be used as a test for fault f p / d
    3). No

    6. Testing

    f = x1 x 2 + x3 x 4 + x5 x 6 = x1 x 2 ⋅ x3 x 4 ⋅ x 4 x5 = x1 x 2 ( x3 + x 4 ) x 4 x5
    = x1 x 2 x3 x 4 x5
    f 8 / 0 = x1 x 2 + x3 x 4 = x1 x 2 ⋅ x3 x 4 = x1 x 2 ( x3 + x 4 )

    F 8 / 0 = x1 x2 x3 x 4 x5 ⊕ ( x1 x 2 x3 + x1 x 2 x 4 )
    = x1 x 2 x3 x 4 x5 ⋅ ( x1 x2 x3 + x1 x2 x 4 ) + x1 x2 x3 x 4 x5 ⋅ ( x1 x 2 x3 + x1 x 2 x4 )
    = x1 x 2 x3 x 4 + x1 x3 x 2 x4 + x1 x 2 x 4 + x1 x3 x 2 x5 + x1 x5 x 2 x 4
    = x1 x 2 x 4 + x1 x3 x 2 x5

    The tests are 11000, 11100, 11001,11101 and 11010

    2) Let us use z to denote the fault

    1 x1 1
    6
    1 x2 2

    z =0 0
    0 x3 3 Z 9
    7 f
    7/1 0 z
    1 x4 4

    1 x7 8
    5

    The test is 11011

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