6.

FULL ADDER

Aim: To Write a VHDL codes for a Full Adder in all models and to simulate them.

Apparatus:
1. Personal computer - 1 no.
2. Xilinx ISE Simulator - Ver.14.5

Theory:
A full-adder is a combinational circuit that forms the arithmetic sum of three input bits.
It consists of three inputs and two outputs. Two of the input variables, denoted by X and
Y, represent the two significant bits to be added. The third input, CIN, represents the
carry from the previous lower significant position. Two outputs are necessary because
the arithmetic sum of three binary digits ranges in value from 0 to 3, and binary 2 or 3
needs two digits. The two outputs are designated by the symbols S for sum and COUT
for carry. The binary variable S gives the value of the least significant bit of the sum.
The binary variable COUT gives the output carry.

Logic Diagram:

Pin Diagram:

Truth Table:

Inputs Outputs
X Y CIN S COUT
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Department of Electronics and Communications Engineering Page No 1

VHDL Code:
a) Structural Model
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;

entity FULL_ADDER is
port (X, Y, CIN: in STD_LOGIC;
S, COUT: out STD_LOGIC);
end FULL_ADDER;

architecture STRUCTURAL of FULL_ADDER is

signal W:STD_LOGIC_VECTOR (0 to 3);
component XOR2
port (A, B: in STD_LOGIC;
C: out STD_LOGIC);
end component;
component AND2
port (D, E: in STD_LOGIC;
F: out STD_LOGIC);
end component;
component OR2
port (G,H: in STD_LOGIC;
I: out STD_LOGIC);
end component;
begin
X1: XOR2 portmap (W(0),X,Y);
X2: XOR2 portmap (S,W(0),CIN);
A1: AND2 portmap (W(1),X,CIN);
A2: AND2 portmap (W(2),Y,CIN);
A3: AND2 portmap (W(3),X,Y);
O1: OR2 portmap (COUT,W(1),W(2),W(3));
end STRUCTURAL;

b) Dataflow Model
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;

entity FULL_ADDER is
port (X, Y, CIN: in STD_LOGIC;
S, COUT: out STD_LOGIC);
end FULL_ADDER;

architecture DATAFLOW of FULL_ADDER is

begin
S <= X xor Y xor CIN;

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 COUT <= (X and CIN) or (Y and CIN) or (X and Y);
end DATAFLOW;

c) Behavioral Model

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;

entity FULL_ADDER is
port (X, Y, CIN: in STD_LOGIC;
S, COUT: out STD_LOGIC);
end FULL_ADDER;

architecture BEHAVIORAL of FULL_ADDER is

begin
process (X,Y,CIN)
variable W:STD_LOGIC_VECTOR (1 to 3);
begin
S <= X xor Y xor CIN;
W(1):= X and CIN;
W(2):= Y and CIN;
W(3):= X and Y;
COUT <= W(1) or W(2) or W(3);
end process;
end BEHAVIORAL;

Result:
Hence VHDL codes for Full adder in all modeling styles were written and simulated using
Xilinx 14.5 version and output is observed.

Department of Electronics and Communications Engineering Page No 3

 7. 8×3 Encoder - 74148
Aim: To Write a VHDL code for 8×3 Encoder - IC74148 and to Simulate it.

Apparatus:

1. Personal computer - 1 no.

2. Xilinx ISE Simulator - Ver.14.5
Theory:

The 74x148 is a commercially available, MSI 8-input priority encoder. The main difference
between this IC and the “generic” priority encoder is that its inputs and outputs are active low.
Also, it has an enable input, EI_L that must be asserted for any of its outputs to be asserted.
Instead of an IDLE output, the ’148 has a GS_L output that is asserted when the device is
enabled and one or more of the request inputs is asserted, called as “Group Select”. The EO_L
signal is an enable output designed to be connected to the EI_L input of another ’148 that
handles lower-priority requests. EO is asserted if EI_L is asserted but no request input is
asserted; thus, a lower-priority 74x148 may be enabled. Figure shows how four 74x148s can be
connected in this way to accept 32 request inputs and produce a 5-bit output, RA4–RA0,
indicating the highest-priority requestor. Since the A2–A0 outputs of at most one ’148 will be
enabled at any time, the outputs of the individual ’148s can be ORed to produce RA2–RA0.
Likewise, the individual GS_L outputs can be combined in a 4-to-2 encoder to produce RA4
and RA3. The RGS output is asserted if any GS output is asserted.

Logic Diagram:

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Pin Diagram:

Truth Table:

Inputs Outputs
EI I0 I1 I2 I3 I4 I5 I6 I7 A2 A1 A0 GS EO
1 x x x x x x x x 1 1 1 1 1
0 x x x x x x x 0 0 0 0 0 1
0 x x x x x x 0 1 0 0 1 0 1
0 x x x x x 0 1 1 0 1 0 0 1
0 x x x x 0 1 1 1 0 1 1 0 1
0 x x x 0 1 1 1 1 1 0 0 0 1
0 x x 0 1 1 1 1 1 1 0 1 0 1
0 x 0 1 1 1 1 1 1 1 1 0 0 1
0 0 1 1 1 1 1 1 1 1 1 1 0 1
0 1 1 1 1 1 1 1 1 1 1 1 1 0

VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;

entity V74x148 is
port (EI_L: in STD_LOGIC;
I_L: in STD_LOGIC_VECTOR (7 downto 0);
A_L: out STD_LOGIC_VECTOR (2 downto 0);
EO_L, GS_L: out STD_LOGIC
end V74x148;

architecture V74x148p of V74x148 is

signal EI: STD_LOGIC;
signal I: STD_LOGIC_VECTOR (7 downto 0);
signal EO, GS: STD_LOGIC;
signal A: STD_LOGIC_VECTOR (2 downto 0);
begin
process (EI_L, I_L, EI, EO, GS, I, A)
variable j: INTEGER range 7 downto 0;
begin
EI <= not EI_L;
I <= not I_L;
EO <= '1'; GS <= '0'; A <= "000";
if (EI)='0' then EO <= '0';
else for j in 7 downto 0 loop

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 if GS = '1' then null;
elsif I(j)='1' then
GS <= '1'; EO <= '0';
A <= CONV_STD_LOGIC_VECTOR(j,3);
end if;
end loop;
end if;
EO_L <= not EO;
GS_L <= not GS;
A_L <= not A;
end process;
end V74x148p;

Result:

Hence VHDL code for 8×3 Encoder IC 74148 in behavioral style is written and simulated using
Xilinx 14.5 version and output is observed.

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 8. DECADE COUNTER - IC7490

Aim: To Write a VHDL code and to Simulate decade counter – IC 7490.

Apparatus:
1. Personal computer - 1 no.
2. Xilinx ISE Simulator - Ver.14.5

Theory:
The 74LS90 is a simple counter, i.e. it can count from 0 to 9 cyclically in its natural
mode. It counts the input pulses and the output is received as a 4-bit binary number
through pins QA, QB, QC and QD. The binary output is reset to 0000 at every tenth pulse
and count starts from 0 again. A pulse is also generated (probably at pin 9) as it resets its
output to 0000. The chip can count up to other maximum numbers and return to zero by
changing the modes of 7490. These modes are set by changing the connection of reset
pins R1 - R4. For example, if either R0(1) & R0(2) are high or R9(1) & R9(2) are ground,
then it will reset QA, QB, QC and QD to 0. If resets R9(1) & R9(2) are high, then the count
on QA, QB, QC and QD goes to 1001.The other high counts can be generated by
connecting two or more 7490 ICs. It has an inbuilt divide-by-two and divide-by-five
counters which can be connected in different fashion by changing the connections. It can
be used as a divide-by-10 counter by connecting QA with (clock) input2, grounding all
the reset pins, and giving pulse at (clock) input1. This enables the cascade connection of
the inbuilt counters. By connecting QA with input1, 7490 can be used for BCD counting
whereas by connecting QD with input2, it can be used for bi-quinary counting.

Logic Diagram:

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Pin Diagram:

7490

Truth Table:

Reset Inputs Output

R0(1) R0(2) R9(1) R9(2) QD QC QB QA
H H L X L L L L
H H X L L L L L
X X H H H L L H
X L X L COUNT
L X L X COUNT
L X X L COUNT
X L L X COUNT

Output
Count
QD QC QB QA
0 L L L L
1 L L L H
2 L L H L
3 L L H H
4 L H L L
5 L H L H
6 L H H L
7 L H H H
8 H L L L
9 H L L H

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;

entity dec_counter is
port (clk : in STD_LOGIC;
r0_1,r0_2: in STD_LOGIC;
r9_1,r9_2: in STD_LOGIC;
q: out STD_LOGIC_VECTOR (3 downto 0));
end dec_counter;

architecture behavioral of dec_counter is

signal count: STD_LOGIC_VECTOR (3 downto 0);
begin
process (clk,r0_1,r0_2,r9_1,r9_2,count)
begin

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 if (r0_1 and r0_2)= '1' then count <= "0000";
elsif (r9_1 and r9_2)= '1' then count <= "1001";
elsif (clk'event and clk = '0') then
count <= count + 1;
if (count=9)then count <="0000";
end if;
end if;
q <= count;
end process;
end behavioral;

Output Waveform:

Result:
Hence VHDL code for decode counter IC 7490 in behavioral style is written and simulated
using Xilinx 14.5 version and output is observed.

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 9. SHIFT REGISTER - IC7495

Aim: To Write a VHDL code for shift register - IC7495 and to Simulate it.

Apparatus:
1. Personal computer - 1 no.
2. Xilinx ISE Simulator - Ver.14.5

Theory:
• The 7495 has parallel and serial inputs, parallel outputs, mode control and two clock
inputs. The register has three modes of operation.
i. Parallel (broadside) load
ii. Shift right
iii. Shift left.
• Parallel loading is accomplished by applying the 4-bits of data and taking the mode
control input high. The data is loaded in to the associated flip-flops and appears at the
outputs after the high to low transition of the clock-2 input. During loading, the entry of
serial data is inhibited.
• Shift right operation is accomplished on the high-to-low transition of clock 1 when the
mode control is low.
• Shift left operation is accomplished on the high-to-low transition of clock 2 when the
mode control is high by connecting the output of each flip-flop to the parallel input of
the previous flip-flop (QD to input C,etc) and the serial data is entered at the input D.

Logic Diagram:

Pin diagram:

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Truth Table:

Inputs Outputs
Mode Clocks Parallel
Serial QA QB QC QD
Control 2 (L) 1 (R) A B C D
H H X X X X X X QA0 QB0 QC0 QD0
H ↓ X X a b c d a b c d
H ↓ X X QB↑ QC↑ QD↑ d QBn QCn QDn d
L L H X X X X X QA0 QB0 QC0 QD0
L X ↓ H X X X X H QAn QBn QCn
L X ↓ L X X X X L QAn QBn QCn
↑ L L X X X X X QA0 QB0 QC0 QD0
↓ L L X X X X X QA0 QB0 QC0 QD0
↓ L H X X X X X QA0 QB0 QC0 QD0
↑ H L X X X X X QA0 QB0 QC0 QD0
↑ H H X X X X X QA0 QB0 QC0 QD0

VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;

entity shift_register_7495 is
Port ( clk1,clk2: in STD_LOGIC;
m_s,sd: in STD_LOGIC;
` d: in STD_LOGIC_VECTOR (3 downto 0);
q: inout STD_LOGIC_VECTOR (3 downto 0));
end shift_register_7495;

architecture Behavioral of shift_register_7495 is

begin
process(clk1,clk2,m_s,sd)
begin
if(m_s ='0') then
if(clk1'event and clk1='0') then
q <= sd & q(3 downto 1);
end if;
elsif(m_s ='1') then
if(clk2'event and clk2='0') then
q<=d(3)& d(2)&d(1)&d(0) ;
end if;
end if;
end process;
end Behavioral;

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Output Waveform:

Result:
Hence VHDL code for Shift Register IC7495 in behavioral style is written and
simulated using Xilinx 14.5 version and output is observed

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 10. ALU DESIGN – 74381

Aim: To write a VHDL code and to Simulate Arithmetic Logic Unit – IC74381

Apparatus:

1. Personal computer - 1 no
2. Xilinx ISE Simulator - Ver.14.5

Theory:

An arithmetic and logic unit (ALU) is a combinational circuit that can perform any of a
number of different arithmetic and logical operations on a pair of b-bit operands. The
operation to be performed is specified by a set of function-select inputs. Typical MSI
ALUs have 4-bit operands and three to five function select inputs.
The IC74381 performs three arithmetic and three logic operations on two 4-bit
words, A and B. Three additional select input codes force the function outputs LOW or
HIGH. Carry propagate and generate outputs are provided for use with carry look ahead
generator for high-speed expansion to longer word lengths. The features are:
• Low input loading minimizes drive requirements
• Performs six arithmetic and logic functions
• Selectable LOW (clear) and HIGH (preset) functions

Pin Diagram:

Truth Table:

Select Inputs
Function
S2 S1 S0
0 0 0 F = 0000
0 0 1 F = B – A – 1 + CIN
0 1 0 F = A – B – 1 + CIN
0 1 1 F = A + B + CIN
1 0 0 F=A B
1 0 1 F=A+B
1 1 0 F = A.B
1 1 1 F = 1111

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VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity ALU74381 is
port (a,b: in STD_LOGIC_VECTOR (3 downto 0);
s: in STD_LOGIC_VECTOR (2 downto 0);
cin: in STD_LOGIC;
f: out STD_LOGIC_VECTOR (3 downto 0));
end ALU74381;

architecture Behavioral of ALU74381 is

begin
process(a,b,cin,s)
begin
case s is
when "000" => f <= "0000";
when "001" => f <= b-a-1+cin;
when "010" => f <= a-b-1+cin;
when "011" => f <= a+b+cin;
when "100" => f <= a xor b;
when "101" => f <= a or b;
when "110" => f <= a and b;
when “111” => f <= "1111";
when others =>f <= "UUUU";
end case;
end process;
end Behavioral;

Result:
Hence VHDL code for ALU 74381 in behavioral style is written and simulated using
Xilinx 14.5 version and output is observed.

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