Specifications GAL22V10

GAL22V10
High Performance E2CMOS PLD
Generic Array Logic™
FEATURES FUNCTIONAL BLOCK DIAGRAM
2 ®
• HIGH PERFORMANCE E CMOS TECHNOLOGY RESET
— 4 ns Maximum Propagation Delay I/CLK

— Fmax = 250 MHz 8

OLMC I/O/Q
— 3.5 ns Maximum from Clock Input to Data Output
I
— UltraMOS® Advanced CMOS Technology
10
• ACTIVE PULL-UPS ON ALL PINS OLMC I/O/Q
I
• COMPATIBLE WITH STANDARD 22V10 DEVICES
12
— Fully Function/Fuse-Map/Parametric Compatible OLMC
I I/O/Q
with Bipolar and UVCMOS 22V10 Devices
• 50% to 75% REDUCTION IN POWER VERSUS BIPOLAR

PROGRAMMABLE
14
— 90mA Typical Icc on Low Power Device I OLMC I/O/Q

AND-ARRAY
— 45mA Typical Icc on Quarter Power Device

(132X44)
16
• E2 CELL TECHNOLOGY I OLMC I/O/Q
— Reconfigurable Logic
— Reprogrammable Cells
16
— 100% Tested/100% Yields I OLMC I/O/Q
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
14
I
OLMC
• TEN OUTPUT LOGIC MACROCELLS I/O/Q
— Maximum Flexibility for Complex Logic Designs
I 12
• PRELOAD AND POWER-ON RESET OF REGISTERS OLMC I/O/Q
— 100% Functional Testability
• APPLICATIONS INCLUDE: I 10

— DMA Control OLMC I/O/Q

— State Machine Control

I
— High Speed Graphics Processing 8
OLMC I/O/Q
— Standard Logic Speed Upgrade
I
• ELECTRONIC SIGNATURE FOR IDENTIFICATION PRESET

DESCRIPTION PIN CONFIGURATION

The GAL22V10, at 4ns maximum propagation delay time, com- DIP

bines a high performance CMOS process with Electrically Eras-
able (E2) floating gate technology to provide the highest perform- PLCC 1 Vcc
I/CLK 24
ance available of any 22V10 device on the market. CMOS cir-
I/CLK

I/O/Q

I/O/Q

I/O/Q
Vcc

I
NC

cuitry allows the GAL22V10 to consume much less power when

I
I

I I/O/Q
compared to bipolar 22V10 devices. E2 technology offers high 4 2 28 26
speed (<100ms) erase times, providing the ability to reprogram I 5 25 I/O/Q I/O/Q
I GAL
or reconfigure the device quickly and efficiently. I I/O/Q
I I/O/Q
I 7 23 I/O/Q
22V10
The generic architecture provides maximum design flexibility by I 6 I/O/Q
allowing the Output Logic Macrocell (OLMC) to be configured by NC GAL22V10 NC
I 18 I/O/Q
the user. The GAL22V10 is fully function/fuse map/parametric I 9 Top View 21 I/O/Q

compatible with standard bipolar and CMOS 22V10 devices. I I/O/Q I I/O/Q

I 11 19 I/O/Q I I/O/Q
Unique test circuitry and reprogrammable cells allow complete 12 14 16 18
AC, DC, and functional testing during manufacture. As a result, I I/O/Q
I
I

NC
GND

I/O/Q
I/O/Q

Lattice Semiconductor delivers 100% field programmability and I I/O/Q

functionality of all GAL products. In addition, 100 erase/write GND 12 13 I
cycles and data retention in excess of 20 years are specified.

Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. July 1997
Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com

22v10_04 1
 Specifications GAL22V10

GAL22V10 ORDERING INFORMATION

Commercial Grade Specifications
Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) Ordering # Package
4 2.5 3.5 140 GAL22V10D-4LJ 28-Lead PLCC
5 3 4 150 GAL22V10C-5LJ 28-Lead PLCC
7.5 5 4.5 140 GAL22V10C-7LP 24-Pin Plastic DIP
4.5 4.5 140 GAL22V10C-7LJ 28-Lead PLCC
6.5 5 140 GAL22V10B-7LP 24-Pin Plastic DIP
140 GAL22V10B-7LJ 28-Lead PLCC
10 7 7 55 GAL22V10D-10QP 24-Pin Plastic DIP
55 GAL22V10D-10QJ 28-Lead PLCC
130 GAL22V10D-10LP, GAL22V10C-10LP or GAL22V10B-10LP 24-Pin Plastic DIP
130 GAL22V10D-10LJ, GAL22V10C-10LJ or GAL22V10B-10LJ 28-Lead PLCC
15 10 8 55 GAL22V10D-15QP or GAL22V10B-15QP 24-Pin Plastic DIP
55 GAL22V10D-15QJ or GAL22V10B-15QJ 28-Lead PLCC
130 GAL22V10D-15LP or GAL22V10B-15LP 24-Pin Plastic DIP
130 GAL22V10D-15LJ or GAL22V10B-15LJ 28-Lead PLCC
25 15 15 55 GAL22V10D-25QP or GAL22V10B-25QP 24-Pin Plastic DIP
55 GAL22V10D-25QJ or GAL22V10B-25QJ 28-Lead PLCC
90 GAL22V10D-25LP or GAL22V10B-25LP 24-Pin Plastic Dip
90 GAL22V10D-25LJ or GAL22V10B-25LJ 28-Pin PLCC

Industrial Grade Specifications

Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) Ordering # Package
7.5 5 4.5 160 GAL22V10C-7LPI 24-Pin Plastic DIP
4.5 4.5 160 GAL22V10C-7LJI 28-Lead PLCC
10 7 7 160 GAL22V10C-10LPI 24-Pin Plastic DIP
160 GAL22V10C-10LJI 28-Lead PLCC
15 10 8 150 GAL22V10D-15LPI or GAL22V10B-15LPI 24-Pin Plastic DIP
150 GAL22V10D-15LJI or GAL22V10B-15LJI 28-Lead PLCC
20 14 10 150 GAL22V10D-20LPI or GAL22V10B-20LPI 24-Pin Plastic DIP
150 GAL22V10D-20LJI or GAL22V10B-20LJI 28-Lead PLCC
25 15 15 150 GAL22V10D-25LPI or GAL22V10B-25LPI 24-Pin Plastic DIP
150 GAL22V10D-25LJI or GAL22V10B-25LJI 28-Lead PLCC

PART NUMBER DESCRIPTION

_
XXXXXXXX XX X X X

GAL22V10D Device Name

GAL22V10C
GAL22V10B
Speed (ns) Grade Blank = Commercial
I = Industrial

L = Low Power Power Package P = Plastic DIP

Q = Quarter Power J = PLCC

2

OUTPUT LOGIC MACROCELL (OLMC)
The GAL22V10 has a variable number of product terms per
OLMC. Of the ten available OLMCs, two OLMCs have access to
eight product terms (pins 14 and 23, DIP pinout), two have ten
product terms (pins 15 and 22), two have twelve product terms
(pins 16 and 21), two have fourteen product terms (pins 17 and
20), and two OLMCs have sixteen product terms (pins 18 and 19).
In addition to the product terms available for logic, each OLMC
has an additional product-term dedicated to output enable control.
The output polarity of each OLMC can be individually programmed
to be true or inverting, in either combinatorial or registered mode.
This allows each output to be individually configured as either
active high or active low.
A R
D
CLK
SP
2 TO 1
MUX
GAL22V10 OUTPUT LOGIC MACROCELL (OLMC)
OUTPUT LOGIC MACROCELL CONFIGURATIONS
Each of the Macrocells of the GAL22V10 has two primary func-
tional modes: registered, and combinatorial I/O. The modes and
the output polarity are set by two bits (SO and S1), which are nor-
mally controlled by the logic compiler. Each of these two primary
modes, and the bit settings required to enable them, are described
below and on the following page.
REGISTERED
In registered mode the output pin associated with an individual
OLMC is driven by the Q output of that OLMC’s D-type flip-flop.
Logic polarity of the output signal at the pin may be selected by
specifying that the output buffer drive either true (active high) or
inverted (active low). Output tri-state control is available as an in-
dividual product-term for each OLMC, and can therefore be de-
fined by a logic equation. The D flip-flop’s /Q output is fed back
into the AND array, with both the true and complement of the
feedback available as inputs to the AND array.
Specifications GAL22V10
The GAL22V10 has a product term for Asynchronous Reset (AR)
and a product term for Synchronous Preset (SP). These two
product terms are common to all registered OLMCs. The Asyn-
chronous Reset sets all registers to zero any time this dedicated
product term is asserted. The Synchronous Preset sets all reg-
isters to a logic one on the rising edge of the next clock pulse after
this product term is asserted.
NOTE: The AR and SP product terms will force the Q output of
the flip-flop into the same state regardless of the polarity of the
output. Therefore, a reset operation, which sets the register output
to a zero, may result in either a high or low at the output pin,
depending on the pin polarity chosen.
4 TO 1
Q
MUX
Q
NOTE: In registered mode, the feedback is from the /Q output of
the register, and not from the pin; therefore, a pin defined as
registered is an output only, and cannot be used for dynamic
I/O, as can the combinatorial pins.
COMBINATORIAL I/O
In combinatorial mode the pin associated with an individual OLMC
is driven by the output of the sum term gate. Logic polarity of the
output signal at the pin may be selected by specifying that the
output buffer drive either true (active high) or inverted (active low).
Output tri-state control is available as an individual product-term
for each output, and may be individually set by the compiler as
either “on” (dedicated output), “off” (dedicated input), or “product-
term driven” (dynamic I/O). Feedback into the AND array is from
the pin side of the output enable buffer. Both polarities (true and
inverted) of the pin are fed back into the AND array.
3
 Specifications GAL22V10

REGISTERED MODE

AR AR

D Q D Q

CLK Q CLK Q

SP SP

ACTIVE LOW ACTIVE HIGH

S0 = 0 S0 = 1
S1 = 0 S1 = 0

COMBINATORIAL MODE

ACTIVE LOW ACTIVE HIGH

S0 = 0 S0 = 1
S1 = 1 S1 = 1

4
 Specifications GAL22V10

GAL22V10 LOGIC DIAGRAM / JEDEC FUSE MAP

DIP (PLCC) Package Pinouts
1 (2)
0 4 8 12 16 20 24 28 32 36 40

0000
ASYNCHRONOUS RESET
(TO ALL REGISTERS)
0044
. 8
. OLMC
. S0 23 (27)
0396 5808
S1
5809

0440
.
. 10 OLMC
.
S0
22 (26)
.
0880 5810
S1
5811
2 (3)
0924
.
. 12
. OLMC 21 (25)
. S0
. 5812
1452 S1
5813
3 (4)
1496
.
.
. 14 OLMC 20 (24)
.
. S0
. 5814
2112 S1
5815
4 (5)
2156
.
.
. 16 19 (23)
. OLMC
. S0
. 5816
. S1
2860 5817

5 (6)
2904
.
.
. 16 18 (21)
.
.
OLMC
. S0
. 5818
3608 S1
5819

6 (7)
3652
.
.
. 14 OLMC 17 (20)
.
. S0
. 5820
4268 S1
5821
7 (9)
4312
.
. 12
. OLMC 16 (19)
. S0
. 5822
4840 S1
5823
8 (10)
4884
.
. 10 OLMC
. S0 15 (18)
. 5824
5324 S1
5825
9 (11)
5368
. 8
. OLMC
. S0 14 (17)
5720 5826
S1
10 (12) 5827
5764 SYNCHRONOUS PRESET
(TO ALL REGISTERS)
11 (13) 13 (16)

5828, 5829 ... Electronic Signature ... 5890, 5891

Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0
M L
S S
B B

5
 Specifications
SpecificationsGAL22V10D
GAL22V10

ABSOLUTE MAXIMUM RATINGS(1) RECOMMENDED OPERATING COND.

Supply voltage VCC ....................................... -0.5 to +7V Commercial Devices:
Ambient Temperature (TA) ............................. 0 to +75°C
Input voltage applied ........................... -2.5 to VCC +1.0V
Supply voltage (VCC)
Off-state output voltage applied........... -2.5 to VCC +1.0V
with Respect to Ground ..................... +4.75 to +5.25V
Storage Temperature.................................. -65 to 150°C
Ambient Temperature with
Industrial Devices:
Power Applied ......................................... -55 to 125°C
Ambient Temperature (TA) ............................ -40 to 85°C
1. Stresses above those listed under the “Absolute Maximum
Ratings” may cause permanent damage to the device. These Supply voltage (VCC)
are stress only ratings and functional operation of the device with Respect to Ground ..................... +4.50 to +5.50V
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)

SYMBOL PARAMETER CONDITION MIN. TYP.3 MAX. UNITS

VIL Input Low Voltage Vss – 0.5 — 0.8 V

VIH Input High Voltage 2.0 — Vcc+1 V

IIL1 Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — –100 µA

IIH Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC — — 10 µA

VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH — — 0.5 V

VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 — — V

IOL Low Level Output Current — — 16 mA

IOH High Level Output Current — — –3.2 mA

IOS2 Output Short Circuit Current VCC = 5V VOUT = 0.5V TA = 25°C –30 — –130 mA

COMMERCIAL
ICC Operating Power VIL = 0.5V VIH = 3.0V L-4 — 90 140 mA
Supply Current ftoggle = 15MHz Outputs Open L-15 — 90 130 mA
L-25 — 75 90 mA
Q-10/-15/-25 — 45 55 mA

INDUSTRIAL
ICC Operating Power VIL = 0.5V VIH = 3.0V L-15/-20/-25 — 75 150 mA
Supply Current ftoggle = 15MHz Outputs Open

1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Characterized but not 100% tested.
3) Typical values are at Vcc = 5V and TA = 25 °C

6
 Specifications
SpecificationsGAL22V10D
GAL22V10

AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions

COM COM COM / IND IND COM / IND

TEST -4 -10 -15 -20 -25

PARAM. DESCRIPTION UNITS
COND.1 MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
tpd A Input or I/O to Comb. Output 1 4 1 10 3 15 3 20 3 25 ns

tco A Clock to Output Delay 1 3.5 1 7 2 8 2 10 2 15 ns

tcf2 — Clock to Feedback Delay — 2.5 — 2.5 — 2.5 — 8 — 13 ns

tsu — Setup Time, Input or Fdbk before Clk↑ 2.5 — 7 — 10 — 14 — 15 — ns

th — Hold Time, Input or Fdbk after Clk↑ 0 — 0 — 0 — 0 — 0 — ns

A Maximum Clock Frequency with 167 — 71.4 — 55.5 — 41.6 — 33.3 — MHz
External Feedback, 1/(tsu + tco)

fmax3 A Maximum Clock Frequency with 200 — 105 — 80 — 45.4 — 35.7 — MHz
Internal Feedback, 1/(tsu + tcf)

A Maximum Clock Frequency with 250 — 105 — 83.3 — 50 — 38.5 — MHz

No Feedback

twh — Clock Pulse Duration, High 2 — 4 — 6 — 10 — 13 — ns

twl — Clock Pulse Duration, Low 2 — 4 — 6 — 10 — 13 — ns

ten B Input or I/O to Output Enabled 1 5 1 10 3 15 3 20 3 25 ns

tdis C Input or I/O to Output Disabled 1 5 1 9 3 15 3 20 3 25 ns

tar A Input or I/O to Asynch. Reset of Reg. 1 4.5 1 13 3 20 3 25 3 25 ns

tarw — Asynch. Reset Pulse Duration 4.5 — 8 — 15 — 20 — 25 — ns

tarr — Asynch. Reset to Clk↑ Recovery Time 3 — 8 — 10 — 20 — 25 — ns

tspr — Synch. Preset to Clk↑ Recovery Time 3 — 10 — 10 — 14 — 15 — ns

1) Refer to Switching Test Conditions section.

2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.

CAPACITANCE (TA = 25°C, f = 1.0 MHz)

SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS

CI Input Capacitance 8 pF VCC = 5.0V, VI = 2.0V

CI/O I/O Capacitance 8 pF VCC = 5.0V, VI/O = 2.0V

*Characterized but not 100% tested.

7
 Specifications
SpecificationsGAL22V10C
GAL22V10

ABSOLUTE MAXIMUM RATINGS(1) RECOMMENDED OPERATING COND.

Supply voltage VCC ....................................... -0.5 to +7V Commercial Devices:
Ambient Temperature (TA) ............................. 0 to +75°C
Input voltage applied ........................... -2.5 to VCC +1.0V
Supply voltage (VCC)
Off-state output voltage applied........... -2.5 to VCC +1.0V
with Respect to Ground ..................... +4.75 to +5.25V
Storage Temperature.................................. -65 to 150°C
Ambient Temperature with
Industrial Devices:
Power Applied ......................................... -55 to 125°C
Ambient Temperature (TA) ............................ -40 to 85°C
1. Stresses above those listed under the “Absolute Maximum
Ratings” may cause permanent damage to the device. These Supply voltage (VCC)
are stress only ratings and functional operation of the device with Respect to Ground ..................... +4.50 to +5.50V
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)

SYMBOL PARAMETER CONDITION MIN. TYP.3 MAX. UNITS

VIL Input Low Voltage Vss – 0.5 — 0.8 V

VIH Input High Voltage 2.0 — Vcc+1 V

IIL1 Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — –100 µA

IIH Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC — — 10 µA

VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH — — 0.5 V

VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 — — V

IOL Low Level Output Current — — 16 mA

IOH High Level Output Current — — –3.2 mA

IOS2 Output Short Circuit Current VCC = 5V VOUT = 0.5V TA = 25°C –30 — –130 mA

COMMERCIAL
ICC Operating Power Supply Current VIL = 0.5V VIH = 3.0V L-5 — 90 150 mA
ftoggle = 15MHz Outputs Open L-7 — 90 140 mA
L-10 — 90 130 mA

INDUSTRIAL
ICC Operating Power Supply Current VIL = 0.5V VIH = 3.0V L-7/-10 — 90 160 mA
ftoggle = 15MHz Outputs Open

1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Characterized but not 100% tested.
3) Typical values are at Vcc = 5V and TA = 25 °C

8
 Specifications
SpecificationsGAL22V10C
GAL22V10

AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions

COM COM/IND COM/IND COM IND

TEST -5 -7 (PLCC) -7 (PDIP) -10 -10

PARAM DESCRIPTION UNITS
COND.1 MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
tpd A Input or I/O to Combinatorial Output 1 5 1 7.5 1 7.5 3 10 1 10 ns

tco A Clock to Output Delay 1 4 1 4.5 1 4.5 2 7 1 7 ns

tcf2 — Clock to Feedback Delay — 3 — 3 — 3 — 2.5 — 2.5 ns

tsu — Setup Time, Input or Fdbk before Clk↑ 3 — 4.5 — 5 — 7 — 7 — ns

th — Hold Time, Input or Fdbk after Clk↑ 0 — 0 — 0 — 0 — 0 — ns

A Maximum Clock Frequency with 142.8 — 111 — 105 — 71.4 — 71.4 — MHz
External Feedback, 1/(tsu + tco)

fmax3 A Maximum Clock Frequency with 166 — 133 — 125 — 105 — 105 — MHz
Internal Feedback, 1/(tsu + tcf)

A Maximum Clock Frequency with 200 — 166 — 142.8 — 105 — 105 — MHz
No Feedback

twh — Clock Pulse Duration, High 2.5 — 3 — 3.5 — 4 — 4 — ns

twl — Clock Pulse Duration, Low 2.5 — 3 — 3.5 — 4 — 4 — ns

ten B Input or I/O to Output Enabled 1 6 1 7.5 1 7.5 3 10 1 10 ns

tdis C Input or I/O to Output Disabled 1 6 1 7.5 1 7.5 3 9 1 9 ns

tar A Input or I/O to Asynch. Reset of Reg. 1 5.5 1 9 1 9 3 13 1 13 ns

tarw — Asynch. Reset Pulse Duration 5.5 — 7 — 7 — 8 — 8 — ns

tarr — Asynch. Reset to Clk↑ Recovery Time 4 — 5 — 5 — 8 — 8 — ns

tspr — Synch. Preset to Clk↑ Recovery Time 4 — 5 — 5 — 10 — 10 — ns

1) Refer to Switching Test Conditions section.

2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section. Characterized initially and after any design or process changes that may affect these
parameters.

CAPACITANCE (TA = 25°C, f = 1.0 MHz)

SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS

CI Input Capacitance 8 pF VCC = 5.0V, VI = 2.0V

CI/O I/O Capacitance 8 pF VCC = 5.0V, VI/O = 2.0V

*Characterized but not 100% tested.

9
 Specifications
SpecificationsGAL22V10B
GAL22V10

ABSOLUTE MAXIMUM RATINGS(1) RECOMMENDED OPERATING COND.

Supply voltage VCC ....................................... -0.5 to +7V Commercial Devices:
Ambient Temperature (TA) ............................. 0 to +75°C
Input voltage applied ........................... -2.5 to VCC +1.0V
Supply voltage (VCC)
Off-state output voltage applied........... -2.5 to VCC +1.0V
with Respect to Ground ..................... +4.75 to +5.25V
Storage Temperature.................................. -65 to 150°C
Ambient Temperature with
Industrial Devices:
Power Applied ......................................... -55 to 125°C
Ambient Temperature (TA) ............................ -40 to 85°C
1. Stresses above those listed under the “Absolute Maximum
Ratings” may cause permanent damage to the device. These Supply voltage (VCC)
are stress only ratings and functional operation of the device with Respect to Ground ..................... +4.50 to +5.50V
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).

DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)

SYMBOL PARAMETER CONDITION MIN. TYP.3 MAX. UNITS

VIL Input Low Voltage Vss – 0.5 — 0.8 V

VIH Input High Voltage 2.0 — Vcc+1 V

IIL1 Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — –100 µA

IIH Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC — — 10 µA

VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH — — 0.5 V

VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 — — V

IOL Low Level Output Current — — 16 mA

IOH High Level Output Current — — –3.2 mA

IOS2 Output Short Circuit Current VCC = 5V VOUT = 0.5V TA = 25°C –30 — –130 mA

COMMERCIAL
ICC Operating Power VIL = 0.5V VIH = 3.0V L-7 — 90 140 mA
Supply Current ftoggle = 15MHz Outputs Open L-10/-15 — 90 130 mA
L-25 — 75 90 mA
Q-15/-25 — 45 55 mA

INDUSTRIAL
ICC Operating Power VIL = 0.5V VIH = 3.0V L-15/-20/-25 — 90 150 mA
Supply Current ftoggle = 15MHz Outputs Open

1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Characterized but not 100% tested.
3) Typical values are at Vcc = 5V and TA = 25 °C

10
 Specifications
SpecificationsGAL22V10B
GAL22V10

AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
COM COM COM / IND IND COM / IND

TEST -7 -10 -15 -20 -25

PARAM. DESCRIPTION UNITS
COND.1 MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
tpd A Input or I/O to Comb. Output 3 7.5 3 10 3 15 3 20 3 25 ns

tco A Clock to Output Delay 2 5 2 7 2 8 2 10 2 15 ns

tcf2 — Clock to Feedback Delay — 2.5 — 2.5 — 2.5 — 8 — 13 ns

tsu1 — Setup Time, Input or Fdbk before Clk↑ 6.5 — 7 — 10 — 14 — 15 — ns

tsu2 — Setup Time, SP before Clock↑ 10 — 10 — 10 — 14 — 15 — ns

th — Hold Time, Input or Fdbk after Clk↑ 0 — 0 — 0 — 0 — 0 — ns

A Maximum Clock Frequency with 87 — 71.4 — 55.5 — 41.6 — 33.3 — MHz
External Feedback, 1/(tsu + tco)

fmax3 A Maximum Clock Frequency with 111 — 105 — 80 — 45.4 — 35.7 — MHz
Internal Feedback, 1/(tsu + tcf)

A Maximum Clock Frequency with 111 — 105 — 83.3 — 50 — 38.5 — MHz

No Feedback

twh — Clock Pulse Duration, High 4 — 4 — 6 — 10 — 13 — ns

twl — Clock Pulse Duration, Low 4 — 4 — 6 — 10 — 13 — ns

ten B Input or I/O to Output Enabled 3 8 3 10 3 15 3 20 3 25 ns

tdis C Input or I/O to Output Disabled 3 8 3 9 3 15 3 20 3 25 ns

tar A Input or I/O to Asynch. Reset of Reg. 3 13 3 13 3 20 3 25 3 25 ns

tarw — Asynch. Reset Pulse Duration 8 — 8 — 15 — 20 — 25 — ns

tarr — Asynch. Reset to Clk↑ Recovery Time 8 — 8 — 10 — 20 — 25 — ns

tspr — Synch. Preset to Clk↑ Recovery Time 10 — 10 — 10 — 14 — 15 — ns

1) Refer to Switching Test Conditions section.

2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.

CAPACITANCE (TA = 25°C, f = 1.0 MHz)

SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS

CI Input Capacitance 8 pF VCC = 5.0V, VI = 2.0V

CI/O I/O Capacitance 8 pF VCC = 5.0V, VI/O = 2.0V

*Characterized but not 100% tested.

11
 Specifications GAL22V10

SWITCHING WAVEFORMS

INPUT or
INPUT or VALID INPUT
VALID INPUT I/O FEEDBACK
I/O FEEDBACK
tsu th
t pd
CLK
COMBINATORIAL
OUTPUT tco
REGISTERED
OUTPUT
Combinatorial Output
1/ fmax
(external fdbk)

Registered Output

INPUT or
I/O FEEDBACK

t dis t en

OUTPUT
CLK
1/ f max (internal fdbk)
Input or I/O to Output Enable/Disable t cf tsu
REGISTERED
FEEDBACK

fmax with Feedback

tw h tw l

CLK

1 / fm a x
(w/o fdbk)

Clock Width

INPUT or
INPUT or
I/O FEEDB ACK
I/O FEEDBACK
DRIVI NG AR
DRIVING SP tarw
tsu th t spr
CLK
CLK

tco tarr
R E G I S T ER E D
REGISTERED
OUTPUT
OUTPUT
tar

Synchronous Preset Asynchronous Reset

12
 Specifications GAL22V10

fmax DESCRIPTIONS
CL K
CLK

LOGIC
LOGIC
R EG I S T E R ARRAY
ARR AY
REGISTER

ts u tc o
fmax with External Feedback 1/(tsu+tco) t cf
Note: fmax with external feedback is cal- t pd
culated from measured tsu and tco.
fmax with Internal Feedback 1/(tsu+tcf)
CLK

Note: tcf is a calculated value, derived by sub-

tracting tsu from the period of fmax w/internal
LOGIC
feedback (tcf = 1/fmax - tsu). The value of tcf is
REGISTER
ARRAY used primarily when calculating the delay from
clocking a register to a combinatorial output
(through registered feedback), as shown above.
tsu + th For example, the timing from clock to a combi-
natorial output is equal to tcf + tpd.
fmax with No Feedback
Note: fmax with no feedback may be less
than 1/(twh + twl). This is to allow for a
clock duty cycle of other than 50%.

13
 Specifications GAL22V10

SWITCHING TEST CONDITIONS

Input Pulse Levels GND to 3.0V GAL22V10D-4 Output Load Conditions (see figure below)

Input Rise and D-4, C-5 1.5ns 10% – 90% Test Condition R1 CL
Fall Times D-10/-15/-20/-25 2.0ns 10% – 90%
A 50Ω 50pF
B & C-7/-10
B Active High 50Ω 50pF
B-15/-20/-25 3ns 10% – 90%
Active Low 50Ω 50pF
Input Timing Reference Levels 1.5V
C Active High 50Ω 50pF
Output Timing Reference Levels 1.5V
Active Low 50Ω 50pF
Output Load See Figure

3-state levels are measured 0.5V from steady-state active +1.45V

level.

Output Load Conditions (except D-4) (see figure below) TEST POINT
R1
Test Condition R1 R2 CL

A 300Ω 390Ω 50pF FROM OUTPUT (O/Q)

UNDER TEST Z0 = 50Ω, CL*
B Active High ∞ 390Ω 50pF
Active Low 300Ω 390Ω 50pF
C Active High ∞ 390Ω 5pF
Active Low 300Ω 390Ω 5pF

+5V

R1

FROM OUTPUT (O/Q)

UNDER TEST TEST POINT

C L*
R2

*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE

14

ELECTRONIC SIGNATURE
An electronic signature (ES) is provided in every GAL22V10
device. It contains 64 bits of reprogrammable memory that can
contain user-defined data. Some uses include user ID codes,
revision numbers, or inventory control. The signature data is
always available to the user independent of the state of the se-
curity cell.
The electronic signature is an additional feature not present in
other manufacturers' 22V10 devices. To use the extra feature of
the user-programmable electronic signature it is necessary to
choose a Lattice Semiconductor 22V10 device type when com-
piling a set of logic equations. In addition, many device program-
mers have two separate selections for the device, typically a
GAL22V10 and a GAL22V10-UES (UES = User Electronic Sig-
nature) or GAL22V10-ES. This allows users to maintain compat-
ibility with existing 22V10 designs, while still having the option to
use the GAL device's extra feature.
The JEDEC map for the GAL22V10 contains the 64 extra fuses
for the electronic signature, for a total of 5892 fuses. However,
the GAL22V10 device can still be programmed with a standard
22V10 JEDEC map (5828 fuses) with any qualified device pro-
grammer.
SECURITY CELL
A security cell is provided in every GAL22V10 device to prevent
unauthorized copying of the array patterns. Once programmed,
this cell prevents further read access to the functional bits in the
device. This cell can only be erased by re-programming the
device, so the original configuration can never be examined once
this cell is programmed. The Electronic Signature is always avail-
able to the user, regardless of the state of this control cell.
LATCH-UP PROTECTION
GAL22V10 devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias is of sufficient
magnitude to prevent input undershoots from causing the circuitry
to latch. Additionally, outputs are designed with n-channel pullups
instead of the traditional p-channel pullups to eliminate any pos-
sibility of SCR induced latching.
DEVICE PROGRAMMING
GAL devices are programmed using a Lattice Semiconductor-
approved Logic Programmer, available from a number of manu-
facturers (see the the GAL Development Tools section). Com-
plete programming of the device takes only a few seconds. Eras-
ing of the device is transparent to the user, and is done automati-
cally as part of the programming cycle.
15
Specifications GAL22V10
OUTPUT REGISTER PRELOAD
When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because certain events
may occur during system operation that throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired
(i.e., illegal) state into the registers. Then the machine can be
sequenced and the outputs tested for correct next state condi-
tions.
The GAL22V10 device includes circuitry that allows each regis-
tered output to be synchronously set either high or low. Thus, any
present state condition can be forced for test sequencing. If
necessary, approved GAL programmers capable of executing test
vectors perform output register preload automatically.
INPUT BUFFERS
GAL22V10 devices are designed with TTL level compatible in-
put buffers. These buffers have a characteristically high imped-
ance, and present a much lighter load to the driving logic than bi-
polar TTL devices.
The input and I/O pins also have built-in active pull-ups. As a re-
sult, floating inputs will float to a TTL high (logic 1). However,
Lattice Semiconductor recommends that all unused inputs and
tri-stated I/O pins be connected to an adjacent active input, Vcc,
or ground. Doing so will tend to improve noise immunity and
reduce Icc for the device. (See equivalent input and I/O schemat-
ics on the following page.)
Typical Input Current
I n p u t C u r r e n t (u A )
0
-20
-40
-60
0 1.0 2.0 3.0 4.0 5.0
In p u t V o lt ag e ( V o lt s)
 Specifications GAL22V10

POWER-UP RESET

Vcc (min.)
Vcc

t su

CLK t wl

t pr
INTERNAL REGISTER Internal Register
Q - OUTPUT Reset to Logic "0"

ACTIVE LOW Device Pin

OUTPUT REGISTER Reset to Logic "1"

ACTIVE HIGH Device Pin

OUTPUT REGISTER Reset to Logic "0"

Circuitry within the GAL22V10 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q out-
puts set low after a specified time (tpr, 1µs MAX). As a result, the
state on the registered output pins (if they are enabled) will be
either high or low on power-up, depending on the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. The
timing diagram for power-up is shown below. Because of the asyn-
chronous nature of system power-up, some conditions must be
met to guarantee a valid power-up reset of the GAL22V10. First,
the Vcc rise must be monotonic. Second, the clock input must
be at static TTL level as shown in the diagram during power up.
The registers will reset within a maximum of tpr time. As in nor-
mal system operation, avoid clocking the device until all input and
feedback path setup times have been met. The clock must also
meet the minimum pulse width requirements.

INPUT/OUTPUT EQUIVALENT SCHEMATICS

PIN PIN

Feedback

Vcc
(Vref Typical = 3.2V) Active Pull-up Active Pull-up
Circuit Circuit
(Vref Typical = 3.2V)

Vcc
Vcc Vref Vcc Tri-State Vref
ESD Control
Protection
Circuit

PIN Data
PIN
Output

ESD
Protection
Circuit

Feedback
(To Input Buffer)

Typical Input Typical Output

16
 Specifications GAL22V10

GAL22V10D-4: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS

Normalized Tpd vs Vcc Normalized Tco vs Vcc Normalized Tsu vs Vcc
1.1 1.1 1.1

RISE
RISE
FALL
Normalized Tpd

Normalized Tco

Normalized Tsu
1.05 RISE 1.05 1.05 FALL
FALL

1 1 1

0.95 0.95 0.95

0.9 0.9 0.9

4.5 4.75 5 5.25 5.5 4.5 4.75 5 5.25 5.5 4.5 4.75 5 5.25 5.5

Supply Voltage (V) Supply Voltage (V) Supply Voltage (V)

Normalized Tpd vs Temp Normalized Tco vs Temp Normalized Tsu vs Temp

1.3 1.2 1.3

1.2 RISE RISE 1.2 RISE

Normalized Tco
Normalized Tpd

Normalized T
FALL FALL FALL
1.1
1.1 1.1

1 1
1

0.9
0.9

0.9 0.8
0.8 -55 -25 0 25 50 75 100 125 -55 -25 0 25 50 75 100 125
-55 -25 0 25 50 75 100 125

Temperature (deg. C) Temperature (deg. C) Temperature (deg. C)

Delta Tpd vs # of Outputs Delta Tco vs # of Outputs

Switching Switching
0 0

-0.1
Delta Tpd (ns)

Delta Tco (ns)

-0.1

-0.2

-0.2 RISE RISE

FALL -0.3 FALL

-0.3 -0.4
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10
Number of Outputs Switching Number of Outputs Switching

Delta Tpd vs Output Loading Delta Tco vs Output Loading

12 12

RISE RISE
Delta Tpd (ns)

8 8
Delta Tco (ns)

FALL FALL

4 4

0 0

-4 -4
0 50 100 150 200 250 300 0 50 100 150 200 250 300

Output Loading (pF) Output Loading (pF)

17
 Specifications GAL22V10

GAL22V10D-4: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS

Vol vs Iol Voh vs Ioh Voh vs Ioh
0.6 4 3.95

3.85

3 3.75
0.4
3.65

Voh (V)
Voh (V)
Vol (V)

2 3.55

3.45
0.2
1 3.35

3.25

0 0 3.15
0 5 10 15 20 25 30 35 40 0 5 10 1 5 2 0 2 5 3 0 3 5 4 0 4 5 50 55 60 0.00 1.00 2.00 3.00 4.00 5.00

Iol (mA) Ioh(mA) Ioh(mA)

Normalized Icc vs Vcc Normalized Icc vs Temp Normalized Icc vs Freq

1.2 1.3 1.2

1.2
1.15
Normalized Icc

1.1
Normalized Icc

Normalized Icc
1.1
1.1
1 1
1.05
0.9
0.9
1
0.8

0.8 0.7 0.95

4.5 4.75 5 5.25 5.5 -55 -25 0 25 50 88 100 125 1 15 25 50 75 1 00
Supply Voltage (V) Temperature (deg. C) Frequency (MHz)

Delta Icc vs Vin (1 input) Input Clamp (Vik)

6 0

5 20
Delta Icc (mA)

4
40
Iik (mA)

3
60

2
80
1
100
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
-3 -2.5 -2 -1.5 -1 -0.5 1

Vin (V) Vik (V)

18
 Specifications GAL22V10

GAL22V10D-10 AND SLOWER: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS

Normalized Tpd vs Vcc Normalized Tco vs Vcc Normalized Tsu vs Vcc
1.1 1.15 1.2

1.1 RISE RISE

Normalized Tpd

1.05 RISE

Normalized Tco

Normalized Tsu
FALL 1.1
FALL FALL
1.05
1 1
1

0.95 0.9
0.95

0.9
0.9 0.8
4.5 4.75 5 5.25 5.5
4.5 4.75 5 5.25 5.5 4.5 4.75 5 5.25 5.5
Supply Voltage (V) Supply Voltage (V) Supply Voltage (V)

Normalized Tpd vs Temp Normalized Tco vs Temp Normalized Tsu vs Temp

1.3 1.3 1.45

1.2 RISE RISE 1.35

RISE
1.2
Normalized Tpd

FALL
Normalized Tco

FALL

Normalized Tsu
FALL
1.25
1.1
1.1
1.15

1
1 1.05

0.9 0.95
0.9
0.85
0.8
-55 -25 0 25 50 75 100 125 0.8 0.75
-55 -25 0 25 50 75 100 1 25 -55 -25 0 25 50 75 100 1 25
Temperature (deg. C)
Temperature (deg. C) Temperature (deg. C)

Delta Tpd vs # of Outputs Delta Tco vs # of Outputs

Switching Switching
0 0
Delta Tpd (ns)

Delta Tco (ns)

-0.4 -0.4
RISE
FALL RISE
FALL
-0.8 -0.8

-1.2 -1.2
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10
Number of Outputs Switching Number of Outputs Switching

Delta Tpd vs Output Loading Delta Tco vs Output Loading

20 20

16 16
RISE RISE
Delta Tpd (ns)

Delta Tco (ns)

12 FALL FALL
12
8
8
4
4
0

-4 0

-8 -4
0 50 100 150 200 250 3 00 0 50 100 150 200 250 3 00

Output Loading (pF) Output Loading (pF)

19
 Specifications GAL22V10

GAL22V10D-10 AND SLOWER: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS

Vol vs Iol Voh vs Ioh Voh vs Ioh
0.6 4.5 4.5
4

3.5 4
0.4 3

Voh (V)

Voh (V)
Vol (V)

2.5
3.5
2

0.2 1.5
1 3

0.5

0 0 2.5
0 5 10 15 20 25 30 35 40 0 20 40 60 0.00 1.00 2.00 3.00 4.00 5.00

Iol (mA) Ioh (mA) Ioh (mA)

Normalized Icc vs Vcc Normalized Icc vs Temp Normalized Icc vs Freq

1.2 1.35 1.4

1.25
1.3
Normalized Icc

Normalized Icc

Normalized Icc
1.1
1.15
1.2
1 1.05
1.1
0.95
0.9
1
0.85

0.8 0.75 0.9

4.5 4.75 5 5.25 5.5 -55 -25 0 25 50 88 100 1 25 1 15 25 50 75 1 00

Supply Voltage (V) Temperature (deg. C) Frequency (MHz)

Delta Icc vs Vin (1 input) Input Clamp (Vik)

7 0

10
6
20
Delta Icc (mA)

5
30
Iik (mA)

4 40

3 50

60
2
70
1 80

0 90
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 -2.5 -2 -1.5 -1 -0.5 0

Vin (V) Vik (V)

20
 Specifications GAL22V10

GAL22V10C-5/-7/-10: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS

Normalized Tpd vs Vcc Normalized Tco vs Vcc Normalized Tsu vs Vcc

1.2 1.2 1.2

PT H->L RISE PT H->L

Normalized Tpd

Normalized Tco

Normalized Tsu
1.1 1.1 1.1
PT L->H FALL PT L->H

1 1 1

0.9 0.9 0.9

0.8 0.8 0.8

4.50 4.75 5.00 5.25 5.50 4.50 4.75 5.00 5.25 5.50 4.50 4.75 5.00 5.25 5.50

Supply Voltage (V) Supply Voltage (V) Supply Voltage (V)

Normalized Tpd vs Temp Normalized Tco vs Temp Normalized Tsu vs Temp

1.3 1.3 1.4

PT H->L 1.2 RISE 1.3 PT H->L

1.2
Normalized Tco
Normalized Tpd

Normalized Tsu
1.2
1.1 PT L->H 1.1 FALL PT L->H
1.1
1 1
1
0.9 0.9
0.9
0.8 0.8 0.8

0.7 0.7 0.7

-55 -25 0 25 50 75 100 125 -55 -25 0 25 50 75 100 125 -55 -25 0 25 50 75 100 125

Temperature (deg. C) Temperature (deg. C) Temperature (deg. C)

Delta Tpd vs # of Outputs Delta Tco vs # of Outputs

Switching Switching
0 0

-0.25
Delta Tpd (ns)

Delta Tco (ns)

-0.25
-0.5

-0.75 -0.5

-1 RISE RISE
-0.75
-1.25 FALL FALL
-1.5 -1
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10

Number of Outputs Switching Number of Outputs Switching

Delta Tpd vs Output Loading Delta Tco vs Output Loading

12 12

10 RISE 10 RISE
Delta Tco (ns)
Delta Tpd (ns)

8 FALL 8 FALL
6 6

4 4

2 2

0 0

-2 -2
0 50 100 150 200 250 300 0 50 100 150 200 250 300

Output Loading (pF) Output Loading (pF)

21
 Specifications GAL22V10

GAL22V10C-5/-7/-10: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS

Vol vs Iol Voh vs Ioh Voh vs Ioh

3 5 4

2.5
4
3.75
2

Voh (V)

Voh (V)
Vol (V)

3
1.5 3.5
2
1
3.25
1
0.5

0 0 3
0.00 20.00 40.00 60.00 80.00 100.00 0.00 10.00 20.00 30.00 40.00 50.00 60.00 0.00 1.00 2.00 3.00 4.00

Iol (mA) Ioh(mA) Ioh(mA)

Normalized Icc vs Vcc Normalized Icc vs Temp Normalized Icc vs Freq.

1.20 1.2 1.30

Normalized Icc

Normalized Icc
Normalized Icc

1.10 1.1 1.20

1.00 1 1.10

0.90 0.9 1.00

0.80 0.8 0.90

4.50 4.75 5.00 5.25 5.50 -55 -25 0 25 50 75 100 125 0 25 50 75 100

Supply Voltage (V) Temperature (deg. C) Frequency (MHz)

Delta Icc vs Vin (1 input) Input Clamp (Vik)

10 0

10
8
Delta Icc (mA)

20
Iik (mA)

6 30

40
4
50
2
60

0 70
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 -2.50 -2.00 -1.50 -1.00 -0.50 0.00

Vin (V) Vik (V)

22
 Specifications GAL22V10

GAL22V10B-7/-10/-15/-25L: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS

Normalized Tpd vs Vcc Normalized Tco vs Vcc Normalized Tsu vs Vcc

1.2 1.2 1.2

PT H->L RISE PT H->L

Normalized Tpd

Normalized Tco

Normalized Tsu
1.1 1.1 1.1
PT L->H FALL PT L->H

1 1 1

0.9 0.9 0.9

0.8 0.8 0.8

4.50 4.75 5.00 5.25 5.50 4.50 4.75 5.00 5.25 5.50 4.50 4.75 5.00 5.25 5.50

Supply Voltage (V) Supply Voltage (V) Supply Voltage (V)

Normalized Tpd vs Temp Normalized Tco vs Temp Normalized Tsu vs Temp

1.3 1.3 1.4

1.2 PT H->L 1.2 RISE 1.3 PT H->L

Normalized Tco
Normalized Tpd

Normalized Tsu
1.2
1.1 PT L->H 1.1 FALL PT L->H
1.1
1 1
1
0.9 0.9
0.9
0.8 0.8 0.8

0.7 0.7 0.7

0
0

0
-55

-25

25

50

75

100

125
100

125

100

125
-55

-25

-55

-25
25

50

75

25

50

75
Temperature (deg. C) Temperature (deg. C) Temperature (deg. C)

Delta Tpd vs # of Outputs Delta Tco vs # of Outputs

Switching Switching

0 0
Delta Tpd (ns)

Delta Tco (ns)

-0.5 -0.5

-1 -1

RISE RISE
-1.5 -1.5
FALL FALL

-2 -2
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10

Number of Outputs Switching Number of Outputs Switching

Delta Tpd vs Output Loading Delta Tco vs Output Loading

12 12

10 RISE 10 RISE
Delta Tco (ns)
Delta Tpd (ns)

8 FALL 8 FALL
6 6

4 4

2 2

0 0

-2 -2
0 50 100 150 200 250 300 0 50 100 150 200 250 300

Output Loading (pF) Output Loading (pF)

23
 Specifications GAL22V10

GAL22V10B-7/-10/-15/-25L: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS

Vol vs Iol Voh vs Ioh Voh vs Ioh

3 5 4.5

2.5
4
4.25
2

Voh (V)

Voh (V)
Vol (V)

3
1.5 4
2
1
3.75
1
0.5

0 0 3.5
0.00 20.00 40.00 60.00 80.00 100.00 0.00 10.00 20.00 30.00 40.00 50.00 60.00 0.00 1.00 2.00 3.00 4.00

Iol (mA) Ioh(mA) Ioh(mA)

Normalized Icc vs Vcc Normalized Icc vs Temp Normalized Icc vs Freq.

1.20 1.2 1.20

Normalized Icc

Normalized Icc
Normalized Icc

1.10 1.1 1.10

1.00 1 1.00

0.90 0.9 0.90

0.80 0.8 0.80

4.50 4.75 5.00 5.25 5.50 -55 -25 0 25 50 75 100 125 0 25 50 75 100

Supply Voltage (V) Temperature (deg. C) Frequency (MHz)

Delta Icc vs Vin (1 input) Input Clamp (Vik)

10 0
10
8 20
Delta Icc (mA)

30
Iik (mA)

6 40
50
4 60
70
2 80
90
0 100
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 -2.00 -1.50 -1.00 -0.50 0.00

Vin (V) Vik (V)

24
 Specifications GAL22V10

GAL22V10B-15/-25Q: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS

Normalized Tpd vs Vcc Normalized Tco vs Vcc Normalized Tsu vs Vcc

1.2 1.2 1.2

Normalized Tpd

Normalized Tco

Normalized Tsu
1.1 1.1 1.1

1 1 1

0.9 0.9 0.9

0.8 0.8 0.8

4.50 4.75 5.00 5.25 5.50 4.50 4.75 5.00 5.25 5.50 4.50 4.75 5.00 5.25 5.50

Supply Voltage (V) Supply Voltage (V) Supply Voltage (V)

Normalized Tpd vs Temp Normalized Tco vs Temp Normalized Tsu vs Temp

1.3 1.3 1.4

1.2 1.3
1.2
Normalized Tpd

Normalized Tco

Normalized Tsu
1.2
1.1 1.1
1.1
1 1
1
0.9 0.9
0.9
0.8 0.8 0.8

0.7 0.7 0.7

0

0
100

125

100

125

100

125
-55

-25

-55

-25

-55

-25
25

50

75

25

50

75

25

50

75
Temperature (deg. C) Temperature (deg. C) Temperature (deg. C)

Delta Tpd vs # of Outputs Delta Tco vs # of Outputs

Switching Switching
0 0
Delta Tco (ns)
Delta Tpd (ns)

-0.25 -0.5

-0.5 -1

-0.75 -1.5

-1 -2
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10

Number of Outputs Switching Number of Outputs Switching

Delta Tpd vs Output Loading Delta Tco vs Output Loading

12 14

10 RISE 12 RISE
Delta Tco (ns)
Delta Tpd (ns)

10
8 FALL FALL
8
6
6
4
4
2
2
0 0

-2 -2
0 50 100 150 200 250 300 0 50 100 150 200 250 300

Output Loading (pF) Output Loading (pF)

25
 Specifications GAL22V10

GAL22V10B-15/-25Q: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS

Vol vs Iol Voh vs Ioh Voh vs Ioh

1 5 4

0.8 4
3.75

Voh (V)

Voh (V)
Vol (V)

0.6 3
3.5
0.4 2

3.25
0.2 1

0 0 3
0.00 20.00 40.00 0.00 10.00 20.00 30.00 40.00 50.00 60.00 70.00 80.00 0.00 1.00 2.00 3.00 4.00

Iol (mA) Ioh(mA) Ioh(mA)

Normalized Icc vs Vcc Normalized Icc vs Temp Normalized Icc vs Freq.

1.20 1.3 2.00

1.2 1.80
Normalized Icc

Normalized Icc
Normalized Icc

1.10
1.1 1.60

1.00 1 1.40

0.9 1.20
0.90
0.8 1.00

0.80 0.7 0.80

4.50 4.75 5.00 5.25 5.50 -55 -25 0 25 75 100 125 0 25 50 75 100

Supply Voltage (V) Temperature (deg. C) Frequency (MHz)

Delta Icc vs Vin (1 input) Input Clamp (Vik)

10 0
10
8
Delta Icc (mA)

20
30
Iik (mA)

6
40
50
4
60
2 70
80
0 90
0.20 0.70 1.20 1.70 2.20 2.70 3.20 3.70 -2.00 -1.50 -1.00 -0.50 0.00

Vin (V) Vik (V)

26
Copyright © 1997 Lattice Semiconductor Corporation.

E2CMOS, GAL, ispGAL, ispLSI, pLSI, pDS, Silicon Forest, UltraMOS, Lattice Semiconductor, L (stylized) Lattice
Semiconductor Corp., L (stylized) and Lattice (design) are registered trademarks of Lattice Semiconductor Corporation.
Generic Array Logic, ISP, ispATE, ispCODE, ispDOWNLOAD, ispDS, ispDS+, ispGDS, ispGDX, ispHDL, ispJTAG, ispStarter,
ispSTREAM, ispTEST, ispTURBO, ispVECTOR, ispVerilog, ispVHDL, Latch-Lock, LHDL, pDS+, RFT, Total ISP and Twin
GLB are trademarks of Lattice Semiconductor Corporation. ISP is a service mark of Lattice Semiconductor Corporation. All
brand names or product names mentioned are trademarks or registered trademarks of their respective holders.

Lattice Semiconductor Corporation (LSC) products are made under one or more of the following U.S. and international
patents: 4,761,768 US, 4,766,569 US, 4,833,646 US, 4,852,044 US, 4,855,954 US, 4,879,688 US, 4,887,239 US, 4,896,296
US, 5,130,574 US, 5,138,198 US, 5,162,679 US, 5,191,243 US, 5,204,556 US, 5,231,315 US, 5,231,316 US, 5,237,218 US,
5,245,226 US, 5,251,169 US, 5,272,666 US, 5,281,906 US, 5,295,095 US, 5,329,179 US, 5,331,590 US, 5,336,951 US,
5,353,246 US, 5,357,156 US, 5,359,573 US, 5,394,033 US, 5,394,037 US, 5,404,055 US, 5,418,390 US, 5,493,205 US,
0194091 EP, 0196771B1 EP, 0267271 EP, 0196771 UK, 0194091 GB, 0196771 WG, P3686070.0-08 WG. LSC does not
represent that products described herein are free from patent infringement or from any third-party right.

The specifications and information herein are subject to change without notice. Lattice Semiconductor Corporation (LSC)
reserves the right to discontinue any product or service without notice and assumes no obligation to correct any errors
contained herein or to advise any user of this document of any correction if such be made. LSC recommends its customers
obtain the latest version of the relevant information to establish, before ordering, that the information being relied upon is
current.

LSC warrants performance of its products to current and applicable specifications in accordance with LSC’s standard
warranty. Testing and other quality control procedures are performed to the extent LSC deems necessary. Specific testing of
all parameters of each product is not necessarily performed, unless mandated by government requirements.

LSC assumes no liability for applications assistance, customer’s product design, software performance, or infringements of
patents or services arising from the use of the products and services described herein.

LSC products are not authorized for use in life-support applications, devices or systems. Inclusion of LSC products in such
applications is prohibited.

LATTICE SEMICONDUCTOR CORPORATION

5555 Northeast Moore Court
Hillsboro, Oregon 97124 U.S.A.
Tel.: (503) 681-0118
FAX: (503) 681-3037
http://www.latticesemi.com July 1997