Acer CN517-71 - Inventec Covini-Alphard Rev X01 - 6050A3087502 (DIAGRAMAS - com.BR)

6 5 4 3 2 1
THIS DRAWING AND SPECIFICATIONS,HEREIN,ARE THE PROPERTY OF INVENTEC

CORPORATION AND SHALL NOT BE REPODUCED,COPIED,OR USED IN WHOLE OR NOTES:
IN PART AS THE BASIS FOR THE MANUFACTURE OR SALE OF ITEMS WITHOUT 1.HSF Property:Comply iSupplier system HSF property attribute up-to-date value.
WRITTEN PERMISSION,INVENTEC CORPORATION, @2018 ALL RIGHT RESERVED.
F F
E E
D
ALPHARD D
Vinafix.com
2018.12.27
C C
B B
A A
Vinafix.com TITLE
INVENTEC
MODEL,PROJECT,FUNCTION
DESIGN / DRAWER XXX DATE 21-OCT-2002
CHECK MAIN BOARD
21-OCT-2002 APPROVAL SIZE CODE DOC.NUMBER REV
FILE NAME A3 CS 1310xxxxx-0-0 X01
DATE CHANGE NO. REV PCB P/N 60xxxxxxxxxx PCB VER XXX SHEET 1 of 139
6 5 4 3 2 1
8 7 6 5 4 3 2 1
TABLE OF CONTENTS
D 01.PROJECT NAME 36.CANNON LAKE_PCH_H (SPI, GPP) 117.EMI D
02.TABLE OF THE CONTENT 37.CANNON LAKE_PCH_H (DMI, USB2) 118.KB_BL /TURBO/HALL SENSOR
03.BLOCK DIAGRAM 38.CANNON LAKE_PCH_H (CLINK, FAN, PCIE/SATA,HOST)
04.TABLE OF SMBUS,I2C 39.CANNON LAKE_PCH_H (AUDIO, SMBUS, JTAG)
05.POWER BLOCK DIAGRAM
06.GPU POWER BLOCK DIAGRAM
40.CANNON LAKE_PCH_H (LPC/ESPI, USB3, SATA)
41.CANNON LAKE_PCH_H (CORE, VCCGPIO, MPHY) SMALL BOARD1&2
07.DC IN 42.CANNON LAKE_PCH_H (RTC)
08.CHARGER(BQ24780S) 43.CANNON LAKE_PCH_H (GND) 120.TUBRO_BOARD/HALL_SENSOR_BOARD
09.SCP/BATT 44.CANNON LAKE_PCH_H (GPP)
C 10.SYSTEM POWER(P5V0DS)
11.SYSTEM POWER(P5V0)
45.CANNON LAKE_PCH_H (GPP, CLKOUT)
46.CANNON LAKE_PCH_H (GPP) SMALL BOARD3 C
12.SYSTEM POWER(P3V3DS) 47.SYSTEM MEMORY(DIMM0)

13.SYSTEM POWER(VDDQ) 48.SYSTEM MEMORY(DIMM1) 121.USB3.1 PORT1
14.SYSTEM POWER(P1V8DS) 49.THERMAL 122.USB3.1 PORT2
15.SYSTEM POWER(P2V5)
16.SYSTEM POWER(P1V05A)
50.ROM
51.EC_ITE8987EVinafix.com 123.SYSTEM LED
124.LAN
17.SYSTEM POWER(PVCCIO) 52.KB_CNTR 125.RJ45/ESD/TRANSFORMER
18.VCORE&GT&SA CONTROLLER_NCP81215 53.TP_CNTR 126.SPK/JACK
54.AUDIO CODEC ALC255 127.USB LAN AUDIO CNTR
B 19.PVCORE B
55.AUDIO LINE
20.PVCCGT
21.PVCCSA
56.STAT HDD CNTR
57.M.2 FOR WLAN FOR 17 SMALL BOARD1&2
22.POWER LOAD SW 58.M.2 FOR SSD1
23.ENABLE PIN 59.M.2 FOR SSD2 129.KB_BL
24.FAN 60.TYPE-C CNTR 130.KB
61.USB_CHARGER
25.PCB SCREW
62.EDP_CNTR
26.COFFEE LAKE_H_1 (PEG, HDMI) 63.TPM
27.COFFEE LAKE_H_2 (DDI, EDP) 64.USB LAN AUDIO CNTR
28.COFFEE LAKE_H_3 (DDR-1) 65.PCIE REPEATER
66.SEQUENCING
A 29.COFFEE LKAE_H_4 (DDR-2) A
67.SEQUENCING
30.COFFEE LAKE_H_5 (CFG)
31.COFFEE LAKE_H_6 (POWER-1)
32.COFFEE LAKE_H_7 (POWER-2)
33.COFFEE LAKE_H_8 (DECOUPLING)
GPU PAGE 71-116 FROM PAGE 72 INVENTEC
34.COFFEE LAKE_H_9 (GT DECOUPLING) TITLE
35.COFFEE LAKE_H_10 (GND) TABLE OF THE CONTENT
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
CHANGE by DATE A3 CS
XXX 21-OCT-2002
PCB P/N 60xxxxxxxxxx PCB VER XXX SHEET 2 of 139
8 7 6 5 4 3 2 1
Vinafix.com
8 7 6 5 4 3 2 1
D
D
C C
Vinafix.com
B B
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
Vinafix.com CHANGE by
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 3 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
I2C0 BC22 PCH_I2C_CLK TOUCH PANEL

BF23 PCH_I2C_DATA
P3V3S_TP
BF21 PCH_I2C1_DATA TP_I2C_DAT
I2C1 L2N7002DW1T1G TOUCH PAD
BE21 PCH_I2C1_CLK TP_I2C_CLK
D
D
COFFEE LAKE - H DIMM_1
DIMM_2
P3V3S
SMBDATA BF26 PCH_3A_SMDATA PCH_3S_SMDATA
SMBCLK BE26 PCH_3A_SMCLK L2N7002DW1T1G PCH_3S_SMCLK
C C
SML0DATA
SML0CLK
Vinafix.com BATTERY
115 EC_SMB1_CLK CHARGER

I2C1 116 EC_SMB1_DATA
B B
P3V3S
111 SMB0_DATA SMB0_DATA_D THERMAL SENSOR
I2C0 110 SMB0_CLK L2N7002DW1T1G SMB0_CLK_D
DP_REDRIVER
EC
ITE8987 HDMI_RETIMER
P3V3A_KBLED
A I2C_DATA_LED A
L2N7002DW1T1G KB_BL_LED
I2C_CLK_LED
95 GPU_THM_DAT
I2C_RST#
I2CS_SDA_R_G
INVENTEC
I2C3 L2N7002DW1T1G GPU TITLE
94 GPU_THM_CLK I2CS_SCL_R_G MODEL,PROJECT,FUNCTION
TABLE OF I2C
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 4 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
POWER BLOCK
IN/EN OUT IN/EN OUT
PVBAT P5V0DS
P5V0DS P2V5
D SY8288CRAC RT8097ALGE
EN_5V EN_2V5 D
PVBAT
P5V0
SY8284CRAC
EN_5V0
LIMIT_SIGNAL
OCP
P3V3DS
ADAPTOR PVBAT
P3V3DS P1V8A
NB680AGD SY8088AAC
EN_3V EN_1V8
C C
P3V3DS
CHARGE PVBAT P1V2 P3V3A
BATT P3V3A_5A_PWEN APL3523A
BQ24780S EN_VDDQ NB685AGQ
EN_VTT P0V6S CORE_PWEN P3V3S
Vinafix.com
PVBAT
P1V05A
P5V0DS
CORE_PWEN
P5V0S
SY8288CRAC P1V8A APL3523A
PVBAT EN_1V05V P1V8S
CORE_PWEN
B B
PVBAT P1V2
PVCCIO VCCPLL_OC
NB681GD PM514BA
EN_VCCIO VCCPLL_OC_EN
P1V05A
PVBAT PVCCSTG
PVCORE RESUME_PWEN
NCP81215MNTXG APL3523A PVCCST
EN_PVCORE CORE_PWEN
PVBAT
PVCCGT
A NCP81151MNTBG A
VRACPU_DRVON
PVBAT
PVCCSA
VRACPU_DRVON
NCP81253MNTBG INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 5 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GPU POWER BLOCK

D
D
IN/EN OUT
PVBAT
PVCORE_DGPU
GPU_EN MP2886AGU
C C
PVBAT
P1V35S_FBVDDQ
RT8816A
Vinafix.com
EN_VRAM_DGPU
P5V0DS
P1V0S_DGPU
RT8068AZQW
EN_1V0S_DGPU
B B
PVBAT
P1V8S_AON1
SY8284RAC
EN_1V8S_DGPU
A A
INVENTEC
TITLE
TABLE OF I2C
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 6 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
D
BEAD,120OHM,25%,6A,0.02OHM,0805inch,100M
1 L6036 2
120OHM_25%_6A
6014B0225501
1 L6035 2
PVADPTR 120OHM_25%_6A
6014B0225501
C CN8 C
8
8
7
1000PF_50V_2
7
0.01uF_50V_2
6
1000PF_50V_2
0.01uF_50V_2
1
2
6
5
1
1
1
5
4
C6038
C6036
C6037
C6035
4
3
3
2
1
2
2
1
2
Vinafix.com
3
ACES_50290_00801_001_8P
D6035
6012B1061701
6011B0102101_DY
SEM_SM24_SOT23_3P_DY
3
B B
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 7 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Vinafix.com
D
D
PVADPTR
1
TP60000
PVBAT NI
TP24 A
Q60010 Q60011 R60000 Q60012 C60019
8 D S 1 1 S D 8 1 2 8 D S 1 1 2
7 2 2 7 3 4 7 2
6 3 3 6 6 3 CSC0603
5 4 4 5 0.005_1%_6 5 4
R60098 1
1UF_25V_3 4.7_5%_6
G G G
NMOS_4D3S NMOS_4D3S NMOS_4D3S
2
AOS_AONS32304 AONS32306 VRACHG_MP1 AOS_AON6368
C60002 OUT 9
1 2 C60018 PVADPTR
1 2
2
2
470PF_50V_2 PAD60000
C60003
1
9 OUT ACDRV 1 2 VADPBL OUT 9 0.1UF_16V_2

C60098
POWERPAD1X1M
1
0.1UF_25V_3
1
P3V3AL D60000
1
C 1 2 C
2
I A1 A2
200K_1%_2
2
2
C60014
10K_5%_2
C60017
R60007
C
R60002
AOS_AON7506_TRANSISTOR
BAT54C_30V_0_6A
2
R60004 R60005
0.1UF_25V_3 0.1UF_25V_3
3
4.3K_5%_2 4.3K_5%_2 I
10UF_25V_5
10UF_25V_5
1
1
15UF_25V
5
6
7
8
1
C60000
C60001
C60099
VRACHG_CMSRC
+
1
ACPRES
10_5%_5
VRACHG_ACDRV
VRACHG_ACN
Q60000
1VRACHG_ACP
D
R60009
51 9 OUT
NMOS_4D3S
VRACHG_ACDET
Vinafix.com
2
9 OUT
51 OUT HW_I_ADC
0.01UF_50V_2
C60009
7
6
5
4
3
2
2
51 OUT IDCHG U60000
1
51K_1%_2
1
G
1UF_25V_3
S
OUT IMVP_PSYS 1 2
IADP
ACN
ACOK
ACDRV
CMSRC
ACP
ACDET
18
C60012
R60003
PVPACK
1
1
4
3
2
1
C60008 C60007 C60005 TML 29
8 IDCHG VCC 28
VRACHG_VCC L60000 R60001
9 27 1 2 1 2
2
2
PMON PHASE VRPCHG_PH

100PF_50V_2 100PF_50V_2 100PF_50V_2 10 26 3 4
PROCHOT# HIDRV VRPCHG_HG R60015 C60015
NEAR EC NEAR IC NEAR IC 11 VRACHG_BST 1
25 2 VRACHG_BST1 1 2
SDA BTST PCMC063T_3R3MN
12 24 2.2_5%_3 0.01_1%_6
2
SCL REGN
10UF_25V_5
10UF_25V_5
10UF_25V_5
IN ACIN 13 23
1
1
1
CMPIN LODRV VRACHG_REGN 0.047UF_16V_2
B B
OUT ACIN_OK#
C60010
C60011
C60025
14 22 D60001
5
6
7
8
3
CMPOUT GND
R60016
C60021
Q60001
1 2
D
BATPRES#
2.2_5%_3
TB_STAT#
AON7752
BATSRC
BATDRV
A1 A2
1 2
1
SRN
ILIM
SRP
0.1UF_25V_3
0.1UF_25V_3
2.2UF_10V_3
0.1UF_16V_2
2
PROCHOT#
1
8 OUT
C60023
C60022
C60020
EC_SMB1_DATA TI_BQ24780S_QFN_28P 15 BAT54C_30V_0_6A_DY
16
17
18
19
20
VRACHG_SNB
21
51 9 BI
1
G
S
51 9 BI EC_SMB1_CLK
2
BATPRES# C60016
4
3
2
1
9 OUT VRACHG_REGN
2
TB_STAT# OUT 8 9 2200PF_50V_2
OUT
2
0_5%_2_DY
2
VRPCHG_LG
TP60002
R60022
1
P3V3AL
TP24
VRACHG_ILIM
2
1
20K_1%_2
R60013
VRACHG_SRP 1 2 VRACHG_SRP1
R60008 10_5%_2
1 2
1
VRACHG_SRN VRACHG_SRN1
A R60010 10_5%_2 A
VRACHG_BATDRV 1 2 VRACHG_BATDRV1
R60021
CPU_PROCHOT# 1 2 PROCHOT# R60011 4.3K_5%_2
51 30 18 OUT IN 8
49.9K_1%_2
1 2
1
2
R60014
SHORT_0402_15 C60024 R60012 10_5%_2
0.1UF_16V_2
2
1
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 8 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
FOR CHARGER
SCP ARP
PVPACK
D
D
D60002 R60020 R60019

1 2 1 2
1 A1 A2 2
3M_5%_2 1M_5%_2
C
BAT54C_30V_0_6A Q60003
3/19 CHANGE
3
S2
8 IN VADPBL 4
G2 5
0.1UF_25V_3
ACDRV
1
9 8 IN
470K_5%_2
3 D2
D1
R60023
R60017
6
1 2
C60013
G1 2 IN 8 VRACHG_REGN
8 IN VRACHG_MP1 1 S1
100K_5%_2
PVADPTR 2N7002KDW
2
A
6015B0153201-001
1
Q60002
100K_5%_2
1 S1 ACPRES
60110GA0450T
R6098
R60024
G1 2 8 51
IN 1 2 3
BAV99
D6098
R60026 6
1 2 D1
9 8 3
C ACDRV OUT D2
4.7K_5%_3 C
G2 5
2
1K_5%_2 4 2
1
470K_5%_2
S2
8 IN VRACHG_ACDET
2N7002KDW
R60018
2
Vinafix.com
PVPACK
B B
BATT
0.1UF_25V_2_DY
1
1 C68
1
C7699
C7689
0.1UF_25V_2 2 1000PF_50V_2
2
0V BATT_ IN P3V3AL
3V BATT_IN NO BATTERY
51 BATT_IN# R7602
9 1 2 100_5%_2 R7603 CN6050
OUT
1 2 8
8
100K_5%_2 7 G2
7 G
OUT B/I 6 G1
6 G
R6050 100_5%_2 TS 5
5
51 8 IN EC_SMB1_CLK 1 2 BATT_CLK 4
4
51 8 BI EC_SMB1_DATA 1 2 3
3
2
R6051 2
10K_5%_2_DY
A 1 A
2
100_5%_2 1
10K_5%_2
AMC_AZ5125_01H_SOD523_2P_DY
AMC_AZ5125_01H_SOD523_2P
R7601
R7604
ACES_50458_00801_Q01_8P
AMC_AZ5125_01H_SOD523_2P
6012B1061601
2
2
100PF_50V_2
100PF_50V_2
1
100PF_50V_2
1
2
2
D7602
1
C7602
D7600
2
D7601
C7600
C7601
I A
R7501
1
INVENTEC
BATPRES#
1 2 BATT_IN#
2
8 OUT IN 9 51 2
1
2
1
0_5%_3
1
TITLE
Block Diagram
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 9 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
D
PVBAT
VRB5V0A_VCC
I VRB_VDD5
SILERGY_SY8288CRAC_QFN_21P
C C
PAD60210 U60200 OUT 17 18 19 20 21 112
1 2 VRP5V0A_VIN
1 2
2 IN NC 10
I I
3 IN
TP60201
4.7UF_25V_3
4.7UF_25V_3
POWERPAD_2_0610 I P5V0DS
10UF_25V_5
4 16
0.1UF_25V_2
IN NC
1
1
1
1
I I
15UF_25V
5 IN
I I I
C60213
C60210
C60211
C60214
C60212
TP24 9
PG OUT 5V_PG
+
I
R60215 C60215
1 R60205 2 1 R60204 2 11 1 1 2 1 2
EN2 BS
I
4
100K_5%_2 0_5%_2 VRB5V0A_BST VRB5V0A_BST1
2
Vinafix.com
0_5%_3 0.1UF_16V_2
2
23 12 L60200 TP60200
IN EN1
VRP5V0A 1 2
LX 6 VRP5V0A_PH 1 2 1
1
EN_5V
RSC_0603 CSC0402
LX 19 NI
NI
15 20 PAD60200 TP24
OUT PCMC063T_2R2MN
R60216
LDO LX I I I I
VRA5V0A_LDO
22UF_6.3V_5
22UF_6.3V_5
22UF_6.3V_5
22UF_6.3V_5
POWERPAD_4_0610
3
CSC0805
I
C60200
C60201
C60202
C60203
C60204
17 VCC OUT 14
I
2
4.7UF_6.3V_2
1
I VRA5V0A_SNB
4.7UF_6.3V_2
NI
1
C60230
7 13
2
GND
GND
GND
C60216
GND FF
C60209
8
18
21
B B
2
2
2
I
SHORT_0402_15
R60203
I 1 2
I
C60231 R60239
2 1 1 2
VRA5V0A_FF VRA5V0A_FF_R VRA5V0A_VOUT
1000PF_50V_2 1K_5%_2
A A
INVENTEC
TITLE
P5V0DS
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 10 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
D
PVBAT I
A
U60250
I
A SILERGY_SY8284CRAC_QFN_20P
PAD60260 VRP5V0_VIN
1 1 2
2 2 IN NC 10
3 IN
POWERPAD_2_0610 I I I
4 16 P5V0
4.7UF_25V_5
4.7UF_25V_5
0.1UF_25V_2
A A A IN NC
1
1
5 IN
I I I
C60260
C60261
C60262
9
A PG A A OUT 5V0_PG
TP60251 R60254 R60265 C60265
1 2 I
C 1 1 211 EN2 BS 1 1 2 VRB5V0_BST1
I
A C
4
EN_5V0 0_5%_3 A
TP24 0.1UF_16V_2 PAD60250
2
0_5%_2 12
23 IN EN1 VRB5V0_BST L60250 VRP5V0 TP60250
LX 6 VRP5V0_PH 1 2 1 2 1
1 2
19 3 4
1
LX NI
15 20 A 3 4 TP24
VRA5V0_LDO OUT LDO LX I I
22UF_6.3V_5
R60266 CYNTEC_PCMB051H_3R3MS POWERPAD_4_0610
100UF_6.3V
A
1
1
3
RSC_0603_DY
C60250
C60251
VRB5V0_VCC
+
17 VCC OUT 14
I I
1 2
1UF_6.3V_2
1UF_10V_2
A A
Vinafix.com
1
1
VRA5V0_SNB
NI
C60280
C60259
7 13
2
GND
GND
GND
GND FF A
C60266
CSC0402_DY
8
18
21
2
2
I
A
R60253
SHORT_0402_15
I 1 I 2
A A
C60281 R60289
1 2 1 2
B B
1K_1%_2
470PF_50V_2
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 11 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
R60199
D short_0402_15
1 2 D
I NEAR TO VCC_GND
1UF_6.3V_2
2 RSC_04021
1
R60110
C60109
NI
TP60101
1
TP24
2
23 EN_3V IN
P3V3DS
3V_LP# IN
VRA3V3A_VCC
I I
TP60102 1
PVBAT R60115 C60115
VRB3V3A_BST
I
TP24 3.3_5%_3 0.1UF_16V_2
PAD60110 VRP3V3A_VIN 1 2 1 2
1 2
1 2 VRB_VDD3
12
11
10
I VRB3V3A_BST1
110 111 114
9
I I
10UF_25V_5
4.7UF_25V_5
0.1UF_25V_2
POWERPAD_2_0610 I I A OUT 13 16 17
1
1
1
I
15UF_25V
108 109
4
L60100
C60113
PAD60100
EN
AGND
VCC
LP#
C60110
C60111
C60112 1 VIN BST 8

VRP3V3A_PH CYNTEC_PCMB062D_1R5MS TP60100
+
SW 7 1 2 VRP3V3A OUT 12 12 IN 1 2 1
VRP3V3A
C 2 PGND C
VOUT
I TP24
LDO
CLK
1
RSC_0603
PG
U60100 NI
POWERPAD_4_0610
2
I I I I
3
22UF_6.3V_3
22UF_6.3V_3
22UF_6.3V_3
22UF_6.3V_3
MPS_NB680AGD_Z_QFN_12P
R60166
CSC_AX1.6
1
3
4
5
6
VRP3V3A_LDO
C60100
C60101
C60102
C60103
C60104
+
OUT 12 23
VRA3V3A_SNB
NI
2
I
1UF_6.3V_2
1
2
2
NI
1
CSC0402
C60191
Vinafix.com
C60166
51 23 OUT 3V3DS_PG 2
2
VRA3V3DS_VOUT
1
I
0.1UF_16V_2
B B
C60190
I P3V3AL
PAD60191
1 2 1 TP60191
12
23
VRP3V3A_LDO IN 1 2
TP24
POWERPAD1X1M
A A
INVENTEC
TITLE
P3V3DS_NB680A
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 12 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
D
R60346
2 1
OUT VRAVDDQ_FB
I
SHORT_0402_15 VDDQ_PG OUT 23
VRAVDDQ_MODE
VRB_VDD3
IN 12 13 16 17 108
109 110 111 114
R60348 2
RSC_0402
I I
I
R60301 R60300
1 R60302 2 1 2 1 2 VO=0.6*(1+R60300/R60301)
NI
TP60301 1
TP24 SHORT_0402_5 10K_1%_2 10.2K_1%_2
1
C PVBAT NI P1V2 C
23 EN_VDDQ IN 1 R60344 2
TP60351 OUT RSC_0402
I 23 EN_VTT IN NI
1 VRAVDDQ_OTW# R60315 C60315 I
NI
C60348
PAD60310 1 2 1 2 1 R60347 2 1 2 VRAVDDQ_VOUT TP60300
16
15
14
13
12
VRPVDDQ_VIN TP24 11 1
1 1 2
2 VRAVDDQ_BST1 RSC_0402
VRAVDDQ_BST 0.1UF_16V_2
I CSC0402 TP24
SHORT_0603_25 I
CSC0805 NI
FB
EN2
MODE
PG
OTW#
EN1
3
I 1 10
POWERPAD_2_0610
0.1UF_25V_2
22UF_25V_5
VIN BST
1
1
1
9 VRPVDDQ_PH 1 L60300 2 VRPVDDQ

SW
C60310
VTTREF
2 3 4
C60311
C60312
Vinafix.com
1 2
AGND
VDDQ
PGND
VTTS
VTT
3V3
I
CYN_PCMC063T_R68MN_4P
22UF_6.3V_3
22UF_6.3V_3
22UF_6.3V_3
I PAD60300
RSC_0603
U60300 NI
1
CSC0603
CSC0603
I POWERPAD_4_0610
MPS_NB685AGQ_Z_QFN_16P
R60316
4
I I I
C60300
C60301
C60302
C60303
C60304
2
3
4
5
6
7
8
NI NI
OUT VRPVTT 13
2
111 110 VRB_VDD3
16 13 12 IN OUT VRPVTT_REF VRA1V35_SNB
109 108 17
CSC0402
114 NI
1
I
C60316
C60350
1UF_6.3V_2
2
2 1
C60309
B 22UF_6.3V_3 B
2
C60351
I 1 2
1
I
R60349 0.22UF_6.3V_2
SHORT_0402_15
2 1 I
CLOSE TO 3V3 & AGND
I P0V6S
PAD60350
13 1 2
VRPVTT IN 1 2
POWERPAD1X1M
NI 1 TP60350
CSC0603
A A
C60352
TP24
2
INVENTEC
TITLE
VDDQ
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 13 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
D
P1V8A
P3V3DS
I
I TAI_TECH_HPC4018B_2R2M VRP1V8A PAD60600
I U60600 1 2 1 TP60600
PAD60610 L60600 VRP1V8A 14 IN 1 2
VRP1V8A_VIN SILERGY_SY8088AAC_SOT23_5P
1 2 4 3 1 2 14
1 2 VIN LX 1 2 OUT POWERPAD1X1M
C VRP1V8A_PH I C
I
I
330PF_50V_2
POWERPAD1X1M 23 1 5
IN EN VFB
20.5K_1%_2
EN_1V8
2
4.7UF_6.3V_3
GND
I
C60605
R60600
1
10UF_6.3V_3
I
C60610
TP60601
1
1
C60600
2
1
2
VRA1V8A_FB
2
Vinafix.com
10K_1%_2
I
R60601
1
VOUT=0.6*(1+(R60600/R60601))
B B
A A
INVENTEC
TITLE
P1V8DS
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 14 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
D
P2V5
AI
PAD60400
15 1 2
VRP2V5 IN 1 2
C C
POWERPAD1x1m
P5V0DS
1 TP60400
TAI_TECH_HPC4018B_2R2M
AI L60400 TP24
PAD60410 U60400
1 2 VRP2V5_VIN 4 3 1 2
I
VRP2V5_PH 15
1 2
1
VIN LX 1 2 OUT VRP2V5
23 EN_2V5 IN EN
GND
POWERPAD1x1m 5 6
22UF_6.3V_3
22UF_6.3V_3
22PF_50V_2
23 OUT PG FB
2 R60400 1
324K_1%_2
10UF_6.3V_3
1
1
1 RICHTEK_RT8097ALGE_TSOT23_6P
2V5_PG
C60405
Vinafix.com
TP60401 I I
C60400
C60401
2
I I
C60410
I
TP24
2
VRA2V5_FB
2
2 R60401 1
100K_1%_2
I
VOUT=0.6*(1+(R60400/R60401))
B B
A A
INVENTEC
TITLE
P2V5
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 15 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
D
PVBAT I A
I A
U60900
PAD60910 SILERGY_SY8288RAC_QFN_20P
1 2 VRP1V05A_VIN
1 2
2 IN NC 10
NI 3 IN VRA_SY8288_VCC
POWERPAD_2_0610 I A A I A TP60901 4 16 P1V05A
10UF_25V_5
0.1UF_25V_2
1 IN NC IN 16
1
1
CSC0805
5 IN
C60910
C60911
I A I A
TP24 9 23
PG OUT 1V05A_PG
C60912
EN_1V05A VRB1V05A_BST R60915 C60915
23 11 1 1 2 1 2 VRB1V05A_BST1
IN EN BS
4
0.1UF_16V_2
2
2
A I I A
12 NC 0_5%_3 TP60900
1 L60900 2 VRP1V05A1 2
LX 6 VRP1V05A_PH 1
VRB_VDD3 19 3 4
RSC_0603
114 LX NI
15 20 A PAD60900 TP24
CYN_PCMC063T_R68MN_4P I
22UF_6.3V_3
22UF_6.3V_3
22UF_6.3V_3
22UF_6.3V_3
108 17 13 12 IN BYP LX I I I NI
R60916
111 110 109 A A A A POWERPAD_4_0610
CSC0603
3
A
VRA_SY8288_VCC
C60900
C60901
C60902
C60903
C60904
VRA1V05A_VOUT
C 16 OUT 17 VCC FB 14 C
2
I A I
4.7UF_6.3V_2
VRA1V05A_SNB
1UF_10V_2
A
7 13 VRA1V05A_ILMT
2
GND
GND
GND
GND ILMT
NI NI
C60909
1
A
C60930
CSC0402
1
RSC_0402
A
R60905
C60916
1K_5%_2
R60920
8
18
21
I
A
I
2
2
A
100K_1%_2
1
2
2
Vinafix.com
2
R60900
VRA1V05A_FF
220PF_50V_2
1
A
C60920
2
2
VRA1V05A_FB
B I B
133K_1%_2
1
A
R60901
2
VO=0.6*(1+R60900/R60901)
A A
Vinafix.com
INVENTEC
TITLE
P1V0A
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 16 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
D
I PVCCIO
VRPVCCIO
R60526 PAD60500
2 1
17 1 2
IN
I
SHORT_0402_15 1 2
R60506 I VRB_VDD3
C60509 POWERPAD_2_0610 TP60500
32 2 1 2 1 12 13 16 1
IN IN
I
VCCIO_VSSSENSE 108 109 110 111 114
32
1UF_6.3V_2 TP24
VCCIO_VCCSENSE IN 2.2_5%_3
CLOSE TO 3V3 & AGND
1 R60505 2 NI
10 18 19 20 21 112
IN
RSC_0603 VRB_VDD5
23 VCCIO_PG OUT
I
13
12
11
10
PVBAT I U60500 R60515 C60515 I
MPS_NB681GD_Z_QFN_13P 1 2 1 2
0.95V FOR PRE ES USE
VRAVCCIO_BST1
I
PAD60510
AGND
PG
3V3
2.2_5%_3
Vout
VRAVCCIO_BST
1 2 VRPVCCIO_VIN 1 9 0.1UF_16V_2 VRPVCCIO

1 2 Vin BST L60500
8 1 2 17
POWERPAD1X1M I I 2 I
SW
7
VRPVCCIO_PH OUT
3 4
10UF_25V_5
0.1UF_25V_2
PGND MODE
1
VRAVCCIO_MODE
C CYN_PCMC063T_R68MN_4P C
SHORT_0402_5
22UF_6.3V_3
22UF_6.3V_3
22UF_6.3V_3
I I
LP#
EN
C1
C0
C60511
1
2
C60510
C60502
I I
R60529
C60500
C60501
RSC_0603
3
4
5
6
NI
1
R60516
2
2
1
2
Vinafix.com
VRAVCCIO_SNB
CSC0402
NI
1
C60516
23
17
VID1_VCCIO IN
23
17
VID0_VCCIO IN
2
23 EN_VCCIO IN
1
470K_5%_2
1 P3V3A
TP60501
R60523
TP24
100K_5%_2
I
R60522
B I B
2
2
22 LP# IN
NI
2 R60524 1 17 23
LOW_PWR_VTG_SHIFT IN OUT VID0_VCCIO
RSC_0402
NI
2 R60525 1 17 23
LOW_PWR_VTG_SHIFT_N IN OUT VID1_VCCIO
RSC_0402
A A
INVENTEC
TITLE
PVCCIO
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 17 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
I
I I
1 2 1 2 21
C66671 IN
6800PF_25V_2
1
1
1 2 C66652 2200PF_50V_2 R66651 10_1%_2 I
VRASA_CSN1
I I
1 2 I
VRASA_ILIM R66650
C66650
C66651
47PF_50V_2 R66605 40.2K_1%_2
0.033UF_16V_2 100K_1%_NTC
I
1 2 VRASA_CSP1_R I R66652 CLOSE TO L66610
C66670 1 2
2
I I R66670
1 2 1 2 C66605 1000PF_50V_2
I C66607 14K_1%_2
VRASA_COMP1 VRASA_COMP 1 2
I R66653 VRASA_CSP1
0.01UF_50V_2 1K_1%_2 I C66682 1 2
1 2 470PF_50V_2 IN 21
I R66607 7.5K_1%_2
1000PF_50V_2 1 2
P3V3S PVCCST
I 127K_1% EN_PVCORE
R66681 R66682
32 VCCSA_VSSSENSE 1 2 VRASA_VSN1 1 2 R66602 23
IN NI
1 2 IN 30
1
VRASA_VSN
SHORT_0402_15 I 2K_1%_2 RSC_0402 I I NI I
1UF_10V_2
100_1%_2
1
1
C66680
45.3_1%_2
PVCORE_PG
RSC_0402
OUT 23 R66000
R66101
R66100
D 1000PF_50V_2
R66104
C66100
I I SHORT_0402_5
I
1 R66693 2 D
R66680 VRAVR_ON
VCCSA_VCCSENSE 1 2 1 R66683 2 VRASA_VSP
2
32 IN 37.4K_1%_2
VRASA_VSP1 VRASA_PWM1 OUT 18
6.98K_1%_2 OUT 21 NI
SHORT_0402_15
1
RSC_0402
I
C66683 VRAVR_ON 18
IN
R66001
1 2 TP66001
I 1
VRACPU_SVID_CLK 1 2 VR_SVID_CLK 30
1000PF_50V_2 IN
VRASA_IMON
R66102 49.9_1%_2 TP24
VR_SVID_ALERT#
2
IN 30
R66180
31 VCCSENSE 1 2
IN VRACPU_SVID_DATA 1 I 2 VR_SVID_DATA
IN 30
1
I C66182 VRACPU_VSP
SHORT_0402_15 I 1 2 R66103 10_1%_2 I R66105
C66180 1 2 CPU_PROCHOT# 8 30
IN 51
1000PF_50V_2 1000PF_50V_2 R66480
75_1%_2 1 2 VGT_VCCSENSE
VRACPU_PROCHOT#
IN 35
1
53
52
51
50
49
48
47
46
45
44
43
42
41
40
R66181 I R66182
VSSSENSE 1 2 2 1 2 VRACPU_VSN C66482 I SHORT_0402_15
31 IN 1 I 2
VRACPU_VSN1 C66480
SHORT_0402_15 1K_1%_2 I 1000PF_50V_2
1000PF_50V_2
I
I C66172 I R66170 I C66170 I R66482 R66481
CSP_1PH
IMON_1PH
PWM_1PH / ICCMAX_1PH
EN
ALERT#
VR_RDY
SCLK
SDIO
1 R66107
Tab
VSP_1ph
VSN_1ph
COMP_1ph
ILIM_1ph
CSN_1ph
1 2 1 2 1 2 2 1 2 1 2 VGT_VSSSENSE
2
IN 35
VRACPU_FB1 1K_1%_2
I VRAGT_VSN1 SHORT_0402_15
26.7K_1%_2 I
47PF_50V_2 49.9_1%_2 270PF_50V_2 R66407 C66470 I R66470 I C66472
C 1 2 1 2 1 2 1 2 C
I I
R66172 C66171 I R66171 I C66107 1 39 VRAGT_FB1
1 2 1 2 1 2 1 2 VSP_4PH VR_HOT# 32.4K_1%_2 47PF_50V_2
2 38 VRAGT_VSP 270PF_50V_2 49.9_1%_2
VSN_4PH VSP_2PH I C66407 I I
VRACPU_COMP1
VRACPU_IMON 3 37 VRAGT_VSN 1 2 I R66471 C66471 R66472
470PF_50V_2 IMON_4PH VSN_2PH 1 2 1 2 1 2
3K_1%_2 3300PF_50V_2 1K_1%_2 VRACPU_DIFFOUT 4 36 VRAGT_IMON
DIFFOUT_4PH IMON_2PH
VRACPU_FB 5 35 VRAGT_DIFFOUT 470PF_50V_2
FB_4PH DIFFOUT_2PH 1K_1%_2
VRACPU_COMP 6 34 VRAGT_FB 3300PF_50V_2 3K_1%_2
COMP_4PH FB_2PH I
VRACPU_CSP1 I I R66151 R66005 VRACPU_ILIM 7 ILIM_4PH COMP_2PH 33 VRAGT_COMP VRAGT_COMP1
1 R66112 2 1 2 VRACPU_CSCOMP 8 U66000 32 VRAGT_ILIM 1 R66305 2 I

18 IN VRACPU_CSCOMP1 30.1K_1%_2 CSCOMP_4PH ILIM_2PH R66451 I
Vinafix.com
19 9 31 1 2
1000PF_50V_2
93.1K_1%_2 75K_1%_2 NI I VRACPU_CSSUM CSSUM_4PH CSCOMP_2PH VRAGT_CSCOMP VRAGT_CSCOMP1 R66412 2 VRAGT_CSP1 20

ON_NCP81215MNTXG_QFN_52P 13K_1%_2 1 18
10 30 IN
1
VRACPU_CSP2 I VRACPU_CSREF CSREF_4PH CSSUM_2PH VRAGT_CSSUM

CSC0402
165K_1%_2
1200PF_50V_2
1 R66122 2 I
VRACPU_CSP1_R 11 29 VRAGT_CSREF I NI 75K_1%_2 54.9K_1%_2
18 IN CSP1_4PH CSREF_2PH
C66151
1
I R66150 VRACPU_CSP2_R 12 28 I
C66150
CSC0402
19
R66152
165K_1%_2
93.1K_1%_2 CSP2_4PH CSP1_2PH VRAGT_CSP1_R
1 2
C66450
I
VRACPU_CSP3_R 13 27 I R66450
C66451
VRACPU_CSP3 R66132 CSP3_4PH CSP2_2PH VRAGT_CSP2_R
1 2
R66452
18 1 2
19
IN 100K_1%_NTC
93.1K_1%_2
2
I 100K_1%_NTC
PWM1_4PH / ICCMAX_4PH
PWM1_2PH / ICCMAX_2PH
VRACPU_CSP4 R66142
PWM4_4PH / ROSC_MPH
1 2 CLOSE TO L66310
PWM2_2PH / ROSC_1PH
2
18 IN NI
TTSENSE_1PH /PSYS
19
PWM3_4PH / VBOOT
93.1K_1%_2 VRB_VDD5
PWM2_4PH / ADDR
R66137 20 21 112
VRACPU_CSP1 1 2 10
IN
TTSENSE_2PH
I
VRACPU_CSN1
TSENSE_4PH
I R66113 1 R66114 2 17 18 19
1 2 19 18 IN
CSP4_4PH
19 IN RSC_0402
4.64K_1%_2
B 10_1%_2 B
DRON
NI
VRMP
R66115
0.01UF_50V_2
VCC
I 1 2 I
1
I VRACPU_CSP4 R66413 VRAGT_CSN1

RSC_0402 R66144 2 1 2
C66113
VRACPU_CSN2 R66123 1 18 20
1
I
2 VRACPU_CSREF C66114
I IN 19 I IN
19 4.64K_1%_2 VRAGT_CSP1
IN 1 2 R66414
0.01UF_50V_2
18 IN I
1 2 I 10_1%_2
10_1%_2 IN 18 20
1
C66144 VRACPU_CSREF
0.047UF_25V_2
14
15
16
17
18
19
20
22
23
24
25
26
21
1 2 5.1K_1%_2
C66413
VRACPU_CSP2 VRACPU_TSENSE VRACPU_CSP4_R 18
I IN
2
VRACPU_CSN3 R66133 19 18 1 R66124 2

1
I
2
IN VRACPU_VRMP 0.047UF_25V_2
I
C66414 VRAGT_CSREF
19 4.64K_1%_2 VRAGT_TSENSE
IN R66195 1 2
IN
10_1%_2 VRACPU_VCC
VRACPU_CSREF C66124 VRACPU_PSYS 2 1 8
I IN 0.047UF_25V_2
2
VRACPU_CSN4 R66143 18 1 2
1
I
2
OUT SHORT_0402_15
I
19 IN IMVP_PSYS
0.047UF_25V_2 R66424
10_1%_2 1 2
VRACPU_CSP3 IN VRB_VDD5 10 17 18 19 20 21 112
I
1
R66134
CSC0402
19 18 1 2 1K_5%_2
IN
C66198
4.64K_1%_2
1
NI I I I
25.5K_1%_2
CSC0402
1
1
102K_1%_2
130K_1%_2
130K_1%_2
16K_1%_2
I NI
24.9K_1%_2
4.3K_1%_2
R66197
C66197
VRACPU_CSREF I C66134 I
R66093
R66091
R66090
R66690
1 2
2 R66092
2 R66393
18 IN I
H-LINE 62 45W CPU.
2
0.047UF_25V_2
VCCIA MAX CURRENT=128A ; LOADLINE = TBD MV/A
2
2
2
R66136 NI
SHORT_0402_15
VCCGT MAX CURRENT = 55A ; LOADLINE = 3.1MV/A 1 2
1
VCCSA MAX CURRENT = 11A ; LOADLINE = 10 MV/A
SHORT_0402_15
RSC_0402
A 112 A
R66461
20
1
VRB_VDD5
PVBAT_CPU 18
IN 10
R66161
I
I IN 19 17
1
1
1K_5%_2
19 I
2_5%_2
R66109
2
21
R66199
0.1UF_16V_2
VRACPU_DRVON
VRACPU_PWM1
VRACPU_PWM2
VRACPU_PWM3
VRACPU_PWM4
C66460
VRAGT_PWM2
2
VRAGT_PWM1
I VRAGT_TSENSE1
0.1UF_16V_2
1
100K_1%_NTC
I I
C66160
VRACPU_TSENSE1
2
1
18.7K_1%_2
100K_1%_NTC
I
I
INVENTEC
R66462
R66460
1
18.7K_1%_2
2
1UF_10V_2
1
1
0.01UF_50V_2
I
R66162
R66160
C66109
I
C66199
2
TITLE
2
OUT
OUT
OUT
OUT
OUT
OUT
OUT
2
CPU VR CONTROLLER
CLOSE TO U66310
DOC.NUMBER REV
Vinafix.com
A3 CS
20
19
19
19
19
CHANGE by XXX DATE 21-OCT-2002

CLOSE TO U66010 PCB P/N PCB VER SHEET
60xxxxxxxxxx XXX 18 of 139
8 7 6 5 4 3 2 1
20
19
21
6 5 4 3 2 1
PVCORE
PVBAT
F F
I I
C66015 TP66000 1 PAD66010 PVBAT_CPU
2
VRACPU_BST11
1 1 R66017 2 1 2
IN VRB_VDD5 10 17 18 19 20 21 112
TP24
1 2 OUT 18 19
330UF_2V_9MR_PANA_-35%
1
3 1UF_6.3V_2
2.2_5%_3 NI NI
1 R66015
0.22UF_16V_2 I I I I I
POWERPAD_2_0610
22UF_6.3V_3
22UF_6.3V_3
22UF_6.3V_3
I I I I
2.2UF_6.3V_2
3.3_5%_3
1
1
1
CSC_DX1.9
CSC_DX1.9
CSC0603
CSC0603
10UF_25V_5
10UF_25V_5
10UF_25V_5
10UF_25V_5
I I I I
C66018
C66017
1
4.7UF_25V_3
4.7UF_25V_3
4.7UF_25V_3
4.7UF_25V_3
VRACPU_BST1
I I I I
15UF_25V
15UF_25V
15UF_25V
15UF_25V
C66000
C66001
C66002
C66004
C66003
C66006
C66007
C66008
C66009
I
C66299
C66298
C66297
C66296
C66010
C66011
C66021
C66020
C66031
C66030
C66041
C66040
+
+
I
I
2
VRACPU_BST12
2
2
2
2
29
2
7
5
PHASE
BOOT
VCC
VCCD
8
18
19
PVBAT_CPU IN 9
VIN
1
10
VIN PWM
30
IN VRACPU_PWM1 18
11
VIN DISB# IN VRACPU_DRVON
18 19 20 21
VIN
THWN 31
20 21 112
2
SMOD#
IN VRB_VDD5 10
18
17
19 PVCORE
I
U66010
ON_NCP302045MNTWG_PQFN_33P
L66010
12 PGND SW 26 VRACPU_PH1 1 2
1 2
E 13 PGND SW 25 3 4 E
3 4
14 PGND SW 24
15 23 MAGLAYERS_MMD_10CZ_R15MGX2I
PGND SW I
28
CGND
AGND
10_5%_3
PGND
VRACPU_CSN11
SW
SW
SW
SW
SW
SW
SW
NC
GL
GL
R66016
R66018 VRACPU_CSN1 I I
1 2
OUT 18 C66025 R66027
27
33
6
32
4
16
17
18
19
20
22
VRACPU_BST21
1
21
SHORT_0402_15 2 1 1 2
VRACPU_SNB1 I IN VRB_VDD5 10 17 18 19 20 21 112
I
1000PF_50V_2
VRACPU_CSP11
1
1
3 1UF_6.3V_2
0.22UF_16V_2 2.2_5%_3
2.2UF_6.3V_2
1
1 R66025
C66016
R66019 VRACPU_CSP1
VRACPU_BST2
C66027
I
3.3_5%_3
2 C66028
1 2
OUT 18
I
I
220_1%_2
2
2
VRACPU_BST22
2
29
7
5
PHASE
BOOT
VCC
VCCD
8
18
19
PVBAT_CPU IN 9
VIN
1
10
VIN PWM
30
IN VRACPU_PWM218
11
VIN DISB#
IN VRACPU_DRVON
18 19 20 21
VIN
THWN 31
20 21 112
D 2 D
I
SMOD#
IN VRB_VDD5 10
18
17
19 PVCORE
U66020
L66020
1 2
13 25 3 4
Vinafix.com
PGND SW
I 3 4
14 PGND SW 24
10_5%_3
15 23 MAGLAYERS_MMD_10CZ_R15MGX2I
PGND SW
R66026
28
CGND
AGND
PGND
VRACPU_CSN21
SW
SW
SW
SW
SW
SW
SW
NC
GL
GL
R66028 VRACPU_CSN2
1
1 2
VRACPU_SNB2 I OUT 18
27
33
6
32
4
16
17
18
19
20
22
21
1
SHORT_0402_15
1000PF_50V_2
C66026
I
VRACPU_CSP21
R66029 VRACPU_CSP2
1 2
OUT 18
2
220_1%_2
I
I
C66035 R66037
C 2
VRACPU_BST31
1 1 2 C
IN VRB_VDD5 10 17 18 19 20 21 112
1
3 1UF_6.3V_2
0.22UF_16V_2 2.2_5%_3
2.2UF_6.3V_2
1
VRACPU_BST3
1 R66035
C66038
C66037
3.3_5%_3
I
I
2
VRACPU_BST32
I
2
2
29
7
PVBAT_CPU I
PHASE
BOOT
VCC
VCCD
I
8
19 18 IN 9
VIN
1
C66045
VRACPU_BST41
R66047
10
VIN PWM
30
IN VRACPU_PWM318 2 1 1 2
IN VRB_VDD5 10 17 18 19 20 21 112
11
VIN DISB#
IN VRACPU_DRVON
18 19 20 21
1
3 1UF_6.3V_2
VIN 0.22UF_16V_2 2.2_5%_3
2.2UF_6.3V_2
1
1 R66045
31
C66047
VRACPU_BST4
THWN
C66048
I
3.3_5%_3
2
SMOD#
IN VRB_VDD5 10 17 18 19 20 21 112
I
I PVCORE
U66030 I
2
2
VRACPU_BST42
2
29
L66030
7
1 2
13 PGND SW 25 3 4
I 3 4
B 14 PGND SW 24 B
2
MAGLAYERS_MMD_10CZ_R15MGX2I
10_5%_3
15 23 PVBAT_CPU
PHASE
BOOT
VCC
VCCD
PGND SW
R66036
28 8
CGND
AGND
PGND
VRACPU_CSN31 19 18 IN VIN
SW
SW
SW
SW
SW
SW
SW
NC
GL
GL
9 1
10
VIN PWM
30
IN VRACPU_PWM418
11
VIN DISB#
IN 18 19 20 21
R66038 VRACPU_CSN3 VIN VRACPU_DRVON
1
1 2 31
VRACPU_SNB3 I OUT 18 THWN
2 20 21 112
27
33
6
32
4
16
17
18
19
20
22
IN
21
SMOD#
VRB_VDD5 10 17
1000PF_50V_2
1
SHORT_0402_15 18 19 PVCORE
I
C66036
I
VRACPU_CSP31
U66040
R66039 VRACPU_CSP3
1 2 ON_NCP302045MNTWG_PQFN_33P
OUT 18
L66040
2
220_1%_2 12 PGND SW 26 VRACPU_PH4 1 2

1 2
13 PGND SW 25 I 3 4
3 4
14 24 2
1000PF_50V_2 10_5%_3
PGND SW
MAGLAYERS_MMD_10CZ_R15MGX2I
R66046
15 PGND SW 23
28
CGND
AGND
PGND
VRACPU_CSN41
SW
SW
SW
SW
SW
SW
SW
NC
GL
GL
VRACPU_SNB4
R66048 VRACPU_CSN4
1 1
I
1 2
OUT 18
C66046
27
33
6
32
4
16
17
18
19
20
22
21
SHORT_0402_15
I
VRACPU_CSP41
R66049 VRACPU_CSP4
1 2
2
OUT 18
A A
220_1%_2
INVENTEC
Vinafix.com TITLE
PVCORE
SIZE CODE DOC.NUMBER REV

CHANGE by XXX DATE 21-OCT-2002 C CS 1310xxxxx-0-0 X01
6 5 4 3 2 1
8 7 6 5 4 3 2 1
112 21 19 18 17 10 VRB_VDD5 20
IN IN PVBAT_GT
2.2_5%_3
I
4
1
4
C66315
ALPHA_AON6994_8P
ALPHA_AON6994_8P
R66317
VRAGT_BST11 2 1
G1
D1
D1
D1
Q1
G1
D1
D1
D1
Q1
I
2
0.22UF_16V_2
2.2_5%_3
R66315
I
2
I
I
Q66311
Q66310
PHASE
1UF_25V_3
PHASE
1
Q2
S2
S2
D
Q2
VRAGT_BST1
G2
S2
S2
S2
G2
S2
C66317
D
1
I
9
8
5
U66310 PVCCGT
9
8
5
1
I
2
4 VCC HG 8 VRPGT_HG1
BST
I
L66310
I SW 7 VRPGT_PH1 1 2
PAD_GND
2 1 2
18 R66311 3 4
VRAGT_PWM1 IN 1 2 3
PWM
5
I
3 4
GND
VRPGT_LG1
2
21
18
19
VRACPU_DRVON IN EN LG
10_5%_3
TRIO_EM_15BM66V03
R66316
ON_NCP81151MNTBG_DFN_8P
51_5%_2
6
9
VRAGT_CSN11
VRAGT_CSP11
VRAGT_SNB1 R66318 VRAGT_CSN1
1
1 2 18
I OUT
1000PF_50V_2
1
SHORT_0402_15
C66316
R66319 VRAGT_CSP1
1 2 18
OUT
2
SHORT_0402_15
C C
PVBAT
Vinafix.com 1
PAD66310
1 2
2 PVBAT_GT OUT 20
4.7UF_25V_3
4.7UF_25V_3
POWERPAD_2_0610 I I
I
1
15UF_25V
15UF_25V
1UF_25V_2
I I
1
C66599
C66598
C66310
C66311
C66312
+
+
2
2
B B
PVCCGT
1
TP66300
TP24
22UF_6.3V_3
22UF_6.3V_3
22UF_6.3V_3
22UF_6.3V_3
22UF_6.3V_3
I I I I
CSC_DX1.9
1
1
1
1
C66308
C66309
C66300
C66301
C66303
C66306
C66307
+
+
2
2
2
2
A A
INVENTEC
TITLE
PVCCGT
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3
SHEET
CS
20 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
D
PVBAT_SA 21
IN
PVBAT
4
AOS_AON6996
PAD66610
G1
D1
D1
D1
Q1
1 2 PVBAT_SA 21
I
R66615
I
C66615 I 1 2 OUT
1 2 1 2
POWERPAD_2_0610 I
10UF_25V_5
10UF_25V_5
I
Q66610
1
VRASA_BST11
PHASE
C66610
C66611
Q2
2.2_5%_3 0.1UF_16V_2
S2
S2
G2
S2
VRASA_BST1
C I PVCCSA C
9
8
5
U66610
2
1 BST HG 8 VRPSA_HG1 I
L66610
18 VRASA_PWM1 2 7 VRPSA_PH1 1 2
IN PWM SW
3 1 2 4
RSC_0603
3 6 3 4
20 19 18 VRACPU_DRVON
IN EN GND
PCME064T_R42MS1R557
R66616
4 5 VRPSA_LG1
Vinafix.com
20 19 18 17 10 VRB_VDD5
IN VCC LG NI
2.2UF_6.3V_2
112
1
PAD
C66617
2
PVCCSA
VRASA_CSN11
VRASA_CSP11
ON_NCP81253MNTBG_DFN_8P
9
VRASA_SNB1
TP66600
2
1
TP24
NI NI
22UF_6.3V_3
22UF_6.3V_3
22UF_6.3V_3
I I I
1
CSC0603
CSC0603
1
CSC0402
R66618
C66616
C66600
C66601
C66602
C66603
C66604
1 2 18
OUT
NI
B SHORT_0402_15 VRASA_CSN1 B
I
2
2
R66619 VRASA_CSP1
1 2 18
OUT
220_1%_2
A A
INVENTEC
TITLE
PVCCSA
DOC.NUMBER REV
IN
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 21 of 139
8 7 6 5 4 3 2 1
6 5 4 3 2 1
P3V3DS
1UF_6.3V_2
IEC PN Vendor Vendor PN
C7019
P3V3A
F I
6019B1184301 Anpec APL3523AQBI-TRG Main source F
A
I
6019B1270101 AOS AOZ1331 2nd
2
A
10UF_6.3V_3
C7010
I
P5V0DS U2 A
TML 15 PAD7003
1 VIN1 VOUT1 14 I 1 1 2
2
2
2 13 A
VIN1 VOUT1
P3V3A_5A_PWEN 3 12 C7013
1 220PF_50V_2
2 POWERPAD_2_0610
51 23 IN I
A 4
EN1 SS1
11
R7024 VBIAS GND
51
109 23 22 IN CORE_PWEN 2 1 CORE_PWEN_RC 5 EN2 SS2 10 1 2 I
A
6 VIN2 VOUT2 9 C7012 220PF_50V_2
1K_5%_2 7 8
P3V3DS VIN2 VOUT2
ANPEC_APL3523A_TDFN_14P
6019B1184301-001 P3V3S
1UF_6.3V_2
I
A
1
C7017
10UF_6.3V_3
I
C7018
A
PAD7002
1 2
2
1 2
2
POWERPAD_2_0610
E E
P5V0DS
1UF_6.3V_2
C7016
2.24 AMP
2 I
A
P5V0S
I
A
Vinafix.com
10UF_6.3V_3
I
C137
A
U7002 15
TML PAD1
I 1 VIN1 VOUT1 14 I 1 1 2
2
2
A 2 A
13 C131
VIN1 VOUT1
CORE_PWEN 1 R7029 2 10K_1%_2 3 12 1 POWERPAD_2_0610
51
109 23 22 IN I
A
EN1 SS1 2
4 VBIAS GND 11 220PF_50V_2
CORE_PWEN 1 R38 2 10K_1%_2 5 10 1 2 I
51
109 23 22 IN 6
EN2 SS2
9 C7014
A
VIN2 VOUT2 1000PF_50V_2 VCCPLL_OC
P1V8A 7 VIN2 VOUT2 8 0.05 AMP DB 1019
ANPEC_APL3523A_TDFN_14P P1V8S
SI 1128
1
1UF_6.3V_2
2
6019B1184301-001 I VCCPLL_OC
A P1V2 I
P5V0DS
C7020
A
R7035
Q7007
D I
A PM514BA
D
150_5%_3
2
I Q10 D D S S
1
2
S1
1
A
VCCPLL_OC_EN 2 C7041 C7042
R143 22 IN G1
2 1 2 1
6
G
1M_5%_2
D1
D2 3 VCCPLL_OC_DIS
VCCPLL_OC_DISCHARGE_EN 5 1UF_6.3V_2 1UF_6.3V_2
G
G2
1
I
Vinafix.com
A
4
S2 C4626
2
2N7002KDW 2 1
0.01UF_50V_2
R144 2M_5%_2_DY P5V0DS
I
A
P1V8A P3V3A
Q7006
1
VCCPLL_OC_EN S1 1
22 IN 2 G1
100K_5%_2
100K_5%_2
6 R7038 1 2 100K_5%_2
2
D1
I I D2 3 R7039 1 2 100K_5%_2
R7066
R7065
A A 5 G2
4
NI S2
A
1
2N7002KDW
CSC0402
1
CPU_C10_PWR_GATE_BASE
SI 1128
C7039
1
CPU_C10_PWR_GATE#
2 3 CPU_C10_PWR_GATE#_R PVCCSTG
B
46 IN E C
2
I
1
A
C C
2
I
Q7010
SHORT_0402_5
A
P5V0DS
R7063
LMBT3904LT1G R7034
I
A
A
150_5%_3
2
Q9
2
I
S1 1
1
I VCCPLL_OC_EN A
R7069 1 A 2 0_5%_2
OUT 22 PVCCSTG_EN 2
R145 22 IN G1
LP# I
17 OUT R7068 1 A 2 0_5%_2 1M_5%_2 6
PVCCSTG_DIS
P D1
D2 3
5 I A
PVCCSTG_DISCHARGE_EN 5 G2
V
1
0 4
5
DU7006 S2
2
1 S 2N7002KDW
+
4 I PVCCSTG_EN
R7070 1 A 2 0_5%_2
OUT 22
CORE_PWEN 2 R146 2M_5%_2_DY
51
109 23 22 IN
-
TC7SET08FU
1
3
P1V05A I
A
C100
2 1
P1V05A P5V0DS 22UF_6.3V_3

I
B I
A
A B
I C7037
A 1 2
C7038
2 1 1UF_6.3V_2
PVCCSTG
PVCCSTG_EN 1UF_6.3V_2 U7003
22 IN TML 15
1 VIN1 VOUT1 14 I
2 13 A
1
R7030 VIN1 VOUT1

10UF_6.3V_3
RESUME_PWEN 1 2200K_5%_2_DY 3 12 1 2 I
51 23 IN I
A 4
EN1 SS1
11
A
VBIAS GND C7035 1000PF_50V_2
C7205
CORE_PWEN 1 R37 2 5 10 1 2 I
51
109 23 22 IN 6
EN2 SS2
9
A
10K_5%_2 VIN2 VOUT2 C17 1000PF_50V_2
I I 7 8
0.01UF_50V_2
A A VIN2 VOUT2
1000PF_50V_2
1
PVCCST
C7032
ANPEC_APL3523A_TDFN_14P
C7034
6019B1184301-001 VCCSFR
I
A
R4570 2 1
2
SHORT_0402_15_NSP
I
10UF_6.3V_3
A
1
C2990
2
A A
INVENTEC
Vinafix.com TITLE
DDR3_SO-DIMM0

CHANGE by XXX DATE C CS 1310xxxxx-0-0 X01
PCB P/N 60xxxxxxxxxx
<ENG> PCB VER 21-OCT-2002
XXX
<VER> SHEET of 22 139
6 5 4 3 2 1
8 7 6 5 4 3 2 1
1. P3V3DS / P5V0DS 3. P1V2 / P1V8 / VCCSFR(PVCCST)

DB 1011
P3V3A NI
2
A
P5VDS_EN R6901 D7000

51 IN
NC
0_5%_2_DY 3 1
1
10K_5%_2
I I I
A
I
A A A
R7008
R7037 BAT54_30V_0.2A_DY
VRP3V3A_LDO 1 2 1 R6900 2 2 R6980 1 EN_5V0 I
12 IN OUT 11 6011A0026801_DY
A
10K_5%_2
A 10K_5%_2 SHORT_0402_5 DDR_VTT_PG_CTRL 1 R7001 2 EN_VTT
I 47 IN OUT 13
2
C7023 1
2 0_5%_2
D I
A P3V3AL VDDQ_PG OUT 13 2 1 NI
A
0.1uF_16V_2
D
R7015 C7015 100PF_50V_2_DY
1 2 R6988 EN_5V OUT 10
10K_5%_2
I 0_5%_2_DY
I
CLOSE TO POWER SIDE
A A
R7012 P3V3A
51 ALWAYS_PW_EN 2 1 EN_3A5A 2 R6987 1 EN_3V 12
IN OUT
SHORT_0402_5 P3V3A
1K_5%_2 I
A P3V3S
10K_5%_2_DY
1
2
I I
0_5%_2
A A
R7006
1 R7033
R7013 C7006
2 R7016 1
10K_5%_2
200K_5%_2 0.1UF_25V_2
A
A
I
I
G
2
S
THERMTRIP# 1V05A_PG
D
D S
OUT 49 16 IN
Q7003
PANJIT_2N7002KW_3P VCCIO_PG R7018 ALL_PWGD_INTO_EC
17 1 2 51
SI 1128 IN OUT
2
0_5%_2
D7001
NC
R7027 P3V3S
1 3 1 2
C 2. P1V0A / P1V8A / P3V3A DIODE-BAT54-TAP-PHP 100_5%_2

C
1
10K_5%_2
I A
EN_2V5
A
I
P3V3A RESUME_PWEN 1 R7040 2
R7010
I I 51 23 22 IN OUT 15
A A
100K_5%_2
0.22UF_6.3V_2
1 R7017 2 1 R7002 2 EN_1V8
1
OUT 14
2
10K_5%_2 0_5%_2
C7033
I
A
Vinafix.com
PVCORE_PG 1 R7009 2 PCH_PWROK
P3V3A_5A_PWEN R148 18 IN OUT 39
51 23 22 IN
0_5%_2
2
0_5%_2_DY
A
C138 2 C140 1
I
0.01UF_50V_2_DY 0.1uF_16V_2
CLOSE TO POWER SIDE I
A
RESUME_PWEN 1 R7041 2
I 51 23 22 IN
2
A
10K_5%_2
D7005
NC
R7042
B 3 1 2V5_PG 1 2 B
15 IN A EN_VDDQ OUT 13
SHORT_0402_5
A
DIODE-BAT54-TAP-PHP I
C7000 D7002
60110GA0367T 2 1
NC
A
P3V3A_5A_PWEN 1 I R7003 2 EN_1V05A 0.1uF_16V_2

51 23 22 IN OUT 16
47K_5%_2
A
I
C139 DIODE-BAT54-TAP-PHP_DY
2 1
I
PVCORE
0.1uF_16V_2 SI_BULD A
R7004 2
51 IN ALL_PWGD_IN 1 EN_PVCORE OUT 18 30
CLOSE TO POWER SIDE 0_5%_2
P3V3AL
2
I
A D7004 R7007
NC
R7014 1 R7021 2 3V3DS_PG

IN 12 51 3 1 100K_5%_2_DY
100K_5%_2_DY I
0_5%_2
A
1 R7019 2 RSMRST# 39 51 DIODE-BAT54-TAP-PHP
OUT
0_5%_2
C7011 R7054
51
109 22 IN CORE_PWEN 1 2 EN_VCCIO OUT 17
0.022UF_16V_2
A 47K_5%_2 A
1000PF_50V_2_DY
1
C7036
P3V3A
2
I
A
R7043
INVENTEC
1 2 VID1_VCCIO OUT 17
100K_5%_2
I
A
R7044 TITLE
1 2 VID0_VCCIO OUT 17
100K_5%_2 Block Diagram
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
<ENG>
DATE
PCB VER XXX
<VER>
21-OCT-2002
A3
SHEET
CS
of 23 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 4300~4349(FAN)
REFERENCE 4411~4449(THERMAL )
TP4300 1
TP4301 1
P5V0S TP24 P5V0S TP24

I I
PAD4300 P5V0S_FAN1 PAD4301

1 1 2
2 1 1 2
2 P5V0S_FAN2
4.7UF_6.3V_3
4.7UF_6.3V_3
0.1UF_16V_2
0.1UF_16V_2
1
1
D POWERPAD1x1m POWERPAD1x1m
1
1
D
C4307
C4303
C4304
C4308
P3V3S P3V3S
2
2
2
1
1
10K_5%_2
10K_5%_2
10K_5%_2
10K_5%_2
1
1
R4300
R4305
R4302
R4301
CN4300 CN4301
51
2
2
1 1 1 1
51 IN FAN1_TACH 2 2 IN FAN2_TACH 2 2
51 IN FAN1_PWM 3 3 G G1 51 IN FAN2_PWM 3 3 G G1
4 G2 4 G2
220pF_50V_2
220pF_50V_2
4 G 4 G
CSC0402_DY
CSC0402_DY
1
1
1
1
TP4302
C4305
1 ACES_50279_00401_Q01_4P TP4303 ACES_50279_00401_Q01_4P

C4301
C4306
C4300
6012B0000520 1 6012B0000520
TP24
TP24
2
2
2
2
C C
FAN1 CN Vinafix.com
CPU FAN2 CN CPU
B B
A A
INVENTEC
TITLE
FAN & THERMAL
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 24 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 0~49(PCB SCREW)
D
D
1
S35
SCREW280_900_700_1P
1
S18
SCREW280_700_1P
S27
1
S19 1
SCREW390_850_700_1P
SCREW280_700_1P
1
S20 1
S25
SCREW280_700_1P SCREW390_850_700_1P
C S21 S26 C
1 1
SCREW280_700_1P SCREW390_1160_850_1P
1
S22 1
S11
SCREW280_700_1P SCREW280_900_550_NP_1P
1
S23 1
S10
Vinafix.com
SCREW280_700_1P SCREW280_850_700_1P
1
S24 1
S16
SCREW280_700_1P SCREW280_850_700_1P
1
S17
SCREW280_700_1P
B PCB B
1
S2
SCREW420_700_1P
1 FIX1 1 FIX5 1
S3
FIX_MASK FIX_MASK SCREW420_700_1P
1 FIX2 1 FIX6 1
S4
1 FIX3 1 FIX7 1
S5

1
S6
1 FIX4 1 FIX8
SCREW420_700_1P
FIX_MASK FIX_MASK
1
S7
SCREW420_700_1P
1
S9
SCREW420_700_1P
A A
INVENTEC
TITLE
XDP & ME CONN.
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 25 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
D
I
A
U4555
74 73 IN PCIE_DGPU_RX0P E25 PEG_RXP_0 PEG_TXP_0 B25 PEG_TX0_DP C4835 2 1 0.22UF_6.3V_1 PCIE_DGPU_TX0P OUT 73 74
74 73 IN PCIE_DGPU_RX0N D25 PEG_RXN_0 PEG_TXN_0 A25 PEG_TX0_DN C4836 2 1 0.22UF_6.3V_1 PCIE_DGPU_TX0N OUT 73 74
74 73 IN PCIE_DGPU_RX1N F24 PEG_RXN_1 PEG_TXN_1 C24 PEG_TX1_DN C4838 2 1 0.22UF_6.3V_1 PCIE_DGPU_TX1N OUT 73 74
C 74 73 IN PCIE_DGPU_RX6P E19 PEG_RXP_6 PEG_TXP_6 B19 PEG_TX6_DP C4831 2 1 0.22UF_6.3V_1 PCIE_DGPU_TX6P OUT 73 74 C
74 73 IN PCIE_DGPU_RX8P D17 PEG_RXP_8 PEG_TXP_8 A17 PEG_TX8_DP C4818 2 1 0.22UF_6.3V_1 PCIE_DGPU_TX8P OUT 73 74
74 73 IN PCIE_DGPU_RX8N E17 PEG_RXN_8 PEG_TXN_8 B17 PEG_TX8_DN C4820 2 1 0.22UF_6.3V_1 PCIE_DGPU_TX8N OUT 73 74
74 73 IN PCIE_DGPU_RX9P F16 PEG_RXP_9 PEG_TXP_9 C16 PEG_TX9_DP C4819 2 1 0.22UF_6.3V_1 PCIE_DGPU_TX9P OUT 73 74
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B B
PVCCIO I AR4501
1 2 PEG_RCOMP G2 PEG_RCOMP
24.9_1%_2
37 DMI_RX0_DP D8 B8 DMI_TX0_DP 37
BI E8
DMI_RXP_0 DMI_TXP_0
A8
BI
37 BI DMI_RX0_DN DMI_RXN_0 DMI_TXN_0 DMI_TX0_DN BI 37
37 DMI_RX1_DP E6 C6 DMI_TX1_DP 37
BI F6
DMI_RXP_1 DMI_TXP_1
B6
BI
37 DMI_RX2_DP D5 B5 DMI_TX2_DP 37
BI E5
DMI_RXP_2 DMI_TXP_2
A5
BI
37 DMI_RX3_DP J8 D4 DMI_TX3_DP 37
BI J9
DMI_RXP_3 DMI_TXP_3
B4
BI
A 37 BI DMI_RX3_DN DMI_RXN_3 DMI_TXN_3 DMI_TX3_DN BI 37
A
3 OF 13
INTEL_J43242_BGA_1440P
INVENTEC
TITLE
SKYLAKE1_H-PEG,HDMI
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 26 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Vinafix.com
D
D
I
A
U4555
K36 D29 EDP_TX0_DP 62

K37
DDI1_TXP_0 EDP_TXP_0
E29
OUT
DDI1_TXN_0 EDP_TXN_0 EDP_TX0_DN OUT 62
J35 F28 EDP_TX1_DP 62
J34
DDI1_TXP_1 EDP_TXP_1
E28
OUT
DDI1_TXN_1 EDP_TXN_1 EDP_TX1_DN OUT 62
H37 A29 EDP_TX2_DP
H36
J37
J38
DDI1_TXP_2
DDI1_TXN_2
DDI1_TXP_3
EDP_TXP_2
EDP_TXN_2
EDP_TXP_3
B29
C28
B28
EDP_TX2_DN
EDP_TX3_DP
EDP_TX3_DN
OUT
OUT
OUT
62
62
62
62
EDP
DDI1_TXN_3 EDP_TXN_3 OUT
D27 C26 EDP_AUX_DP 62
E27
DDI1_AUXP EDP_AUXP
B26
OUT
DDI1_AUXN EDP_AUXN EDP_AUX_DN OUT 62
C H34 DDI2_TXP_0 C
H33 DDI2_TXN_0
F37 A33 DP_UTIL 1
DDI2_TXP_1 EDP_DISP_UTIL
TP4500 PVCCIO
G38 DDI2_TXN_1
F34 DDI2_TXP_2
I A
F35 D37 DISP_RCOMP 1 R4544 2
DDI2_TXN_2 DISP_RCOMP
E37 DDI2_TXP_3 24.9_1%_2
E36 DDI2_TXN_3
Vinafix.com
F26 DDI2_AUXP
E26 DDI2_AUXN
12PF_50V_2_DY
C34 DDI3_TXP_0
D34 DDI3_TXN_0
C4594
B36 DDI3_TXP_1
B34 DDI3_TXN_1
F33 DDI3_TXP_2
E33 DDI3_TXN_2
C33 DDI3_TXP_3
B33 DDI3_TXN_3
G27 AUD_CPU_SCLK 39
A27
PROC_AUDIO_CLK
G25
IN
DDI3_AUXP PROC_AUDIO_SDI AUD_CPU_SDI IN 39 A
B B27 G29 AUD_CPU_SDOP 1 2 AUD_PCH_SDI 39
B
DDI3_AUXN
4 of 13
PROC_AUDIO_SDO OUT
R4928 I 20_5%_2
A A
INVENTEC
TITLE
SKYLAKE2_H-DDI,EDP
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 27 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
I
A
U4555
47 BI M_A_DQ<0> BR6 DDR0_DQ_0/DDR0_DQ_0 DDR0_CKP_0/DDR0_CKP_0 AG1 M_CLK_DDR0_DP BI 47
47 BI M_A_DQ<1> BT6 DDR0_DQ_1/DDR0_DQ_1 DDR0_CKN_0/DDR0_CKN_0 AG2 M_CLK_DDR0_DN BI 47
47 BI M_A_DQ<2> BP3 DDR0_DQ_2/DDR0_DQ_2 DDR0_CKP_1/DDR0_CKP_1 AK2 M_CLK_DDR1_DP BI 47
47 BI M_A_DQ<3> BR3 DDR0_DQ_3/DDR0_DQ_3 DDR0_CKN_1/DDR0_CKN_1 AK1 M_CLK_DDR1_DN BI 47
47 BI M_A_DQ<4> BN5 DDR0_DQ_4/DDR0_DQ_4 NC/DDR0_CKP_2 AL3
47 BI M_A_DQ<5> BP6 DDR0_DQ_5/DDR0_DQ_5 NC/DDR0_CKN_2 AK3
D 47 M_A_DQ<6> BP2 AL2
BI DDR0_DQ_6/DDR0_DQ_6 NC/DDR0_CKP_3
D
47 BI M_A_DQ<7> BN3 DDR0_DQ_7/DDR0_DQ_7 NC/DDR0_CKN_3 AL1
47 BI M_A_DQ<8> BL4 DDR0_DQ_8/DDR0_DQ_8
47 BI M_A_DQ<9> BL5 DDR0_DQ_9/DDR0_DQ_9 DDR0_CKE_0/DDR0_CKE_0 AT1 M_CKE0 BI 47
47 BI M_A_DQ<10> BL2 DDR0_DQ_10/DDR0_DQ_10 DDR0_CKE_1/DDR0_CKE_1 AT2 M_CKE1 BI 47
47 BI M_A_DQ<11> BM1 DDR0_DQ_11/DDR0_DQ_11 DDR0_CKE_2/DDR0_CKE_2 AT3
47 BI M_A_DQ<12> BK4 DDR0_DQ_12/DDR0_DQ_12 DDR0_CKE_3/DDR0_CKE_3 AT5
47 BI M_A_DQ<13> BK5 DDR0_DQ_13/DDR0_DQ_13
47 BI M_A_DQ<14> BK1 DDR0_DQ_14/DDR0_DQ_14 DDR0_CS#_0/DDR0_CS#_0 AD5 M_CS#0 BI 47
47 BI M_A_DQ<15> BK2 DDR0_DQ_15/DDR0_DQ_15 DDR0_CS#_1/DDR0_CS#_1 AE2 M_CS#1 BI 47
47 BI M_A_DQ<16> BG4 DDR0_DQ_16/DDR0_DQ_32 NC/DDR0_CS#_2 AD2
47 BI M_A_DQ<17> BG5 DDR0_DQ_17/DDR0_DQ_33 NC/DDR0_CS#_3 AE5
47 BI M_A_DQ<18> BF4 DDR0_DQ_18/DDR0_DQ_34
47 BI M_A_DQ<19> BF5 DDR0_DQ_19/DDR0_DQ_35 DDR0_ODT_0/DDR0_ODT_0 AD3 M_ODT0 BI 47
47 BI M_A_DQ<20> BG2 DDR0_DQ_20/DDR0_DQ_36 NC/DDR0_ODT_1 AE4 M_ODT1 BI 47
47 BI M_A_DQ<21> BG1 DDR0_DQ_21/DDR0_DQ_37 NC/DDR0_ODT_2 AE1
47 BI M_A_DQ<22> BF1 DDR0_DQ_22/DDR0_DQ_38 NC/DDR0_ODT_3 AD4
47 BI M_A_DQ<23> BF2 DDR0_DQ_23/DDR0_DQ_39
47 BI M_A_DQ<24> BD2 DDR0_DQ_24/DDR0_DQ_40 DDR0_CAB_4/DDR0_BA_0 AH5 M_A_BS0 BI 47
47 BI M_A_DQ<25> BD1 DDR0_DQ_25/DDR0_DQ_41 DDR0_CAB_6/DDR0_BA_1 AH1 M_A_BS1 BI 47
47 BI M_A_DQ<26> BC4 DDR0_DQ_26/DDR0_DQ_42 DDR0_CAA_5/DDR0_BG_0 AU1 M_A_BG0 BI 47
47 BI M_A_DQ<27> BC5 DDR0_DQ_27/DDR0_DQ_43
47 BI M_A_DQ<28> BD5 DDR0_DQ_28/DDR0_DQ_44 DDR0_CAB_3/DDR0_MA_16 AH4 M_A_RAS# BI 47
C 47 BI M_A_DQ<29> BD4 DDR0_DQ_29/DDR0_DQ_45 DDR0_CAB_2/DDR0_MA_14 AG4 M_A_WE# BI 47 C
47 BI M_A_DQ<30> BC1 DDR0_DQ_30/DDR0_DQ_46 DDR0_CAB_1/DDR0_MA_15 AD1 M_A_CAS# BI 47
47 BI M_A_DQ<31> BC2 DDR0_DQ_31/DDR0_DQ_47
47 BI M_A_DQ<32> AB1 DDR0_DQ_32/DDR1_DQ_0 DDR0_CAB_9/DDR0_MA_0 AH3 M_A_A_0 BI 47
47 BI M_A_DQ<33> AB2 DDR0_DQ_33/DDR1_DQ_1 DDR0_CAB_8/DDR0_MA_1 AP4 M_A_A_1 BI 47
47 BI M_A_DQ<34> AA4 DDR0_DQ_34/DDR1_DQ_2 DDR0_CAB_5/DDR0_MA_2 AN4 M_A_A_2 BI 47
47 BI M_A_DQ<35> AA5 DDR0_DQ_35/DDR1_DQ_3 NC/DDR0_MA_3 AP5 M_A_A_3 BI 47
47 BI M_A_DQ<36> AB5 DDR0_DQ_36/DDR1_DQ_4 NC/DDR0_MA_4 AP2 M_A_A_4 BI 47
47 BI M_A_DQ<37> AB4 DDR0_DQ_37/DDR1_DQ_5 DDR0_CAA_0/DDR0_MA_5 AP1 M_A_A_5 BI 47
47 BI M_A_DQ<38> AA2 DDR0_DQ_38/DDR1_DQ_6 DDR0_CAA_2/DDR0_MA_6 AP3 M_A_A_6 BI 47
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47 BI M_A_DQ<39> AA1 DDR0_DQ_39/DDR1_DQ_7 DDR0_CAA_4/DDR0_MA_7 AN1 M_A_A_7 BI 47
47 BI M_A_DQ<40> V5 DDR0_DQ_40/DDR1_DQ_8 DDR0_CAA_3/DDR0_MA_8 AN3 M_A_A_8 BI 47
47 BI M_A_DQ<41> V2 DDR0_DQ_41/DDR1_DQ_9 DDR0_CAA_1/DDR0_MA_9 AT4 M_A_A_9 BI 47
47 BI M_A_DQ<42> U1 DDR0_DQ_42/DDR1_DQ_10 DDR0_CAB_7/DDR0_MA_10 AH2 M_A_A_10 BI 47
47 BI M_A_DQ<43> U2 DDR0_DQ_43/DDR1_DQ_11 DDR0_CAA_7/DDR0_MA_11 AN2 M_A_A_11 BI 47
47 BI M_A_DQ<44> V1 DDR0_DQ_44/DDR1_DQ_12 DDR0_CAA_6/DDR0_MA_12 AU4 M_A_A_12 BI 47
47 BI M_A_DQ<45> V4 DDR0_DQ_45/DDR1_DQ_13 DDR0_CAB_0/DDR0_MA_13 AE3 M_A_A_13 BI 47
47 BI M_A_DQ<46> U5 DDR0_DQ_46/DDR1_DQ_14 DDR0_CAA_9/DDR0_BG_1 AU2 M_A_BG1 BI 47
47 BI M_A_DQ<47> U4 DDR0_DQ_47/DDR1_DQ_15 DDR0_CAA_8/DDR0_ACT# AU3 M_A_ACT# BI 47
47 BI M_A_DQ<48> R2 DDR0_DQ_48/DDR1_DQ_32
47 BI M_A_DQ<49> P5 DDR0_DQ_49/DDR1_DQ_33 NC/DDR0_PAR AG3 M_A_PARITY BI 47
47 BI M_A_DQ<50> R4 DDR0_DQ_50/DDR1_DQ_34 NC/DDR0_ALERT# AU5 M_A_ALERT# BI 47
47 BI M_A_DQ<51> P4 DDR0_DQ_51/DDR1_DQ_35
B 47 M_A_DQ<52> R5 B
BI DDR0_DQ_52/DDR1_DQ_36
47 BI M_A_DQ<53> P2 DDR0_DQ_53/DDR1_DQ_37 DDR0_DQSN_0/DDR0_DQSN_0 BR5 M_A_DQS0_DN BI 47
47 BI M_A_DQ<54> R1 DDR0_DQ_54/DDR1_DQ_38 DDR0_DQSN_1/DDR0_DQSN_1 BL3 M_A_DQS1_DN BI 47
47 BI M_A_DQ<55> P1 DDR0_DQ_55/DDR1_DQ_39 DDR0_DQSN_2/DDR0_DQSN_4 BG3 M_A_DQS2_DN BI 47
47 BI M_A_DQ<56> M4 DDR0_DQ_56/DDR1_DQ_40 DDR0_DQSN_3/DDR0_DQSN_5 BD3 M_A_DQS3_DN BI 47
47 BI M_A_DQ<57> M1 DDR0_DQ_57/DDR1_DQ_41 DDR0_DQSN_4/DDR1_DQSN_0 AA3 M_A_DQS4_DN BI 47
47 BI M_A_DQ<58> L4 DDR0_DQ_58/DDR1_DQ_42 DDR0_DQSN_5/DDR1_DQSN_1 U3 M_A_DQS5_DN BI 47
47 BI M_A_DQ<59> L2 DDR0_DQ_59/DDR1_DQ_43 DDR0_DQSN_6/DDR1_DQSN_4 P3 M_A_DQS6_DN BI 47
47 BI M_A_DQ<60> M5 DDR0_DQ_60/DDR1_DQ_44 DDR0_DQSN_7/DDR1_DQSN_5 L3 M_A_DQS7_DN BI 47
47 BI M_A_DQ<61> M2 DDR0_DQ_61/DDR1_DQ_45
47 BI M_A_DQ<62> L5 DDR0_DQ_62/DDR1_DQ_46 DDR0_DQSP_0/DDR0_DQSP_0 BP5 M_A_DQS0_DP BI 47
47 BI M_A_DQ<63> L1 DDR0_DQ_63/DDR1_DQ_47 DDR0_DQSP_1/DDR0_DQSP_1 BK3 M_A_DQS1_DP BI 47
BF3 M_A_DQS2_DP 47
BA2
DDR0_DQSP_2/DDR0_DQSP_4
BC3
BI
NC/DDR0_ECC_0 DDR0_DQSP_3/DDR0_DQSP_5 M_A_DQS3_DP BI 47
BA1 AB3 M_A_DQS4_DP 47
AY4
NC/DDR0_ECC_1 DDR0_DQSP_4/DDR1_DQSP_0
V3
BI
AY5 R3 M_A_DQS6_DP 47
BA5
M3
BI
BA4 NC/DDR0_ECC_5
AY1 NC/DDR0_ECC_6 DDR0_DQSP_8/DDR0_DQSP_8 AY3
AY2 NC/DDR0_ECC_7 1 OF 13 DDR0_DQSN_8/DDR0_DQSN_8 BA3
DDR CHANNEL A
A A
INVENTEC
TITLE
SKYLAKE_H-DDR-1
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 28 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P1V2
0.1UF_16V_2_DY
1
1K_1%_2
I
R4150
A
C4170
U4555
48 BI M_B_DQ<0> BT11 DDR1_DQ_0/DDR0_DQ_16 DDR1_CKP_0/DDR1_CKP_0 AM9 M_CLK_DDR2_DP BI 48 I
M_B_DQ<1> BR11 AN9 M_CLK_DDR2_DN P0V6S_DIMM0_VREF_CA
48 BI DDR1_DQ_1/DDR0_DQ_17 DDR1_CKN_0/DDR1_CKN_0 BI 48 A
2
48 BI M_B_DQ<2> BT9 DDR1_DQ_2/DDR0_DQ_18 DDR1_CKP_1/DDR1_CKP_1 AM7 M_CLK_DDR3_DP BI 48
48 BI M_B_DQ<3> BR8 DDR1_DQ_3/DDR0_DQ_19 DDR1_CKN_1/DDR1_CKN_1 AM8 M_CLK_DDR3_DN BI 48
48 BI M_B_DQ<4> BP11 DDR1_DQ_4/DDR0_DQ_20 NC/DDR1_CKP_2 AM11
48 BI M_B_DQ<5> BN11 DDR1_DQ_5/DDR0_DQ_21 NC/DDR1_CKN_2 AM10
48 BI M_B_DQ<6> BP8 DDR1_DQ_6/DDR0_DQ_22 NC/DDR1_CKP_3 AJ10
48 BI M_B_DQ<7> BN8 DDR1_DQ_7/DDR0_DQ_23 NC/DDR1_CKN_3 AJ11
D 48 M_B_DQ<8> BL12
D
0.1UF_16V_2
M_B_DQ<9> BL11 AT8 M_CKE2
1
48 BI BI 48
1K_1%_2
DDR1_DQ_9/DDR0_DQ_25 DDR1_CKE_0/DDR1_CKE_0
48 BI M_B_DQ<10> BL8 DDR1_DQ_10/DDR0_DQ_26 DDR1_CKE_1/DDR1_CKE_1 AT10 M_CKE3 BI 48 I
R4152
C4171
48 BI M_B_DQ<11> BJ8 DDR1_DQ_11/DDR0_DQ_27 DDR1_CKE_2/DDR1_CKE_2 AT7 A
48 BI M_B_DQ<12> BJ11 DDR1_DQ_12/DDR0_DQ_28 DDR1_CKE_3/DDR1_CKE_3 AT11
48 M_B_DQ<13> BJ10 I
A
M_B_DQ<14> BL7 AF11 M_CS#2
2
48 BI DDR1_DQ_14/DDR0_DQ_30 DDR1_CS#_0/DDR1_CS#_0 BI 48
48 BI M_B_DQ<15> BJ7 DDR1_DQ_15/DDR0_DQ_31 DDR1_CS#_1/DDR1_CS#_1 AE7 M_CS#3 BI 48
48 BI M_B_DQ<16> BG11 DDR1_DQ_16/DDR0_DQ_48 NC/DDR1_CS#_2 AF10
48 BI M_B_DQ<17> BG10 DDR1_DQ_17/DDR0_DQ_49 NC/DDR1_CS#_3 AE10
48 BI M_B_DQ<18> BG8 DDR1_DQ_18/DDR0_DQ_50
48 BI M_B_DQ<19> BF8 DDR1_DQ_19/DDR0_DQ_51 DDR1_ODT_0/DDR1_ODT_0 AF7 M_ODT2 BI 48
48 BI M_B_DQ<20> BF11 DDR1_DQ_20/DDR0_DQ_52 NC/DDR1_ODT_1 AE8 M_ODT3 BI 48
48 BI M_B_DQ<21> BF10 DDR1_DQ_21/DDR0_DQ_53 NC/DDR1_ODT_2 AE9 DDR_CA_CPU_VREF_A 1 R4153 2
M_B_DQ<22> BG7 AE11 29 IN
48 BI DDR1_DQ_22/DDR0_DQ_54 NC/DDR1_ODT_3
M_B_DQ<23> BF7 2_1%_2
48 BI DDR1_DQ_23/DDR0_DQ_55
M_B_DQ<24> BB11 AH10 M_B_RAS# I
0.022UF_16V_2
48 BI DDR1_DQ_24/DDR0_DQ_56 DDR1_CAB_3/DDR1_MA_16 BI 48
M_B_DQ<25> BC11 AH11 M_B_WE# A
1
48 BI DDR1_DQ_25/DDR0_DQ_57 DDR1_CAB_2/DDR1_MA_14 BI 48
48 BI M_B_DQ<26> BB8 DDR1_DQ_26/DDR0_DQ_58 DDR1_CAB_1/DDR1_MA_15 AF8 M_B_CAS# BI 48
C4172
48 BI M_B_DQ<27> BC8 DDR1_DQ_27/DDR0_DQ_59
48 BI M_B_DQ<28> BC10 DDR1_DQ_28/DDR0_DQ_60 DDR1_CAB_4/DDR1_BA_0 AH8 M_B_BS0 BI 48
48 BI M_B_DQ<29> BB10 DDR1_DQ_29/DDR0_DQ_61 DDR1_CAB_6/DDR1_BA_1 AH9 M_B_BS1 BI 48 I
A
M_B_DQ<30> BC7 AR9 M_B_BG0
2
48 BI DDR1_DQ_30/DDR0_DQ_62 DDR1_CAA_5/DDR1_BG_0 BI 48
C 48 BI M_B_DQ<31> BB7 DDR1_DQ_31/DDR0_DQ_63 C
48 BI M_B_DQ<32> AA11 DDR1_DQ_32/DDR1_DQ_16 DDR1_CAB_9/DDR1_MA_0 AJ9 M_B_A_0 BI 48
48 BI M_B_DQ<33> AA10 DDR1_DQ_33/DDR1_DQ_17 DDR1_CAB_8/DDR1_MA_1 AK6 M_B_A_1 BI 48 DDR_CA_CPU_VREF_RC
48 BI M_B_DQ<34> AC11 DDR1_DQ_34/DDR1_DQ_18 DDR1_CAB_5/DDR1_MA_2 AK5 M_B_A_2 BI 48
1
48 BI M_B_DQ<35> AC10 AL5 M_B_A_3 BI 48
24.9_1%_2
DDR1_DQ_35/DDR1_DQ_19 NC/DDR1_MA_3
M_B_DQ<36> AA7 AL6 M_B_A_4
R4155
48 BI DDR1_DQ_36/DDR1_DQ_20 NC/DDR1_MA_4 BI 48
48 BI M_B_DQ<37> AA8 DDR1_DQ_37/DDR1_DQ_21 DDR1_CAA_0/DDR1_MA_5 AM6 M_B_A_5 BI 48
48 M_B_DQ<38> AC8 AN7 M_B_A_6 48
I
BI DDR1_DQ_38/DDR1_DQ_22 DDR1_CAA_2/DDR1_MA_6 BI A
48 BI M_B_DQ<39> AC7 DDR1_DQ_39/DDR1_DQ_23 DDR1_CAA_4/DDR1_MA_7 AN10 M_B_A_7 BI 48
2
P1V2
Vinafix.com
48 BI M_B_DQ<40> W8 DDR1_DQ_40/DDR1_DQ_24 DDR1_CAA_3/DDR1_MA_8 AN8 M_B_A_8 BI 48
48 BI M_B_DQ<41> W7 DDR1_DQ_41/DDR1_DQ_25 DDR1_CAA_1/DDR1_MA_9 AR11 M_B_A_9 BI 48
48 BI M_B_DQ<42> V10 DDR1_DQ_42/DDR1_DQ_26 DDR1_CAB_7/DDR1_MA_10 AH7 M_B_A_10 BI 48
48 BI M_B_DQ<43> V11 DDR1_DQ_43/DDR1_DQ_27 DDR1_CAA_7/DDR1_MA_11 AN11 M_B_A_11 BI 48
M_B_DQ<44> W11 AR10 M_B_A_12
0.1UF_16V_2_DY
48 BI DDR1_DQ_44/DDR1_DQ_28 DDR1_CAA_6/DDR1_MA_12 BI 48
1
1K_1%_2
48 BI M_B_DQ<45> W10 DDR1_DQ_45/DDR1_DQ_29 DDR1_CAB_0/DDR1_MA_13 AF9 M_B_A_13 BI 48
M_B_DQ<46> V7 AR7
R4144
48 BI DDR1_DQ_46/DDR1_DQ_30 DDR1_CAA_9/DDR1_BG_1 M_B_BG1 BI 48
C4165
48 BI M_B_DQ<47> V8 DDR1_DQ_47/DDR1_DQ_31 DDR1_CAA_8/DDR1_ACT# AT9 M_B_ACT# BI 48
48 BI M_B_DQ<48> R11 DDR1_DQ_48/DDR1_DQ_48 I
48 BI M_B_DQ<49> P11 DDR1_DQ_49/DDR1_DQ_49 NC/DDR1_PAR AJ7 M_B_PARITY BI 48 A
2
48 BI M_B_DQ<50> P7 DDR1_DQ_50/DDR1_DQ_50 NC/DDR1_ALERT# AR8 M_B_ALERT# BI 48
48 M_B_DQ<51> R8 P0V6S_DIMM1_VREF_DQ
48 BI M_B_DQ<52> R10 DDR1_DQ_52/DDR1_DQ_52
B 48 M_B_DQ<53> P10 BN9 M_B_DQS0_DN 48
B
BI DDR1_DQ_53/DDR1_DQ_53 DDR1_DQSN_0/DDR0_DQSN_2 BI
48 BI M_B_DQ<54> R7 DDR1_DQ_54/DDR1_DQ_54 DDR1_DQSN_1/DDR0_DQSN_3 BL9 M_B_DQS1_DN BI 48
48 BI M_B_DQ<55> P8 DDR1_DQ_55/DDR1_DQ_55 DDR1_DQSN_2/DDR0_DQSN_6 BG9 M_B_DQS2_DN BI 48
48 BI M_B_DQ<56> L11 DDR1_DQ_56/DDR1_DQ_56 DDR1_DQSN_3/DDR0_DQSN_7 BC9 M_B_DQS3_DN BI 48
M_B_DQ<57> M11 AC9 M_B_DQS4_DN
1
48 BI BI 48
1K_1%_2
DDR1_DQ_57/DDR1_DQ_57 DDR1_DQSN_4/DDR1_DQSN_2
48 BI M_B_DQ<58> L7 DDR1_DQ_58/DDR1_DQ_58 DDR1_DQSN_5/DDR1_DQSN_3 W9 M_B_DQS5_DN BI 48
R4145
0.1UF_16V_2
M_B_DQ<59> M8 R9 M_B_DQS6_DN
1
48 BI DDR1_DQ_59/DDR1_DQ_59 DDR1_DQSN_6/DDR1_DQSN_6 BI 48
48 BI M_B_DQ<60> L10 DDR1_DQ_60/DDR1_DQ_60 DDR1_DQSN_7/DDR1_DQSN_7 M9 M_B_DQS7_DN BI 48
C4167
48 M_B_DQ<61> M10 I
A
M_B_DQ<62> M7 BP9 M_B_DQS0_DP I
2
48 BI DDR1_DQ_62/DDR1_DQ_62 DDR1_DQSP_0/DDR0_DQSP_2 BI 48
48 BI M_B_DQ<63> L8 DDR1_DQ_63/DDR1_DQ_63 DDR1_DQSP_1/DDR0_DQSP_3 BJ9 M_B_DQS1_DP BI 48 A
BF9 M_B_DQS2_DP
2
DDR1_DQSP_2/DDR0_DQSP_6 BI 48
AW11 BB9 M_B_DQS3_DP 48
AY11
AA9
BI
NC/DDR1_ECC_1 DDR1_DQSP_4/DDR1_DQSP_2 M_B_DQS4_DP BI 48
AY8 V9 M_B_DQS5_DP DDR_DQ_CPU_VREF_B
NC/DDR1_ECC_2 DDR1_DQSP_5/DDR1_DQSP_3 BI 48 1 R4148 2
AW8 P9 M_B_DQS6_DP 29 IN
NC/DDR1_ECC_3 DDR1_DQSP_6/DDR1_DQSP_6 BI 48
AY10 L9 M_B_DQS7_DP 2_1%_2
NC/DDR1_ECC_4 DDR1_DQSP_7/DDR1_DQSP_7 BI 48
0.022UF_16V_2
I
1
AW10 NC/DDR1_ECC_5
AY7 AW9 A
C4169
AW7 NC/DDR1_ECC_7 DDR1_DQSN_8/DDR1_DQSN_8 AY9
I
A
2
A A
1 I 2
R4518 A 121_1%_2 DDR_RCOMP_0 G1 DDR_RCOMP_0 DDR_VREF_CA BN13 DDR_CA_CPU_VREF_A
BI 29
1 I 2 DDR_DQ_CPU_VREF_RC
DDR_RCOMP_1 H1 BP13 DDR_DQ_CPU_VREF_A 1
1
R4541 A 75_1%_2 DDR_RCOMP_1 DDR0_VREF_DQ
TP4524
24.9_1%_2
1 I 2
R4540 A 100_1%_2 DDR_RCOMP_2 J2 DDR_RCOMP_2 2 OF 13 DDR1_VREF_DQ BR13 DDR_DQ_CPU_VREF_B
BI 29
R4149
DDR CHANNEL B
I
INTEL_J43242_BGA_1440P A
2
INVENTEC
TITLE
SKYLAKE4_H-DDR-2
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 29 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PVCCIO
R4535
30 IN CFG<0> 1 2
PVCCST 2.2K_5%_2
R4530
I
CFG<7>1 2
1
30 IN
100_5%_2
A
56.2_1%_2
U4555
R4509
R4538
1K_5%_2_DY
D
I I 45 CLK_CPU_DP B31 BN25 CFG<0> 30
R4529
D
A A IN BCLKP CFG_0 IN 30 IN CFG<2> 1 2
CLK_CPU_DN A32 BN27 CFG<1> 1
2
2
45 IN BCLKN CFG_1
BN26 CFG<2> TP4512
CFG_2 IN 30
VR_SVID_ALERT# CLK_CPU_PCIBCLK_DP D35 BN28 CFG<3> 1 1K_5%_2_DY
18 IN 45 IN PCI_BCLKP CFG_3
VR_SVID_CLK CLK_CPU_PCIBCLK_DN C36 BR20 CFG<4> TP4513
18 IN 45 IN PCI_BCLKN CFG_4 IN 30 R4528
18 IN VR_SVID_DATA CFG_5 BM20 CFG<5> IN 30 30 IN CFG<5> 1 2
2 R4511 1 45 IN CLK_CPUNSSC_DP E31 CLK24P CFG_6 BT20 CFG<6> IN 30
220_5%_2 45 IN CLK_CPUNSSC_DN D31 CLK24N CFG_7 BP20 CFG<7> IN 30 1K_5%_2_DY
CFG_8 BR23 CFG<8> 1
BR22 CFG<9> TP4503 R4526
CFG_9 IN 30 CFG<6> 1
I CFG_10 BT23 CFG<10> 1 30 IN 2
A CFG_11 BT22 CFG<11> 1 TP4504
BM19 CFG<12> 1 TP4505 1K_5%_2_DY
CFG_12
BR19 CFG<13> 1 TP4506
CFG_13
BP19 CFG<14> 1 TP4507
CFG_14
VIDALERT# BH31 BT19 CFG<15> 1 TP4508
VIDALERT# CFG_15
BH32 TP4509
VIDSCK
BH29 VIDSOUT CFG_17 BN23 CFG<17> 1
CPU_PROCHOT#_R BR30 BP23 CFG<16> 1 TP4510
30 IN PROCHOT# CFG_16 PVCCSTG
BP22 CFG<19> 1 TP4511
CFG_19
DDR_PG_CTRL BT13 BN22 CFG<18> 1 TP4501
47 OUT DDR_VTT_CNTL CFG_18
TP4502 H_TDO 1 R4516 I 2 100_5%_2
A
C BR27 C
BPM#_0
H_TDI 1 R4515 I
2
BT27 A 51_5%_2
BPM#_1
I BPM#_2 BM31
VCCST_PWRGD R4510 I
30 IN R4722 1 2 A 60.4_1%_2 VCCST_PWRGD_CPU H13 VCCST_PWRGD BPM#_3 BT30 H_TMS 1 A 2 51_5%_2
39 30 H_PWRGD BT31 R4508

IN PROCPWRGD
H_TCK 1 I
A 2 51_5%_2
38 IN PLTRST_CPU# BP35 RESET# PROC_TDO BT28 H_TDO OUT 40
38 IN H_PM_SYNC BM34 PM_SYNC PROC_TDI BL32 H_TDI IN 40
38 IN H_PM_DOWN R4513 1 A 2 I 20_5%_2 H_PM_DOWN_R BP31 PM_DOWN PROC_TMS BP28 H_TMS IN 40
PCH_PECI R4514 1 A 2 I H_PECI BT34 BR28 H_TCK
Vinafix.com
51 38 BI 12.1_1%_2 PECI PROC_TCK IN 39
30 IN CPU_THERMTRIP# J31 THERMTRIP#
BP30 H_TRST# 40
BR33
PROC_TRST#
BL30
IN
SKTOCC# PROC_PREQ# H_PREQ# IN 40
R4520 PROC_SELECT# BN1 BP27 H_PRDY# 30 CFG<4> IN
PROC_SELECT# PROC_PRDY# IN 40
0_5%_2_DY PVCCST
1
R4533 CATERR_N BM30 CATERR# I
1K_5%_2
49.9_1%_2_DY BT25 CFG_RCOMP R4519 1 A 2 49.9_1%_2
CFG_RCOMP
STRAPPING:
R4523
AT13 ZVM#
P3V3A
AW13 MSM# DP ENABLE/DISABLE I
0 : ENABLED A
2
AU13 RSVD1
AY13
100K_5%_2
1
RSVD2
R4742
B PVCCST B
5 OF 13
I
A
1
1K_5%_2
30 CFG<9> IN
R4739
2
1K_1%_2_DY
Q4751
S1 1
R4534
2
2
G1
6 VCCST_PWRGD OUT 30 PVCCSTG
D1
D2 3
39 30 H_PWRGD
23 18 IN EN_PVCORE 5 G2 IN I
CSC0201_DY
A
4
1
1
1K_5%_2
S2
CSC0201_DY
C4704
R4507
2N7002KDW
1
CLOSE TO CPU
C4702
I
A I
A
C4612
2
2
1 2 1 R4505 2 CPU_PROCHOT#_R IN 30
2
499_1%_2
47PF_50V_2
PVCCST
I CPU_PROCHOT#
A A 51 18 8 BI A
1
200_5%_2
PVCCST
R4743
I
A
2
R4736
1 2
THERMTRIP_BASE 1K_5%_2
INVENTEC
1
38 IN PCH_THERMTRIP# 3
A
2 CPU_THERMTRIP# OUT 30
Vinafix.com
B
C E
LMBT3904LT1G TITLE
Q4758
I MODEL,PROJECT,FUNCTION
SKYLAKE5_H-CFG
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3
SHEET
CS
30 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PLACE IN BACK SIDE PVCORE
EDS VER0.7
I I I I I I I I I I I
10UF_6.3V_2
10UF_6.3V_2
10UF_6.3V_2
10UF_6.3V_2
10UF_6.3V_2
10UF_6.3V_2
10UF_6.3V_2
10UF_6.3V_2
10UF_6.3V_2
10UF_6.3V_2
10UF_6.3V_2
A A A A A A A A A A A
PVCORE
1
1
PVCORE PVCORE
47UF X 5 22UF X 12
C4536
C4533
C4532
C4529
C4528
C4525
C4524
C4521
C4520
C4517
C4516
I PVCORE PVCORE
A
U4555
10UF X 21 1UF X 24 I
A
AA13 AH13 U4555

VCC1 VCC64
2
2
AA31 VCC2 VCC65 AH14
K14 VCC1 VCC64 W35
L13 VCC2 VCC65 W36
L14 W37
AA34 VCC5 VCC68 AH31 PVCORE VCC3 VCC66
N13 VCC4 VCC67 W38
I I I I I I I I I I AA35 VCC6 VCC69 AH32
N14 Y29
10UF_6.3V_2
10UF_6.3V_2
10UF_6.3V_2
10UF_6.3V_2
10UF_6.3V_2
10UF_6.3V_2
10UF_6.3V_2
10UF_6.3V_2
10UF_6.3V_2
10UF_6.3V_2
10UF_6.3V_2_DY
A A A A A A A A A A AA36 AJ14 VCC5 VCC68

1
1
VCC7 VCC70 N30 Y30
D AA37 VCC8 VCC71 AJ29 I I I I I
VCC6 VCC69
C4535
C4534
C4531
C4530
C4527
C4526
C4523
C4522
C4519
C4518
N31 Y31 D
47UF_6.3V_5
47UF_6.3V_5
47UF_6.3V_5
47UF_6.3V_5
47UF_6.3V_5
A A A A A VCC7 VCC70
C4537
AA38 AJ30
1
VCC9 VCC72 N32 Y32
AB29 AJ31 VCC8 VCC71
VCC10 VCC73
C4503
C4502
C4501
C4500
C4720
N35 VCC9 VCC72 Y33
AB30 VCC11 VCC74 AJ32
N36 VCC10 VCC73 Y34
AB31 AJ33
2
2
VCC12 VCC75 N37 Y35
VCC13 VCC76 N38 Y36
2
VCC14 VCC77 P13
AB36 AJ36 VCC13
VCC15 VCC78 P14
AB37 AK31 VCC14
VCC16 VCC79 P29
I I I I AB38 AK32 VCC15
22UF_6.3V_3
22UF_6.3V_3
22UF_6.3V_3
22UF_6.3V_3
A A A A VCC17 VCC80 P30
1
AC13 AK33 VCC16
VCC18 VCC81 P31
PLACE IN BOTTOM SIDE VCC17
C4539
AK34
C4538
C4598
C4599
AC14 VCC19 VCC82 P32 VCC18
AC29 VCC20 VCC83 AK35
P33 VCC19
P34 VCC20
P35
2
AC32 AK38 VCC21
VCC23 VCC86 P36
AC33 AL13 VCC22
VCC24 VCC87 R13
AC34 AL29 VCC23
VCC25 VCC88 R31
AC35 AL30 VCC24
VCC26 VCC89 R32
AC36 AL31 VCC25
VCC27 VCC90 R33
AD13 AL32 VCC26
VCC28 VCC91 R34
AD14 AL35 VCC27
VCC29 VCC92 R35
AD31 AL36 VCC28
PVCORE VCC30 VCC93 R36 VCC29
C AD32 VCC31 VCC94 AL37 C
R37 VCC30
AD33 VCC32 VCC95 AL38
R38 VCC31
AD34 VCC33 VCC96 AM13
I I I I I I I I I I T29 VCC32
AD35 AM14
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
A A A A A A A A A A VCC34 VCC97 T30
1
1
AD36 AM29 VCC33
VCC35 VCC98 T31 VCC34
C4758
C4753
C4746
C4745
C4744
C4568
C4558
C4557
C4556
C4614
T32 VCC35
T35 VCC36
AE13 VCC38 VCC101 AM32
T36 VCC37
AE14 VCC39 VCC102 AM33
T37
2
2
AE30 AM34 VCC38
VCC40 VCC103 T38
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AE31 AM35 VCC39
VCC41 VCC104 U29
AE32 AM36 VCC40
VCC42 VCC105 U30
AE35 AN13 VCC41
VCC43 VCC106 U31
AE36 AN14 VCC42
VCC44 VCC107 U32
AE37 AN31 VCC43
VCC45 VCC108 U33
I I I I I I I I I I I AE38 VCC46 VCC109 AN32 PVCORE VCC44
U34
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
A A A A A A A A A A A AF29 AN33 VCC45

1
VCC47 VCC110 U35

AF30 AN34 VCC46
VCC48 VCC111 U36
C4808
C4807
C4800
C4699
C4566
C4552
C4563
C4562
C4549
C4561
C4560
AF31 AN35 VCC47

VCC49 VCC112
VCCSENSE 1 R21 I 2 100_1%_2 V13
AF32 AN36 A VCC48
VCC50 VCC113 V14
AF33 AN37 VCC49
VCC51 VCC114 V31
AF34 AN38 VCC50
2
VCC52 VCC115
VSSSENSE 1 R4531 I 2 100_1%_2 V32
AF35 AP13 A VCC51
VCC53 VCC116 V33
B AF36 VCC54 VCC117 AP30 VCC52 B
V34 VCC53
AF37 VCC55 VCC118 AP31
V35 VCC54
AF38 VCC56 VCC119 AP32
V36 VCC55
AG14 VCC57 VCC120 AP35
V37 VCC56
AG31 VCC58 VCC121 AP36
V38 VCC57
I I I AG32 VCC59 VCC122 AP37
W13
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
A A A AG33 AP38 VCC58

1
VCC60 VCC123 W14

AG34 K13 VCC59
VCC61 VCC124 W29
C4559
C4697
C4667
AG35 VCC60
VCC62 W30
AG36 VCC61
VCC63 W31 VCC62
W32 VCC63
2
10 OF 13
AG37 VCCSENSE 18
VCC_SENSE
AG38 VSSSENSE
OUT INTEL_J43242_BGA_1440P
9 OF 13 VSS_SENSE OUT 18
PVCORE
22UF_6.3V_3
22UF_6.3V_3
22UF_6.3V_3
22UF_6.3V_3
22UF_6.3V_3
22UF_6.3V_3
22UF_6.3V_3
22UF_6.3V_3
I I I I I I I I
A A A A A A A A
1
A A
C4551
C4515
C4514
C4513
C4512
C4511
C4510
C4509
2
INVENTEC
TITLE
SKYLAKE6_H-POWER
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 31 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
D
P1V2
PVCCSA I
I
A
A
U4555
U4555
J30 VCCSA1 VDDQ1 AA6

E2 RSVD_TP5
K29 VCCSA2 VDDQ2 AE12
1 IST_TRIG E3 IST_TRIG
K30 VCCSA3 VDDQ3 AF5 TP4523 E1 RSVD_TP4
K31 VCCSA4 VDDQ4 AF6
D1 RSVD_TP3
K32 VCCSA5 VDDQ5 AG5
K33 VCCSA6 VDDQ6 AG9
BR1 RSVD_TP1 RSVD11 BK28
K34 VCCSA7 VDDQ7 AJ12
BT2 RSVD_TP2 RSVD10 BJ28
K35 VCCSA8 VDDQ8 AL11
L31 VCCSA9 VDDQ9 AP6
BN35
L32 VCCSA10 11.1A 2A VDDQ10 AP7 RSVD15
L35 VCCSA11 VDDQ11 AR12

J24 RSVD28
L36 VCCSA12 VDDQ12 AR6
H24 RSVD27
L37 VCCSA13 VDDQ13 AT12
BN33 RSVD14
L38 VCCSA14 VDDQ14 AW6
BL34 RSVD13
M29 VCCSA15 VDDQ15 AY6
M30 VCCSA16 VDDQ16 J5
C N29 RSVD30 C
M31 VCCSA17 VDDQ17 J6
R14 RSVD31
M32 VCCSA18 VDDQ18 K12
AE29 RSVD2
M33 VCCSA19 VDDQ19 K6
AA14 RSVD1
M34 VCCSA20 VDDQ20 L12
AP29 RSVD5
M35 VCCSA21 VDDQ21 L6
AP14 RSVD4
M36 VCCSA22 VDDQ22 R6
A36 VSS_A36
VDDQ23 T6
W6
PVCCIO VDDQ24 A37
VDDQ25 Y12 VCCPLL_OC VSS_A37
AG12
Vinafix.com
VCCIO1
G15 40 IN PCH2CPU_TRIGGER H23 PROC_TRIGIN
VCCIO2 I
G17 PVCCST 40 IN CPU2PCH_TRIGGER R4840 1 2 A 30_5%_2 CPU_TRIGOUT J23 PROC_TRIGOUT
VCCIO3
G19 VCCIO4 VCCPLL_OC1 BH13
F30 RSVD24
G21 BJ13
VCCIO5 VCCPLL_OC2 PVCCSTG
H15 VCCIO6 VCCPLL_OC3 G11
H16 VCCIO7 E30
H17 VCCIO8 5.5A 0.12A VCCST H30 RSVD23
H19 VCCIO9
H20 VCCIO10 VCCSTG2 H29
B30 RSVD7 RSVD12 BL31
H21 VCCIO11
PVCCST C30 RSVD21 RSVD3 AJ8
H26 VCCIO12 VCCSTG1 G30
RSVD25 G13
H27 VCCIO13
B J15 VCCIO14 VCCPLL1 H28 B
G3
J16 VCCIO15 0.145A VCCPLL2 J28
J3
RSVD26
C38
22UF_6.3V_3
22UF_6.3V_3
J17 I I RSVD29 RSVD22

VCCIO16 A A C1
1
J19 RSVD20
VCCIO17 32 BR2
J20 M38 RSVD17
VCCSA_VCCSENSE
C4541
C4540
VCCIO18 VCCSA_SENSE OUT 18 BR35 BP1 1

J21 M37 RSVD19 RSVD16
VCCIO19 VSSSA_SENSE VCCSA_VSSSENSE OUT 18 BR31 B38 TP4526
RSVD18 RSVD8 1
J26 VCCIO20 32 TP4527
BH30 RSVD9 RSVD6 B2 1
J27 H14 VCCIO_VCCSENSE 17 TP4528
VCCIO21 VCCIO_SENSE OUT
2
J14 VCCIO_VSSSENSE 32 17
VSSIO_SENSE OUT 32
13 OF 13
12 OF 13
INTEL_J43242_BGA_1440P PVCCIO
R4524 100_1%_2
I
32 17 IN VCCIO_VCCSENSE 1 A 2
R4522 100_1%_2
I
32 17 IN VCCIO_VSSSENSE 1 A 2
A PVCCSA A
100_1%_2
32 18 IN VCCSA_VCCSENSE 1R4517 I
A 2
100_1%_2
32 18 IN VCCSA_VSSSENSE 1R4521 I
A 2
INVENTEC
TITLE
SKYLAKE7_H-POWER
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 32 of 139
8 7 6 5 4 3 2 1
A
B
C
D
8
8
C4765
C4791
2 1
2 1
I
A
I
A
22UF_6.3V_3 P1V2
1UF_6.3V_2
PVCCSA
C4789 C4776
C4717 2 1
I
A
2 1
Vinafix.com
I
A
1UF_6.3V_2_DY 22UF_6.3V_3
10UF_6.3V_3
PVCCSA
C4790 C4764
2 1
I
A
1UF_6.3V_2_DY
22UF_6.3V_3
C4732
2 1
I
A
7
7
22UF_6.3V_3
PLACE IN TOP SIDE

C4787 C4775
2 1I
2 1
I
A
A
C4786
P1V2
2 1 C4709 10UF_6.3V_2 10UF_6.3V_2
I
A
PVCCSA
C4774
1UF_6.3V_2 22UF_6.3V_3_DY C4782 2 1
2 1
I
A
PVCCSA
A
C4726 C4708 10UF_6.3V_2

10UF_6.3V_2
2 1
I
A
22UF_6.3V_3_DY C4781 C4773
1UF_6.3V_2 2 1 2 1
I
I
A
A
C4706
10UF_6.3V_2 10UF_6.3V_2
VCCPLL_OC
2 1
I
A
6
6
C4772
47UF_6.3V_5 C4780 2 1
2 1
I
A
I
A
C4703
2 1 10UF_6.3V_2
10UF_6.3V_2
I
A
PLACE U4555 PIN BH13,BJ13,G11

47UF_6.3V_5 C4779 C4771
2 1 2 1
I
I
A
A
10UF_6.3V_2 10UF_6.3V_2
C4770
C4778 2 1
2 1
I
A
I
A
PLACE IN BACK SIDE
10UF_6.3V_2
10UF_6.3V_2
C4718
C4769
2 1 2 1
I
I
A
A
C4783
2 1 22UF_6.3V_3 10UF_6.3V_2
I
A
5
5
10UF_6.3V_2 C4768
PLACE IN BACK SIDE
C4716 2 1
I
A
2 1
I
A
C4733 10UF_6.3V_2
2 1 22UF_6.3V_3
I
A
10UF_6.3V_2 C4763
C4719 2 1
I
A
C4731 10UF_6.3V_2
2 1 22UF_6.3V_3_DY
I
A C4508
10UF_6.3V_2 2 1
I
A
PVCCIO
10UF_6.3V_2
4
C4766
4
2 1
I
A
PLACE IN BACK SIDE 1UF_6.3V_2 C4701

Vinafix.com
PVCCSTG
P1V2
10UF_6.3V_2_DY
C4700
2 1
I
A
10UF_6.3V_2
C4730
2 1
I
A
1UF_6.3V_2
PVCCST
PCB P/N
CHANGE by
3
3
XXX
P1V2
C4729
PVCCSA
2 1
I
EDS VER0.7
A
10UF X 7 1UF X 1
1UF_6.3V_2
47UF X 2 22UF X 2
10UF X 11 22UF X 4
60xxxxxxxxxx
PVCCST
DATE
PLACE U4555 PINH29,G30 PLACE U4555 PINH30 PLACE U4555 PINH28,J28
PCB VER
2
XXX
2
21-OCT-2002
PLACE CLOSE TO CPU Y12 PIN (ONE 10UF)
A3
SIZE
TITLE
CS
SHEET
CODE
33
of
139
1
DOC.NUMBER
1
1310xxxxx-0-0
SKYLAKE8_H-DECOUPLING
INVENTEC
X01
REV
A
B
C
D
A
B
C
D
C4723
2 1
8
8
PVCORE
47UF_6.3V_5_DY
C4722
2 1
47UF_6.3V_5_DY
C4721
2 1 C4688
2 1
I
A
Vinafix.com
47UF_6.3V_5_DY
PVCCGT
10UF_6.3V_2
EDS VER0.7
PVCCGT
C4687
C4715 2 1
47UF X 3 22UF X 7
10UF X 10 1UF X 12
I
A
2 1
10UF_6.3V_2
PVCORE
10UF_6.3V_2_DY
C4711
2 1 C4683
2 1
I
A
7
10UF_6.3V_2_DY
7
C4710
10UF_6.3V_2
2 1 C4682
2 1
I
A
10UF_6.3V_2_DY
C4698
10UF_6.3V_2
2 1
C4681
10UF_6.3V_2_DY 2 1
I
A
C4696
2 1 10UF_6.3V_2
10UF_6.3V_2_DY C4680
C4695 2 1
I
A
2 1 10UF_6.3V_2
10UF_6.3V_2_DY
C4694
C4659
2 1 2 1
I
A
6
6
10UF_6.3V_2_DY 10UF_6.3V_2
I
A
C4693
C4602
2 1 C4658
2 1 2 1
I
A
10UF_6.3V_2_DY
C4692
10UF_6.3V_2 47UF_4V_3
2 1 C4600
C4657 2 1
2 1
I
A
10UF_6.3V_2_DY
I
A
C4691
10UF_6.3V_2 47UF_6.3V_5
2 1 C4589
C4656 2 1
I
A
10UF_6.3V_2_DY 2 1
I
A
C4690 47UF_6.3V_5
PVCCGT
10UF_6.3V_2
2 1
10UF_6.3V_2_DY
C4689
2 1
5
5
10UF_6.3V_2_DY
C4686
2 1
10UF_6.3V_2_DY
PLACE IN TOP SIDE
C4685
2 1
10UF_6.3V_2_DY C4627
C4684
2 1
2 1
I
A
10UF_6.3V_2_DY 1UF_6.3V_2
PVCCGT
C4679
C4628
H82 CPU
2 1
2 1
I
A
10UF_6.3V_2_DY
1UF_6.3V_2
4
C4629
4
2 1
I
A
1UF_6.3V_2
Vinafix.com
C4630
2 1
I
A
C4585
1UF_6.3V_2 2 1
I
A
C4631
2 1 22UF_6.3V_3
PVCCGT
I
A
C4584
1UF_6.3V_2
2 1
I
A
C4761
2 1 22UF_6.3V_3
I
A
C4583
PCB P/N
1UF_6.3V_2
CHANGE by 2 1
3
I
A
C4660
3 2 1 22UF_6.3V_3
I
A
1UF_6.3V_2 C4582
XXX
C4661 2 1
I
A
2 1
I
22UF_6.3V_3
A
1UF_6.3V_2 C4581
60xxxxxxxxxx
C4662 2 1
I
A
2 1
I
22UF_6.3V_3
A
1UF_6.3V_2 C4580
C4797
2 1
DATE
2 1
I
A
I
A
PCB VER
22UF_6.3V_3
1UF_6.3V_2
C4555
C4785
2
XXX
2 1
2
C4670 2 1
I
A
I
A
2 1
22UF_6.3V_3
PVCORE
1UF_6.3V_2
1UF_6.3V_2_DY C4554
C4760
C4669
21-OCT-2002
2 1
2 1
2 1
I
A
A
NI
1UF_6.3V_2_DY 1UF_6.3V_2 22UF_6.3V_3

A3
SIZE
C4663 C4588
2 1
TITLE
OPEN
CS
PLACE IN BACK SIDE
A
SHEET
NI
CODE
1UF_6.3V_2_DY
22UF_6.3V_3
34
C4668
of
1UF_6.3V_2_DY
139
SKYLAKE9_H-GT
1
DOC.NUMBER
1
1310xxxxx-0-0
INVENTEC
DECOUPLING
X01
REV
A
B
C
D
8 7 6 5 4 3 2 1
PVCCGT
PVCCGT
I I
I A A
A I
A U4555 U4555
U4555 BN4 F15 AT14 BD35
A10 AK4 U4555 VSS_325 VSS_409 VCCGT1 VCCGT80
VSS_1 VSS_82 AW5 BJ15 BN7 F17 AT31 BD36
A12 AL10 VSS_163 VSS_244 VSS_326 VSS_410 VCCGT2 VCCGT81
VSS_2 VSS_83 AY12 BJ18 BP12 F19 AT32 BE31
VSS_5 VSS_86 B9 BJ29 BP21 F23 AT35 BE34
VSS_6 VSS_87 BA10 BJ30 BP24 F25 AT36 BE35
VSS_9 VSS_90 BA37 BJ33 BP29 F3 AU14 BE38
VSS_10 VSS_91 BA38 BJ34 BP33 F31 AU29 BF13
A6 AM1 VSS_172 VSS_253 VSS_335 VSS_419 VCCGT11 VCCGT90
D VSS_11 VSS_92 BA6 VSS_173 VSS_254 BJ35 BP34 VSS_336 VSS_420 F36 AU30 VCCGT12 VCCGT91 BF14
A9 VSS_12 VSS_93 AM12 D
BA7 VSS_174 VSS_255 BJ36 BP7 VSS_337 VSS_421 F4 AU31 VCCGT13 VCCGT92 BF29
AA12 VSS_13 VSS_94 AM2
BA8 VSS_175 VSS_256 BK13 BR12 VSS_338 VSS_422 F5 AU32 VCCGT14 VCCGT93 BF30
BA9 VSS_176 VSS_257 BK14 BR14 VSS_339 VSS_423 F8 AU35 VCCGT15 VCCGT94 BF31
BB1 VSS_177 VSS_258 BK15 BR18 VSS_340 VSS_424 F9 AU36 VCCGT16 VCCGT95 BF32
AB33 VSS_16 VSS_97 AM38
BB12 VSS_178 VSS_259 BK18 BR21 VSS_341 VSS_425 G10 AU37 VCCGT17 VCCGT96 BF35
BB2 VSS_179 VSS_260 BK22 BR24 VSS_342 VSS_426 G12 AU38 VCCGT18 VCCGT97 BF36
BB29 VSS_180 VSS_261 BK25 BR25 VSS_343 VSS_427 G14 AV29 VCCGT19 VCCGT98 BF37
AC1 VSS_19 VSS_100 AN12
BB3 VSS_181 VSS_262 BK29 BR26 VSS_344 VSS_428 G16 AV30 VCCGT20 VCCGT99 BF38
BB30 VSS_182 VSS_263 BK6 BR29 VSS_345 VSS_429 G18 AV31 VCCGT21 VCCGT100 BG29
BB4 VSS_183 VSS_264 BL13 BR34 VSS_346 VSS_430 G20 AV32 VCCGT22 VCCGT101 BG30
AC38 VSS_24 VSS_105 AP10
BC12 VSS_186 VSS_267 BL19 BT12 VSS_349 VSS_433 G24 AV35 VCCGT25 VCCGT104 BG33
BC13 VSS_187 VSS_268 BL20 BT14 VSS_350 VSS_434 G26 AV36 VCCGT26 VCCGT105 BG34
BC14 VSS_188 VSS_269 BL21 BT18 VSS_351 VSS_435 G28 AW14 VCCGT27 VCCGT106 BG35
BC33 VSS_189 VSS_270 BL22 BT21 VSS_352 VSS_436 G4 AW31 VCCGT28 VCCGT107 BG36
AD10 VSS_28 VSS_109 AP34
BC34 VSS_190 VSS_271 BL29 BT24 VSS_353 VSS_437 G5 AW32 VCCGT29 VCCGT108 BH33
BC6 VSS_191 VSS_272 BL33 BT26 VSS_354 VSS_438 G6 AW33 VCCGT30 VCCGT109 BH34
BD10 VSS_192 VSS_273 BL35 BT29 VSS_355 VSS_439 G8 AW34 VCCGT31 VCCGT110 BH35
AD29 VSS_31 VSS_112 AR1
BD11 VSS_193 VSS_274 BL38 BT32 VSS_356 VSS_440 G9 AW35 VCCGT32 VCCGT111 BH36
BD12 VSS_194 VSS_275 BL6 BT5 VSS_357 VSS_441 H11 AW36 VCCGT33 VCCGT112 BH37
BD37 VSS_195 VSS_276 BM11 C11 VSS_358 VSS_442 H12 AW37 VCCGT34 VCCGT113 BH38
C BD6 VSS_196 VSS_277 BM12 C13 VSS_359 VSS_443 H18 AW38 VCCGT35 VCCGT114 BJ16 C
BD7 VSS_197 VSS_278 BM13 C15 VSS_360 VSS_444 H22 AY29 VCCGT36 VCCGT115 BJ17
AE33 VSS_36 VSS_117 AR3
BE1 VSS_200 VSS_281 BM2 C21 VSS_363 VSS_447 H35 AY32 VCCGT39 VCCGT118 BJ21
AF1 VSS_39 VSS_120 AR32
BE2 VSS_201 VSS_282 BM21 C23 VSS_364 VSS_448 J10 AY35 VCCGT40 VCCGT119 BJ23
BE4 VSS_205 VSS_286 BM25 C31 VSS_368 VSS_452 J32 BA13 VCCGT44 VCCGT123 BJ37
AF3 AR37
Vinafix.com
VSS_44 VSS_125 BE5 BM26 C37 J33 BA14 BJ38
AF4 AR38 VSS_206 VSS_287 VSS_369 VSS_453 VCCGT45 VCCGT124
VSS_45 VSS_126 BE6 BM27 C5 J36 BA29 BK16
AG10 AR4 VSS_207 VSS_288 VSS_370 VSS_454 VCCGT46 VCCGT125
VSS_46 VSS_127 BF12 BM28 C8 J4 BA30 BK17
AG11 AR5 VSS_208 VSS_289 VSS_371 VSS_455 VCCGT47 VCCGT126
VSS_47 VSS_128 BF33 BM29 C9 J7 BA31 BK19
AG13 AT29 VSS_209 VSS_290 VSS_372 VSS_456 VCCGT48 VCCGT127
VSS_48 VSS_129 BF34 BM3 D10 K1 BA32 BK20
VSS_49 VSS_130 BF6 BM33 D12 K10 BA33 BK21
VSS_50 VSS_131 BG12 BM35 D14 K11 BA34 BK23
AG6 AU10 VSS_212 VSS_293 VSS_375 VSS_459 VCCGT51 VCCGT130
VSS_53 VSS_134 BG37 BM6 D20 K38 BB13 BK27
AH12 AU33 VSS_215 VSS_296 VSS_378 VSS_462 VCCGT54 VCCGT133
VSS_54 VSS_135 BG38 BM7 D22 K4 BB14 BL15
VSS_55 VSS_136 BG6 BM8 D24 K5 BB31 BL16
VSS_56 VSS_137 BH1 BM9 D26 K7 BB32 BL17
B VSS_57 VSS_138 BH10 VSS_219 VSS_300 BN12 D28 VSS_382 VSS_466 K8 BB33 VCCGT58 VCCGT137 BL23 B
AH36 VSS_58 VSS_139 AU8
BH11 VSS_220 VSS_301 BN14 D3 VSS_383 VSS_467 K9 BB34 VCCGT59 VCCGT138 BL24
AH6 VSS_59 VSS_140 AU9
BH12 VSS_221 VSS_302 BN18 D30 VSS_384 VSS_468 L29 BB35 VCCGT60 VCCGT139 BL25
AJ1 VSS_60 VSS_141 AV37
AJ13 VSS_61 VSS_142 AV38
AJ2 VSS_62 VSS_143 AW1
BH4 VSS_225 VSS_306 BN21 E34 VSS_388 VSS_472 M12 BC29 VCCGT64 VCCGT143 BL36
BH5 VSS_226 VSS_307 BN24 E35 VSS_389 VSS_473 M13 BC30 VCCGT65 VCCGT144 BL37
BH6 VSS_227 VSS_308 BN29 E38 VSS_390 VSS_474 N10 BC31 VCCGT66 VCCGT145 BM15
BH9 VSS_230 VSS_311 BN34 N3 VSS_393 VSS_477 N2 BC36 VCCGT69 VCCGT148 BM36
W4 VSS_69 VSS_150 U6
T2 P38 N33 BT8 BC37 BM37
W5 VSS_70 VSS_151 V12 VSS_231 VSS_312 VSS_394 VSS_478 VCCGT70 VCCGT149 PVCCGT
T3 VSS_232 VSS_313 P6 N34 VSS_395 VSS_479 BR9 BC38 VCCGT71 VCCGT150 BN15 A
Y10 VSS_71 VSS_152 V29 I
T33 VSS_233 VSS_314 R12 N4 VSS_396 BD13 VCCGT72 VCCGT151 BN16 R4525
Y11 V30
VSS_72 VSS_153 T34 R29 N5 A3 BD14 BN17 35 18 VGT_VCCSENSE 1 2 100_1%_2
Y13 VSS_73 VSS_154 A14
T4
VSS_234 VSS_315
AY14 N6
VSS_397 VSS_A3
A34 BD29
VCCGT73 VCCGT152
BN36
IN A
Y14 AD7 VSS_235 VSS_316 VSS_398 VSS_A34 VCCGT74 VCCGT153
VSS_74 VSS_155 T5 BD38 N7 A4 BD30 BN37 R4527 I
Y37 V6 VSS_236 VSS_317 VSS_399 VSS_A4 VCCGT75 VCCGT154
35 18 VGT_VSSSENSE 1 2 100_1%_2
Y38
VSS_75 VSS_156
W1
T7 VSS_237 VSS_318 R30 N8 VSS_400 VSS_B3 B3 BD31 VCCGT76 VCCGT155 BN38 IN
VSS_76 VSS_157 T8 T1 N9 B37 BD32 BP15
Y7 W12 VSS_238 VSS_319 VSS_401 VSS_B37 VCCGT77 VCCGT156
VSS_77 VSS_158 T9 T10 P12 BR38 BD33 BP16
VSS_239 VSS_320 VSS_402 VSS_BR38 1 VCCGT78 VCCGT157
Y8 VSS_78 VSS_159 W2 TP4525
U37 VSS_240 VSS_321 T11 P37 VSS_403 VSS_BT3 BT3 BD34 VCCGT79 VCCGT158 BP17
Y9 VSS_79 VSS_160 W3
U38 VSS_241 VSS_322 T12 M14 VSS_404 VSS_BT35 BT35 BP37 VCCGT159 VCCGT164 BR37
AK29 VSS_80 VSS_161 W33
BJ12 VSS_242 VSS_323 T13 M6 VSS_405 VSS_BT36 BT36 BP38 VCCGT160 VCCGT165 BT15
A AK30 VSS_81 VSS_162 W34 A
6 OF 13 BJ14 VSS_243 VSS_324 T14 N1 VSS_406 VSS_BT4 BT4 BR15 VCCGT161 VCCGT166 BT16
7 OF 13 F11 VSS_407 VSS_C2 C2 BR16 VCCGT162 VCCGT167 BT17
INTEL_J43242_BGA_1440P F13 D38 BR17 BT37
INTEL_J43242_BGA_1440P VSS_408 VSS_D38 VCCGT163 VCCGT168
8 OF 13
INTEL_J43242_BGA_1440P AH37 VGT_VSSSENSE 18 35

VSSGT_SENSE
AH38
OUT
VCCGT_SENSE VGT_VCCSENSE OUT 18 35
11 OF 13
INVENTEC
TITLE
SKYLAKE10_H-GND
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 35 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P3V3A
R4911
I
1 2 A
100K_5%_2
I
A
U4710
R_GPP_A11 BE36 AV29 PLT_RST# 36 P3V3A
GPP_A11/PME#/SD_VDD2_PWR_EN# GPP_B13/PLTRST# OUT
R15 RSVD2 Y47 PCH_TP_I2C_INT# 53
R13 RSVD1
GPP_K16/GSXCLK
Y46
BI
GPP_K12/GSXDOUT TB_HTPLG IN
D GPP_K13/GSXSLOAD Y48
GPP_K14/GSXDIN W46 D
GPP_K15/GSXSRESET# AA45
1 VSS AL37 VSS R4708
TP4713 1 TP AN35
TP4702 TP 57 36 OUT PCH_W_DISABLE2# 1 2
AL47 THERM_SCI# 49
63 50 OUT PCH_SPI_SI 1 R133 2
33_5%_2 AU41 SPI0_MOSI
GPP_E3/CPU_GP0
AM45
BI 10K_5%_1
GPP_E7/CPU_GP1
63 50 IN PCH_SPI_SO 1 R134 2
33_5%_2 BA45 SPI0_MISO BF32
GPP_B3/CPU_GP2 PCH_W_DISABLE2# IN 36 57
50 OUT PCH_SPI_CS0# 1 R135 2
33_5%_2 AY47 SPI0_CS0# BC33
GPP_B4/CPU_GP3 PCH_CIO_PLUG_EVENTOUT 36
63 50 OUT PCH_SPI_CLK 1 R136 2
33_5%_2 AW47 SPI0_CLK
1 SPI0_CS1# AW48
TP4714 SPI0_CS1# AE44 P3V3A
GPP_H18/SML4ALERT# P3V3A
50 OUT PCH_SPI_SO2 R4701 1 2 33_5%_2 AY48 SPI0_IO2 GPP_H17/SML4DATA AJ46
50 OUT PCH_SPI_SO3 R4721 1 2 33_5%_2 BA46 SPI0_IO3 GPP_H16/SML4CLK AE43 R4834
63 OUT PCH_SPI_CS2# AT40 SPI0_CS2# GPP_H15/SML3ALERT# AC47 1 2 R4711
AD48 36 PCH_CIO_PLUG_EVENT
1 2
BE19 GPP_D1/SPI1_CLK/SBK1_BK1
GPP_H14/SML3DATA
AF47 10K_5%_1 OUT
33OHM FOR 3.3V AND 15 OHM FOR 1.8V BF19 GPP_D0/SPI1_CS#/SBK0_BK0
GPP_H13/SML3CLK
GPP_H12/SML2ALERT# AB47 1 R4835 2
100K_5%_1
BF18 GPP_D3/SPI1_MOSI/SBK3_BK3
GPP_H11/SML2DATA AD47
BE18 I A
GPP_D2/SPI1_MISO/SBK2_BK2
GPP_H10/SML2CLK AE48 20K_5%_2 P3V3_RTC
BC17 GPP_D22/SPI1_IO3 R4833
BD17 GPP_D21/SPI1_IO2 1 OF 13 INTRUDER# BB44 INTRUDER# 1 2
1M_5%_2
C C
Vinafix.com P3V3A
1
I
A
C33
2
1
R4776
2 PCH_PLTRST#_BUF 73 74
0.1UF_16V_2 OUT
U4700
36 IN PLT_RST# 1 B VCC 5 0_5%_2
2 A
3 GND Y 4 BUF_PLT_RST# OUT 51 57 58 59 63 64
NXP_74LVC1G08GW_TSOT353_5P
B B
1
R4729
100K_5%_2
A A
INVENTEC
TITLE
PCH-SPI,GPP
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 36 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
I
A
U4710
26 IN DMI_TX0_DN K34 DMI0_RXN USB2N_1 J3 USB2_REAR_1N BI 60
26 IN DMI_TX0_DP J35 DMI0_RXP USB2P_1 J2 USB2_REAR_1P BI 60
26 OUT DMI_RX0_DN C33 DMI0_TXN USB2N_2 N13 USB2.0 TYPE-C
26 OUT DMI_RX0_DP B33 DMI0_TXP USB2P_2 N15
26 IN DMI_TX1_DN G33 K4 USB2_REAR_3N BI 61
26 DMI_TX1_DP F34
DMI1_RXN USB2N_3
K3 USB2_REAR_3P 61
CHARGER
IN DMI1_RXP USB2P_3 BI
26 OUT DMI_RX1_DN C32 M10 USB_P4_DN BI 64
D 26 DMI_RX1_DP B32
DMI1_TXN USB2N_4
L9 USB_P4_DP 64
USB 2.0 TYPE-A
OUT DMI1_TXP USB2P_4 BI D
26 IN DMI_TX2_DN K32 DMI2_RXN USB2N_5 M1 USB_P5_DN BI 64 USB 2.0 TYPE-A
26 IN DMI_TX2_DP J32 DMI2_RXP USB2P_5 L2 USB_P5_DP BI 64
26 OUT DMI_RX2_DN C31 DMI2_TXN USB2N_6 K7
26 OUT DMI_RX2_DP B31 DMI2_TXP USB2P_6 K6
26 IN DMI_TX3_DN G30 DMI3_RXN USB2N_7 L4 USB_CAM_R_DN BI 62
26 IN DMI_TX3_DP F30 DMI3_RXP USB2P_7 L3 USB_CAM_R_DP BI 62 WEBCAM
26 OUT DMI_RX3_DN C29 DMI3_TXN USB2N_8 G4 TP_D- BI 62
26 OUT DMI_RX3_DP B29 DMI3_TXP USB2P_8 G5 TP_D+ BI 62 TOUCH PANEL
A25 DMI7_TXP USB2N_9 M6
B25 DMI7_TXN USB2P_9 N8
P24 DMI7_RXP USB2N_10 H3
R24 DMI7_RXN USB2P_10 H2
C26 DMI6_TXP USB2N_11 R10
B26 DMI6_TXN USB2P_11 P9
F26 DMI6_RXP USB2N_12 G1
G26 DMI6_RXN USB2P_12 G2
B27 DMI5_TXP USB2N_13 N3
C27 N2 IN USB2_OC0#
DMI5_TXN USB2P_13
L26 E5 USB_BT_DN 57 P3V3A
M26
DMI5_RXP USB2N_14
F6
BI BLUETOOTH IN USB2_OC2#
DMI5_RXN USB2P_14 USB_BT_DP BI 57
0.1UF_6.3V_1
0.1UF_6.3V_1
D29
1
DMI4_TXP
E28 AH36 I
DMI4_TXN GPP_E9/USB2_OC0# USB2_OC0# R4783 1 A 2 10K_5%_2
C4707
C4705
K29 AL40 I
C DMI4_RXP GPP_E10/USB2_OC1# USB2_OC1# R4774 1 A 2 10K_5%_2 C
M29 AJ44 I
DMI4_RXN GPP_E11/USB2_OC2# USB2_OC2# R4767 1 A 2 10K_5%_2
AL41 I
GPP_E12/USB2_OC3# USB2_OC3# R4760 1 A 2 10K_5%_2
G17 AV47 1 2
2
PCIE1_RXN/USB31_7_RXN GPP_F15/USB2_OC4# R4720 10K_5%_2
F16 PCIE1_RXP/USB31_7_RXP GPP_F16/USB2_OC5# AR35 R4726 1 2 10K_5%_2
A17 PCIE1_TXN/USB31_7_TXN GPP_F17/USB2_OC6# AR37 R4727 1 2 10K_5%_2
B17 PCIE1_TXP/USB31_7_TXP GPP_F18/USB2_OC7# AV43 R4728 1 2 10K_5%_2
R21 PCIE2_RXN/USB31_8_RXN
P21 F4 USB2_COMP R4756 1 2 113_1%_2
B18
PCIE2_RXP/USB31_8_RXP
PCIE2_TXN/USB31_8_TXN
USB2_COMP
USB2_VBUSSENSE F3 USB2_VBUSSENSE R4758 1 2 I
A 1K_5%_2
P/N 6013A0075301
Vinafix.com
C18 PCIE2_TXP/USB31_8_TXP RSVD1 U13
I
BOM: USE 113_1%_2 P3V3DS
K18 PCIE3_RXN/USB31_9_RXN USB2_ID G3 USB2_ID R4759 1 2 A 1K_5%_2
J18 PCIE3_RXP/USB31_9_RXP
B19 BE41 GPD7 37
C19
PCIE3_TXN/USB31_9_TXN GPD7 OUT
PCIE3_TXP/USB31_9_TXP
N18 G45 PCIE_SSD_TX24P 59
R18
PCIE4_RXN/USB31_10_RXN PCIE24_TXP
G46
IN
PCIE4_RXP/USB31_10_RXP PCIE24_TXN PCIE_SSD_TX24N IN 59
D20 Y41 PCIE_SSD_RX24P 59 R4793
C20
PCIE4_TXN/USB31_10_TXN PCIE24_RXP
Y40
OUT GPD7
PCIE4_TXP/USB31_10_TXP PCIE24_RXN PCIE_SSD_RX24N OUT 59 37 OUT 1 2
F20 G48 PCIE_SSD_TX23P 59
G20
PCIE5_RXN PCIE23_TXP
G49
IN
PCIE5_RXP PCIE23_TXN PCIE_SSD_TX23N IN 59 100K_5%_2
B21 W44 PCIE_SSD_RX23P 59
A22
PCIE5_TXN PCIE23_RXP
W43
OUT
PCIE5_TXP PCIE23_RXN PCIE_SSD_RX23N OUT 59
B K21 H48 PCIE_SSD_TX22P 59 SSD2 B
J21
PCIE6_RXN PCIE22_TXP
H47
IN
PCIE6_RXP PCIE22_TXN PCIE_SSD_TX22N IN 59
D21 U41 PCIE_SSD_RX22P 59
C21
PCIE6_TXN PCIE22_RXP
U40
OUT
PCIE6_TXP PCIE22_RXN PCIE_SSD_RX22N OUT 59
B23 F46 PCIE_SSD_TX21P 59
C23
PCIE7_TXP PCIE21_TXP
G47
IN
PCIE7_TXN PCIE21_TXN PCIE_SSD_TX21N IN 59
J24 R44 PCIE_SSD_RX21P 59
L24
PCIE7_RXP PCIE21_RXP
T43
OUT
PCIE7_RXN PCIE21_RXN PCIE_SSD_RX21N OUT 59
F24 PCIE8_RXN
G24 PCIE8_RXP
B24 PCIE8_TXN
C24 PCIE8_TXP
2 OF 13
A A
INVENTEC
TITLE
PCH-DMI,USB2,USB3
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 37 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
I
A
U4710
D 57 OUT CL_CLK1 AR2 CL_CLK G36
PCIE9_RXN PCIE_SSD_RX9N IN 58
57 OUT CL_DATA1 AT5 CL_DATA F36 D
PCIE9_RXP PCIE_SSD_RX9P IN 58
57 OUT CL_RST#1 AU4 CL_RST# C34
PCIE9_TXN PCIE_SSD_TX9N OUT 58
D34 PCIE_SSD_TX9P 58
P48 GPP_K8
PCIE9_TXP OUT
V47
V48
GPP_K9
GPP_K10 PCIE10_RXN K37 PCIE_SSD_RX10N IN 58
SSD1
W47 J37 PCIE_SSD_RX10P 58
GPP_K11 PCIE10_RXP
C35
IN
PCIE10_TXN PCIE_SSD_TX10N OUT 58
PCIE10_TXP B35 PCIE_SSD_TX10P OUT 58
L47 GPP_K0
L46 GPP_K1
PCIE15_RXN/SATA2_RXN F44
U48 GPP_K2
PCIE15_RXP/SATA2_RXP E45
51 IN EC_SCI# U47 GPP_K3 B40
N48 PCIE_15_SATA_2_TXN
GPP_K4 C40
N47 PCIE15_TXP/SATA2_TXP
GPP_K5
P47 GPP_K6
PCIE16_RXN/SATA3_RXN L41
R46 GPP_K7
PCIE16_RXP/SATA3_RXP M40
PCIE16_TXN/SATA3_TXN B41
58 OUT PCIE_SSD_TX11P C36 PCIE11_TXP/SATA0A_TXP C41
PCIE16_TXP/SATA3_TXP
58 OUT PCIE_SSD_TX11N B36
SSD1 58 PCIE_SSD_RX11P F39
PCIE11_TXN/SATA0A_TXN
IN PCIE11_RXP/SATA0A_RXP
PCIE17_RXN/SATA4_RXN K43 PCIE17_HDD_RX_DN IN 56
58 IN PCIE_SSD_RX11N G38 PCIE11_RXN/SATA0A_RXN K44 PCIE17_HDD_RX_DP IN 56
PCIE17_RXP/SATA4_RXP
A42 PCIE17_SSD_TX_DN C4954 1 2 0.01UF_50V_2 PCIE17_HDD_TX_C_DN HDD 56
C 38 OUT PLT_ID0 AR42 GPP_F10/SATA_SCLOCK
PCIE17_TXN/SATA4_TXN
B42
OUT C
PCIE17_TXP/SATA4_TXP PCIE17_SSD_TX_DP C4955 1 2 0.01UF_50V_2 PCIE17_HDD_TX_C_DP OUT 56
38 OUT PLT_ID1 AR48 GPP_F11/SATA_SLOAD
38 OUT PLT_ID3 AU47 GPP_F13/SATA_SDATAOUT0 P41
PCIE18_RXN/SATA5_RXN
38 OUT PLT_ID2 AU46 GPP_F12/SATA_SDATAOUT1 R40
57 PCIE_WLAN_TX14N C39 C42
OUT PCIE14_TXN/SATA1B_TXN PCIE18_TXN/SATA5_TXN
57
57
57
OUT
IN
PCIE_WLAN_TX14P
PCIE_WLAN_RX14N
PCIE_WLAN_RX14P
D39
D46
C47
PCIE14_TXP/SATA1B_TXP
PCIE14_RXN/SATA1B_RXN
PCIE18_TXP/SATA5_TXP D42
AK48 SATA_LED# 38
Vinafix.com
IN PCIE14_RXP/SATA1B_RXP GPP_E8/SATA_LED# OUT
GPP_E0/SATAXPCIE0/SATAGP0 AH41
B38
Vinafix.com
65 OUT PCIE_LAN_TX13N C4960 1 2 0.1UF_16V_2 PCIE13_TXN/SATA0B_TXN AJ43 M2_SSD1_DET#
C38 GPP_E1/SATAXPCIE1/SATAGP1 IN 38 58
65 OUT PCIE_LAN_TX13P C4961 1 2 0.1UF_16V_2 PCIE13_TXP/SATA0B_TXP AK47
C45 GPP_E2/SATAXPCIE2/SATAGP2
65 PCIE_LAN_RX13N
IN C46
PCIE13_RXN/SATA0B_RXN
GPP_F0/SATAXPCIE3/SATAGP_3 AN47
PVCCST
65 PCIE_LAN_RX13P
IN PCIE13_RXP/SATA0B_RXP
GPP_F1/SATAXPCIE4/SATAGP4 AM46
GPP_F2/SATAXPCIE5/SATAGP5 AM43 TP24
58 OUT PCIE_SSD_TX12P E37 PCIE12_TXP/SATA1A_TXP AM47 GPP_F3 1
2
PCIE_SSD_TX12N D38 GPP_F3/SATAXPCIE6/SATAGP6 TP4704
58 OUT
SSD1 58 PCIE_SSD_RX12P J41
PCIE12_TXN/SATA1A_TXN
GPP_F4/SATAXPCIE7/SATAGP7 AM48
IN PCIE12_RXP/SATA_1A_RXP
R4786
58 IN PCIE_SSD_RX12N H42 PCIE12_RXN/SATA1A_RXN AU48
GPP_F21/EDP_BKLTCTL INV_PWM_PCH OUT 62 1K_5%_2
A
I
B44 AV46 LCM_BKLTEN 51 62
A44
PCIE20_TXP/SATA7_TXP GPP_F20/EDP_BKLTEN
AV44
OUT
LCM_VDDEN 62
1
R37
PCIE20_TXN/SATA7_TXN GPP_F19/EDP_VDDEN OUT I
A
R35 AD3 PCH_THERMTRIP#_R 1 R4785 2 PCH_THERMTRIP#
PCIE20_RXN/SATA7_RXN THRMTRIP# OUT 30
B D43 AF2 PCH_R_PECI 1 B
PCIE19_TXP/SATA6_TXP PECI 620_5% A 2 I PCH_PECI
IN 30 51
C44 AF3 H_PM_SYNC_R R4778 1 2 AI 30_5%_2 H_PM_SYNC 30
N42
PCIE19_TXN/SATA6_TXN PM_SYNC
AG5
OUT R79
PCIE19_RXP/SATA6_RXP PLTRST_CPU# PLTRST_CPU# OUT 30
M44 AE2 H_PM_DOWN 12.1_1%_2
PCIE19_RXN/SATA6_RXN 3 OF 13 PM_DOWN IN 30
P3V3S
1 R4707 2 M2_SSD1_DET# IN 38 58
10K_5%_2
P3V3S P3V3S
P3V3S P3V3S P3V3S R4749
1 2 SATA_LED# OUT 38
10K_5%_2
100K_5%_2_DY
100K_5%_2_DY
100K_5%_2_DY
100K_5%_2_DY
100K_5%_2_DY
2
2
2
2
R4781
R4780
R4784
R4782
R4779
1
1
1
38 IN PLT_ID2 44 IN GPP_F14
38 IN PLT_ID3
A 38 IN PLT_ID038 IN PLT_ID1 A
100K_5%_2
100K_5%_2
2
2
100K_5%_2
100K_5%_2
100K_5%_2
2
2
R4789
R4788
R4791
R4790
R4787
1
1
1
INVENTEC
TITLE
PCH-CLINK,FAN,PCIE/SATA,HOST
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 38 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P3V3A
SLP_S3# OUT 39 51
1
R4718
PCH_CNVI_PWR_EN#
1 R4733 2
100K_5%_2 39 IN 10K_5%_2_DY
PCH_WAKE# 1 R4747 2
64 57 39 IN 1K_5%_2
2
ME_FLASH_EN 1 R4861 2
51 IN
1K_5%_2 P3V3A
I
A R4909 2
IA I U4710
1
54 HDA_BCLK R4972 1 2 A 33_5%_2 HDA_R_BCLK BD11 BF36 10K_5%_2_DY

OUT HDA_BCLK/I2S0_SCLK GPP_A12/BM_BUSY#/ISH_GP6/SX_EXIT_HOLDOFF#
D 54 IN HDA_SDIN0 BE11 HDA_SDI0/I2S0_RXD GPP_A8/CLKRUN# AV32
54 OUT HDA_SDO R4869 1 2I 33_5%_2 HDA_SDO_R BF12 HDA_SDO/I2S0_TXD A P1V2 D
54 OUT HDA_SYNC R4903 1 2A 33_5%_2 HDA_R_SYNC BG13 HDA_SYNC/I2S0_SFRM GPD11/LANPHYPC BF41
1 R4771 2 I
I
54 OUT HDA_RST# R4901 1 2A 33_5%_2 HDA_R_RST# BE10 HDA_RST#/I2S1_SCLK GPD9/SLP_WLAN# BD42 SLP_WLAN# OUT 57 470_5%_2
BF10 HDA_SDI1/I2S1_RXD
BE12 BB46 1 R4770 2 DDR4_DRAMRST#_CPUOUT
I2S1_TXD/SNDW2_DATA DRAM_RESET# A 47 48
BD12 I2S1_SFRM/SNDW2_CLK GPP_B2/VRALERT# BE32 C4802 SHORT_0402_5
GPP_B1/GSPI1_CS1#/TIME_SYNC1 BF33 1 2
I BE29 PCH_CNVI_PWR_EN# 39
GPP_B0/GSPI0_CS1# OUT
27 OUT AUD_CPU_SDI 1 R4927 2 A 30_5%_2 AUD_PCH_SDO AM2 HDACPU_SDO GPP_K17/ADR_COMPLETE R47 0.1UF_16V_2_DY
P3V3A
27 IN AUD_PCH_SDI I AN3 HDACPU_SDI GPP_B11/I2S_MCLK AP29
27 OUT AUD_CPU_SCLK1 R4930 2 A 30_5%_2 AUD_CPU_SCLK_R AM3 HDACPU_SCLK SYS_PWROK AU3 SYS_PWROK IN 51
BB47 PCH_WAKE# 39 57 64
AV18 GPP_D8/I2S2_SCLK
WAKE#
BE40
IN
AW18 GPD6/SLP_A# SLP_A 1
TP24 TP4700
GPP_D7/I2S2_RXD BF40
SLP_LAN# SLP_LAN# TP24
1 TP4703
46 IN CNV_CLKREQ BA17 GPP_D6/I2S2_TXD/MODEM_CLKREQ BC28
GPP_B12/SLP_S0# SLP_S0# TP24
1 TP4701
46 IN CNV_RF_RESET# BE16 GPP_D5/I2S2_SFRM/CNV_RF_RESET# BF42 R4912 2
BF15 GPD4/SLP_S3# SLP_S3# OUT 39 51 51 39 IN SUSWARN# 1
GPP_D20/DMIC_DATA0/SNDW4_DATA BE42
BD16 GPD5/SLP_S4# SLP_S4# OUT 51 10K_5%_2_DY
GPP_D19/DMIC_CLK0/SNDW4_CLK BC42
AV16 GPD10/SLP_S5# SLP_S5#_3R 1
TP24 P3V3A
GPP_D18/DMIC_DATA1/SNDW3_DATA TP4705
AW15 GPP_D17/DMIC_CLK1/SNDW3_CLK R4713
BE45 SUSCLK32_PCH SYS_RESET# 1 2
GPD8/SUSCLK
BF44
OUT 39 39 IN
GPD0/BATLOW# PCH_BATLOW# IN 39 10K_5%_2
C BE35 SUSACK# 51
C
GPP_A15/SUSACK# IN
42 IN RTC_RST# BE47 RTCRST# GPP_A13/SUSWARN#/SUSPWRDNACK BC37 SUSWARN# OUT 39 51
42 IN SRTC_RST# BD46 SRTCRST#
23 IN PCH_PWROK AY42 PCH_PWROK GPD2/LAN_WAKE# BG44

51 23 IN RSMRST# BA47 RSMRST# GPD1/ACPRESENT BG42 ACPRESENT
IN 39
BD39 SLP_SUS# 51
SLP_SUS#
BE46
OUT
SB_PWRBTN# 51
51 IN DPWROK AW41 DSW_PWROK
GPD3/PWRBTN#
AU2
IN
SYS_RESET# 39
39 BI SMBALERT# BE25 GPP_C2/SMBALERT#
SYS_RESET#
AW29
IN
Vinafix.com
PCH_SPKR 54
39 BI PCH_3A_SMCLK BE26 GPP_C0/SMBCLK
GPP_B14/SPKR
AE3
IN
H_PWRGD 30
39 BI PCH_3A_SMDATA BF26 GPP_C1/SMBDATA
CPUPWRGD OUT
39 OUT ESPI_LPC# BF24 GPP_C5/SML0ALERT# AL3
BF25 STRAP ITP_PMODE ITP_PMODE OUT 39
SHORT_0402_5
GPP_C3/SML0CLK AH4
BE24 PCH_JTAGX PCH_JTAGX 1 A 2 H_TCK IN 30
GPP_C4/SML0DATA AJ4
BD33 PCH_JTAG_TMS PCH_TMS IN 39 R4532
GPP_B23/SML1ALERT#/PCHHOT# AH3
BF27 PCH_JTAG_TDO PCH_TDO IN
40 39 40
GPP_C6/SML1CLK AH2
BE27 PCH_JTAG_TDI PCH_TDI IN 39 40
GPP_C7/SML1DATA AJ3
4 OF 13 PCH_JTAG_TCK PCH_TCK IN 39
LAYOUT NOTE:PLACE R4808 NEAR PCH
P3V3A LAYOUT NOTE:JTAG_TMS TERMINATIONS NEED TO BE PLACED NEAR PCH
LAYOUT NOTE:JTAG_TDI TERMINATIONS NEED TO BE PLACED NEAR PCH P3V3DS
B LAYOUT NOTE:JTAG_TDO TERMINATIONS NEED TO BE PLACED NEAR XDP B
39 BI SMBALERT# R4717 1 2 1K_5%_2
P3V3A
39 IN ESPI_LPC# R4702 1 2
4.7K_5%_2_DY
R4805
2
R4703 1 2 100K_5%_2 1 2
HIGH = ESPI MODE
10K_5%_2 D4801
NC
PCH_3A_SMCLK 2 R4828 1
LOW = LPC MODE 39 IN ACPRESENT 1 3 EC_ACPRESENT
39 OUT IN 39 51
2.2K_5%_2
THE SIGNAL HAS A WEAK INTERNAL PULL-DOWN RESISTOR.(20K OHM) R4804 DIODE-BAT54-TAP-PHP
R4913 1 2
39 PCH_3A_SMDATA2 1
BI 10K_5%_2
P3V3AL 2.2K_5%_2
39 PCH_BATLOW#
OUT
2
P1V05A
R367
10K_5%_2
EC_ACPRESENT ITP_PMODE R4891
OUT 39 51 39 IN 2 1 I A
1
2.2K_5%_2
P3V3S R4890 I
P3V3S 2.2K_5%_2 PCH_JTAGX SUSCLK32_PCH1 I R4753 2 SUSCLK 1 R4706 2 M2_WLAN_SUSCLK
A I
2 R4705 IN 1K_5%_2_DY 39 IN OUT 57 A
A 1 I A 33_5%_2 0_5%_2
Q4702
S1 1 PCH_3S_SMCLK 47 48 R4876 2 I
IN 40 39 IN PCH_TDO 1 100_5%_2_DY 1 R4750 2
2 G1 M2_SSD1_SUSCLK OUT 58
6 PCH_3A_SMCLK 39 0_5%_2
D1 IN
D2 3 PCH_3A_SMDATA
BI 39 40 39 IN PCH_TDI R4879 51_5%_2_DY I
5 1 R4710 2 M2_SSD2_SUSCLK
G2
OUT 59
4 PCH_3S_SMDATA 47 48 P3V3S 0_5%_2
S2 IN 40 39 IN PCH_TMSR4880 51_5%_2_DY
2N7002KDW 2 1 I A
R4775
2.2K_5%_2
39 IN
PCH_TCK
R4881 51_5%_2_DY INVENTEC
TITLE
PCH-AUDIO,SMBUS,JTAG
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 39 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P3V3A
R4873
I R4908
51 40 IN SERIRQ 2 1 A 10K_5%_2 1 2
0_5%_2
40 GPP_A7 1 R4813 2I A
10K_5%_2
IN A
KB_RST# I 1 R4723 2
51 40 IN 10K_5%_2
I
A
U4710
60 BI USB3_TX1N F9 USB31_1_TXN BB39 1 2
LPC_ESPI_IO0 R4846 IA 15_5%_2 LPC_AD<0> 51
60 BI USB3_TX1P F7 USB31_1_TXP
GPP_A1/LAD0/ESPI_IO0
AW37 1 2
BI
D 60 USB3_RX1N D11 GPP_A2/LAD1/ESPI_IO1 LPC_ESPI_IO1 R4847 IA 15_5%_2 LPC_AD<1>
BI 51
BI USB31_1_RXN
GPP_A3/LAD2/ESPI_IO2 AV37 LPC_ESPI_IO2 R4848 1 2 IA 15_5%_2 LPC_AD<2>
BI 51 D
60 BI USB3_RX1P C11 USB31_1_RXP BA38 1 2
LPC_ESPI_IO3 R4849 IA 15_5%_2 LPC_AD<3> 51
GPP_A4/LAD3/ESPI_IO3 BI
TYPE_C 60 BI USB3_TX2N C3 USB31_2_TXN
60 BI USB3_TX2P D4 USB31_2_TXP BE38
GPP_A5/LFRAME#/ESPI_CS0# LPC_FRAME# OUT 51
60 BI USB3_RX2N B9 USB31_2_RXN AW35 R4904 2 SERIRQ_ESPI_RST#
GPP_A6/SERIRQ/ESPI_CS1# SERIRQ 1 1
TP24
60 BI USB3_RX2P C9 USB31_2_RXP BA36 TP4806
GPP_A7/PIRQA#/ESPI_ALERT0# GPP_A7 OUT 40 OUT 40 51 0_5%_2_DY
C17 BE39 KB_RST# 40 51
C16
USB31_6_TXN GPP_A0/RCIN#/ESPI_ALERT1#
BF38
IN R4902 2
USB31_6_TXP GPP_A14/SUS_STAT#/ESPI_RESET# ESPI_RST# 1
G14 1
R4852 2 33_5%_2 CLK_LPC_DEBUG_R 51 0_5%_2
F14
USB31_6_RXN OUT
USB31_6_RXP BB36 LPC_ESPI_CLK 1 R4850 2 CLK_LPC_EC 1 R4897 2
GPP_A9/CLKOUT_LPC0/ESPI_CLK 33_5%_2 OUT 51
64 BI USB3_TX5N C15 USB31_5_TXN GPP_A10/CLKOUT_LPC1 BB34 1 2 22_5%_2 1
TP24 100K_5%_2_DY
USB3_TX5P B15 TP4804
64 BI USB31_5_TXP R4800
TYPE_A_L2 64 BI USB3_RX5N J13 USB31_5_RXN GPP_K19/SMI# T48 EC_SMI# OUT 40 51
64 BI USB3_RX5P K13 USB31_5_RXP GPP_K18/NMI# T47
61 BI USB3_TX3P G12 USB31_3_TXP

61 BI USB3_TX3N F11 USB31_3_TXN GPP_E6/SATA_DEVSLP2 AH40
CHARGER 61 BI USB3_RX3P C10 USB31_3_RXP GPP_E5/SATA_DEVSLP1 AH35 DEVSLP_SSD1 IN 58
61 BI USB3_RX3N B10 USB31_3_RXN GPP_E4/SATA_DEVSLP0 AL48
P3V3A
AP47 TP24
GPP_F9/SATA_DEVSLP7 DEVSLP_SSD7 1
USB3_TX4P C14 AN37 TP4805
64 BI USB31_4_TXP GPP_F8/SATA_DEVSLP6
64 BI USB3_TX4N B14 USB31_4_TXN GPP_F7/SATA_DEVSLP5 AN46
C TYPE_A_L1 USB3_RX4P J15 AR47 WHEN USED AS DEVSLP, NO EXTERNAL PULL-UP OR PULLDOWN TERMINATION REQUIRED FROM SATA HOST DEVSLP C
64 BI USB31_4_RXP GPP_F6/SATA_DEVSLP4 R4699
64 BI USB3_RX4N K16 USB31_4_RXN GPP_F5/SATA_DEVSLP3 AP48 51 40 IN EC_SMI# 1 2
6 OF 13
100K_5%_2_DY
I
A
U4710
RSVD7
RSVD8
Y14
Y15
Vinafix.com
RSVD6 U37
RSVD5 U35
RSVD3 N32
RSVD4 R32
RSVD2 AH15
B RSVD1 AH14 B
AL2 PCH_PREQ# 40
PREQ#
AM5
OUT
PRDY# PCH_PRDY# OUT 40
AM4 PCH_TRST# 40
CPU_TRST#
AK3 PCH_TRIGOUTGGER R4792 1
OUT
TRIGGER_OUT A I 2 30_5%_2 PCH2CPU_TRIGGER OUT 32
10 OF 13TRIGGER_IN AK2 CPU2PCH_TRIGGER 32
IN
39 PCH_TMS 1 R4794 2
0_5%_2 H_TMS 30
IN OUT
39 PCH_TDO 1 R4796 2
0_5%_2 H_TDO 30
IN OUT
39 PCH_TDI 1 R4797 2
0_5%_2 H_TDI 30
A IN OUT A
40 PCH_PREQ# 1 R4798 2
0_5%_2 H_PREQ# 30
IN OUT
40 PCH_PRDY# 1 R4799 2
0_5%_2 H_PRDY# 30
IN OUT
40 PCH_TRST# 1 R4801 2
0_5%_2 H_TRST# 30
IN OUT
INVENTEC
TITLE
PCH-LPC/ESPI,USB,SATA
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 40 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P3V3A
I
DCPRTC
1UF_6.3V_2
A
1
P1V05A
P3V3A
0.1UF_16V_2
C4813
1
I
C4814
1UF_6.3V_2
A
1
P3V3A
2
10UF_6.3V_2
1
1
P1V05A
22UF_6.3V_3
I I I I
C4815
I
1UF_6.3V_2
1UF_6.3V_2
A A A A
I
C4863
C4862
C4861
C4855
2
A I A
1UF_6.3V_2
A
1
U4710
AA22 AW9
2
VCCPRIM_1P051 VCCPRIM_3P32
AA23
C4817
22UF_6.3V_3
I I VCCPRIM_1P052
2
1UF_6.3V_2
1UF_6.3V_2
A A AB20 BF47
10UF_6.3V_2
1
1
I
A
I
A
VCCPRIM_1P053 DCPRTC1 P3V3_RTC
D AB22 VCCPRIM_1P054 DCPRTC2 BG47
C4854
C4853
C4852
C4851
AB23 D
2
VCCPRIM_1P055
AB27 VCCPRIM_1P056 VCCPRIM_3P35 V23
AB28 VCCPRIM_1P057 P3V3A
VCCSPI AN44
2 AB30
2
VCCPRIM_1P058
AD20 VCCPRIM_1P059 BC49
0.1UF_16V_2
0.1UF_16V_2_DY
AD23 VCCRTC1
1UF_6.3V_2_DY
1
VCCPRIM_1P0510
VCCRTC2 BD49 P3V3A
AD27 VCCPRIM_1P0511
C4872
AD28 AN21
C4875
C4876
VCCPRIM_1P0512 VCCPGPPG_3P3
P1V05A AD30 VCCPRIM_1P0513 AY8
1
AF23 VCCPRIM_3P33 I
P3V3A I
1UF_6.3V_2
VCCPRIM_1P0516 BB7 A
AF27 VCCPRIM_3P34
C4870
2
VCCPRIM_1P0517 A
AF30 AC35 P3V3A
1
I P1V05A VCCPRIM_1P0518 VCCPGPPHK1

1UF_6.3V_2
A AC36
0.1UF_16V_2
0.1UF_16V_2
P3V3A
1UF_6.3V_2
VCCPGPPHK2
C4864
U26
1
VCCPRIM_1P0523 I I P3V3S
1UF_6.3V_2
U29 AE35 A A
2
VCCPRIM_1P0524 VCCPGPPEF1
C4869
C4867
C4868
1
C4829
P1V05A V25 AE36
2
1UF_6.3V_2
A VCCPRIM_1P0525 VCCPGPPEF2
R4915 2
C4866
V27 VCCHDA
0_5%_2
1
0.1UF_16V_2
VCCPRIM_1P0526 IN A
R4906
AN24
2
V28 VCCPGPPD
1
VCCPRIM_1P0527 I I SHORT_0402_15
V30 AN26
1
2
I VCCPRIM_1P0528 VCCPGPPBC1 A A R4916
C4871
1UF_6.3V_2
A V31 AP26
0.1UF_16V_2
VCCPRIM_1P0529 VCCPGPPBC2
C4865
C4890
2
0_5%_2_DY
1
VCCDSW_1P5 AD31 VCCPRIM_1P0514 VCCPGPPA AN32
P3V3A
I
1
I AE17
P1V05A
2
A
1UF_6.3V_2
A VCCPRIM_1P0515 AT44
VCCPRIM_3P31
C4859
C C
2
W22 VCCDUSB_1P051 I
BE48
1UF_6.3V_2
W23 VCCDSW_3P31 A
1
VCCDUSB_1P052 BE49
1
I
P1V05A
VCCDSW_3P32 P3V3DS
1UF_6.3V_2
A
C4860
C4891
BG45 BB14
C4816
2
VCCDSW_1P051 VCCHDA
0.1UF_16V_2
BG46 VCCDSW_1P052 I
AG19
0.1UF_16V_2
1UF_6.3V_2
VCCPRIM_1P83 A
1
1
I W31 AG20 PCH_VCCPRIM_1P8_R
1UF_6.3V_2
A VCCPRIM_MPHY_1P05 VCCPRIM_1P84
2
C4858
AN15 VCCHDA
2
2
VCCPRIM_1P85 I
C4825
C4824
D1
1UF_6.3V_2
VCCPRIM_1P0521 AR15 A
1
E1 VCCPRIM_1P86
1 AI R4920 2
VCCPRIM_1P0522 BB11
0_5%_2
VCCPRIM_1P87
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R4918 I
C4827
P1V05A C49 PCH_VCCPRIM_1P8 P1V8A
VCCAMPHYPLL_1P051 AF19 IN
2
2
D49 VCCPRIM_1P81 A
VCCAMPHYPLL_1P052 AF20 0_5%_2_DY
E49 VCCPRIM_1P82
VCCAMPHYPLL_1P053
P1V05A
2
2 R4864 1 VCC_XTAL P2 AG31
A VCCA_XTAL_1P051 VCCPRIM_1P0520
P1V8A_1P 1 I R4924 2
P3 AF31 A
1
I I VCCA_XTAL_1P052 VCCPRIM_1P0519 I
SHORT_0603_25
22UF_6.3V_3
22UF_6.3V_3_DY
22UF_6.3V_3_DY
0_5%_2
1UF_6.3V_2
A A A
1
P1V8A
1UF_6.3V_2
W19 VCCA_SRC_1P051 VCCPRIM_1P241 AK22

C4846
C4845
C4809
C4877
1UF_6.3V_2_DY
2 R4851A 1 VCCAMPHYPLL W20 VCCA_SRC_1P052 VCCPRIM_1P242 AK23
C4830
PCH_VCCPRIM_1P8 R4900
SHORT_0603_25 C1 AJ22 INTERNAL VRM MODE EXTERNAL VRM MODE
C5
VCCAPLL_1P054 VCCDPHY_1P241
C2 AJ23 0_5%_2_DY I
2
2
1UF_6.3V_2
VCCAPLL_1P055 VCCDPHY_1P242 A
22UF_6.3V_3_DY
22UF_6.3V_3_DY
1
BG5 R4918 INSTALL NON-INSTALL
10UF_6.3V_2
1
2
I I V19 VCCDPHY_1P243
1UF_6.3V_2
A A VCCA_BCLK_1P05
P1V05A R4924 NON-INSTALL INSTALL
C4857
C4856
C4874
C4873
B B1 VCCAPLL_1P051 VCCMPHY_SENSE K47 B

R4920 INSTALL INSTALL
C4
B2 VCCAPLL_1P052 VSSMPHY_SENSE K46
0.1UF_16V_2
B3 VCCAPLL_1P053 C4835 INSTALL 4.7UF INSTALL 1UF
2
P1V05A 8 OF 13
2
2
C3
I
1UF_6.3V_2
1
I
P1V05A
10UF_6.3V_2_DY
A A
2
C4844
C4843
2
VCCPRIM_1P2
P1V05A VCCDPHY_1P243
4.7UF_6.3V_3
4.7UF_6.3V_3
I I I I
0.1UF_16V_2
1UF_6.3V_2
1UF_6.3V_2
A A A A
1
I
1UF_6.3V_2
A
10UF_6.3V_2
1
P1V05A
C10
I
A
P1V05A
C6
C7
C8
C9
C4848
C4847
100_5%_2_DY
I
2
I
1UF_6.3V_2
A
1
P1V05A A
2
C4850
R4872
A I A
1UF_6.3V_2
A
1
0.1UF_16V_2
1
C4892
2
C4849
VCCMPHY_SENSE_L R4874 1 A 2 SHORT_0402_15

IN VCCMPHY_SENSE
VSSMPHY_SENSE_L R4875 1 A 2 SHORT_0402_15
IN VSSMPHY_SENSE
2
100_5%_2_DY
R4870
INVENTEC
TITLE
PCH-CORE,VCCGPIO,MPHY,USB
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3
SHEET
CS
41 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
D
P3V3AL
TP16
1
0_5%_2
P3V3AL_RTC_BAT_BOT P3V3AL_RTC_BAT I
R4751
I
A A
CN4700 I D4700
D4711 A
NC
2
3 1 2 R4769 1 P3V3AL_RTC_BAT_R 1 2 VRP3V3A_RTC
47K_5%_2_DY
G 1 A1 A2
4 G 2 2 1K_5%_2
C
DIODE-BAT54-TAP-PHP_DY
R4752
ACES_50224_0020N_001_2P BAT54C_30V_0_6A
3
6012B1052801 A I
R4832
1 2
P3V3_RTC
0_5%_2 C4712
1 I 2
A
C C
1UF_6.3V_2
I
R4762
2 1A SRTC_RST# OUT 39 42
Vinafix.com
1
I
27K_1%_2
1
27K_1%_2 I
A
1UF_6.3V_2
A
R4764
C4713
Vinafix.com
2
OUT RTC_RST# 39 42
0_5%_3_DY
1
I
1UF_6.3V_2
A
C4714
R4795
2
NOTE: COIN BATTERY DISCHARGE TOOL
B B
R7031
100K_5%_2
1 2
LPC & ESPI TABLE
LPC MODE ESPI MODE
R4710 INSTAL UNINSTAL Q300

1 S1
G1 2 EC_RTC_RESET IN 42 51
R4709 UNINSTAL INSTAL SRTC_RST# 6
42 39 OUT D1
42 39 OUT RTC_RST# 3 D2
G2 5 EC_RTC_RESET IN 42 51
4
S2
1
2N7002KDW
R7032
100K_5%_2
2
4/27 MODIFY
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 42 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
I
I A
A
U4710
U4710
1 A2 VSS_1 VSS_73 AL12 BG3 VSS_145 VSS_196 M24
D TP4711 A28 VSS_2 VSS_74 AL17 BG33 VSS_146 VSS_197 M32
A3 VSS_3 VSS_75 AL21 BG37 VSS_147 VSS_198 M34 D
A33 VSS_4 VSS_76 AL24 BG4 VSS_148 VSS_199 M49
A37 VSS_5 VSS_77 AL26 1 BG48 VSS_149 VSS_200 M5
A4 AL29 TP4709 C12 N12
VSS_6 VSS_78 VSS_150 VSS_201
A45 VSS_7 VSS_79 AL33 C25 VSS_151 VSS_202 N16
A46 VSS_8 VSS_80 AL38 C30 VSS_152 VSS_203 N34
A47 VSS_9 VSS_81 AM1 C4 VSS_153 VSS_204 N35
1 A48 VSS_10 VSS_82 AM18 C48 VSS_154 VSS_205 N37
TP4710 A5 AM32 C5 N38
VSS_11 VSS_83 VSS_155 VSS_206
A8 VSS_12 VSS_84 AM49 D12 VSS_156 VSS_207 P26
AA19 VSS_13 VSS_85 AN12 D16 VSS_157 VSS_208 P29
AA27 VSS_16 VSS_88 AN38 D33 VSS_160 VSS_211 R12
AA28 VSS_17 VSS_89 AP4 D8 VSS_161 VSS_212 R16
AA30 VSS_18 VSS_90 AP46 E10 VSS_162 VSS_213 R26
AA31 VSS_19 VSS_91 AR12 E13 VSS_163 VSS_214 R29
AB19 VSS_22 VSS_94 AR38 E19 VSS_166 VSS_217 R38
AB25 VSS_23 VSS_95 AT1 E22 VSS_167 VSS_218 R4
AB31 VSS_24 VSS_96 AT16 E24 VSS_168 VSS_219 T17
C AC12 VSS_25 VSS_97 AT18 E26 VSS_169 VSS_220 T18 C
AC17 VSS_26 VSS_98 AT21 E31 VSS_170 VSS_221 T32
AD1 VSS_31 VSS_103 AT34 E8 VSS_175 VSS_226 U12
AD19 VSS_32 VSS_104 AT45 F41 VSS_176 VSS_227 U15
AD2 VSS_33 VSS_105 AV11 F43 VSS_177 VSS_228 U17
AD22 VSS_34 VSS_106 AV39 F47 VSS_178 VSS_229 U21
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AD25 VSS_35 VSS_107 AW10 G44 VSS_179 VSS_230 U24
AD49 VSS_36 VSS_108 AW4 G6 VSS_180 VSS_231 U33
AE12 VSS_37 VSS_109 AW40 H8 VSS_181 VSS_232 U38
AE33 VSS_38 VSS_110 AW46 J10 VSS_182 VSS_233 V20
AE38 VSS_39 VSS_111 B47 J26 VSS_183 VSS_234 V22
AF22 VSS_42 VSS_114 BA12 J40 VSS_186 VSS_237 W25
AG1 VSS_45 VSS_117 BA5 J48 VSS_189 VSS_240 W30
AG22 VSS_46 VSS_118 BA6 J9 VSS_190 VSS_241 Y10
AG23 VSS_47 VSS_119 BB41 K11 VSS_191 VSS_242 Y12
B AG25 VSS_48 VSS_120 BB43 K39 VSS_192 VSS_243 Y17 B
AG27 VSS_49 VSS_121 BB9 M16 VSS_193 VSS_244 Y33
AG28 VSS_50 VSS_122 BC10 M18 VSS_194 VSS_245 Y38
AG30 VSS_51 VSS_123 BC13 M21 VSS_195 12 OF 13 VSS_246 Y9
AG49 VSS_52 VSS_124 BC15
AH12 VSS_53 VSS_125 BC19
AH17 BC24 INTEL_J44894_BGA_874P
VSS_54 VSS_126
AJ19 VSS_57 VSS_129 BC35
AJ28 VSS_61 VSS_133 BD43
AJ30 VSS_62 VSS_134 BE44
AJ31 VSS_63 VSS_135 BF1 1
AK19 BF2 TP4708
VSS_64 VSS_136
AK20 VSS_65 VSS_137 BF3
AK28 VSS_68 VSS_140 BG17
A AK46 VSS_72 VSS_144 BG28 A
9 OF 13
INVENTEC
TITLE
PCH-GND
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 43 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
STARPPING
DDPB_CTRLDATA:PORT B DETECT 0:DISABLE P3V3S
I
PORTB/PORTC:TBT DDPC_CTRLDATA:PORT C DETECT 1:ENABLE
A
U4710 PORTD:HDMI
DPB_DDCCLK 1 R4806 2
AL13 DPB_DDCCLK 44 IN 2.2K_5%_2_DY
GPP_I5/DDPB_CTRLCLK OUT 44
R4853 I 2
100K_5%_21 A DP_P1_HPD IN 44 44 IN DP_P1_HPD AT6 GPP_I0/DDPB_HPD0/DISP_MISC0 GPP_I6/DDPB_CTRLDATA AR8 DPB_DDCDATA OUT 44 DPB_DDCDATA 1 R4807 2
DP_P2_HPD AN10 AN13 DPC_DDCCLK 44 IN 2.2K_5%_2_DY
44 IN GPP_I1/DDPC_HPD1/DISP_MISC1 GPP_I7/DDPC_CTRLCLK OUT 44
1 R4854 I 2 DP_P2_HPD 1 HDMI_HPDET AP9 AL10 DPC_DDCDATA
100K_5%_2 A IN 44 TP4807 TP24 GPP_I2/DPPD_HPD2/DISP_MISC2 GPP_I8/DDPC_CTRLDATA OUT 44 DPC_DDCCLK 1 R4808 2
TPM_PIRQ# AL15 AL9 HDMI_DDCCLK 44 IN 2.2K_5%_2_DY
63 IN GPP_I3/DPPE_HPD3/DISP_MISC3 GPP_I9/DDPD_CTRLCLK OUT 44
D 1 R4858 I 2 EDP_HPD AR3 HDMI_DDCDATA
100K_5%_2 A IN 44 62 GPP_I10/DDPD_CTRLDATA OUT 44 R4809 2
GPP_F23/DDPF_CTRLDATA AN40 44 IN DPC_DDCDATA 1 2.2K_5%_2_DY D
R4859 I 2 PCH_DGPU_PWR_EN# GPP_F22/DDPF_CTRLCLK AT49 R4935 2
1
100K_5%_2 44 44 HDMI_DDCCLK 1 2.2K_5%_2_DY
A IN IN
AP41 GPP_F14 38 R4919 2
62 44 IN EDP_HPD AN6 GPP_I4/EDP_HPD/DISP_MISC4
GPP_F14/EXT_PWR_GATE#/PS_ON# OUT 44 IN 1
HDMI_DDCDATA 2.2K_5%_2_DY
DGPU_PWR_EN 73 91 93 105 M45 FGC6_FB_EN 89 105
OUT GPP_K23/IMGCLKOUT1 OUT
3
GPP_K22/IMGCLKOUT0 L48
Q4 T45 EVENT_PCH#
GPP_K21 IN 44
I
D
T46 GC6_FB_EN_PCH1 44
44 IN PCH_DGPU_PWR_EN# 1 G A
GPP_K20
AJ47
OUT
5 OF 13 GPP_H23/TIME_SYNC0
S
L2N7002WT1G
P3V3S 2
R4822 1 2 10K_5%_2 EVENT_PCH# OUT 44

R4922 R4921
105 89 73 IN GC6_FB_EN_PCH 1 2GC6_FB_EN_PCH1
OUT 44 89 73 IN GPU_EVENT_PCH# 1 2 EVENT_PCH# OUT 44
C R4815 1 210K_5%_2_DY PCH_DGPU_PWR_EN#
OUT 44 C
0_5%_2 0_5%_2
P3V3A
Vinafix.com
I
A P1V8A
U4710
1 R4826 2 GPP_B22 BA26 GPP_B22/GSPI1_MOSI
GPP_D9/ISH_SPI_CS#/GSPI2_CS0# BA20
1K_5%_2_DY 44 PCH_DGPU_PWR_EN# BD30 GPP_B21/GSPI1_MISO
P3V3A OUT AU26 GPP_B20/GSPI1_CLK GPP_D10/ISH_SPI_CLK/GSPI2_CLK BB20
44 PCH_HOLD_RST#
OUT AW26 GPP_B19/GSPI1_CS0# GPP_D11/ISH_SPI_MISO/GP_BSSB_CLK/GSPI2_MISO BB16
51 DGPU_PWROK
IN GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI AN18 R4824
1 R4802 2 BE30 HPGP_W_DISABLE#
1 I A
2
GPP_B18/GSPI0_MOSI 57 44 OUT
10K_5%_2_DY BD29 GPP_B17/GSPI0_MISO GPP_D16/ISH_UART0_CTS#/CNV_WCEN BF14
BF29 AR18 HPGP_W_DISABLE# 10K_5%_2
GPP_B16/GSPI0_CLK GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/CNV_WFEN OUT 44 57
44 IN ALERT_PCH# BB26 GPP_B15/GSPI0_CS0# GPP_D14/ISH_UART0_TXD/I2C2_SCL BF17
R4820 1 2 10K_5%_2 ALERT_PCH# OUT 44 GPP_D13/ISH_UART0_RXD/I2C2_SDA BE17
B TP4800 TP24 1 UART0_TXD BB24 GPP_C9/UART0_TXD B
R4803 1 2 10K_5%_2_DY PCH_HOLD_RST#
OUT 44 1 UART0_RXD BE23
TP4801 TP24 GPP_C8/UART0_RXD
TP4802 TP24 1 AP24 GPP_C11/UART0_CTS# P3V3S
TP4803 TP24 1 BA24 GPP_C10/UART0_RTS#
R4818
R4882 1 2 10K_5%_2 RUNSCI# 44 BD21 GPP_C15/UART1_CTS#/ISH_UART1_CTS# AG45 GPP_H20 1 I A 2 10K_5%_2
OUT AW24 GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_H20/ISH_I2C0_SCL
AH46
TOUCH_INT# GPP_H19/ISH_I2C0_SDA GPP_H19 1 2
R4819 1 2 10K_5%_2
OUT 44 62 TOUCH_INT# AP21 GPP_C13/UART1_TXD/ISH_UART1_TXD
62 44 OUT R4811 I A 10K_5%_2
R149 1 2 100K_5%_2 TOUCH_PWR_EN 44 62 62 44 TOUCH_PWR_EN AU24 GPP_C12/UART1_RXD/ISH_UART1_RXD AH47
OUT OUT GPP_H22/ISH_I2C1_SCL
AH48
GPP_H21/ISH_I2C1_SDA
44 IN RUNSCI# AV21 GPP_C23/UART2_CTS#
AW21 GPP_C22/UART2_RTS#
P3V3A BE20 GPP_C21/UART2_TXD
BD20 GPP_C20/UART2_RXD AV34 BRD_ID3 44
GPP_A23/ISH_GP5
AW32
OUT
GPP_A22/ISH_GP4 BRD_ID2 OUT 44
53 44 PCH_I2C1_CLK BE21 BA33 BRD_ID1 44
R4810 BI BF21
GPP_C19/I2C1_SCL GPP_A21/ISH_GP3
BE34
OUT
53 44 BI PCH_I2C1_DATA GPP_C18/I2C1_SDA GPP_A20/ISH_GP2 BRD_ID0 OUT 44
1 2 2.2K_5%_2 PCH_I2C1_CLK 44 53
IN 62 44 IN PCH_I2C_CLK BC22 GPP_C17/I2C0_SCL GPP_A19/ISH_GP1 BD34 DP_MA_HPD# OUT 73 93 P3V3S
R4812 PCH_I2C_DATA BF23 BF35 HDMI_MB_HPD#
1 22.2K_5%_2 PCH_I2C1_DATA 62 44 IN GPP_C16/I2C0_SDA GPP_A18/ISH_GP0 OUT 73 95
IN 44 53 BD38 TOUCH_RST#
BE15 GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7 OUT 62
R4825 GPP_D4/ISH_I2C2_SDA/I2C3_SDA/SBK4_BK4 R4831
1 22.2K_5%_2 PCH_I2C_CLK 44 62 BE14 2 1
IN GPP_D23/ISH_I2C2_SCL/I2C3_SCL
11 OF 13
R4827
1 22.2K_5%_2 PCH_I2C_DATA 44 62 100K_5%_2_DY
IN
INTEL_J44894_BGA_874P 44 IN BRD_ID3
A A
R4836
2 1
P3V3S
P3V3S P3V3S
100K_5%_2
R4842
2 1 R4839 R4837
2 1 2 1
100K_5%_2_DY
BRD_ID0 100K_5%_2_DY 100K_5%_2_DY
44 IN
INVENTEC
44 IN BRD_ID1 44 IN BRD_ID2
R4823 R4843
IRMT_HOLD_RST# 1 2 PCH_HOLD_RST# 2 1 R4841 R4838
74 73 IN OUT 44 2 1 2 1
0_5%_2 100K_5%_2 TITLE

100K_5%_2 100K_5%_2
PCH-GPP
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 44 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
D
I
A
U4710
BE33 GPP_A16/CLKOUT_48
C\L\K\O\U\T\_\I\T\P\X\D\P\ Y3
30 OUT CLK_CPUNSSC_DP D7 CLKOUT_CPUNSSC_P Y4
CLKOUT_ITPXDP_P
30 OUT CLK_CPUNSSC_DN C6 C\L\K\O\U\T\_\C\P\U\N\S\S\C\
B6 CLK_CPU_PCIBCLK_DN 30
C\L\K\O\U\T\_\C\P\U\P\C\I\B\C\L\K\ OUT
30 OUT CLK_CPU_DP B8 CLKOUT_CPUBCLK_P CLKOUT_CPUPCIBCLK_P A6 CLK_CPU_PCIBCLK_DP OUT 30
30 OUT CLK_CPU_DN C8 C\L\K\O\U\T\_\C\P\U\B\C\L\K\
CLKOUT_PCIE_N0 AJ6
45 OUT XTAL24_OUT U9 XTAL_OUT AJ7
CLKOUT_PCIE_P0
45 IN XTAL24_IN U10 XTAL_IN
I AH9 CLK_PCIE_DGPU_100MHZ_N 73 74
R4892 1 2 A 60.4_1%_2 XCLK_BIASREF T3 XCLK_BIASREF
CLKOUT_PCIE_N1
AH10
OUT
CLKOUT_PCIE_P1 CLK_PCIE_DGPU_100MHZ_P OUT 73 74
P3V3S 45 RTC_X1 BA49
IN RTCX1
CLKOUT_PCIE_N2 AE14 CLK_PCIE_SSD1_DN OUT 58
45 OUT RTC_X2 BA48 RTCX2 AE15
CLKOUT_PCIE_P2 CLK_PCIE_SSD1_DP OUT 58
C C
45 IN CLKREQ0# BF31 GPP_B5/SRCCLKREQ0# AE6
CLKOUT_PCIE_N3 CLK_PCIE_SSD2_DN OUT 59
74 73 IN PEX_CLKREQ# BE31 GPP_B6/SRCCLKREQ1# AE7
CLKOUT_PCIE_P3 CLK_PCIE_SSD2_DP OUT 59
58 IN CLKREQ_SSD1# AR32 GPP_B7/SRCCLKREQ2#
59 IN CLKREQ_SSD2# BB30 GPP_B8/SRCCLKREQ3# AC2
CLKOUT_PCIE_N4
45 IN CLKREQ4# BA30 GPP_B9/SRCCLKREQ4# AC3
CLKOUT_PCIE_P4
45 IN CLKREQ5# AN29 GPP_B10/SRCCLKREQ5#
45 IN CLKREQ6# AE47 GPP_H0/SRCCLKREQ6#
R4755 1 2 10K_1%_2_DY CLKREQ0# OUT 45 CLKOUT_PCIE_N5 AB2
45 IN CLKREQ7# AC48 GPP_H1/SRCCLKREQ7# AB3
CLKOUT_PCIE_P5
45 IN CLKREQ8# AE41 GPP_H2/SRCCLKREQ8#
Vinafix.com
R4714 1 2 10K_1%_2_DY CLKREQ4# OUT 45 45 IN CLKREQ9# AF48 GPP_H3/SRCCLKREQ9# W4
CLKOUT_PCIE_N6
45 IN CLKREQ10# AC41 GPP_H4/SRCCLKREQ10# W3
CLKOUT_PCIE_P6
45 IN CLKREQ11# AC39 GPP_H5/SRCCLKREQ11#
R4715 1 2 10K_1%_2_DY CLKREQ5# OUT 45
45 IN CLKREQ12# AE39 GPP_H6/SRCCLKREQ12# W7
AB48 CLKOUT_PCIE_N7
64 CLKREQ13_LAN#
OUT GPP_H7/SRCCLKREQ13#
CLKOUT_PCIE_P7 W6
R4754 1 2 10K_1%_2_DY CLKREQ6# OUT 45 57 OUT CLKREQ14_WLAN# AC44 GPP_H8/SRCCLKREQ14#
45 IN CLKREQ15# AC43 GPP_H9/SRCCLKREQ15# AC14
CLKOUT_PCIE_N8
R4757 1 2 10K_1%_2_DY CLKREQ7# OUT 45 V2 CLKOUT_PCIE_P8 AC15
CLKOUT_PCIE_N15
V3 CLKOUT_PCIE_P15
CLKOUT_PCIE_N9 U2
R4763 1 2 10K_1%_2_DY CLKREQ8# OUT 45 U3
CLKOUT_PCIE_P9
57 OUT CLK_WLAN_DN T2 CLKOUT_PCIE_N14
57 OUT CLK_WLAN_DP T1 CLKOUT_PCIE_P14
B R4761 1 2 10K_1%_2_DY CLKREQ9# OUT 45 CLKOUT_PCIE_N10 AC9 B
CLKOUT_PCIE_P10 AC11
64 OUT CLK_LAN_DN AA1 CLKOUT_PCIE_N13
R4765 1 2 10K_1%_2_DY CLKREQ10# OUT 45 64 OUT CLK_LAN_DP Y2 CLKOUT_PCIE_P13 AE9
CLKOUT_PCIE_N11
CLKOUT_PCIE_P11 AE11
AC7 CLKOUT_PCIE_N12
R4766 1 2 10K_1%_2_DY CLKREQ11# OUT 45 AC6 CLKOUT_PCIE_P12 R6
7 OF 13 CLKIN_XTAL CLKIN_XTAL IN 57
R4768 1 2 10K_1%_2_DY CLKREQ12# OUT 45

R4773 1 2 10K_1%_2_DY CLKREQ15# OUT 45
I
A I
C4767 A
C4828
A 1 2 RTC_X1 OUT 45 1 R4719 2 I A
XTAL24_IN
45 IN XTAL24_IN_R 1 A 2
1
18PF_50V_2 33_5%_2
1
12PF_50V_2
CSC0201
I
1
2
A
C4738
10M_5%_2
3
2
1M_5%_2
2 R4862
I L4700 I
A A
R4898
X4750
X4751
32.768KHZ_12.5PF I TXC_24MHZ_12PF
I A
2
MCF12102G900-T_DY
A
4
3
C4788 I
4
1
A
1 2 RTC_X2 IN 45 C4826
R4716 2
INVENTEC
1 I
45 1 2
18PF_50V_2 XTAL24_OUT OUT A
33_5%_2 XTAL24_OUT_R
1
15PF_50V_2
CSC0201
C4739
TITLE
PCH-GPP,CLKOUT
2
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 45 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
I
A
U4710
BD4 WR_CLK_DN 57
AW13
CNV_WR_CLKN
BE3
IN
GPP_G0/SD_CMD CNV_WR_CLKP WR_CLK_DP IN 57
BE9 GPP_G1/SD_D0
BF8 BB3 WR_LANE0_DN 57
GPP_G2/SD_D1 CNV_WR_D0N IN
BF9 GPP_G3/SD_D2 CNV_WR_D0P BB4 WR_LANE0_DP IN 57 WLAN
BG8 BA3 WR_LANE1_DN 57
BE8
GPP_G4/SD_D3 CNV_WR_D1N
BA2
IN
GPP_G5/SD_CD# CNV_WR_D1P WR_LANE1_DP IN 57
BD8 GPP_G6/SD_CLK
AV13 BC5 WT_CLK_DN 57
GPP_G7/SD_WP CNV_WT_CLKN
BB6
IN
CNV_WT_CLKP WT_CLK_DP IN 57
D AP3 GPP_I11/M2_SKT2_CFG0
AP2 BE6 WT_LANE0_DN 57 D
AN4
GPP_I12/M2_SKT2_CFG1 CNV_WT_D0N
BD7
IN
GPP_I13/M2_SKT2_CFG2 CNV_WT_D0P WT_LANE0_DP IN 57
AM7 BG6 WT_LANE1_DN 57
GPP_I14/M2_SKT2_CFG3 CNV_WT_D1N
BF6
IN
CNV_WT_D1P WT_LANE1_DP IN 57
CNV_PA_BLANKING AV6 BA1 WP_RCOMP 1 I R4600 2
57 OUT GPP_J0/CNV_PA_BLANKING CNV_WT_RCOMP A
22 OUT CPU_C10_PWR_GATE# AY3 GPP_J1/CPU_VCCIO_PWR_GATE# 150_1%_2
AR13 GPP_J11/A4WP_PRESENT PCIE_RCOMPN B12 PCIE_RCOMPN 2 AI R4608 1
AV7 GPP_J10 PCIE_RCOMPP A13 PCIE_RCOMPP 100_1%_2
AW3 BE5 I
GPP_J_2 SD_RCOMP_1P8 SD3_1P8_RCOMP R4605 1 A 2 200_1%_2
AT10 BE4 I
GPP_J_3 SD_RCOMP_3P3 SD3_3P3_RCOMP R4606 1 A 2 200_1%_2
57 46 IN CNV_BRI_DT AV4 GPP_J_4_CNV_BRI_DT_UART0_RTSB GPPJ_RCOMP_1P81 BD1
CNV_BRI_RSP AY2 STRAP BE1
57 46 IN GPP_J5/CNV_BRI_RSP/UART0_RXD GPPJ_RCOMP_1P82
I
57 46 IN CNV_RGI_DT BA4 GPP_J6/CNV_RGI_DT/UART0_TXD GPPJ_RCOMP_1P83 BE2 GPPJ_RCOMP R4607 1 A 2 200_1%_2
CNV_RGI_RSP AV3 STRAP
57 46 IN GPP_J7/CNV_RGI_RSP/UART0_CTS#
57 IN CNV_UART_RXD AW2 GPP_J8/CNV_MFUART2_RXD RSVD2 Y35
57 46 IN CNV_UART_TXD AU9 GPP_J9/CNV_MFUART2_TXD RSVD3 Y36
RSVD1 BC1 RSVD1 1 P1V8A

AL35 TP1 1 TP4600 TP24
13 OF 13 TP
TP4601 TP24
57 46 IN CNV_BRI_DT R4724 1 2 10K_5%_2

INTEL_J44894_BGA_874P CNV_RGI_DT 1 2
57 46 IN R4731 20K_5%_2
C C
57 46 IN CNV_RGI_RSP R4732 1 2 20K_5%_2
57 46 IN CNV_BRI_RSP R4725 1 2 20K_5%_2
M.2 CNVI STRAP XTAG_SELECT_1

HIGH => 24MHZ
Vinafix.com
HIGH => DISABLE
LOW => ENABLE LOW => 38.4MHZ
R4772
39 IN CNV_CLKREQ 1 2 MODEM_CLKREQ_R OUT 57
SHORT_0402_5 57 46 IN CNV_RGI_DT 57 46 IN CNV_BRI_DT
10K_5%_2_DY
10K_5%_2_DY
1
1
R4604
R4603
R4777
2
CNV_RF_RESET# 1 2 CNV_RF_RESET#_R
2
39 IN OUT 57
B SHORT_0402_5 B
1
75K_1%_2
R4748
CNVI RGI_DT PIN GETS THE PULL-DOWN RESISTOR (1K OHM) FROM THE INTERNAL CRF MODULE
2
P1V8A
VCCSPI HARD STRAP
10K_5%_2_DY
HIGH => 1.8V
1
LOW => 3.3V
R4601
2
57 46 IN CNV_UART_TXD
100K_5%_2
2
R4602
A A
1
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 46 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CN4100 P1V2
CN4100
6026B0375701-001
6026B0375701-001
10UF_6.3V_3
10UF_6.3V_3
10UF_6.3V_3
10UF_6.3V_3
10UF_6.3V_3
10UF_6.3V_3
10UF_6.3V_3
10UF_6.3V_3
I I I I I I I I
28 IN M_A_A_0 144 A0 DQ_0 8 M_A_DQ<5>
BI 28 A A A A A A A A
330UF_2.5V
111 1
1
VDD VSS
28 IN M_A_A_1 133 A1 DQ_1 7 M_A_DQ<1> BI 28 112 VDD VSS 2
C4115
C4114
C4113
C4109
C4108
C4107
C4106
28 IN M_A_A_2 132 A2 DQ_2 20 M_A_DQ<7>
BI 28
+
117 5
C35
C37
VDD VSS
A
28 IN M_A_A_3 131 A3 DQ_3 21 M_A_DQ<6>
BI 28 118 VDD VSS 6
28 IN M_A_A_4 128 A4 DQ_4 4 M_A_DQ<0> BI 28 123 9
I
VDD VSS
28 IN M_A_A_5 126 A5 DQ_5 3 M_A_DQ<4> BI 28 124 10
2
VDD VSS
28 IN M_A_A_6 127 A6 DQ_6 16 M_A_DQ<3>
BI 28 129 VDD VSS 14
28 IN M_A_A_7 122 A7 DQ_7 17 M_A_DQ<2>
28 IN M_A_A_8 125 A8 DQ_8 28 M_A_DQ<8>
28 IN M_A_A_9 121 A9 DQ_9 29 M_A_DQ<13>
BI 28 136 19
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
VDD VSS
M_A_A_10 146 41 M_A_DQ<11>
1
28 IN A10/AP DQ_10 BI 28 I I I I I I I I
141 22
A A A A A A A A VDD VSS
28 IN M_A_A_11 120 A11 DQ_11 42 M_A_DQ<10>
BI 28
C4123
C4121
C4120
C4119
C4118
C4117
C4116
D 28 M_A_A_12 119 24 M_A_DQ<9> 28
142 VDD VSS 23
IN BI
C36
A12 DQ_12
28 M_A_A_13 158 25 M_A_DQ<12> 28
147 VDD VSS 26 D
IN A13 DQ_13 BI 148 VDD VSS 27
28 IN M_A_WE# 151 A14/WE# DQ_14 38 M_A_DQ<14>
M_A_CAS# 156 37 M_A_DQ<15>
2
28 IN A15/CAS# DQ_15 BI 28 154 31
VDD VSS
28 IN M_A_RAS# 152 A16/RAS# DQ_16 50 M_A_DQ<16>
49 M_A_DQ<20> 28
DQ_17 BI P2V5 160 VDD VSS 36
28 IN M_A_BS0 150 BA0 DQ_18 62 M_A_DQ<18>
28 IN M_A_BS1 145 BA1 DQ_19 63 M_A_DQ<23>
BI 28
VSS 40
28 IN M_A_BG0 115 BG0 DQ_20 46 M_A_DQ<17>
BI 28 43
10UF_6.3V_3_DY
VSS
M_A_BG1 113 45 M_A_DQ<21>
1UF_6.3V_2_DY
28 IN BG1 DQ_21 BI 28 257 44
10UF_6.3V_3
I VPP VSS
58 M_A_DQ<19> 28
BI
1UF_6.3V_2
DQ_22 A
259 47
1
I VPP VSS
28 IN M_CLK_DDR0_DP 137 CK0_T DQ_23 59 M_A_DQ<22>
BI 28 A
VSS 48
M_CLK_DDR0_DN 70 M_A_DQ<24>
C4137
C4100
C4134
28 139 28
IN CK0_C DQ_24 BI
C4131
258 VTT VSS 51
28 IN M_CLK_DDR1_DP 138 CK1_T DQ_25 71 M_A_DQ<29>
BI 28
VSS 52
28 IN M_CLK_DDR1_DN 140 CK1_C DQ_26 83 M_A_DQ<31>
BI 28
VSS 56
84 M_A_DQ<26> 28
DQ_27 BI 57
2
VSS
M_CS#0 149 66 M_A_DQ<25>
P3V3S P3V3S P3V3S
28 IN
M_CS#1 157
CS0# DQ_28
67 M_A_DQ<28>
BI 28
48 39 IN DDR4_DRAMRST#_CPU
108 RESET# VSS 60
28 IN
162
CS1# DQ_29
79 M_A_DQ<30>
BI 28
IN PM_EXTTS#0_R 134 EVENT# VSS 61
CS2#/C0/NC DQ_30 BI 28 M_A_ALERT# 116 64
165 80 M_A_DQ<27> 28 OUT ALERT# VSS
BI 28
0_5%_2_DY
0_5%_2_DY
0_5%_2_DY
CS3#/C1/NC DQ_31
28 IN M_A_ACT# 114 ACT# VSS 65
174 M_A_DQ<36> 28
DQ_32 BI P0V6S VSS 68
28 IN M_CKE0 109 CKE0 DQ_33 173 M_A_DQ<33>
BI 28
R4214
R4212
R4210
VSS 69
28 IN M_CKE1 110 CKE1 DQ_34 187 M_A_DQ<38>
BI 28
VSS 72
C 186 M_A_DQ<39> 28 C
DQ_35 BI 255 VDDSPD VSS 73
28 IN M_ODT0 155 ODT0 DQ_36 170 M_A_DQ<32>
BI 28 164 VREFCA VSS 77
M_ODT1 161 169 M_A_DQ<37>
1UF_6.3V_2_DY
28 IN ODT1 DQ_37 BI 28 M_A_PARITY 143 78
10UF_6.3V_3
183 M_A_DQ<34> I 28 IN PARITY VSS
DQ_38 BI 28 A
81
1
1
I I VSS
92 182 M_A_DQ<35> 28
BI
1UF_6.3V_2
1UF_6.3V_2
CB0/NC DQ_39 A A
82
SHORT_0402_15
SHORT_0402_15
SHORT_0402_15
VSS
C4138
C4103
C4102
C4101
195 M_A_DQ<44>
A
R4213
A
R60
A
91 28
CB1/NC DQ_40 BI 85
R4211
VSS
101 194 M_A_DQ<45> 28
CB2/NC DQ_41 BI VSS 86
105 207 M_A_DQ<47> 28
CB3/NC DQ_42 BI 201 VSS VSS 89
88 208 M_A_DQ<46> 28
CB4/NC DQ_43 BI 202 90
2
2
2
VSS VSS
87 191 M_A_DQ<41> 28
CB5/NC DQ_44 BI
Vinafix.com
205 VSS VSS 93
100 190 M_A_DQ<40> 28
104 203 M_A_DQ<43> 28
204 M_A_DQ<42> 28
DQ_47 BI 210 VSS VSS 99
SA0_DIM0 256 SA0 DQ_48 216 M_A_DQ<54>
BI 28 213 VSS VSS 102
SA1_DIM0 260 SA1 DQ_49 215 M_A_DQ<50>
BI 28 P3V3S 214 VSS VSS 103
SA2_DIM0 166 SA2 DQ_50 228 M_A_DQ<51>
BI 28 217 VSS VSS 106
229 M_A_DQ<55> 28
48 39 IN PCH_3S_SMDATA 254 SDA DQ_52 211 M_A_DQ<52>
BI 28 222 VSS VSS 167
48 39 IN PCH_3S_SMCLK 253 SCL DQ_53 212 M_A_DQ<48>
BI 28
I P0V6S_DIMM0_VREF_CA 223 VSS VSS 168
224 M_A_DQ<49>
2.2UF_6.3V_2
0.1UF_16V_2
DQ_54 BI 28 A
226 171
1
VSS VSS
225 M_A_DQ<53> 28
28 BI M_A_DQS0_DP 13 DQS0_T DQ_56 237 M_A_DQ<56>
BI 28
C4105
C4104
230 VSS VSS 175
A
28 BI M_A_DQS0_DN 11 DQS0_C DQ_57 236 M_A_DQ<61>
BI 28
B 28 M_A_DQS1_DP 34 249 M_A_DQ<58> 28
231 VSS VSS 176 B
BI DQS1_T DQ_58 BI 234 180
I
VSS VSS
M_A_DQS1_DN 32 250 M_A_DQ<59>
0.1UF_16V_2_DY
28 BI DQS1_C DQ_59 BI 28 I
235 181
2
A VSS VSS
M_A_DQS2_DP 55 232 M_A_DQ<57>
2.2UF_6.3V_2
28 BI DQS2_T DQ_60 BI 28 238 184
1
VSS VSS
BI 28 239 VSS VSS 185
28 BI M_A_DQS3_DP 76 DQS3_T DQ_62 245 M_A_DQ<62>
BI 28
C4111
243 188
C34
VSS VSS
BI 28 244 VSS VSS 189
28 BI M_A_DQS4_DP 179 DQS4_T
247 VSS VSS 192
28 BI M_A_DQS4_DN 177 DQS4_C DM0#/DBI0# 12
248 193
2
28 M_A_DQS5_DP 200 33 P1V2 VSS VSS
BI DQS5_T DM1#/DBI1#
251 VSS VSS 196
252 VSS VSS 197
28 BI M_A_DQS6_DP 221 DQS6_T DM3#/DBI3# 75
G1 G1
G2
28 M_A_DQS7_DP 242 199 P3V3A P3V3A G2
BI DQS7_T DM5#/DBI5#
97 DQS8_T DM7#/DBI7# 241
95 96 ARGOSY_D4AR0_26010_1P52_260P
DQS8_C DM8#/DBI8#
2
10K_5%_2
R4116 2
10K_5%_2
I
R41
I
A
A
ARGOSY_D4AR0_26010_1P52_260P
1
1
DDR_VTT_PG_CTRL OUT 23
A A
3
I
D
Vinafix.com DDR_PG_CTRL# 1 G A P1V2
10K_5%_2_DY
I
Q2
S A
I L2N7002WT1G
C
I 1 R4201 2 PM_EXTTS#0_R
A
R44
A
Q1
2
DDR_PG_CTRL 1 R42 2 DDR_PG_CTRL_R 240_1%_2

B
30 B
IN MMBT4401
330_5%_2
E
I
INVENTEC
E
A
1 R43 2 TITLE
100K_5%_2
DDR4_SO-DIMM0
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 47 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P1V2
10UF_6.3V_3
10UF_6.3V_3
10UF_6.3V_3
10UF_6.3V_3
10UF_6.3V_3
10UF_6.3V_3
10UF_6.3V_3
10UF_6.3V_3
I I I I I I I I
A A A A A A A A
330UF_2.5V
1
1
C4139
C4156
C4153
C4152
C4149
C4148
C4143
C4142
C4140
+
A
CN4125 CN4125
6026B0363901-001 6026B0363901-001
I
2
2
111 VDD VSS 1
29 IN M_B_A_0 144 A0 DQ_0 8 M_B_DQ<4>
BI 29 112 VDD VSS 2
29 IN M_B_A_1 133 A1 DQ_1 7 M_B_DQ<1>
BI 29 117 VDD VSS 5
29 IN M_B_A_2 132 20 M_B_DQ<7>
BI 29
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
A2 DQ_2
118 6
1
I I I I I I I I VDD VSS
D 29 IN M_B_A_3 131 A3 DQ_3 21 M_B_DQ<3>
BI 29 A A A A A A A A
123 VDD VSS 9
C4157
C4155
C4154
C4151
C4150
C4147
C4146
C4141
29 IN M_B_A_4 128 A4 DQ_4 4 M_B_DQ<5>
BI 29 D
124 VDD VSS 10
29 IN M_B_A_5 126 A5 DQ_5 3 M_B_DQ<0>
29 IN M_B_A_6 127 A6 DQ_6 16 M_B_DQ<2>
29 IN M_B_A_7 122 A7 DQ_7 17 M_B_DQ<6>
BI 29 135 18
2
VDD VSS
29 IN M_B_A_8 125 A8 DQ_8 28 M_B_DQ<9>
29 IN M_B_A_9 121 A9 DQ_9 29 M_B_DQ<10>
29 IN M_B_A_10 146 A10/AP DQ_10 41 M_B_DQ<11>
BI 29 142 23
29 M_B_A_11 120 42 M_B_DQ<13> 29 P2V5 VDD VSS
IN A11 DQ_11 BI 147 VDD VSS 26
29 IN M_B_A_12 119 A12 DQ_12 24 M_B_DQ<8>
29 IN M_B_A_13 158 A13 DQ_13 25 M_B_DQ<14>
M_B_WE# 151 38 M_B_DQ<12>
10UF_6.3V_3_DY
29 IN A14/WE# DQ_14 BI 29 154 31
1UF_6.3V_2_DY
VDD VSS
M_B_CAS# 156 37 M_B_DQ<15>
10UF_6.3V_3
29 IN A15/CAS# DQ_15 BI 29 I
159 35
1UF_6.3V_2
A VDD VSS
M_B_RAS# 152 50 M_B_DQ<22>
1
29 IN A16/RAS# DQ_16 BI 29 I
160 36
A VDD VSS
49 M_B_DQ<17> 29
DQ_17 BI
C4136
C4135
C4133
163 VDD VSS 39
C4132
29 IN M_B_BS0 150 BA0 DQ_18 62 M_B_DQ<19>
BI 29
VSS 40
29 IN M_B_BS1 145 BA1 DQ_19 63 M_B_DQ<21>
BI 29
VSS 43
29 IN M_B_BG0 115 BG0 DQ_20 46 M_B_DQ<16>
BI 29 257 VPP VSS 44
M_B_BG1 113 45 M_B_DQ<18>
2
29 IN BG1 DQ_21 BI 29 259 47
VPP VSS
58 M_B_DQ<23> 29
DQ_22 BI VSS 48
29 IN M_CLK_DDR2_DP137 CK0_T DQ_23 59 M_B_DQ<20>
BI 29 258 VTT VSS 51
29 IN M_CLK_DDR2_DN139 CK0_C DQ_24 70 M_B_DQ<28>
BI 29
VSS 52
29 IN M_CLK_DDR3_DP138 CK1_T DQ_25 71 M_B_DQ<27>
BI 29
VSS 56
29 IN M_CLK_DDR3_DN140 CK1_C DQ_26 83 M_B_DQ<29>
BI 29
C 84 M_B_DQ<26> VSS 57 C
M_CS#2 149
DQ_27
66 M_B_DQ<25>
BI 29 P0V6S 47 39 IN DDR4_DRAMRST#_CPU
108 RESET# VSS 60
P3V3S P3V3S P3V3S
29 IN
M_CS#3 157
CS0# DQ_28
67 M_B_DQ<30>
BI 29
IN PM_EXTTS#1_R 134 EVENT# VSS 61
29 IN CS1# DQ_29 BI 29 M_B_ALERT# 116 64
162 79 M_B_DQ<24> 29 OUT ALERT# VSS
CS2#/C0/NC DQ_30 BI 29 M_B_ACT# 114 65
80 M_B_DQ<31> 29 IN ACT# VSS
SHORT_0402_15
165 29
1UF_6.3V_2_DY
CS3#/C1/NC DQ_31 BI 68
0_5%_2_DY
0_5%_2_DY
1
10UF_6.3V_3
I VSS
174M_B_DQ<39> 29
BI P3V3S
1UF_6.3V_2
1UF_6.3V_2
DQ_32 A
69
1
I I VSS
M_CKE2 173M_B_DQ<38>
R4218
A
29 109 29
IN CKE0 DQ_33 BI A A
R4220
R4216
VSS 72
C4128
C4127
C4126
29 IN M_CKE3 110 CKE1 DQ_34 187M_B_DQ<32>
BI 29
C4125
255 VDDSPD VSS 73
186M_B_DQ<36> 29
DQ_35 BI 164 VREFCA VSS 77
M_ODT2 170M_B_DQ<34>
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29 155 29
IN ODT0 DQ_36 BI M_B_PARITY 143 78
2
M_ODT3 161 169M_B_DQ<35> I 29 IN PARITY VSS
2.2UF_6.3V_2
0.1UF_16V_2
29 IN ODT1 DQ_37 BI 29 A
81
1
2
2
VSS
183M_B_DQ<33> 29
BI
0_5%_2_DY
DQ_38
82
1
VSS
92 182M_B_DQ<37>
SHORT_0402_15
SHORT_0402_15
CB0/NC DQ_39 BI 29
C4130
C4129
A
VSS 85
195M_B_DQ<40>
R4217
A
91 29
CB1/NC DQ_40 BI
R4219
R4219
VSS 86
101 194M_B_DQ<45>
I
CB2/NC DQ_41 BI 29 201 89
VSS VSS
105 207M_B_DQ<42> 29
CB3/NC DQ_42 BI 202 90
2
2
VSS VSS
88 208M_B_DQ<46> 29
CB4/NC DQ_43 BI 205 93
2
VSS VSS
87 191M_B_DQ<41> 29
100 190M_B_DQ<44> 29
104 203M_B_DQ<47> 29
204M_B_DQ<43> 29
SA0_DIM1 256 SA0 DQ_48 216M_B_DQ<54>
BI 29 214 VSS VSS 103
B SA1_DIM1 260 SA1 DQ_49 215M_B_DQ<48>
BI 29 B
217 VSS VSS 106
SA2_DIM1 166 SA2 DQ_50 228M_B_DQ<55>
BI 29 218 VSS VSS 107
229M_B_DQ<49> 29
DQ_51 BI P0V6S_DIMM1_VREF_DQ 222 VSS VSS 167
47 39 IN PCH_3S_SMDATA 254 SDA DQ_52 211M_B_DQ<52>
BI 29 223 VSS VSS 168
47 39 IN PCH_3S_SMCLK 253 SCL DQ_53 212M_B_DQ<51>
BI 29 226 VSS VSS 171
224M_B_DQ<50> 29
225M_B_DQ<53> 29
29 BI M_B_DQS0_DP 13 DQS0_T DQ_56 237M_B_DQ<61>
BI 29 231 VSS VSS 176
M_B_DQS0_DN 11 236M_B_DQ<62>
0.1UF_16V_2
2.2UF_6.3V_2_DY
29 BI DQS0_C DQ_57 BI 29 234 180
1
VSS VSS
BI 29 235 VSS VSS 181
C4145
29 BI M_B_DQS1_DN 32 DQS1_C DQ_59 250M_B_DQ<58>
BI 29
C4144
238 VSS VSS 184
BI 29 I
A 239 VSS VSS 185
BI 29 243 VSS VSS 188
BI 29 244 189
2
VSS VSS
BI 29 247 192
29 M_B_DQS4_DP 179 P1V2 I VSS VSS
BI DQS4_T A
248 VSS VSS 193
29 BI M_B_DQS4_DN 177 DQS4_C DM0#/DBI0# 12
1 R4200 2
P1V2 PM_EXTTS#1_R 251 VSS VSS 196
29 BI M_B_DQS5_DP 200 DQS5_T DM1#/DBI1# 33
240_1%_2 252 VSS VSS 197
G1 G1
G2 G2
97 241 ARGOSY_D4AS0_26001_1P52_260P
DQS8_T DM7#/DBI7#
A 95 DQS8_C DM8#/DBI8# 96 A
ARGOSY_D4AS0_26001_1P52_260P
INVENTEC
TITLE
DDR4,SO-DIMM1
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 48 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE NUMBER:4450~4499
THERM SENSOR
D
D
P3V3S
1
A
0.1UF_16V_2
I
1
A
C4450
C E
3 2
14K_1%_2
Q4450
P3V3S LMBT3904LT1G
R4452
2
6015B0048201
I 1
A TP4450
C4451
10.5K_1%_2
TP24
1 2
R4453
1000PF_50V_2 U4450
1 8 SMB0_CLK_D 50 73 92 95
H_THERMDA
VDD SCL BI
2 7 SMB0_DATA_D 50 73 92 95
D+ SCA
I BI
R4455 I H_THERMDC 3 D- ALERT# 6 R4454 1 2 A THERM_SCI# BI 36
C 23 THERMTRIP# 1 A
2 H_THERM# 4 5 C
OUT T_CRIT# GND
short_0402_5_nsp
6019B1814201
short_0402_15_nsp
NUVOTON_NCT7718W_MSOP_8P
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B B
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 49 of 139
8 7 6 5 4 3 2 1
6 5 4 3 2 1
REFERENCE 300~389(KBC)
F F
E E
R311 P3V3S R325 2.2K_5%_2 P3V3S THERMAL SENSOR

1 2 I
51 OUT SPI_EC_CLK PCH_SPI_CLK
IN 36 50 63 2 1 I A
HDMI
A
Q303
33_5%_2 S1 1 SMB0_CLK_D
2
IN 49 73 92 95
G1
51 OUT SPI_EC_SO 1 R11 2 PCH_SPI_SO

IN 36 50 63
D1
D2
6
3
SMB0_CLK
SMB0_DATA
BI 51 118 DP
33_5%_2 5
BI 51 118
G2
R12 4 SMB0_DATA_D P3V3S
51 OUT SPI_EC_SI 1 2 PCH_SPI_SI
IN 36 50 63 S2 IN 49 73 92 95
33_5%_2
2N7002KDW 2 1 I A
R327
SPI_EC_CS0# 1 R13 2 PCH_SPI_CS0#
51 OUT IN 36 50 2.2K_5%_2
SHORT_0402_5
D D
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P3V3A
0.1UF_16V_2
C C
1
C309
R7 1 2 10K_5%_2
2
P3V3A
U300
PCH_SPI_CS0# 1 8
50 36 IN CS VCC
XU300
R55 PCH_SPI_CS0# 1 8
63 50 36 OUT PCH_SPI_SO 2 DO_IO1 HOLD_IO3 7 1 2 1K_5%_2 50 36 IN PCH_SPI_SO 2
CE# VDD
7 PCH_SPI_SO3
63 50 36 OUT PCH_SPI_SO2 3
SO HOLD#
6 PCH_SPI_CLK
IN 36 50
1 2 R330 3 WP_IO2 CLK 6 PCH_SPI_CLK
IN 36 50 63
50 36 IN 4
WP# SCK
5 PCH_SPI_SI
IN 36 50 63
1K_5%_2
VSS SI
IN 36 50 63
4 5 PCH_SPI_SI
GND DI_IO0 IN 36 50 63
ACES_91960_0084L_8P
WINB_W25Q128JVSIQ_SOIC_8P 6026B0150101 P3V3A
R56
6019B1604101 PCH_SPI_SO3 1 2 1K_5%_2
IN 36 50
PCH_SPI_SO2
IN 36 50
B B
A A
INVENTEC
Vinafix.com TITLE
Block Diagram
R390 FOR INTEL DEBUG SIZE CODE DOC.NUMBER REV

CHANGE by XXX DATE 21-OCT-2002 A3 CS 1310xxxxx-0-0 X01
6 5 4 3 2 1
6 5 4 3 2 1
EC P3V3S
1
R25
F Location 300 ~ 389 VCC(1.8V OR 3.3V) VSTBY_FSPI(1.8V OR 3.3V)

18.7K_1%_2
FOR DPTF F
2
IT8987E_CX PIN13 : LPCCLK/GPM4(3) PIN5 : SERIRQ/GPM6(3)
2013EE1B PIN10 : LAD0/GPM0(3)
PIN9 : LAD1/GPM1(3)
PIN105 : FSCK/GPG7
PIN101 : FSCE#/GPG3
LOCAL_SHUTDOWN#
OUT 51
A
P3V3AL
1
PIN8 : LAD2/GPM2(3) PIN102 : FMOSI/GPG4
Ver.05_20120824 PIN7 : LAD3/GPM3(3)
PIN6 : LFRAME#/GPM5(3)
PIN103 : FMISO/GPG5 R26
100K_1%_NTC
C65
CSC0402_DY
51 23 22 IN P3V3A_5A_PWEN 2
100K_5%_2
R314
A
1 I
EC_GPG2 2 R324 1
51 IN I
2
2
10K_5%_2
LID_SW_LCM# R336
62 51 OUT
10K_5%_2_DY
R359
118 51 50 BI SMB0_CLK I A 2 1
2.2K_5%_2
P3V3AL P3V3AL P3V3A R360
P3V3AL SMB0_DATA I A 2 1
I 118 51 50 BI
2
A
2.2K_5%_2
D300
R24 I R361
20mA 1 2
1 R28
NC
A SHORT_0402_15
3 1 L1 I
2 51 9 8 BI EC_SMB1_CLK I A 2 1
1 2 A BLM15AG121SN1D_500mA P3V3AL_EC_VSTBY_PLL 100K_5%_2 I 2.2K_5%_2
R326
A Intel DS3 function support R362
1 2 I 0_5%_2 P3V3AL_EC_AVCC
DIODE-BAT54-TAP-PHP
A
1 R334 2 51 9 8 BI EC_SMB1_DATA I A 2 1
P3V3AL_EC_FSPI 2.2K_5%_2
60110GA0367T EC_RST# 10K_5%_2_DY
IN 51 NI
A
A
P5VDS_EN 2 R348 1
E I
I
A R302 1 2 220_5%_2 I LID_SW#
IN 118
51 23 OUT I
E
A A 100K_5%_2
SB_PWRBTN#
0.1uF_16V_2
0.1uF_16V_2
0.1uF_16V_2
0.1uF_16V_2
0.1uF_16V_2
0.1uF_16V_2
0.1uF_16V_2
1
1
1
1
R350 1 2 100_5%_2
1 R321 2 2
C63
1 1 2
I
A
USBPWR_EN
OUT 39
R352 100_5%_2 I OUT 60 64
C310
C316
A
DPWROK
83 SB_PWRBTN#_EC
OUT
C308
C307
C306
C313
39
SBPWR_EN_EC
100K_5%_2
C62
0.1uF_16V_2
LID_SW#_R
LCM_BKLTEN
AMP_EN
IN 38 51 62
62 51 38 OUT LCM_BKLTEN
OUT 54
2
GPU_OVERT_EC#
2
R312
2
1 I 2 TOUCHPAD_I2C_INT#
OUT 73 89
A
I I I I I I I
A
P5VDS_EN
IN 53
A A A A A A A 0_5%_2 OUT 23 51 R349 100K_5%_2
P3V3A LID_SW_LCM#
I
A
SYS_PWROK
OUT 51 62
R354 2 OUT 39
1
I I
Platform Intel AMD 1 2mA P3V3S_EC_VCC
I
A A
114
121
106
127
P3V3S
11
19
26
50
92
74
84
82
20
99
98
97
96
93
SHORT_0603_25 C304 1 R3012
3
R319,R318 10KΩ NA 2 1
100K_5%_2
I
A
R319 1 2 10K_5%_2 I
EC_SMI# 0.1uF_16V_2
A IN 40 51
1 2 10K_5%_2 I
EC_SCI# LPC_AD<0> 10 110 SMB0_CLK EC_PECI
EGCLK/GPE3
EGCS#/GPE2
L80HLAT/BAO/GPE0
L80LLAT/GPE7
GPH7
ID6/GPH6
ID5/GPH5
ID4/GPH4
ID3/GPH3
CLKRUN#/ID0/GPH0
VCC
VSTBY
VSTBY
VSTBY
VSTBY
VSTBY
AVCC
R318
EGAD/GPE1
VSTBY_FSPI
IN BI BI
VSTBY(PLL)
A 38 51 51 40 LAD0/GPM0(3) SMCLK0/GPB3 50 51 118
LPC_AD<1> 9 111 SMB0_DATA
BUF_PLT_RST# 51 40 BI LAD1/GPM1(3) SMDAT0/GPB4
BI 50 51 118 NI
1
1 R347 2 LPC_AD<2> 8 SM BUS 115 EC_SMB1_CLK A
R317 1 2 10K_5%_2 I
A A20GATE
IN 51
58 57
64
51
63
36
59
IN I
A
51 40 BI LPC_AD<3> 7
LAD2/GPM2(3) SMCLK1/GPC1
116 EC_SMB1_DATA
BI 8 9 51
C314
SHORT_0402_15 51 40 BI 22
LAD3/GPM3(3) SMDAT1/GPC2
117 R300
PCH_PECI
BI 8 9 51
R331 EC_PECI 1 2 47pF_50V_2_DY
LPCRST#/GPD2 PECI/SMCLK2/GPF6(3)
IN 30 38
C314
2
43_5%_2 I
CLK_LPC_EC 1 2 13 118 SLP_SUS#
40 IN NI
A
I
A
LPCCLK/GPM4(3) SMDAT2/PECIRQT#/GPF7(3) A IN 39
C315
SHORT_0402_15 51 40 IN LPC_FRAME# 6 LFRAME#/GPM5(3) For Intel platform
2 1
17 LPCPD#/GPE6
R345 12PF_50V_2_DY A20GATE 126 PS/2

73
105 D IN ALL_POWER_GOOD1 2 DGPU_PWROK
OUT 44 51
51 OUT SERIRQ 5
GA20/GPB5(3)
85 CHARGE_USBPWR_EN D
40 BI SERIRQ/GPM6(3)
LPC
PS2CLK0/CEC/TMB0/GPF0
OUT 61
0_5%_2
Platform Intel AMD 51 40 OUT EC_SMI# 15 ECSMI#/GPD4(3) PS2DAT0/TMB1/GPF1 86 KEYBOARD_ID
IN 51 P3V3A
EC_SCI# 23 89 TP_CLK
51 38 OUT ECSCI#/GPD3
GPIO
PS2CLK2/GPF4
BI 53
R315 330Ω 0Ω 51 OUT EC_RST# 14 WRST# PS2DAT2/GPF5 90 TP_DATA
BI 53
KB_RST# 4 R304 1 2 10K_5%_2
40 OUT CHG_LED 16
KBRST#/GPB6(3)
1 2
I
A
U1
64 OUT PWUREQ#/BBO/SMCLK2ALT/GPC7(3) R306 10K_5%_2 I
R315 A A
51 OUT RSMRST_EC 2 1 I
R342
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A 24
2 1 PWR_LED
1
330_5%_2 I PWM0/GPA0
OUT 64
10K_5%_2 PWM1/GPA1 25 P3V3A_5A_PWEN OUT 22 23 51
I ITE_IT8987E_CX_LQFP_128P_HP 28 FAN2_PWM
A
EC_RTC_RESET113
PWM2/GPA2
29 AC_LED
OUT 24
P3V3AL
R316 42 OUT CRX0/GPC0 PWM3/GPA3
OUT 64
RESUME_PWEN 123 CIR 30 FAN1_PWM R392
10K_5%_2 23 22 OUT CTX0/TMA0/GPB2(3) PWM4/GPA4
31 TOUCH_PAD_DISABLE
OUT 24 2 I
A 1
2
P3V3S PWM5/GPA5
OUT 53
10K_5%_2
DGPU_PWROK 80
6019B1650401 PWM R341 1 2 10K_5%_2 I
A 51 IN KEYBOARD_ID 2
R393
NI
A 1
51 44 IN SLP_S3# 119
DAC4/DCD0#/GPJ4(3)
47 FAN1_TACH 10K_5%_2_DY
39 OUT TYPEC_3A 33
DSR0#/GPG6 TACH0A/GPD6(3)
48 ALL_PWGD_INTO_EC
IN 24
60 OUT GINT/CTS0#/GPD5 TACH1A/TMA1/GPD7(3)
IN 23
1
TYPEC_1A5 88 KEYBOARD_ID RGB BL

60 OUT PS2DAT1/RTS0#/GPF3
2.2K_5%_2
2.2K_5%_2
ME_FLASH_EN 81 120 ALWAYS_PW_EN R392 MOUNT OPEN

39 OUT DAC5/RIG0#/GPJ5(3) TMRI0/GPC4(3)
OUT 23
R329
R328
SUSWARN# 87 124 ALL_PWGD_IN

39 OUT WOL_PWEN 109
PS2CLK1/DTR0#/GPF2 TMRI1/GPC6(3)
OUT 23
R393 OPEN MOUNT
64 OUT TXD/SOUT0/GPB1 C300 1 2
EC_CPU_PROCHOT# 108 noise cap NI
51 OUT RXD/SIN0/GPB0 A
2
0.1uF_16V_2_DY
I A
I A
71 107 R333 I
R351 BATT_IN# 1 2 EC_PWRBTN#
1 2
9 IN I_ADP_R 72
ADC5/DCD1#/GPI5(3)
UART port
PWRSW/GPE4
18
100_5%_2 A IN 52
HW_I_ADC 3V3DS_PG
8 IN I SHORT_0402_15
A
GPU_ID 73
ADC6/DSR1#/GPI6(3)
WAKE UP
RI1#/GPD0(3)
21
OUT 12 23
R303 SLP_S4#
C EC_SMBDATA0 1 2 GPU_THM_DAT C351
51 IN ACPRES 35
ADC7/CTS1#/GPI7(3) RI2#/GPD1
CORE_PWEN
IN 39
C
89 73 BI BI 51 CSC0402_DY 9 8 IN RTS1#/GPE5
OUT 109
22 23
1 2
PCSPKR_EC_3 34
NI
A
54 OUT EC_ACPRESENT 122
PWM7/RIG1#/GPA7
112 2 R320 1
0_5%_2 39 OUT DTR1#/SBUSY/GPG1/ID7 RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7
95 I
GPU_THM_DAT
R305
51 BI GPU_THM_CLK 94
CTX1/SOUT1/GPH2/SMDAT3/ID2 10K_5%_2 I
A
A
EC_SMBCLK0 1 2 GPU_THM_CLK 51 BI CRX1/SIN1/SMCLK3/GPH1/ID1 C301 C321

89 73 BI BI 51 2 1 2 1
C312 SPI_EC_CLK 105
0_5%_2 2 NI
A 1 50 BI SPI_EC_CS0# 101
FSCK/GPG7
0.1uF_16V_2_DY NI
50 BI FSCE#/GPG3 noise cap A 100PF_50V_2
P3V3S SPI_EC_SI 102 EXTERNAL SERIAL FLASH
NI
A
220pF_50V_2_DY 50 BI SPI_EC_SO 103
FMOSI/GPG4
66 LOCAL_SHUTDOWN#
50 BI FMISO/GPG5 ADC0/GPI0(3)
IN 51 R307
CN301 C311 67 1 2 IDCHG
1 1 2 NI
A 1
SCAN_OUT<16> 56
ADC1/GPI1(3)
68 PHASE_ID
IN 8
LPC_AD<0> 2 52 OUT KSO16/SMOSI/GPC3(3) ADC2/GPI2(3)
IN 0_5%_2
51
51 40 BI 2 SCAN_OUT<17> 57 69 MB_SHUTDOWN# 1 R323 2 DGPU_PWRLEVEL
51 40 BI LPC_AD<1> 3 3
220pF_50V_2_DY 52 OUT KB_BLON 32
KSO17/SMISO/GPC5(3) ADC3/GPI3(3)
70 OVRM_EN_EC
OUT 73 89
LPC_AD<2> 4 118 52 OUT PWM6/SSCK/GPA6 ADC4/GPI4(3)
OUT 98 0_5%_2
51 40 BI LPC_AD<3> 5
4
51 40 BI 5 EC_GPG2 100 A/D D/A
64 63 59 58 57 51 36 IN BUF_PLT_RST# 6 6
51 OUT SUSACK# 125
SSCE0#/GPG2
SPI ENABLE P3V3AL
LPC_FRAME# 7 39 OUT SSCE1#/GPG0 R337
51 40 IN 8
7
TACH2/GPJ0(3) 76 EC_GPJ0
OUT 51 118 2 I
A 1
8 SCAN_OUT<0> 36 77 EC_CTL3
CLK_LPC_DEBUG_R 9 G1 52 OUT KSO0/PD0 GPJ1(3)
OUT 61 10K_5%_2
40 IN 10
9 G
G2 52 OUT SCAN_OUT<1> 37 KSO1/PD1 DAC2/TACH0B/GPJ2(3) 78 ISCT_WLANPW_EN#
OUT 57 PHASE_ID 2 R322 I
1
10 G
52 OUT SCAN_OUT<2> 38 KSO2/PD2 DAC3/TACH1B/GPJ3(3) 79 FAN2_TACH
OUT 24
51 IN A
SCAN_OUT<3> 39 10K_5%_2
ACES_50696_0100M_001_10P 52 OUT KSO3/PD3
6012B0430403 SCAN_OUT<4> 40
52 OUT SCAN_OUT<5> 41
KSO4/PD4
KSO5/PD5
KBMX Phase_ID B A C / D
KSO6/PD6
52 OUT KSO7/PD7 R337 10K_short 10K_short 10K_open
SCAN_OUT<8> 44
B 52 OUT SCAN_OUT<9> 45
KSO8/ACK#
R322 10K_open 10K_short 10K_short B
KSO9/BUSY
52 OUT KSO10/PE 3V 1.5V 0V
SCAN_OUT<11> 51 2 EC_CTL1
KSO11/ERR#
CLOCK
GPJ7
128 EC_CTL2
OUT 61
KSO12/SLCT GPJ6
OUT 61
52 OUT KSO13 P3V3AL
KSI3/SLIN#
P3V3S
KSI1/AFD#
KSI0/STB#
KSI2/INIT#
SCAN_OUT<14> 54
52 OUT KSO14
VCORE
SCAN_OUT<15> 55 1 R343 2
AVSS
52 OUT KSO15
KSI4
KSI5
KSI6
KSI7
VSS
VSS
VSS
VSS
VSS
10K_5%_2 I
A
R344
I
EC_GPJ0 2 1
GPU_ID
2 R338 1
118 51 OUT A
51 IN NI 10K_5%_2
58
59
60
62
63
64
65
27
49
104
75
12
61
91
A
I 10K_5%_2_DY
SCAN_IN<0>
52 IN A
2
SCAN_IN<1>
0.1uF_16V_2
52 IN SCAN_IN<2> 2
C303
1
52 IN
A
GPU_ID G2 G1 G0
I
SCAN_IN<3>
C302
52 IN SCAN_IN<4> 0.1uF_16V_2
52 IN R343 10K_short 10K_open 10K_short
SCAN_IN<5>
R346
52 IN R338 10K_open 10K_short 10K_short
1
SCAN_IN<6>
51 IN RSMRST_EC 1 2 I RSMRST#
OUT 23 39
52 IN SCAN_IN<7>
SHORT_0402_15
A 52 IN
TP24
TP24
1
R339 I
TP306
TP307
EC_CPU_PROCHOT# 1 2 CPU_PROCHOT#
51 IN A OUT 8 18 30
75_5%_2
A A
INVENTEC
Vinafix.com TITLE
Block Diagram

6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 200~249(POWER CONN)

REFERENCE 250~299(KB/TP CONN)
EC_PWRBTN# SFI_SFI0402ML120C_LF_SMD_2P_DY
51 OUT
R254 D258
1 2 1 2
P3V3AL 1 2
R255 0_5%_2
1 2
100PF_50V_2
KEYBOARD CONN
1
10K_5%_2
C251
2
ENTERY_6905K_E28N_00R_28P
D SCAN_IN<7..0>
52 51 IN 0 SCAN_IN<0> 1 2 D
28 28 G2
G2 D250 1 2 SFI_SFI0402ML120C_LF_SMD_2P_DY
27 G1
52 51 IN SCAN_IN<0> 27 G1
26 1 SCAN_IN<1> 1
D251 1 2 2
SFI_SFI0402ML120C_LF_SMD_2P_DY
52 51 IN SCAN_IN<1> 26
25
52 51 IN SCAN_IN<2> 25
24 2 SCAN_IN<2> 1
D252 1 2 2
52 51 IN SCAN_IN<3> 24
23
52 51 IN SCAN_IN<4> 23
22 3 SCAN_IN<3> 1
D253 1 2 2
52 51 IN SCAN_IN<5> 22
21
52 51 IN SCAN_IN<6> 21
20 4 SCAN_IN<4> 1
D254 1 2 2
52 51 IN SCAN_IN<7> 20
19
18 5 SCAN_IN<5> 1
D255 1 2 2
17
16 6 SCAN_IN<6> 1
D256 1 2 2
15
14 7 SCAN_IN<7> 1
D257 1 2 2
13
12
11
3/21 CHANGE
10
9
8
7
C 51 SCAN_OUT<2> 6 6 C
OUT 5
4
3
2
1
1
CN250
6012B1002701
NEE TO CHANGE 6012B1002701
Vinafix.com
5/2 REVERSE
P5V0S Q250
PM513BA P5V0S_KBLED
3 2 118
S D OUT
100K_5%_2
2.2UF_6.3V_2
1
1
G
B B
R251
C250
1
R253 C255
2
1 2 1 2
2
100K_5%_2
I
D
CSC0402_DY
Q251
D
118 51 IN KB_BLON G G
PANJIT_2N7002KW_3P
S
S
ACES_50505_00401_001_4P
4 G2
4 G
3 G1
3 G
2
2
1
1
A A
CN251
6012B0317706
KEYBOARD LED CONN INVENTEC

TITLE
Block Diagram
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 52 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
D
C C
P3V3S_TP P3V3S_TP
2
6/8 MODIFY 6/8 MODIFY
R287
P3V3S_TP R288
Vinafix.com
2.2K_5%_2 2.2K_5%_2
Q281
S1 1 TP_I2C_DAT 53
1
BI
2 G1
6 PCH_I2C1_DATA 44
D1 BI
D2 3 PCH_I2C1_CLK 44
P3V3A P3V3S_TP BI
5 G2
4 TP_I2C_CLK 53
S2 BI
2N7002KDW R2891 2 0_5%_2_DY
10K_5%_2_DY
R2901 2 0_5%_2_DY
2
2
10K_5%_2
R282
R285
B B
1
36 PCH_TP_I2C_INT# 1 R280 2
BI
SHORT_0402_5
R286
51 TOUCHPAD_I2C_INT# 1 2 1 2 TP_I2C_INT# 53
BI BI
R281 SHORT_0402_5
0_5%_2
P3V3S_TP
6/8 CHANGE P3V3A I
A
PAD282
1 1 2
2
P3V3S_TP
POWERPAD1X1M
TOUCHPAD CONN (CLICK PAD)
CN280
1 1
51 TP_CLK 2
BI 2
51 TP_DATA 3
BI 3
4 4
A 53 TP_I2C_DAT 5 A
IN 5
53 TP_I2C_CLK 6 G1
BI 6 G
53 TP_I2C_INT# 7 G2
BI 7 G
51 TOUCH_PAD_DISABLE 8
IN 8
ENTERY_6916K_Q08N_08L_8P
1
1
2
6012B0245916
D281
D282
D283
INVENTEC
3
LITEON_L30ESDXVC3_2_DSOT23_3P_DY
LITEON_L30ESDXVC3_2_DSOT23_3P_DY TITLE
LITEON_L30ESDXVC3_2_DSOT23_3P_DY
Block Diagram
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 53 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 500~549(AUDIO CODEC)

P5V0S P5V0S_AUDIO_AVDD
C501
1 2 R500
1 2
10UF_6.3V_3
AGND_AUDIO SHORT_0603_25
2.2UF_6.3V_2
1 R531 2 AGND_AUDIO
1
P1V8S_AUDIO BLM18PG121SN1(6014B0041601_0603)
100K_5%_2
1 C503
C502
1UF_6.3V_2
1 2 P1V8S P1V8S_AUDIO
I
2
C511
10UF_6.3V_3
R515
1 2
1
P3V3S
D HP_R OUT 55 SHORT_0402_5
C513
2
HP_L 55
D
OUT
1UF_6.3V_2
LINE1_REF_L
1
OUT 55
10UF_6.3V_3
2
LINE1_REF_R OUT 55
C532
MIC2_REF 64 P5V0S_AUDIO_AVDD
OUT
AGND_AUDIO P5V0S
1
P5V0S
0.1UF_16V_2
1
36
35
34
33
32
31
30
29
28
27
26
25
4.7UF_10V_3
1
SHORT_0603_25
R513
C504
P5V0S_PVDD
C505
1 2 D501
U500
10UF_6.3V_3_DY
0.1UF_16V_2_DY
VREF
CPVDD
CBN
HP-OUT-R
LINE1-VREFO-R
HP-OUT-L
LINE1-VREFO-L
CPVEE
LDO1-CAP
10UF_6.3V_3
MIC2-VREFO
AVDD1
AVSS1
0.1UF_16V_2
2
1
2
AMC_AZ2015_01H_SOD523_2P_DY
1
C515
C514
C522
C519
37 CBP LINE2-L 24
AGND_AUDIO 38 ANALOG 23
2
2
AVSS2 LINE2-R
2
C512 AGND_AUDIO
C 1 2 39 22 LINE1_L 55 C
LDO2-CAP LINE1-L BI
10UF_6.3V_3 40 AVDD2
DIGITAL LINE1-R 21 LINE1_R
BI 55 P3V3AL
41 20 1 R514 2
PVDD1 NC
EMC R509
SHORT_0603_25
64 SPK_OUT_R_L_P 1 2 SPK_OUT_L_P 42 19 C531 1 2 4.7UF_6.3V_3
C523 OUT SPK-L+ MIC-CAP
AGND_AUDIO
SHORT_0603_25
2 1 R508
64 OUT SPK_OUT_R_L_N 1 2 SPK_OUT_L_N 43 SPK-L- MIC2-R/SLEEVE 18 SLEEVE BI 64
(THERMAL PAD 3X3 VIAS)
SHORT_0603_25
Vinafix.com
0.1UF_16V_2 SPK_OUT_R_R_N 1 R510 2 SPK_OUT_R_N 44 17 RING2
64 OUT SPK-R- MIC2-L/RING2 BI 64
SHORT_0603_25
C524 SPK_OUT_R_R_P 1 R511 2 SPK_OUT_R_P 45 16
2 1 64 OUT SPK-R+ MONO-OUT
SHORT_0603_25
46 15 1 R501 2
PVDD2 SPDIFO/FRONT JD
0.1UF_16V_2
PLACEMENT CLOSE TO CODEC 20K_1%_2_DY AGND_AUDIO
10UF_6.3V_3
C525 47 14
0.1UF_16V_2
PDB MIC2/LINE2 JD
2 1
1
48 13 1 R502 2 HPS IN 64
GPIO0/DMIC-DATA
C521
C520
SPDIF-OUT HP/LINE1 JD
0.1UF_16V_2
GPIO1/DMIC-CLK
54 51 IN AMP_EN 200K_5%_2
49 P3V3S
SDATA-OUT
TML
LDO3-CAP
SDATA-IN
BIT-CLK
DVDD-IO
PCBEEP
RESETB
DC_DET
2
2
1 R504 2
DVDD
SYNC
B AGND_AUDIO B
100K_5%_2
1 R521 2 PCH_SPKR
REA_ALC255_CG_MQFN_48P IN 39
22K_5%_2
C507
R505 6/13 MODIFY 3/20 MODIFIED
P3V3S P3V3S 1 2 1 2 PCSPKR_EC_3 51
IN
10
12
1
11
22K_5%_2 C5061
0.1UF_16V_2 2
1
10UF_6.3V_3
CSC0402_DY
0.1UF_16V_2
10UF_6.3V_3
1
R525 R503
C530
1 2
100K_5%_2
C517
C516
4.7K_5%_2
6/13 MODIFY
2
HDA_RST#
2
IN 39
AMP_EN
2
2
OUT 51 54 HDA_SYNC IN 39
HDA_R_SDIN0 1 R507 2 HDA_SDIN0 IN 39

TIED UNDER OR NEAR CODEC 75_5%_2
HDA_R_BITCLK 1 R506 2 HDA_BCLK
IN 39
PAD500
1 2 SHORT_0402_5
HDA_SDO
1 2 IN 39
POWERPAD1X1M 62 BI DMIC_DATA
R512
62 BI DMIC_CLK 1 2 DMIC_CLK_R
P3V3S
A PAD501
A
Vinafix.com
100_5%_2
1 1 2
2
22PF_50V_2
POWERPAD1X1M
1
10UF_6.3V_3
0.1UF_16V_2
22PF_50V_2
1
1
1
C18
C510
C509
PAD502 C508
1 1 2
2
2
INVENTEC
POWERPAD1X1M
2
RESERVE FOR EMI RESERVE FOR EMI

TITLE
Block Diagram
AGND_AUDIO DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 54 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERCE 600~649(JACK/MIC/SPEAKER)
AUDIO JACKS
D
D
LINE1_REF_L 1 R606 2
54 IN
4.7K_5%_2
C602
54 IN LINE1_L 1 2
4.7UF_6.3V_3
54 IN HP_L R605 1 2 61.9_1%_2 HP_R_L OUT 64
54 IN HP_R R604 1 2 61.9_1%_2 HP_R_R OUT 64
C603
54 IN LINE1_R 1 2
4.7UF_6.3V_3
LINE1_REF_R 1 R607 2
54 IN
4.7K_5%_2
C C
Vinafix.com
B B
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 55 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
D
SATA HDD CABLE CONN on MB

SATA HDD P5V0S 1.15A
Location 1700 ~ 1749 I
PAD1700
1 1 2
2
C C
POWERPAD1X1M
22UF_6.3V_5_DY
22UF_6.3V_5
1
1
0.1uF_16V_2
C1701
C1700
C20
2
CABLE PIN DEFINE FOLLOW ARGAMA
2
CN1700
Vinafix.com
1 1
2 2
3 3
4 4
38 OUT PCIE17_HDD_RX_DP C1702 1 2 0.01uF_50V_2 PCIE17_HDD_RX_C_DP 5 5
38 OUT PCIE17_HDD_RX_DN C1703 1 2 0.01uF_50V_2 PCIE17_HDD_RX_C_DN 6 6
7 7
38 IN PCIE17_HDD_TX_C_DN 8 8
38 IN PCIE17_HDD_TX_C_DP 9 9 G G1
10 10 G G2
ACES_51540_01041_Q01_10P
6012B0541002
B B
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 56 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
M.2 FOR WLAN/BT R1355 2

CN1300
P3V3A_WLAN
1 I 6026B0276201-002
0_5%_2
L1300 1
37 USB_BT_DP 1 4 USB2_M2_BT_DP_L 3
GND1
2 CLOSE TO PIN2,4
BI USB_D+ 3P3VAUX1
USB_BT_DN 2 3 USB2_M2_BT_DN_L 5 4
10UF_6.3V_3
0.01UF_50V_2
37 BI USB_D- 3P3VAUX2
0.1UF_16V_2
7 6
1
GND2 LED1*
MCF12102G900-T_DY
NI CRITICAL CNV_WR_D1N_R 9 8
57 OUT SDIO_CLK PCM_CLK
C1319
C1318
C1310
R1356 2 57 OUT CNV_WR_D1P_R 11 SDIO_CMD PCM_SYNC 10 CNV_RF_RESET#_R OUT 46 57
1 I 13 SDIO_DAT0 PCM_IN 12
0_5%_2 CNV_WR_D0N_R MODEM_CLKREQ_R
57 OUT 15 SDIO_DAT1 PCM_OUT 14
OUT 46 57 I I I
CNV_WR_D0P_R 17 16
2
57 OUT SDIO_DAT2 LED2*
19 SDIO_DAT3 GND3 18
D 57 CNV_WR_CLKN_R 21 20
OUT SDIO_WAKE UART_WAKE
D
57 OUT CNV_WR_CLKP_R 23 SDIO_RESET UART_RX 22 CNV_BRI_RSP_R OUT 57
CS KEY E PS
33 GND4 UART_TX 32 CNV_RGI_DT_R OUT 57

PCIE_WLAN_TX14P C1323 1 2 0.1UF_16V_2 PCIE_WLAN_CTX6P 35 34 CNV_RGI_RSP_R
38 IN PETP0 UART_CTS OUT 57
38 IN PCIE_WLAN_TX14N C1322 1
I I 2 0.1UF_16V_2 PCIE_WLAN_CTX6N 37 PETN0 UART_RTS 36 CNV_BRI_DT_R OUT 57
39 GND5 RSRVD1 38 CLINKRST# R1345 1 I 2 0_5%_2 CL_RST#1 IN 38
P3V3A_WLAN 38 IN PCIE_WLAN_RX14P 41 PERP0 RSRVD2 40 CLINKDAT R1346 1 I 2 0_5%_2 CL_DATA1 BI 38
38 IN PCIE_WLAN_RX14N 43 PERN0 RSRVD3 42 CLINKCLK R1347 1 I 2 0_5%_2 CL_CLK1 IN 38
45 GND6 COEX3 44 CNV_PA_BLANKING_R OUT 57
2
I 45 OUT CLK_WLAN_DP 47 REFCLKP0 COEX2 46 CNV_UART_TXD_R OUT 57

I
4.7K_5%_2
CLK_WLAN_DN CNV_UART_RXD_R
R1360
45 49 48 57
OUT REFCLKN0 COEX1 OUT
51 50 M2_WLAN_SUSCLK
2
GND7 SSCLK OUT 39

10K_5%_2
57 45 OUT CLKREQ14_WLAN# 53 CLKEQ0* PERSTO* 52 BUF_PLT_RST# OUT 36 51 58 59 63 64

R1359
57 OUT WLAN_WAKE# 55 PEWAKE0* RSRVD/W_DISABLE2* 54 M.2_W_DISABLE2# OUT 57

1
57 56 M.2_W_DISABLE1# 57 P3V3A_WLAN
GND8 W_DISABLE1* OUT
C C
1
64 39 PCH_WAKE# 3I 2 WLAN_WAKE# IN 57
CS PS
OUT
B
C E P3V3A
Q1314
LMBT3904LT1G CNV_WT_D1N_R 59 58 WLAN_I2C_DAT 1
57 OUT RESERVED_2ND_PETP1 I2C_DATA R1325
CNV_WT_D1P_R 61 60 WLAN_I2C_CLK 1 TP1300 1 2
57 OUT RESERVED_2ND_PETN1 I2C_CLK
63 62 TP1307
GND9 ALERT I 0_5%_5_DY
1UF_6.3V_2
B
CNV_WT_D0N_R 65 64 WLAN_CLK
1
57 OUT RESERVED_2ND_PERP1 RSRVD4 OUT 57 U1300
Vinafix.com
P3V3A_WLAN 57 OUT CNV_WT_D0P_R 67 RESERVED_2ND_PERN1 RSRVD5 66 I NI I
C1300
4 VBIAS VOUT 8
69 68
18PF_50V_2_DY
GND10 RSRVD6
R1357 VOUT 7
I CNV_WT_CLKN_R 71 70
0.1UF_16V_2
12PF_50V_2
1 2 WLAN_CLKREQ14# OUT 57 OUT RSRVD7 RESERVED
1
1
57 CNV_WT_CLKP_R 73 72 VIN
57 OUT RSRVD8 3P3VAUX3
2
P3V3A_WLAN VIN
C1317
C1316
C1315
10K_5%_2 75 74
2
GND11 3P3VAUX4
CT 6
220PF_50V_2
G1 G1 G2 G2
1
WLAN_CLKREQ14#
1 R1358 2 CLKREQ14_WLAN# OUT
57 IN 45 57 3 5
100K_5%_2
2
ON GND
C1301
10UF_6.3V_3
0.01UF_50V_2
0_5%_2
R1300
9
0.1UF_16V_2
2
TML
1
LOTES_APCI0062_P001A_NGFF_E_KEY_75P
R1338 2
C1314
C1313
C1312
46 OUT WR_CLK_DN 1 I CNV_WR_CLKN_R IN 57
0_5%_2
2
ANPEC_APL3526QBI_TRG_TDFN_8P
R1337 2
1
46 OUT WR_CLK_DP 1 I CNV_WR_CLKP_R IN 57 I I I
B 0_5%_2
B
3
46 CNV_PA_BLANKING 1 I R1361 2 CNV_PA_BLANKING_R 57 Q1300
OUT IN
0_5%_2 I
D
R1362 2
CLOSE TO PIN72,74 1 G A
46 OUT CNV_UART_TXD 1 I CNV_UART_TXD_R IN 57 R1354 2
46 OUT WT_CLK_DN 1 I CNV_WT_CLKN_R IN 57
0_5%_2
S
0_5%_2
L2N7002WT1G
CNV_UART_RXD R1363 2 CNV_UART_RXD_R WT_CLK_DP R1353 2 CNV_WT_CLKP_R
46 OUT 1 I IN 57 46 OUT 1 I IN 57
2
0_5%_2 0_5%_2
46 CNV_BRI_DT 1 I R1364 2 CNV_BRI_DT_R 57 39 SLP_WLAN#
OUT IN IN
0_5%_2
R1301
R1365 2 1 2
46 CNV_RGI_RSP 1 I CNV_RGI_RSP_R 57 P3V3A_WLAN P3V3A_WLAN
OUT IN
0_5%_2
100K_5%_2
R1350 1
100K_5%_2
CNV_RGI_DT R1321 2 CNV_RGI_DT_R
46 OUT 1 I IN 57
51 ISCT_WLANPW_EN#
0_5%_2 IN
1
46 CNV_BRI_RSP 1 I R1320 2 CNV_BRI_RSP_R 57

OUT IN
0_5%_2
G
WR_LANE0_DN R1366 2 CNV_WR_D0N_R HPGP_W_DISABLE# 3 2 M.2_W_DISABLE1#

46 OUT 1 I IN 57 44 IN D S
OUT 57 R1334
0_5%_2 I 1 2 MODEM_CLKREQ_R OUT 46 57
A 46 WR_LANE0_DP 1 I R1324 2 CNV_WR_D0P_R 57
Q1312 71.5K_1%_2 A
OUT IN L2N7002WT1G
0_5%_2 1 R1335 2 CNV_RF_RESET#_R
P3V3A_WLAN P3V3A_WLAN OUT 46 57
WR_LANE1_DN R1328 2 CNV_WR_D1N_R
46 OUT 1 I IN 57 75K_1%_2_DY
0_5%_2
R1351 1
100K_5%_2
WR_LANE1_DP R1329 2 CNV_WR_D1P_R

46 OUT 1 I IN 57
0_5%_2 ST1300 1
1
WT_LANE0_DN R1330 2 CNV_WT_D0N_R

46 IN 1 I OUT 57
L2N7002WT1G
0_5%_2 STANDOFF_3.2_6.0
INVENTEC
G
3.33MM
2
46 WT_LANE0_DP 1 I R1331 2 CNV_WT_D0P_R 57

IN OUT 6052B0407801
0_5%_2 36 IN PCH_W_DISABLE2# 3 D S 2 M.2_W_DISABLE2# OUT 57
WT_LANE1_DN R1367 2 CNV_WT_D1N_R R1342 I
46 IN 1 I OUT 57 1 2 Q1313 TITLE
0_5%_2
10K_5%_2 MODEL,PROJECT,FUNCTION
WT_LANE1_DP R1368 2 CNV_WT_D1P_R
46 IN 1 I OUT 57
45 CLKIN_XTAL 1 I R1352 2 WLAN_CLK 57
Block Diagram
0_5%_2 OUT IN DOC.NUMBER REV
0_5%_2 SIZE CODE 1310xxxxx-0-0 X01
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 57 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P3V3S
I
PAD1901
M.2 FOR SSD 1 1 2

2
1000PF_50V_2
POWERPAD1X1M
10UF_6.3V_2
0.1UF_16V_2
1
1
1
C1933
C1932
C1931
2
2
2
D
D
CN1901
6026B0436901-001
1 GND_1
3 KEY M 2
GND_3 3.3VAUX_2
38 OUT PCIE_SSD_RX9N 5 PERn3 3.3VAUX_4 4
38 OUT PCIE_SSD_RX9P 7 PERp3 NC_6 6
9 GND_9 NC_8 8
38 IN PCIE_SSD_TX9N C1916 1 I 2 0.22UF_6.3V_2 SSD1_TX9N 11 PETn3 DAS/DSS# 10 SSD1_SATA_LED# 1
PCIE_SSD_TX9P TP1901
38 IN C1919 1 I 2 0.22UF_6.3V_2 SSD1_TX9P 13 PETp3 3.3VAUX_12 12
15 GND_15 3.3VAUX_14 14
38 OUT PCIE_SSD_RX10P 19 PERp2 3.3VAUX_18 18
21 GND_21 NC_20 20
38 IN PCIE_SSD_TX10N C1917 1 I 2 0.22UF_6.3V_2 SSD1_TX10N 23 PETn2 NC_22 22
38 IN PCIE_SSD_TX10P C1918 1 I 2 0.22UF_6.3V_2 SSD1_TX10P 25 PETp2 NC_24 24
27 GND_27 NC_26 26
38 OUT PCIE_SSD_RX11N 29 PERn1 NC_28 28
33 GND_33 NC_32 32
C 38 IN PCIE_SSD_TX11N C1920 1 I 2 0.22UF_6.3V_2 SSD1_TX11N 35 PETn1 NC_34 34 C
38 IN PCIE_SSD_TX11P C1921 1 I 2 0.22UF_6.3V_2 SSD1_TX11P 37 PETp1 NC_36 36
39 GND_39 DEVSLP 38 SSD1_DEVSLP IN 58
38 OUT PCIE_SSD_RX12P POLARITY REVERSAL FOR SATA SSD 41 PERn0/SATA-B+ NC_40 40
38 OUT PCIE_SSD_RX12N 43 PERp0/SATA-B- NC_42 42
45 GND_45 NC_44 44
38 IN PCIE_SSD_TX12N C1922 1 I 2 0.22UF_6.3V_2 SSD1_TX12N 47 PETn0/SATA-A- NC_46 46
38 IN PCIE_SSD_TX12P C1923 1 I 2 0.22UF_6.3V_2 SSD1_TX12P 49 PETp0/SATA-A+ NC_48 48
51 GND_51 PERST#/NC_50 50 BUF_PLT_RST# IN 36 51 57 59 63 64
45 IN CLK_PCIE_SSD1_DN 53 REFCLKN CLKREQ#/NC_52 52 SSD_CLKREQ2# OUT 58
Vinafix.com
45 IN CLK_PCIE_SSD1_DP 55 REFCLKP PEWake#/NC_54 54 SSD1_WAKE# 1
57 56 TP1900
GND_57 NC_56
58
P3V3S NC_58
10K_5%_2
CS KEY M PS
R1905
KEY M
KEY M
1
R1906 67 68 M2_SSD1_SUSCLK 39
M2_SSD1_DET# NC_67 SUSCLK IN
38 1 2 69 70
B OUT PEDET 3.3VAUX_70
B
71 GND_71 3.3VAUX_72 72
0_5%_2_DY 73 GND_73 3.3VAUX_74 74
75
3
L2N7002WT1G
GND_75
10UF_6.3V_2
0.1UF_16V_2
Q1900
1
D
G 1
C1913
C1936
GND_G1
GND_G2
S
I 2
2
2
1 ST1902 LOTUS_APCI0107_P001H_75P
STANDOFF_3.2_6.0
G2
G1
3.33MM
6052B0407801
A A
P3V3S
SSD_CLKREQ2# 1 R1901 2 CLKREQ_SSD1#

CLKREQ_SSD1# OUT 58 IN OUT 45 58
R1904 1 2 I A 10K_5%_2 45 58
0_5%_2
40 IN DEVSLP_SSD1 1 R1900 2 SSD1_DEVSLP OUT 58

INVENTEC
0_5%_2 TITLE
Block Diagram
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 58 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NGFF SSD2(PCIE/SATA 2X) Vinafix.com

P3V3S
I
PAD1902
1 1 2
2
1000PF_50V_2
POWERPAD1X1M
10UF_6.3V_2
0.1UF_16V_2
D
1
1
1
D
C1900
C1901
C1902
2
2
CN1900
6026B0436901-001
PCH AUTO SWAP DN/DP WHEN PCIE INTERFACE 1 GND_1
3 KEY M 2
GND_3 3.3VAUX_2
9 GND_9 NC_8 8
37 IN PCIE_SSD_TX21N C1925 1 I 2 0.22UF_6.3V_2 SSD_TX4N 11 PETn3 DAS/DSS# 10 SSD2_SATA_LED# 1
PCIE_SSD_TX21P TP1902
37 IN C1924 1 I 2 0.22UF_6.3V_2 SSD_TX4P 13 PETp3 3.3VAUX_12 12
15 GND_15 3.3VAUX_14 14
37 OUT PCIE_SSD_RX22P 19 PERp2 3.3VAUX_18 18
21 GND_21 NC_20 20
37 IN PCIE_SSD_TX22N C1927 1 I 2 0.22UF_6.3V_2 SSD_TX3N 23 PETn2 NC_22 22
37 IN PCIE_SSD_TX22P C1926 1 I 2 0.22UF_6.3V_2 SSD_TX3P 25 PETp2 NC_24 24
27 GND_27 NC_26 26
37 OUT PCIE_SSD_RX23N 29 PERn1 NC_28 28
C 37 PCIE_SSD_RX23P 31 30 C
OUT PERp1 NC_30
33 GND_33 NC_32 32
37 IN PCIE_SSD_TX23N C1928 1 I 2 0.22UF_6.3V_2 SSD_TX2N 35 PETn1 NC_34 34
37 IN PCIE_SSD_TX23P C1909 1 I 2 0.22UF_6.3V_2 SSD_TX2P 37 PETp1 NC_36 36
39 GND_39 DEVSLP 38
37 OUT PCIE_SSD_RX24N 41 PERn0/SATA-B+ NC_40 40
37 OUT PCIE_SSD_RX24P 43 PERp0/SATA-B- NC_42 42
45 GND_45 NC_44 44
37 IN PCIE_SSD_TX24N C1930 1 I 2 0.22UF_6.3V_2 SSD_TX1N 47 PETn0/SATA-A- NC_46 46
PCIE_SSD_TX24P C1929 1 I 2 0.22UF_6.3V_2 SSD_TX1P
Vinafix.com
37 49 48
IN PETp0/SATA-A+ NC_48
51 GND_51 PERST#/NC_50 50 BUF_PLT_RST# IN 36 51 57 58 63 64
45 IN CLK_PCIE_SSD2_DN 53 REFCLKN CLKREQ#/NC_52 52 SSD_CLKREQ3# OUT 59
45 IN CLK_PCIE_SSD2_DP 55 REFCLKP PEWake#/NC_54 54 SSD2_WAKE# 1
57 56 TP1903
GND_57 NC_56
NC_58 58
CS KEY M PS
KEY M
KEY M
1 ST1901
STANDOFF_3.2_6.0
B 3.33MM B
6052B0407801 67 68 M2_SSD2_SUSCLK 39
NC_67 SUSCLK IN
69 PEDET 3.3VAUX_70 70
71 GND_71 3.3VAUX_72 72
73 GND_73 3.3VAUX_74 74
75 GND_75
10UF_6.3V_2
0.1UF_16V_2
1
1
1 ST1903
STANDOFF_3.2_6.0
C1937
C1908
GND_G1
P3V3S 3.33MM GND_G2
6052B0407801
2
2
LOTUS_APCI0107_P001H_75P
R1903 1 2 I A 10K_5%_2 CLKREQ_SSD2# OUT

G2
45 59
G1
SSD_CLKREQ3# 1 R1902 2 CLKREQ_SSD2#

59 IN OUT 45 59
0_5%_2
A A
M.2 CARD USES; SATA SIGNALING (LOW) OR PCIE SIGNALING (HIGH)
INVENTEC
TITLE
REFERENCE NUMBER:1950~1999
SATA HDD CONN.
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 59 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P3V3A
P5V0DS
TYPE C OVP
4.7K_5%_2_DY
10K_5%_2_DY
2
10K_5%_2
I R2402 2
R2401 2
R2403
U8 CRITICAL
I
P5V0DS
1
NI
TYPEC_3A P3V3DS
1
OUT 51 60
1
P5V0DS
TYPEC_1A5 OUT 51 60
120K_1%_2 1 10
GND NFAULT
I R2410 2 REXT PMODE2 9 2R2400 10K_5%_2_DY
1 PUSB3_PWR2
1 2 3 IN PMODE1 8
60 OUT VBUS_EN 4 VBUS_EN/Attached CC1 7 TYPEC_CC1 OUT 60
D I I
5 6 TYPEC_CC2 60
DIR CC2 OUT U2500 D
10UF_6.3V_3
TP2400
1
1
0.1UF_16V_2
U2502
1 POLARITY 64 51 USBPWR_EN 1 5 6 1
I I IN B VCC IN OUT
100UF_6.3V_DY
C2403
C2402
60 IN VBUS_EN 2 A 60 IN TYPEC_SET 5 SET GND 2 I I I
220PF_50V_2
220PF_50V_2
10UF_25V_5
10UF_25V_5
10UF_25V_5
B B B
3 4 4 3
1
GND Y EN(EN#) FLAG
EP
C2548
C2552
VIA_VP225_DFN_10P NXP_74LVC1G08GW_TSOT353_5P
C2547
C2551
+
C87
C88
2
11
GMT_G518B1TP1U_TSOT23_6P
10K_5%_2
2
I 3.5A
2
1UF_6.3V_2
B
R2411
1
C2549
I1
2
TYPEC_SET 60
OUT
D
C2503
0_5%_3
D
0.22UF_25V_2 G Q5 TYPEC_3A
USB3_TX1P 2 1 USB3_C_TX1P 1 R2514 2 USB3_L_TX1P G
IN 51 60
40 IN I 60
C C
D
40 USB3_TX1N 2 1 USB3_C_TX1N 1 2 USB3_L_TX1N OUT 60
PANJIT_2N7002KW_3P
IN I
S
R2515
OUT
C2502 Q6
D
0_5%_3 G TYPEC_1A5
0.22UF_25V_2
S
G
IN 51 60
C2501 PANJIT_2N7002KW_3P
0_5%_3
S
0.22UF_25V_2
USB3_TX2P 2 1 USB3_C_TX2P 1 R2503 2 USB3_L_TX2P
40 IN I 60
USB3_TX2N 2 1 USB3_C_TX2N 1 2 USB3_L_TX2N OUT
S
40 IN I 60
R2502
OUT
C2504
0_5%_3
Vinafix.com
0.22UF_25V_2 0.33UF_25V_2
0_5%_3
C2500
USB3_RX1N 2 I 1 1 R2512 2 USB3_L_RX1N
2
40 OUT I 60
OUT
2
4/27 MODIFY
8.45K_1%_2
21K_1%_2
21K_1%_2
I
USB3_RX1P 1 2 USB3_L_RX1P
R2649
40 2 1 60
OUT I
R2680
R2681
R2513 0_5%_3
OUT
C2511
I
0.33UF_25V_2 1 R2509 2
1
USB2_CN_1P
1
IN 60 220K_5%_2
I
USB2_CN_1N 1 R2508 2
IN 60
CRITICAL 220K_5%_2
D7503 I
1 Line-1 NC 10
2 Line-2 NC 9
B 3 GND GND 8 B
4 Line-3 NC 7
5 Line-4 NC 6 0.33UF_25V_2
C2510
0_5%_3 PUSB3_PWR2
6011B0172501 USB3_RX2N 2 I 1 1 R2504 2 USB3_L_RX2N
40 OUT I 60
AMAZING_AZ1045_04F_R7G_10P TYPEC_CC2 60
OUT
IN 40 OUT USB3_RX2P 2 I
1 1 I 2 USB3_L_RX2P 60
TYPEC_CC1 60 R2505 0_5%_3
OUT CN2500
IN C2509
I A1 GND GND B12
0.33UF_25V_2 1 R2507 2 USB3_L_TX1P A2 B11 USB3_L_RX1P
60 IN SSTXp1 SSRXp1
IN 60
220K_5%_2 60 IN USB3_L_TX1N A3 B10 USB3_L_RX1N IN 60
USB3_L_RX2N IN 60 I
SSTXn1 SSRXn1
R2506 A4 VBUS VBUS B9

1 2
USB3_L_RX2P IN 60 60 IN TYPEC_CC1 A5 CC1 SBU2 B8
220K_5%_2 USB2_CN_1P A6 B7 USB2_CN_1N
CRITICAL 60 IN Dp1 Dn2
IN 60
D7504 I
USB2_CN_1N A7 B6 USB2_CN_1P
60 IN IN 60
1 Line-1 NC 10 0_5%_2_DY EMI A8
Dn1 Dp2
B5 TYPEC_CC2 60
2 Line-2 NC 9
1 NI R2510 2
SBU1 CC2
IN
A9 VBUS VBUS B4
3 GND GND 8
60 OUT USB3_L_RX2N A10 SSRXn2 SSTXn2 B3 USB3_L_TX2N 60
4 Line-3 NC 7 OUT
60 OUT USB3_L_RX2P A11 SSRXp2 SSTXp2 B2 USB3_L_TX2P 60
5 Line-4 NC 6 L2500 C7583 OUT
A12 B1
37 BI USB2_REAR_1P 2 3 USB2_CN_1P 60 1 2 GND GND
6011B0172501
37 USB2_REAR_1N 1 4 USB2_CN_1N OUT 60
AMAZING_AZ1045_04F_R7G_10P BI OUT G1 G6
USB3_L_TX1P IN 60 0.1UF_16V_2
G1 G6
MCF12102G900-T G2 G2 G7 G7
USB3_L_TX1N I CRITICAL C7555 G3 G8
IN 60 6014B0247601 1 2 G3 G8
A 1 2 G4 G4 G9 G9 A
NI
R2511 G5 G5 G10 G10
0.1UF_16V_2
USB3_L_TX2N 0_5%_2_DY
IN 60 C7553
1 2 SINGATRON_2UB3C02_101211F_24P
USB3_L_TX2P IN 60 6012B0909301
CRITICAL DGND_CHASSIS2
D7505 I 0.1UF_16V_2
1 Line-1 NC 10 C7554
2 Line-2 NC 9 1 2
3 GND GND 8
INVENTEC
4 Line-3 NC 7 0.1UF_16V_2
5 Line-4 NC 6
6011B0172501
AMAZING_AZ1045_04F_R7G_10P USB3_L_RX1P TITLE
IN 60 DGND_CHASSIS2
USB3_L_RX1N MODEL,PROJECT,FUNCTION
IN 60 Block Diagram
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3
SHEET
CS
60 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
USB CHARGER
D
D
C C
P5V0DS
61 IN USB_CHR_POWER
Vinafix.com 61 OUT
1 NI R2523 2
0_5%_2_DY
I CRITICAL
1
1 NI R2500 2 L2501 USB_CHR_POWER IN 61
U63_STATUS# USB2_CHR_3N USB2_CN_3N
1
OUT 61 61 BI 1 4
10K_5%_2_DY 61 BI USB2_CHR_3P 2 3 USB2_CN_3P
C2521 C2522 22UF_6.3V_5
+
C2520 6014B0247601
MCF12102G900-T
1 NI R2501 2 USB_CHR# 1 2
OUT 61 100UF_6.3V 0.1UF_16V_2
2
NI 0_5%_2_DY CN2501
B 10K_5%_2_DY
2
61
R2524 1 B
OUT VBUS
61 2
OUT D-
3 D+
0_5%_3 4
P5V0DS R2529 2
GND
40 OUT USB3_RX3N 1 I USB3_L_RX3N 5 SSRX- G1 G1
40 OUT USB3_RX3P 1 2 USB3_L_RX3P 6 SSRX+ G2 G2
R2551 2
I MAX IS 2.5A. I
R2530 7 GND G3 G3
ILIM_HI 1
8 G4
4.7UF_6.3V_2
0.1UF_16V_2
I 0_5%_3 SSTX- G4
1
19.6K_1%_2 9
61 OUT SSTX+
R2552 2
C2506
C2505
ILIM_LO 1
I
33K_1%_2
P5V0DS 61 OUT TCONN_18_35690_1A63_0_9P
I I
USB_CHR# OUT 61 C2518 I
0_5%_3 6012B1062301
17
16
15
14
13
0.1UF_16V_2
2
USB3_TX3N 2 1 USB3_C_TX3N 1 I R2531 2 USB3_L_TX3N

2 R2559 1
40 IN
10K_5%_2
U2501
40 IN USB3_TX3P 2 1 USB3_C_TX3P 1 I 2 USB3_L_TX3P
PWPD
GND
ILIM_LO
FAULT#
ILIM_HI
I
I R2532
C2519
0_5%_3
1 12 USB_CHR_POWER 0.1UF_16V_2
IN OUT OUT 61 61 OUT DGND_CHASSIS2
USB2_REAR_3N 2 11 USB2_CHR_3N
10UF_6.3V_3_DY
37 BI DM_OUT DM_IN OUT 61

CRITICAL
USB2_REAR_3P 3 10 USB2_CHR_3P
0.1UF_16V_2
37 BI DP_OUT I DP_IN OUT 61

1
1
SET_R 4 ILIM_SET STATUS# 9 U63_STATUS# OUT 61

CRITICAL
I
C2507
C2508
CTL1
CTL2
CTL3
A D7500 A
EN
TML 11
USB3_L_RX3N 1 10 USB3_L_RX3P
2
TEXAS_TPS2546RTER_QFN_16P NI 61 IN I/O-1 I/O-6 IN 61

I
USB_CHR_POWER 2 9
5
6
7
8
61 IN VDD GND
3 NC NC 8
61 IN USB2_CN_3N 4 I/O-2 I/O-5 7 USB2_CN_3P IN 61
CHARGE_USBPWR_EN1 R2555 2 USB_PWR_EN USB3_L_TX3N 5 6 USB3_L_TX3P
51 IN 61 IN I/O-3 I/O-4 IN 61
I
1
0_5%_2
AMAZING_AZ1065_06F_10P
51 EC_CTL1 1 R2554 2 CTL1 I
IN C7573
INVENTEC
I
0_5%_2
0.1UF_16V_2
EC_CTL2 1 R2553 2 CTL2
2
51 IN I
0_5%_2
TITLE
P5V0DS
R2557 MODEL,PROJECT,FUNCTION
2 1 CTL3 Block Diagram
10K_5%_2_DY DOC.NUMBER REV
EC_CTL3 1 R2558 2 SIZE CODE
51 IN 1310xxxxx-0-0 X01
Vinafix.com I
0_5%_2 CHANGE by
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 61 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFFERENCE 3000~3049(LCM)
EDP CONN
R3005
R3013 38 IN INV_PWM_PCH 1 2 EDP_PWM
OUT 62
51 38 IN LCM_BKLTEN 1 2 2.2K_5%_2_DY EDP_BKLTEN
OUT 62
1
100_5%_2
1
2
C3008
D R3006
R3008 C3007
100K_5%_2
100K_5%_2_DY 680PF_50V_2_DY D
CSC0402_DY
D3000
2
2
1
51 IN LID_SW_LCM# 1 2 CRITICAL
I
1N4148WS_DY
EDP
R3014
2 1 P3V3A P1V8S CN5
62 CPU_EDP_TX3_DP 1
IN CPU_EDP_TX3_DN
1
0_5%_2 62 2
IN 2
R3002 1
100K_5%_2
3 3
62 CPU_EDP_TX2_DP 4
IN CPU_EDP_TX2_DN
4
5
1
62 IN 5
L2N7002WT1G 6 6
CPU_EDP_TX1_DP 7
G
62 IN 7
2
62 CPU_EDP_TX1_DN 8
TOUCH_INT# 3 2 TOUCH_INT#_L
IN 8
44 D S 62 9
IN OUT CPU_EDP_TX0_DP
9
62 10
I IN CPU_EDP_TX0_DN
10
Q3000 62 11
IN 11
12 12
62 CPU_EDP_AUX_DP 13
C BI CPU_EDP_AUX_DN
13
C
62 14
BI 14
15 15
TP_D- 1 L3001 LS_SHORT_0504
4 16
37 BI 16
37 TP_D+ 2 3 17
BI 17
18 18
19 19
R3004 2 62 EDP_BKLTEN 20
1 IN EDP_PWM
20
62 21
P3V3S 100_5%_2 IN EDP_HPD
21
44 22
I IN 22
Vinafix.com
A 23 23
U3000
PAD3000 44 TOUCH_PWR_EN 24
IN PCH_I2C_CLK
24
5 1 1 2 44 25
IN OUT 1 2 IN PCH_I2C_DATA
25
2 44 26
GND IN 26
2.2UF_6.3V_2
4 3 POWERPAD1X1M TOUCH_INT#_L 27
1
DIS EN 62 IN 27
R40 44 TOUCH_RST# 28
L3002 IN 28
2 LCM_VDDEN USB_CAM_R_DN
C3000
1 38 37 1 4 29
NUVO_NCT3521U_SOT23_5P IN OUT USB_CAM_R_DP
29
6019B0849401 0_5%_2 37 2 3 LS_SHORT_0504 30
OUT 30
31 31
0.033UF_16V_2 DMIC_R_CLK 32
2
62 IN 32
P3V3S 62 DMIC__R_DATA 33
IN 33
C3003
34 34
P3V3S_LCDVDD2
FUSE3001 1 2 LITTELFUSE_0805L110ULYR 35 35
B 36 36 G1 G1 B
2.2UF_6.3V_2
0.1UF_16V_2
37 G2
1
37 G2
38 38 G3 G3
C3001
C3002
39 39 G4 G4
40 40 G5 G5
CSC0402_DY
CSC0402_DY
PVBAT
1
1
2
2
I 6012B0773101
A
C3011
C3012
PAD3001 FUSE3000
1 2 1 2 ACES_51398_0407T_001_40P
1 2
4.7UF_25V_3
0.1UF_25V_2
POWERPAD1X1M
1
1.5A_24V
2
C3009
C3010
62 C3013 1
CPU_EDP_TX0_DP 2 0.1UF_6.3V_1 EDP_TX0_DP 27
IN OUT
62 C3014 1
CPU_EDP_TX0_DN 2 0.1UF_6.3V_1 EDP_TX0_DN 27
IN OUT
2
62 C3017 1
IN OUT
62 C3016 1
IN OUT
62 C3026 1
IN OUT
62 C3027 1
IN OUT
62 C3028 1
IN OUT
A 62 IN C3029 1
CPU_EDP_TX3_DN 2 0.1UF_6.3V_1 EDP_TX3_DN
OUT 27 A
62 C3019 1
CPU_EDP_AUX_DN 2 0.1UF_6.3V_1 EDP_AUX_DN 27
BI BI I
62 C3020 1
CPU_EDP_AUX_DP 2 0.1UF_6.3V_1 EDP_AUX_DP 27
BI BI DMIC_CLK R3001 2 DMIC_R_CLK
54 1 62
IN DMIC_DATA DMIC__R_DATA
OUT
54 1R3000 2 SHORT_0402_5 62
IN OUT
C3004 100_5%_2
2 1
10PF_50V_2_DY
2
C3005
1 INVENTEC
10PF_50V_2_DY TITLE
Block Diagram
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 62 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TPM DO NOT INSTALL

D
D
P3V3A
P3V3S
4.7UF_6.3V_2
0.1UF_16V_2
1
1
C3501
PAD3500
C3502
1 1 2
2
0.1UF_16V_2
0.1UF_16V_2
POWERPAD1X1M
4.7UF_6.3V_2
0.1UF_16V_2
2
1
2
C3500
C3505
C3504
C3503
2
2
C P3V3A C
2018/04/27 MODIFIED
22
U3500
1
8
2
2
10K_5%_2
10K_5%_2
10K_5%_2
R3502
R3500
R3501
VSB
VHIO2
VHIO1
PLACEMENT TO REDUCE STUB
Vinafix.com
2
1
NC1
NC2 3
44 TPM_PIRQ# 18 5
OUT PCH_SPI_SI TPM_SPI_SI
SPI_IRQ#/GPIO2 NC3
50 36 IN R3506 1 233_5%_2 21 MOSI/GPIO7 NC4 7
50 36 PCH_SPI_SO R3505 1 233_5%_2 TPM_SPI_SO 24 9
IN PCH_SPI_CS2#
MISO NC5
36 IN R3504 1 2SHORT_0402_5 TPM_SPI_CS2# 20 SCS#/GPIO5 NC6 10
50 36 PCH_SPI_CLK R3503 1 233_5%_2 TPM_SPI_CLK 19 11
IN SCLK NC7
NC8 12
29 SDA/GPIO0 NC9 14
30 SCL/GPIO1 NC10 15
NC11 25
13 GPIO4/SINT# NC12 26
6 GPIO3 NC13 27
B 4 PP/GPIO6 NC14 28 B
NC15 31
64 59 58 57 51 36 BUF_PLT_RST# 17 32
IN RESET# NC16
GND1
GND2
B.M,
NUVOTON_NPCT750AAAYX_QFN_32P
6019B1730201
33
16
23
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 63 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P3V3DS
P3V3A CN603
50
50
49 G2
49 G2
48 G1
48 G1
47
47
60 51 USBPWR_EN 46
IN USB_P4_DP 46
37 45
IN USB_P4_DN 45
37 44
IN 44
43
43
37 USB_P5_DP 42
IN 42
D 37 IN USB_P5_DN 41
41
40
40
D
40 USB3_TX4P 39
IN USB3_TX4N 39
40 38
IN 38
37
37
40 USB3_RX4P 36
IN USB3_RX4N 36
40 35
IN 35
34
34
40 USB3_TX5P 33
IN USB3_TX5N 33
40 32
IN 32
31
31
40 USB3_RX5P 30
IN USB3_RX5N 30
40 29
IN 29
28
28
65 REP_LAN_TX13P 27
P5V0 IN REP_LAN_TX13N 27
65 26
IN 26
25
25
CN604 65 REP_LAN_C_RX13P 24
IN REP_LAN_C_RX13N 24
65 23
1 1 IN 23
22
2 2 22
45 CLK_LAN_DP 21
3 3 G G1 IN CLK_LAN_DN 21
45 20
4 4 G G2 IN WOL_PWEN 20
51 19
IN BUF_PLT_RST# 19
63 59 58 57 51 36 18
C ACES_50224_00401_001_4P IN PCH_WAKE# 18 C
57 39 17
6012B0069910 IN CLKREQ13_LAN# 17
45 16
IN CHG_LED 16
51 15
IN AC_LED 15
51 14
IN PWR_LED 14
51 13
IN 13
54 IN SPK_OUT_R_L_P 12
12
54 IN SPK_OUT_R_L_N 11
11
54 IN SPK_OUT_R_R_N 10
10
54 IN SPK_OUT_R_R_P 9
9
HPS
Vinafix.com
54 8
OUT 8
54 OUT MIC2_REF 7
7
54 OUT SLEEVE 6
6
54 BI RING2 5
5
4
4
55 IN HP_R_L 3
3
55 OUT HP_R_R 2
2
1
1
ACES_51540_05001_001_50P
6012B0541005
B B
AGND_AUDIO
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 64 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PCIE REPEATER
P3V3S
D P3V3S
1 R1701 2 D
4.7K_5%_2_DY
10UF_6.3V_3
1 R1700 2 PCIE_REP_EN#
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
OUT 65
1
I
1
1
4.7K_5%_2
REAR1_SWA
C1711
I I I I 65 IN
C1715
C1714
C1713
C1712
REAR1_FGA IN 65
65 IN SATA_PCIE_SEL REAR1_A_EQ1 IN 65
I
P3V3S
2
2
1 R1718 2 SATA_PCIE_SEL OUT 65

I 4.7K_5%_2
P3V3S
P3V3S
31
30
29
28
27
26
U1700
HGND
GND
MODE
SWA
FGA
EQA1
1 VDD VDD 25
38 PCIE_LAN_TX13P 2 24 REP_LAN_TX13P 64
P3V3S IN PCIE_LAN_TX13N
AIP AOP
REP_LAN_TX13N
OUT
38 3 23 64
IN AIN AON OUT
4 GND GND 22
C NI 1 R1702 2 REAR1_A_EQ0 65 1 5 CRITICAL 21 REAR1_A_EQ0 65
C
OUT TP1700
TEST# EQA0 IN
1K_5%_2_DY 6 GND I EQB0 20 REAR1_B_EQ0 IN 65
7 GND GND 19
NI 1 R1703 2 REAR1_A_EQ1 65 65 PCIE_LAN_C_RX13N 8 18 REP_LAN_RX13N 65
OUT OUT PCIE_LAN_C_RX13P
BON BIN
REP_LAN_RX13P
IN
1K_5%_2_DY 65 9 17 65
OUT BOP BIP IN
NI 1 R1704 2 REAR1_B_EQ0 65
10 VDD VDD 16
OUT
1K_5%_2_DY
EQB1
SWB
GND
FGB
NI 1
EN#
R1705 2 REAR1_B_EQ1 OUT 65
Vinafix.com
1K_5%_2_DY
NI 1
12
13
14
15
R1706 2
11
REAR1_FGA OUT 65
PCIE_REP_EN# PERICOM_PI3EQX12902A_TQFN_30P
1K_5%_2_DY 65 IN
NI 1 R1707 2 REAR1_FGB
65
OUT
1K_5%_2_DY REAR1_B_EQ1 IN 65
NI 1 R1708 2 REAR1_SWA 65 65 REAR1_SWB REAR1_FGB 65
OUT IN IN
1K_5%_2_DY
NI 1 R1709 2 REAR1_SWB 65
OUT
1K_5%_2_DY
C1704
B B
C1710 65 REP_LAN_RX13N 1 2 REP_LAN_C_RX13N 64
NI 1 R1710 2 IN OUT
REAR1_A_EQ0 OUT 65 PCIE_LAN_RX13N PCIE_LAN_C_RX13N
38 1 2 65 0.1UF_16V_2
1K_5%_2_DY OUT IN
0.1UF_16V_2 C1705
NI 1 R1711 2 REAR1_A_EQ1 65 C1706
OUT PCIE_LAN_RX13P PCIE_LAN_C_RX13P 65 IN REP_LAN_RX13P 1 2 REP_LAN_C_RX13P
OUT 64
1K_5%_2_DY 38 1 2 65
OUT IN
NI 1 R1712 2 REAR1_B_EQ0 65 0.1UF_16V_2
0.1UF_16V_2
OUT
1K_5%_2_DY
NI 1 R1713 2 REAR1_B_EQ1 65
OUT
1K_5%_2_DY
NI 1 R1715 2 REAR1_FGA 65
OUT
1K_5%_2_DY
NI 1 R1714 2 REAR1_FGB
65
OUT
1K_5%_2_DY
NI 1 R1716 2 REAR1_SWA 65
OUT
1K_5%_2_DY
NI 1 R1717 2 REAR1_SWB 65
OUT
1K_5%_2_DY
A A
Vinafix.com INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 65 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
D
C C
Vinafix.com
B B
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 66 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
D
C C
Vinafix.com
B B
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 67 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
D
C C
Vinafix.com
B B
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 68 of 139
8 7 6 5 4 3 2 1
07e30a1209261000d00169fd1b0036e2
8 7 6 5 4 3 2 1
D
D
C C
Vinafix.com
B B
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 69 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
D
C C
Vinafix.com
B B
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 70 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
D
N18E-G0
C N18E-G1 C
N18E-G2 MAX-Q
Vinafix.com
B
8GB DDR5 256M X 16 X 2 X6 B
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 71 of 139
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PCA CODE NAME： N18E-G0/G1/G2 MAX-Q

G0 : 6019B1850001
G1 : 6019B1849201
G2 MAXQ:6019B1849301
D
PCB VERSION：X01 D
BOARD SIZE:
SCH P/N:
PCB P/N:
PCA P/N:
C
BOM ATTRIBUTE TRUTH TABLE C
I: INSTALL
NI: NON-INSTALL
DY: NON-INSTALL
Vinafix.com MP: PRODUCTION
PROTO: PRE-PRODUCTION
CRITICAL: CRITICAL PART
B
PVCORE_DGPU = NVVDD B
P1V35 S_DGPU= FBVDD

P1V0S_DGPU = PEX_VDD
SAMSUNG K4Z80325BC-HC14
6019B1847601
A A
MICRON MT61K256M32JE-14:A
6019B1847701
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
CHANGE by DATE A3 CS
XXX 21-OCT-2002
8 Vinafix.com 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CLK_PCIE_DGPU_100MHZ_P
74
74
74
45
45
26
IN
IN CLK_PCIE_DGPU_100MHZ_N
PCIE_DGPU_RX15P
OUT
OUT CONNECTION TO MAINBOARD
OUT OUT
74 26 OUT PCIE_DGPU_RX15N OUT
74 26 IN PCIE_DGPU_TX15P OUT
74 26 IN PCIE_DGPU_TX15N OUT 74 45 OUT PEX_CLKREQ# IN
105 93 91 44 IN DGPU_PWR_EN OUT
74 26 OUT PCIE_DGPU_RX14P OUT
74 26 PCIE_DGPU_RX14N PCIE CLK REQUESTD#
OUT OUT GPU PWR ENABLE COME FROM PCH/EC
D 74 26 IN PCIE_DGPU_TX14P OUT MAKE SURE 10K P3V3S PULL UP
74 26 IN PCIE_DGPU_TX14N OUT 105 51 OUT ALL_POWER_GOOD IN D
74 26 OUT PCIE_DGPU_RX13P OUT 74 36 IN PCH_PLTRST#_BUF OUT
74 26 OUT PCIE_DGPU_RX13N OUT GPU ALL S RAIL GOOD
74 26 PCIE_DGPU_TX13P PCH PLATFORM RESET# MAKE SURE 10K P3V3S PULL UP
IN OUT
74 26 IN PCIE_DGPU_TX13N OUT MAKE SURE 100K PULL TO GND
74 26 OUT PCIE_DGPU_RX12P OUT 93 44 OUT DP_MA_HPD# IN
74 26 OUT PCIE_DGPU_RX12N OUT 74 44 IN IRMT_HOLD_RST# OUT
74 26 PCIE_DGPU_TX12P DP HPD TO MAINBOARD
IN OUT PCH HOLD RESET#
74 26 IN PCIE_DGPU_TX12N OUT
MAKE SURE 100K PULL TO GND MAKE SURE 10K P3V3S PULL UP
74 26 OUT PCIE_DGPU_RX11P OUT 95 92 73 50 49 SMB0_DATA_D
74 26 OUT PCIE_DGPU_RX11N OUT TO PCH BI BI
95 92 73 50 49 SMB0_CLK_D
BI BI
74 26 IN PCIE_DGPU_TX11P OUT 89 44 IN GPU_EVENT_PCH# OUT
74 26 IN PCIE_DGPU_TX11N OUT DP REDRIVER I2C CONNECT TO MOBARD
74 26 PCIE_DGPU_RX10P PCH INFORM GPU WILL EXIT GC6 MODS MAINBOARD NEED TO PULL UP
OUT OUT
C 74 26 IN PCIE_DGPU_TX10P OUT C
95 44 OUT HDMI_MB_HPD# IN
74 26 IN PCIE_DGPU_TX10N OUT 89 51 IN DGPU_PWRLEVEL OUT
74 26 OUT PCIE_DGPU_RX9P OUT HDMI HPD TO MB
49
50
73
92
95 SMB0_DATA_D
BI BI
74 26 OUT PCIE_DGPU_RX8P OUT 95 92 73 50 49 BI SMB0_CLK_D
BI
Vinafix.com
74 26 IN PCIE_DGPU_TX8P OUT HDMI RETIMER I2C TO MB
74 26 IN PCIE_DGPU_TX8N OUT MAINBOARD NEED TO PULL UP
74 26 IN PCIE_DGPU_TX7N OUT 89 51 OUT GPU_OVERT_EC# IN
B 74 26 OUT PCIE_DGPU_RX6N OUT 3.3V LEVEL B
74 26 PCIE_DGPU_TX6P OVER TEMPERATURE TO PCH OR EC
IN OUT
105 89 44 OUT GC6_FB_EN_PCH IN
3.3V LEVEL
74 26 PCIE_DGPU_TX5N GC6 ENABLE SIGNAL TO PCH OR EC
IN OUT
74 26 IN PCIE_DGPU_TX3N OUT EC
74 26 OUT PCIE_DGPU_RX2P OUT 89 51 BI EC_SMBDATA0 BI
A 74 26 OUT PCIE_DGPU_RX2N OUT A
89 51 BI EC_SMBCLK0 BI
GPU I2C, COMMUNCATED WITH EC
74 26 OUT PCIE_DGPU_RX1N OUT THIS SIGNAL REQUIRE AN EXTERNAL PULL UP
74
74
26
26
OUT
OUT
PCIE_DGPU_RX0P
PCIE_DGPU_RX0N
OUT
OUT
INVENTEC
TITLE
74 26 IN PCIE_DGPU_TX0N OUT MODEL,PROJECT,FUNCTION
Block Diagram
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 73 of 139
8 7 6 5 4 3 2 1
07e30a1209261000d00169fd1b0036e2
8 7 6 5 4 3 2 1
P1V8S_AON1
0.1UF_16V_2
C50020
TP50022
2
1 I
5
A
U50020 PLACE BETWEEN BGA AND POWER SUPPLY
PCH_PLTRST#_BUF TP24 1
+
F 73 36 IN 4 PEX_DGPU_RST# F
IRMT_HOLD_RST# 2
OUT 74 89
73 44 IN
TP50021
100K_1%_2
-
1
NEAR BGA
100K_1%_2_DY
1 TC7SZ08FU
PLACE UNDER BGA P1V0S_DGPU
R50020
3
TP24
100K_1%_2
NI
1
2
A
R50022
R50021
4.7UF_6.3V_2
4.7UF_6.3V_2
1
1
1UF_6.3V_1
1UF_6.3V_1
1UF_6.3V_1
1UF_6.3V_1
1UF_6.3V_1
1UF_6.3V_1
1UF_6.3V_1
1UF_6.3V_1
2
10UF_10V_5
10UF_10V_5
22UF_4V_3
1
1
C50038
C50039
C50042
C50030
C50031
C50032
C50033
C50034
C50035
C50036
C50037
C50040
C50041
2
1
2
2
10UF_10V_5
4.7UF_6.3V_2
22UF_4V_3
1
1
P1V8S_MAIN1 P1V8S_AON1
1
1UF_6.3V_1
1UF_6.3V_1
1UF_6.3V_1
1UF_6.3V_1
1UF_6.3V_1
1UF_6.3V_1
1UF_6.3V_1
1UF_6.3V_1
C50058
C50060
10K_1%_2
C50050
C50051
C50052
C50053
C50054
C50055
C50056
C50057
C50059
R50010
2
2
2
ALL_PG_REQ
10K_1%_2
R50011
E E
P3V3S X6S OR X7R
U50000
10K_1%_2
X6S OR X7R
R50012
G
1/22 PCI_EXPRESS
G
D S
BK44 PEX_WAKE*
PEX_CLKREQ#
A
I
D S
73 45 OUT PEX_DVDD_1 BB35
PJA138K PEX_DGPU_RST# BK26 BB36
89 74 IN PEX_RST* PEX_DVDD_2
BC35
TP50010 Q50010 PEX_DVDD_3
PEX_GPU_CLKREQ# BL26 BC36 P1V8S_MAIN1
PEX_CLKREQ* PEX_DVDD_4
PEX_DVDD_5 BD33 PLACE UNDER BGA NEAR BGA
CLK_PCIE_DGPU_100MHZ_P BM26 BD36
73 45 IN CLK_PCIE_DGPU_100MHZ_N BM27
PEX_REFCLK PEX_DVDD_6
73 45 IN PEX_REFCLK*
BB33
PEX_CVDD_1
4.7UF_6.3V_2
PCIE_DGPU_RX15P C55700 1 2 0.22UF_6.3V_1 PEG_CPU_RX15P_C BG26 BC33
1
1UF_6.3V_1
1UF_6.3V_1
1UF_6.3V_1
1UF_6.3V_1
1UF_6.3V_1
73 26 OUT
10UF_10V_5
10UF_10V_5
22UF_4V_3
PEX_TX0 PEX_CVDD_2
4.7UF_6.3V_2
1
1
C50075
PCIE_DGPU_RX15N C55701 1 2 0.22UF_6.3V_1 PEG_CPU_RX15N_C BH26
73 26 OUT PEX_TX0*
C50076
C50070
C50071
C50072
C50073
C50074
C50079
C50077
C50078
PCIE_DGPU_TX15P BL27
73 26 IN PCIE_DGPU_TX15N BK27
PEX_RX0
73 26 IN PEX_RX0*
2
2
2
PCIE_DGPU_RX14P C55702 1 2 0.22UF_6.3V_1 PEG_CPU_RX14P_C BF26
73 26 OUT PCIE_DGPU_RX14N PEG_CPU_RX14N_C BE26
PEX_TX1
BB26
73 26 OUT C55703 1 2 0.22UF_6.3V_1 PEX_TX1* PEX_HVDD_1
PEX_HVDD_2 BB27
D PCIE_DGPU_TX14P BK29 BB29 D
73 26 IN PCIE_DGPU_TX14N BL29
PEX_RX1 PEX_HVDD_3
BB32
73 26 IN PEX_RX1* PEX_HVDD_4
10UF_10V_5
22UF_4V_3
4.7UF_6.3V_2
BC26
1
1UF_6.3V_1
1UF_6.3V_1
1UF_6.3V_1
1UF_6.3V_1
1UF_6.3V_1
PEX_HVDD_5
C50085
PCIE_DGPU_RX13P C55704 1 2 0.22UF_6.3V_1 PEG_CPU_RX13P_C BF27 BC27
73 26 OUT PEX_TX2 PEX_HVDD_6
C50087
C50080
C50081
C50082
C50083
C50084
C50086
PCIE_DGPU_RX13N C55705 1 2 0.22UF_6.3V_1 PEG_CPU_RX13N_C BG27 BC29
73 26 OUT PEX_TX2* PEX_HVDD_7
BC30
PEX_HVDD_8
PCIE_DGPU_TX13P BM29 BC32
73 26 IN PCIE_DGPU_TX13N BM30
PEX_RX2 PEX_HVDD_9
BD27
2
2
2
73 26 IN
Vinafix.com
PEX_RX2* PEX_HVDD_10
PEX_HVDD_11 BD30
PCIE_DGPU_RX12P C55706 1 2 0.22UF_6.3V_1 PEG_CPU_RX12P_C BG29
73 26 OUT PCIE_DGPU_RX12N PEG_CPU_RX12N_C BH29
PEX_TX3
73 26 OUT C55707 1 2 0.22UF_6.3V_1 PEX_TX3*
73 26 IN PCIE_DGPU_TX12P BL30 PEX_RX3

X6S OR X7R X6S OR X7R
PCIE_DGPU_TX12N BK30
73 26 IN PEX_RX3*

PEX_TX4
73 26 OUT C55709 1 2 0.22UF_6.3V_1 PEX_TX4*
PCIE_DGPU_TX11P BK32
PEX_RX4
73 26 IN PEX_RX4* P1V8S_MAIN1
73 26 OUT PCIE_DGPU_RX10N PEG_CPU_RX10N_C BG30
PEX_TX5 I
A
73 26 OUT C55711 1 2 0.22UF_6.3V_1 PEX_TX5*
BB30 PEX_PLL_HVDD_SVDD 1 R50090 2
PEX_PLL_HVDD
PCIE_DGPU_TX10P BM32 0_5%_3
73 26 IN PEX_RX5
4.7UF_6.3V_2
PCIE_DGPU_TX10N BM33
1
1UF_6.3V_1
1UF_6.3V_1
73 26 IN PEX_RX5*
C50091
C50092
C50090
C PCIE_DGPU_RX9P C55712 1 2 0.22UF_6.3V_1 PEG_CPU_RX9P_C BG32 C
PEX_TX6
73 26 OUT C55713 1 2 0.22UF_6.3V_1 PEX_TX6*
PCIE_DGPU_TX9P BL33
2
PEX_RX6
73 26 IN PEX_RX6*

PEX_TX7
73 26 OUT C55715 1 2 0.22UF_6.3V_1 PEX_TX7*
73 26 IN PCIE_DGPU_TX8P BK35 PEX_RX7 PLACE NEAR GPU X7R

PCIE_DGPU_TX8N BL35
73 26 IN PEX_RX7*

PEX_TX8
73 26 OUT C55717 1 2 0.22UF_6.3V_1 PEX_TX8*
PCIE_DGPU_TX7P BM35
PEX_RX8
73 26 IN PEX_RX8*

PEX_TX9
73 26 OUT C55719 1 2 0.22UF_6.3V_1 PEX_TX9*
PCIE_DGPU_TX6P BL36
PEX_RX9
73 26 IN PEX_RX9*

PEX_TX10
73 26 OUT C55721 1 2 0.22UF_6.3V_1 PEX_TX10*
B 73 26 IN PCIE_DGPU_TX5P BK38 PEX_RX10 B

PCIE_DGPU_TX5N BL38
73 26 IN PEX_RX10*

PEX_TX11
73 26 OUT C55723 1 2 0.22UF_6.3V_1 PEX_TX11*
PCIE_DGPU_TX4P BM38
PEX_RX11
73 26 IN PEX_RX11*

PEX_TX12
73 26 OUT C55725 1 2 0.22UF_6.3V_1 PEX_TX12*
PCIE_DGPU_TX3P BL39
PEX_RX12
73 26 IN PEX_RX12*

PEX_TX13
73 26 OUT C55727 1 2 0.22UF_6.3V_1 PEX_TX13*
PCIE_DGPU_TX2P BK41
PEX_RX13
73 26 IN PEX_RX13*

PEX_TX14
73 26 OUT C55729 1 2 0.22UF_6.3V_1 PEX_TX14*
PCIE_DGPU_TX1P BM41
PEX_RX14
73 26 IN PEX_RX14*
A PCIE_DGPU_RX0P C55730 1 2 0.22UF_6.3V_1 PEG_CPU_RX0P_C BH41 A

PEX_TX15
OUT C55731 1 2 0.22UF_6.3V_1
INVENTEC
73 26 PEX_TX15*
PCIE_DGPU_TX0P BL42 BL44 DGPU_PEX_TERMP R50091

73 26 IN PEX_RX15 PEX_TERMP
Vinafix.com
PCIE_DGPU_TX0N BK42
73 26 IN PEX_RX15*
2.49K_1%_2 TITLE
55700 - 55799 MODEL,PROJECT,FUNCTION

Block Diagram
50000 - 50099 NVIDIA_N18E_G1_KD_QS_A1_BGA_2228P CHANGE by XXX DATE 21-OCT-2002

SIZE
A3
CODE
CS
DOC.NUMBER
1310xxxxx-0-0
REV
X01
6 5 4 3 2 1
6 5 4 3 2 1
F GPU FRAME BUFFER A F
U50000
2/22 FBA
FBA_D0 U51 Y51 FBA_CMD0

79 BI FBA_D1 U48
FBA_D0 FBA_CMD0
Y52 FBA_CMD1
BI 79
79 BI FBA_D2 U50
FBA_D1 FBA_CMD1
Y49 FBA_CMD2_RST
BI 79
79 BI FBA_D3 U49
FBA_D2 FBA_CMD2
AA52 FBA_CMD3
BI 79
79 BI FBA_D4 R51
FBA_D3 FBA_CMD3
AA51 FBA_CMD4
BI 79
79 BI FBA_D5 R50
FBA_D4 FBA_CMD4
AA50 FBA_CMD5
BI 79
E 79 BI FBA_D6 R47
FBA_D5 FBA_CMD5
AC50 FBA_CMD6
BI 79
E
79 BI FBA_D7 U46
FBA_D6 FBA_CMD6
AC51 FBA_CMD7
BI 79
79 BI FBA_D8 V46
FBA_D7 FBA_CMD7
AC52 FBA_CMD8
BI 79
79 BI FBA_D9 Y45
FBA_D8 FBA_CMD8
AC49 FBA_CMD9
BI 79
79 BI FBA_D10 Y47
FBA_D9 FBA_CMD9
AD52 FBA_CMD10_CKE
BI 79
79 BI FBA_D11 Y46
FBA_D10 FBA_CMD10
AD51 FBA_CMD11
BI 79
79 BI FBA_D12 V50
FBA_D11 FBA_CMD11
AD50 FBA_CMD12
BI 79
79 BI FBA_D13 V47
FBA_D12 FBA_CMD12
AF50 FBA_CMD13
BI 79
79 BI FBA_D14 U52
FBA_D13 FBA_CMD13
AF51 FBA_CMD14
BI 79
79 BI FBA_D15 V51
FBA_D14 FBA_CMD14
AF52 FBA_CMD15
BI 79
79 BI FBA_D16 AJ44
FBA_D15 FBA_CMD15
AN50 FBA_CMD16
BI 79
79 BI FBA_D17 AG48
FBA_D16 FBA_CMD16
AN51 FBA_CMD17
BI 80
79 BI FBA_D18 AJ45
FBA_D17 FBA_CMD17
AN52 FBA_CMD18_RST
BI 80
79 BI FBA_D19 AG49
FBA_D18 FBA_CMD18
AM49 FBA_CMD19
BI 80
79 BI FBA_D20 AF46
FBA_D19 FBA_CMD19
AM52 FBA_CMD20
BI 80
79 BI FBA_D21 AF47
FBA_D20 FBA_CMD20
AM51 FBA_CMD21
BI 80
79 BI FBA_D22 AF48
FBA_D21 FBA_CMD21
AM50 FBA_CMD22
BI 80
79 BI FBA_D23 AD47
FBA_D22 FBA_CMD22
AK50 FBA_CMD23
BI 80
79 BI FBA_D24 AD49
FBA_D23 FBA_CMD23
AK51 FBA_CMD24
BI 80
79 BI FBA_D25 AD48
FBA_D24 FBA_CMD24
AK52 FBA_CMD25
BI 80
79 BI FBA_D26 AC46
FBA_D25 FBA_CMD25
AJ49 FBA_CMD26_CKE
BI 80
79 BI FBA_D27 AC47
FBA_D26 FBA_CMD26
AJ52 FBA_CMD27
BI 80
79 BI FBA_D28 AA47
FBA_D27 FBA_CMD27
AJ51 FBA_CMD28
BI 80
79 BI FBA_D29 AA46
FBA_D28 FBA_CMD28
AJ50 FBA_CMD29
BI 80
79 BI FBA_D30 AA45
FBA_D29 FBA_CMD29
AG50 FBA_CMD30
BI 80
79 BI FBA_D31 Y44
FBA_D30 FBA_CMD30
AG51 FBA_CMD31
BI 80
79 BI FBA_D31 FBA_CMD31 BI 80 P1V35S_FBVDDQ
FBA_D32 AW51 AF49 FBA_CMD32
D 80 BI FBA_D33 BA52
FBA_D32 FBA_CMD32
AG52 FBA_CMD33
BI 79
D
80 BI FBA_D34 AW50
FBA_D33 FBA_CMD33
Y50 FBA_DEBUG0
BI 80
80 BI FBA_D34 FBA_CMD34 R50120 1 2 60.4K_1%_2_DY
FBA_D35 BA51 AR50 FBA_DEBUG1 R50121 1 2 60.4K_1%_2_DY
80 BI FBA_D36 BA50
FBA_D35 FBA_CMD35
80 BI FBA_D37 BB50
FBA_D36
80 BI FBA_D38 BA49
FBA_D37
80 BI FBA_D39 AW49
FBA_D38
AA44
80 BI FBA_D39 FBA_DBG_RFU1
Vinafix.com
FBA_D40 AV48 AN44
80 BI FBA_D41 AT49
FBA_D40 FBA_DBG_RFU2
80 BI FBA_D42 AT47
FBA_D41
80 BI FBA_D43 AT48
FBA_D42
80 BI FBA_D44 AT46
FBA_D43
AG45 FBA_CLK0
80 BI FBA_D45 AV51
FBA_D44 FBA_CLK0
AG46 FBA_CLK0#
OUT 79
80 BI FBA_D46 AV52
FBA_D45 FBA_CLK0*
AK46 FBA_CLK1
OUT 79
80 BI FBA_D47 AV49
FBA_D46 FBA_CLK1
AK45 FBA_CLK1#
OUT 80
80 BI FBA_D48 AJ48
FBA_D47 FBA_CLK1* OUT 80
80 BI FBA_D49 AJ46
FBA_D48
80 BI FBA_D50 AJ47
FBA_D49
80 BI FBA_D51 AK49
FBA_D50
80 BI FBA_D52 AM47
FBA_D51
80 BI FBA_D53 AM46
FBA_D52
80 BI FBA_D54 AN48
FBA_D53
80 BI FBA_D55 AN49
FBA_D54
80 BI FBA_D56 AM44
FBA_D55
U45 FBA_WCK01
80 BI FBA_D57 AM45
FBA_D56 FBA_WCK01
U44 FBA_WCK01#
OUT 79
80 BI FBA_D58 AN45
FBA_D57 FBA_WCK01*
V45 FBA_WCKB01
OUT 79
80 BI FBA_D59 AN46
FBA_D58 FBA_WCKB01
V44 FBA_WCKB01#
OUT 79
C 80 BI FBA_D60 AR48
FBA_D59 FBA_WCKB01*
AC45 FBA_WCK23
OUT 79
C
80 BI FBA_D61 AN47
FBA_D60 FBA_WCK23
AC44 FBA_WCK23#
OUT 79
80 BI FBA_D62 AR47
FBA_D61 FBA_WCK23*
AD46 FBA_WCKB23
OUT 79
80 BI FBA_D63 AR46
FBA_D62 FBA_WCKB23
AD45 FBA_WCKB23#
OUT 79
80 BI FBA_D63 FBA_WCKB23*
AV47 FBA_WCK45
OUT 79
FBA_WCK45
AV46 FBA_WCK45#
OUT 80
FBA_DBI0 U47
FBA_WCK45*
AW48 FBA_WCKB45
OUT 80
79 OUT FBA_DBI1 Y48
FBA_DQM0 FBA_WCKB45
AW47 FBA_WCKB45#
OUT 80
79 OUT FBA_DBI2 AG47
FBA_DQM1 FBA_WCKB45*
AR45 FBA_WCK67
OUT 80
79 OUT FBA_DBI3 AC48
FBA_DQM2 FBA_WCK67
AR44 FBA_WCK67#
OUT 80
79 OUT FBA_DBI4 BB51
FBA_DQM3 FBA_WCK67*
AT45 FBA_WCKB67
OUT 80
80 OUT FBA_DBI5 AV50
FBA_DQM4 FBA_WCKB67
AT44 FBA_WCKB67#
OUT 80
80 OUT FBA_DBI6 AM48
FBA_DQM5 FBA_WCKB67* OUT 80
80 OUT FBA_DBI7 AR49
FBA_DQM6
80 OUT FBA_DQM7
FBA_EDC0 R48
79 OUT FBA_EDC1 V48
FBA_DQS_WP0
79 OUT FBA_EDC2 AF44
FBA_DQS_WP1
79 OUT FBA_EDC3 AA48
FBA_DQS_WP2
79 OUT FBA_EDC4 BB52
FBA_DQS_WP3
TP50100 OUT 75 76 77 78 P1V8S_MAIN1
80 OUT FBA_EDC5 AT50
FBA_DQS_WP4
1
80 OUT FBA_EDC6 AK48
FBA_DQS_WP5
80 OUT FBA_DQS_WP6 TP24 L50100
FBA_EDC7 AR51 AN42 FB_PLLAVDD
80 OUT FBA_DQS_WP7 FBA_PLL_AVDD
22UF_4V_3 FBMA_11_160808_300A25T
1
1
1
4.7UF_6.3V_2
4.7UF_6.3V_2
1
1UF_6.3V_1
C50103
W45
C50102
GND_694
B B
C50101
W47 GND_695
C50100
W49 GND_696
W51 GND_697
W6
2
GND_698
2
W8 GND_699
Y14 GND_700
PLACE NEAR GPU
Y15 GND_701
X6S OR X7R
PLACE UNDER GPU
FB_PLLAVDD AF42
78 77 76 75 IN FB_REFPLL_AVDD0
L29 FB_REFPLL_AVDD1 X6S OR X7R
1
1
1UF_6.3V_1
1UF_6.3V_1
C50111
C50110
NVIDIA_N18E_G1_KD_QS_A1_BGA_2228P
2
PLACE UNDER GPU

X6S OR X7R
A A
INVENTEC
Vinafix.com TITLE
Block Diagram
50100 - 50199 CHANGE by XXX DATE 21-OCT-2002

SIZE
A3
CODE
CS
DOC.NUMBER
1310xxxxx-0-0
REV
X01
6 5 4 3 2 1
6 5 4 3 2 1
F
GPU FRAME BUFFER B F
U50000
3/22 FBB
FBB_D0 H32 B35 FBB_CMD0

81 BI FBB_D1 D32
FBB_D0 FBB_CMD0
A35 FBB_CMD1
BI 81
81 BI FBB_D2 A33
FBB_D1 FBB_CMD1
D35 FBB_CMD2_RST
BI 81
81 BI FBB_D3 B32
FBB_D2 FBB_CMD2
A36 FBB_CMD3
BI 81
81 BI FBB_D4 E32
FBB_D3 FBB_CMD3
B36 FBB_CMD4
BI 81
81 BI FBB_D5 G32
FBB_D4 FBB_CMD4
C36 FBB_CMD5
BI 81
81 BI FBB_D6 J30
FBB_D5 FBB_CMD5
C38 FBB_CMD6
BI 81
81 BI FBB_D7 F32
FBB_D6 FBB_CMD6
B38 FBB_CMD7
BI 81
81 BI FBB_D8 H36
FBB_D7 FBB_CMD7
A38 FBB_CMD8
BI 81
81 BI FBB_D9 G36
FBB_D8 FBB_CMD8
D38 FBB_CMD9
BI 81
81 BI FBB_D10 J36
FBB_D9 FBB_CMD9
A39 FBB_CMD10_CKE
BI 81
81 BI FBB_D11 F36
FBB_D10 FBB_CMD10
B39 FBB_CMD11
BI 81
81 BI FBB_D12 F33
FBB_D11 FBB_CMD11
C39 FBB_CMD12
BI 81
E 81 BI FBB_D13 D33
FBB_D12 FBB_CMD12
C41 FBB_CMD13
BI 81
E
81 BI FBB_D14 J32
FBB_D13 FBB_CMD13
B41 FBB_CMD14
BI 81
81 BI FBB_D15 G33
FBB_D14 FBB_CMD14
A41 FBB_CMD15
BI 81
81 BI FBB_D16 E45
FBB_D15 FBB_CMD15
B49 FBB_CMD16
BI 81
81 BI FBB_D17 D45
FBB_D16 FBB_CMD16
A49 FBB_CMD17
BI 82
81 BI FBB_D18 F45
FBB_D17 FBB_CMD17
A48 FBB_CMD18_RST
BI 82
81 BI FBB_D19 G45
FBB_D18 FBB_CMD18
D47 FBB_CMD19
BI 82
81 BI FBB_D20 D42
FBB_D19 FBB_CMD19
A47 FBB_CMD20
BI 82
81 BI FBB_D21 E42
FBB_D20 FBB_CMD20
B47 FBB_CMD21
BI 82
81 BI FBB_D22 F42
FBB_D21 FBB_CMD21
C47 FBB_CMD22
BI 82
81 BI FBB_D23 H41
FBB_D22 FBB_CMD22
C45 FBB_CMD23
BI 82
81 BI FBB_D24 E41
FBB_D23 FBB_CMD23
B45 FBB_CMD24
BI 82
81 BI FBB_D25 F39
FBB_D24 FBB_CMD24
A45 FBB_CMD25
BI 82
81 BI FBB_D26 E39
FBB_D25 FBB_CMD25
D44 FBB_CMD26_CKE
BI 82
81 BI FBB_D27 D39
FBB_D26 FBB_CMD26
A44 FBB_CMD27
BI 82
81 BI FBB_D28 F38
FBB_D27 FBB_CMD27
B44 FBB_CMD28
BI 82
81 BI FBB_D29 E38
FBB_D28 FBB_CMD28
C44 FBB_CMD29
BI 82
81 BI FBB_D30 D36
FBB_D29 FBB_CMD29
C42 FBB_CMD30
BI 82
81 BI FBB_D31 E36
FBB_D30 FBB_CMD30
B42 FBB_CMD31
BI 82
81 BI FBB_D31 FBB_CMD31 BI 82 P1V35S_FBVDDQ
FBB_D32 M50 D41 FBB_CMD32
82 BI FBB_D33 P48
FBB_D32 FBB_CMD32
A42 FBB_CMD33
BI 81
82 BI FBB_D34 M51
FBB_D33 FBB_CMD33
C35 FBB_DEBUG0
BI 82
82 BI FBB_D34 FBB_CMD34 R50220 1 2 60.4K_1%_2_DY
FBB_D35 M49 B50 FBB_DEBUG1 R50221 1 2 60.4K_1%_2_DY
82 BI FBB_D36 P47
FBB_D35 FBB_CMD35
82 BI FBB_D37 P52
FBB_D36
82 BI FBB_D38 R46
FBB_D37
82 BI FBB_D39 P46
FBB_D38
J35
D 82 BI FBB_D40 L50
FBB_D39 FBB_DBG_RFU1
J41 D
82 BI FBB_D41 L51
FBB_D40 FBB_DBG_RFU2
82 BI FBB_D42 L52
FBB_D41
82 BI FBB_D43 L49
FBB_D42
82 BI FBB_D44 M46
FBB_D43
H42 FBB_CLK0
82 BI FBB_D45 L47
FBB_D44 FBB_CLK0
G42 FBB_CLK0#
OUT 81
82 BI FBB_D46 M48
FBB_D45 FBB_CLK0*
F47 FBB_CLK1
OUT 81
82 BI FBB_D46 FBB_CLK1 OUT 82
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FBB_D47 M47 E47 FBB_CLK1#
82 BI FBB_D48 D48
FBB_D47 FBB_CLK1* OUT 82
82 BI FBB_D49 C50
FBB_D48
82 BI FBB_D50 C48
FBB_D49
82 BI FBB_D51 C49
FBB_D50
82 BI FBB_D52 E49
FBB_D51
82 BI FBB_D53 E50
FBB_D52
82 BI FBB_D54 F49
FBB_D53
82 BI FBB_D55 F48
FBB_D54
82 BI FBB_D56 F50
FBB_D55
J33 FBB_WCK01
82 BI FBB_D57 D52
FBB_D56 FBB_WCK01
H33 FBB_WCK01#
OUT 81
82 BI FBB_D58 J50
FBB_D57 FBB_WCK01*
G35 FBB_WCKB01
OUT 81
82 BI FBB_D59 H48
FBB_D58 FBB_WCKB01
H35 FBB_WCKB01#
OUT 81
82 BI FBB_D60 H51
FBB_D59 FBB_WCKB01*
J39 FBB_WCK23
OUT 81
82 BI FBB_D61 J51
FBB_D60 FBB_WCK23
H39 FBB_WCK23#
OUT 81
82 BI FBB_D62 H49
FBB_D61 FBB_WCK23*
F41 FBB_WCKB23
OUT 81
82 BI FBB_D63 H52
FBB_D62 FBB_WCKB23
G41 FBB_WCKB23#
OUT 81
82 BI FBB_D63 FBB_WCKB23*
L46 FBB_WCK45
OUT 81
FBB_WCK45
L45 FBB_WCK45#
OUT 82
FBB_DBI0 C32
FBB_WCK45*
M44 FBB_WCKB45
OUT 82
C 81 IN FBB_DBI1 E33
FBB_DQM0 FBB_WCKB45
M45 FBB_WCKB45#
OUT 82
C
81 IN FBB_DBI2 E44
FBB_DQM1 FBB_WCKB45*
H47 FBB_WCK67
OUT 82
81 IN FBB_DBI3 G39
FBB_DQM2 FBB_WCK67
H46 FBB_WCK67#
OUT 82
81 IN FBB_DBI4 P49
FBB_DQM3 FBB_WCK67*
J47 FBB_WCKB67
OUT 82
82 IN FBB_DBI5 L48
FBB_DQM4 FBB_WCKB67
J46 FBB_WCKB67#
OUT 82
82 IN FBB_DBI6 D50
FBB_DQM5 FBB_WCKB67* OUT 82
82 IN FBB_DBI7 H50
FBB_DQM6
82 IN FBB_DQM7
FBB_EDC0 B33
81 BI FBB_EDC1 E35
FBB_DQS_WP0
81 BI FBB_EDC2 G44
FBB_DQS_WP1
81 BI FBB_EDC3 H38
FBB_DQS_WP2
TP50200
81 BI FBB_EDC4 P50
FBB_DQS_WP3
1
82 BI FBB_EDC5 J48
FBB_DQS_WP4
82 BI FBB_DQS_WP5 TP24
FBB_EDC6 D51
82 BI FBB_EDC7 F51
FBB_DQS_WP6
L38 FB_PLLAVDD
82 BI FBB_DQS_WP7 FBB_PLL_AVDD IN 75 77 78
1
1UF_6.3V_1
Y16 GND_702
Y17 GND_703
C50200
Y18
Y19
GND_704
GND_705
X6S OR X7R
Y20 GND_706
2
Y21 GND_707
Y22 GND_708
Y23 GND_709
B B
PLACE UNDER GPU
A A
INVENTEC
Vinafix.com TITLE
Block Diagram
50200 - 50299 SIZE

A3
CODE
CS
DOC.NUMBER
1310xxxxx-0-0
REV
X01
6 5 4 3 2 1
6 5 4 3 2 1
GPU FRAME BUFFER C

F F
U50000
4/22 FBC
FBC_D0 C6 C11 FBC_CMD0

83 BI FBC_D1 D6
FBC_D0 FBC_CMD0
B11 FBC_CMD1
BI 83
83 BI FBC_D2 A6
FBC_D1 FBC_CMD1
A11 FBC_CMD2_RST
BI 83
83 BI FBC_D3 B6
FBC_D2 FBC_CMD2
D11 FBC_CMD3
BI 83
83 BI FBC_D4 B4
FBC_D3 FBC_CMD3
A12 FBC_CMD4
BI 83
83 BI FBC_D5 A4
FBC_D4 FBC_CMD4
B12 FBC_CMD5
BI 83
83 BI FBC_D6 B3
FBC_D5 FBC_CMD5
C12 FBC_CMD6
BI 83
83 BI FBC_D7 C4
FBC_D6 FBC_CMD6
C14 FBC_CMD7
BI 83
83 BI FBC_D8 D9
FBC_D7 FBC_CMD7
B14 FBC_CMD8
BI 83
83 BI FBC_D9 C9
FBC_D8 FBC_CMD8
A14 FBC_CMD9
BI 83
83 BI FBC_D10 E9
FBC_D9 FBC_CMD9
D14 FBC_CMD10_CKE
BI 83
83 BI FBC_D11 B9
FBC_D10 FBC_CMD10
A15 FBC_CMD11
BI 83
83 BI FBC_D12 B8
FBC_D11 FBC_CMD11
B15 FBC_CMD12
BI 83
83 BI FBC_D13 A8
FBC_D12 FBC_CMD12
C15 FBC_CMD13
BI 83
83 BI FBC_D14 F6
FBC_D13 FBC_CMD13
C17 FBC_CMD14
BI 83
83 BI FBC_D15 E6
FBC_D14 FBC_CMD14
B17 FBC_CMD15
BI 83
83 BI FBC_D16 F18
FBC_D15 FBC_CMD15
B24 FBC_CMD16
BI 83
83 BI FBC_D16 FBC_CMD16 BI 84
E 83 BI FBC_D17 G18 FBC_D17 FBC_CMD17 A24 FBC_CMD17
BI 84 E
FBC_D18 E18 D23 FBC_CMD18_RST
83 BI FBC_D19 H18
FBC_D18 FBC_CMD18
A23 FBC_CMD19
BI 84
83 BI FBC_D20 D15
FBC_D19 FBC_CMD19
B23 FBC_CMD20
BI 84
83 BI FBC_D21 E15
FBC_D20 FBC_CMD20
C23 FBC_CMD21
BI 84
83 BI FBC_D22 G17
FBC_D21 FBC_CMD21
C21 FBC_CMD22
BI 84
83 BI FBC_D23 H17
FBC_D22 FBC_CMD22
B21 FBC_CMD23
BI 84
83 BI FBC_D24 J15
FBC_D23 FBC_CMD23
A21 FBC_CMD24
BI 84
83 BI FBC_D25 H15
FBC_D24 FBC_CMD24
D20 FBC_CMD25
BI 84
83 BI FBC_D26 E14
FBC_D25 FBC_CMD25
A20 FBC_CMD26_CKE
BI 84
83 BI FBC_D27 F14
FBC_D26 FBC_CMD26
B20 FBC_CMD27
BI 84
83 BI FBC_D28 H11
FBC_D27 FBC_CMD27
C20 FBC_CMD28
BI 84
83 BI FBC_D29 G11
FBC_D28 FBC_CMD28
C18 FBC_CMD29
BI 84
83 BI FBC_D30 F11
FBC_D29 FBC_CMD29
B18 FBC_CMD30
BI 84
83 BI FBC_D31 E11
FBC_D30 FBC_CMD30
A18 FBC_CMD31
BI 84
83 BI FBC_D31 FBC_CMD31 BI 84 P1V35S_FBVDDQ
FBC_D32 J29 A17 FBC_CMD32
84 BI FBC_D33 F30
FBC_D32 FBC_CMD32
D17 FBC_CMD33
BI 83
84 BI FBC_D34 H29
FBC_D33 FBC_CMD33
A9 FBC_DEBUG0
BI 84
84 BI FBC_D34 FBC_CMD34 R50320 1 2 60.4K_1%_2_DY
FBC_D35 G30 C24 FBC_DEBUG1 R50321 1 2 60.4K_1%_2_DY
84 BI FBC_D36 B30
FBC_D35 FBC_CMD35
84 BI FBC_D37 A30
FBC_D36
84 BI FBC_D38 H30
FBC_D37
84 BI FBC_D39 C30
FBC_D38
J14
84 BI FBC_D40 D27
FBC_D39 FBC_DBG_RFU1
J23
84 BI FBC_D41 J26
FBC_D40 FBC_DBG_RFU2
84 BI FBC_D42 F27
FBC_D41
84 BI FBC_D43 G27
FBC_D42
84 BI FBC_D43
FBC_CLK0
D 84 BI FBC_D44 C27 FBC_D44 FBC_CLK0 G15
OUT 83 D
FBC_D45 B27 F15 FBC_CLK0#
84 BI FBC_D46 A27
FBC_D45 FBC_CLK0*
H21 FBC_CLK1
OUT 83
84 BI FBC_D47 G29
FBC_D46 FBC_CLK1
J21 FBC_CLK1#
OUT 84
84 BI FBC_D48 H20
FBC_D47 FBC_CLK1* OUT 84
84 BI FBC_D49 D18
FBC_D48
84 BI FBC_D50 G20
FBC_D49
84 BI FBC_D51 E20
FBC_D50
84 BI
Vinafix.com
FBC_D51
FBC_D52 F23
84 BI FBC_D53 E21
FBC_D52
84 BI FBC_D54 D21
FBC_D53
84 BI FBC_D55 E23
FBC_D54
84 BI FBC_D56 G24
FBC_D55
F8 FBC_WCK01
84 BI FBC_D57 H26
FBC_D56 FBC_WCK01
G8 FBC_WCK01#
OUT 83
84 BI FBC_D58 F24
FBC_D57 FBC_WCK01*
G9 FBC_WCKB01
OUT 83
84 BI FBC_D59 G26
FBC_D58 FBC_WCKB01
F9 FBC_WCKB01#
OUT 83
84 BI FBC_D60 F26
FBC_D59 FBC_WCKB01*
H12 FBC_WCK23
OUT 83
84 BI FBC_D61 D26
FBC_D60 FBC_WCK23
G12 FBC_WCK23#
OUT 83
84 BI FBC_D62 B26
FBC_D61 FBC_WCK23*
G14 FBC_WCKB23
OUT 83
84 BI FBC_D63 C26
FBC_D62 FBC_WCKB23
H14 FBC_WCKB23#
OUT 83
84 BI FBC_D63 FBC_WCKB23*
J27 FBC_WCK45
OUT 83
FBC_WCK45
H27 FBC_WCK45#
OUT 84
FBC_DBI0 A5
FBC_WCK45*
E29 FBC_WCKB45
OUT 84
83 IN FBC_DBI1 C8
FBC_DQM0 FBC_WCKB45
F29 FBC_WCKB45#
OUT 84
83 IN FBC_DBI2 J18
FBC_DQM1 FBC_WCKB45*
G23 FBC_WCK67
OUT 84
83 IN FBC_DBI3 F12
FBC_DQM2 FBC_WCK67
H23 FBC_WCK67#
OUT 84
83 IN FBC_DBI4 D29
FBC_DQM3 FBC_WCK67*
H24 FBC_WCKB67
OUT 84
84 IN FBC_DQM4 FBC_WCKB67
FBC_WCKB67#
OUT 84
C 84 IN FBC_DBI5 E27 FBC_DQM5 FBC_WCKB67* J24
OUT 84 C
FBC_DBI6 F20
84 IN FBC_DBI7 E26
FBC_DQM6
84 IN FBC_DQM7
FBC_EDC0 D5
83 BI FBC_EDC1 D8
FBC_DQS_WP0
83 BI FBC_EDC2 E17
FBC_DQS_WP1
83 BI FBC_EDC3 E12
FBC_DQS_WP2
TP50300
83 BI FBC_EDC4 E30
FBC_DQS_WP3
1
84 BI FBC_EDC5 B29
FBC_DQS_WP4
84 BI FBC_DQS_WP5 TP24
FBC_EDC6 G21
84 BI FBC_EDC7 E24
FBC_DQS_WP6
L17 FB_PLLAVDD
84 BI FBC_DQS_WP7 FBC_PLL_AVDD IN 75 76 78
1
1UF_6.3V_1
Y24 GND_710
Y25 GND_711
C50300
Y26
Y27
GND_712
GND_713
X6S OR X7R
Y28 GND_714
2
Y29 GND_715
Y30 GND_716
Y31 GND_717
PLACE UNDER GPU

B B
A A
INVENTEC
Vinafix.com TITLE
Block Diagram
50300 - 50399 SIZE

A3
CODE
CS
DOC.NUMBER
1310xxxxx-0-0
REV
X01
6 5 4 3 2 1
6 5 4 3 2 1
GPU FRAME BUFFER D

F F
U50000
5/22 FBD
FBD_D0 AK8 AD2 FBD_CMD0

85 BI FBD_D1 AK4
FBD_D0 FBD_CMD0
AD1 FBD_CMD1
BI 85
85 BI FBD_D2 AK2
FBD_D1 FBD_CMD1
AD4 FBD_CMD2_RST
BI 85
85 BI FBD_D3 AK3
FBD_D2 FBD_CMD2
AC1 FBD_CMD3
BI 85
85 BI FBD_D4 AK5
FBD_D3 FBD_CMD3
AC2 FBD_CMD4
BI 85
85 BI FBD_D5 AK6
FBD_D4 FBD_CMD4
AC3 FBD_CMD5
BI 85
85 BI FBD_D6 AK9
FBD_D5 FBD_CMD5
AA3 FBD_CMD6
BI 85
85 BI FBD_D7 AK7
FBD_D6 FBD_CMD6
AA2 FBD_CMD7
BI 85
85 BI FBD_D8 AG4
FBD_D7 FBD_CMD7
AA1 FBD_CMD8
BI 85
85 BI FBD_D9 AF9
FBD_D8 FBD_CMD8
AA4 FBD_CMD9
BI 85
85 BI FBD_D10 AG6
FBD_D9 FBD_CMD9
Y1 FBD_CMD10_CKE
BI 85
85 BI FBD_D11 AG7
FBD_D10 FBD_CMD10
Y2 FBD_CMD11
BI 85
85 BI FBD_D12 AJ4
FBD_D11 FBD_CMD11
Y3 FBD_CMD12
BI 85
85 BI FBD_D13 AJ5
FBD_D12 FBD_CMD12
V3 FBD_CMD13
BI 85
85 BI FBD_D14 AJ6
FBD_D13 FBD_CMD13
V2 FBD_CMD14
BI 85
85 BI FBD_D15 AG5
FBD_D14 FBD_CMD14
V1 FBD_CMD15
BI 85
85 BI FBD_D16 Y6
FBD_D15 FBD_CMD15
L3 FBD_CMD16
BI 85
E 85 BI FBD_D17 Y5
FBD_D16 FBD_CMD16
L2 FBD_CMD17
BI 86
E
85 BI FBD_D18 V5
FBD_D17 FBD_CMD17
L1 FBD_CMD18_RST
BI 86
85 BI FBD_D19 Y4
FBD_D18 FBD_CMD18
M4 FBD_CMD19
BI 86
85 BI FBD_D20 AA6
FBD_D19 FBD_CMD19
M1 FBD_CMD20
BI 86
85 BI FBD_D21 AA5
FBD_D20 FBD_CMD20
M2 FBD_CMD21
BI 86
85 BI FBD_D22 AC5
FBD_D21 FBD_CMD21
M3 FBD_CMD22
BI 86
85 BI FBD_D23 AC4
FBD_D22 FBD_CMD22
P3 FBD_CMD23
BI 86
85 BI FBD_D24 AD7
FBD_D23 FBD_CMD23
P2 FBD_CMD24
BI 86
85 BI FBD_D25 AC6
FBD_D24 FBD_CMD24
P1 FBD_CMD25
BI 86
85 BI FBD_D26 AF6
FBD_D25 FBD_CMD25
R4 FBD_CMD26_CKE
BI 86
85 BI FBD_D27 AD6
FBD_D26 FBD_CMD26
R1 FBD_CMD27
BI 86
85 BI FBD_D28 AF7
FBD_D27 FBD_CMD27
R2 FBD_CMD28
BI 86
85 BI FBD_D29 AF8
FBD_D28 FBD_CMD28
R3 FBD_CMD29
BI 86
85 BI FBD_D30 AF2
FBD_D29 FBD_CMD29
U3 FBD_CMD30
BI 86
85 BI FBD_D31 AF3
FBD_D30 FBD_CMD30
U2 FBD_CMD31
BI 86
P1V35S_FBVDDQ
85 BI FBD_D32 F4
FBD_D31 FBD_CMD31
V4 FBD_CMD32
BI 86
86 BI FBD_D33 E1
FBD_D32 FBD_CMD32
U1 FBD_CMD33
BI 85
86 BI FBD_D34 F3
FBD_D33 FBD_CMD33
AD3 FBD_DEBUG0
BI 86
86 BI FBD_D34 FBD_CMD34 R50420 1 2 60.4K_1%_2_DY
FBD_D35 F5 J3 FBD_DEBUG1 R50421 1 2 60.4K_1%_2_DY
86 BI FBD_D36 D2
FBD_D35 FBD_CMD35
86 BI FBD_D37 D1
FBD_D36
86 BI FBD_D38 C3
FBD_D37
86 BI FBD_D39 C2
FBD_D38
AC9
86 BI FBD_D40 J5
FBD_D39 FBD_DBG_RFU1
P9
86 BI FBD_D41 J4
FBD_D40 FBD_DBG_RFU2
86 BI FBD_D42 L8
FBD_D41
86 BI FBD_D43 J2
FBD_D42
D 86 BI FBD_D44 F1
FBD_D43
Y8 FBD_CLK0 D
86 BI FBD_D45 F2
FBD_D44 FBD_CLK0
Y7 FBD_CLK0#
OUT 85
86 BI FBD_D46 H4
FBD_D45 FBD_CLK0*
R8 FBD_CLK1
OUT 85
86 BI FBD_D47 H5
FBD_D46 FBD_CLK1
R7 FBD_CLK1#
OUT 86
86 BI FBD_D48 V7
FBD_D47 FBD_CLK1* OUT 86
86 BI FBD_D49 V8
FBD_D48
86 BI FBD_D50 V6
FBD_D49
86 BI FBD_D50
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FBD_D51 V9
86 BI FBD_D52 U4
FBD_D51
86 BI FBD_D53 R5
FBD_D52
86 BI FBD_D54 R6
FBD_D53
86 BI FBD_D55 U8
FBD_D54
86 BI FBD_D56 P6
FBD_D55
AJ8 FBD_WCK01
86 BI FBD_D57 R9
FBD_D56 FBD_WCK01
AJ7 FBD_WCK01#
OUT 85
86 BI FBD_D58 P4
FBD_D57 FBD_WCK01*
AG8 FBD_WCKB01
OUT 85
86 BI FBD_D59 P5
FBD_D58 FBD_WCKB01
AG9 FBD_WCKB01#
OUT 85
86 BI FBD_D60 L7
FBD_D59 FBD_WCKB01*
AD8 FBD_WCK23
OUT 85
86 BI FBD_D61 L6
FBD_D60 FBD_WCK23
AD9 FBD_WCK23#
OUT 85
86 BI FBD_D62 L4
FBD_D61 FBD_WCK23*
AC7 FBD_WCKB23
OUT 85
86 BI FBD_D63 L5
FBD_D62 FBD_WCKB23
AC8 FBD_WCKB23#
OUT 85
86 BI FBD_D63 FBD_WCKB23*
J6 FBD_WCK45
OUT 85
FBD_WCK45
J7 FBD_WCK45#
OUT 86
FBD_DBI0 AJ1
FBD_WCK45*
H7 FBD_WCKB45
OUT 86
85 IN FBD_DBI1 AG1
FBD_DQM0 FBD_WCKB45
H6 FBD_WCKB45#
OUT 86
85 IN FBD_DBI2 AA7
FBD_DQM1 FBD_WCKB45*
P8 FBD_WCK67
OUT 86
85 IN FBD_DBI3 AD5
FBD_DQM2 FBD_WCK67
P7 FBD_WCK67#
OUT 86
85 IN FBD_DBI4 D3
FBD_DQM3 FBD_WCK67*
M7 FBD_WCKB67
OUT 86
C 86 IN FBD_DBI5 H3
FBD_DQM4 FBD_WCKB67
M8 FBD_WCKB67#
OUT 86
C
86 IN FBD_DBI6 U5
FBD_DQM5 FBD_WCKB67* OUT 86
86 IN FBD_DBI7 M9
FBD_DQM6
86 IN FBD_DQM7
FBD_EDC0 AJ3
85 BI FBD_EDC1 AG2
FBD_DQS_WP0
85 BI FBD_EDC2 AA9
FBD_DQS_WP1
85 BI FBD_EDC3 AF4
FBD_DQS_WP2
TP50400
85 BI FBD_EDC4 E3
FBD_DQS_WP3
1
86 BI FBD_EDC5 H2
FBD_DQS_WP4
86 BI FBD_DQS_WP5 TP24
FBD_EDC6 U6
86 BI FBD_EDC7 M5
FBD_DQS_WP6
V11 FB_PLLAVDD
86 BI FBD_DQS_WP7 FBD_PLL_AVDD
1
IN 75 76 77
Y32 GND_0718 1UF_6.3V_1

Y33 GND_0719
C50400
Y34
Y35
GND_0720
GND_0721
X6S OR X7R
Y36 GND_0722
2
Y37 GND_0723
Y38 GND_0724
Y39 GND_0725
N18E-G3
PLACE UNDER GPU
B B
FBD N/A
A A
INVENTEC
Vinafix.com TITLE
50400 - 50499 SIZE

Block
CODE
Diagram
DOC.NUMBER REV
6 5 4 3 2 1
6 5 4 3 2 1
U50500
P1V35S_FBVDDQ
U50500
A11 VSS_1 VDD_1 A1

F A13 VSS_2 VDD_2 A14 F
A2 VSS_3 VDD_3 E10
A4 VSS_4 VDD_4 E5
FBA_CMD0 H3 K1 FBA1_VREFC
B1 VSS_5 VDD_5 H13 75 IN FBA_CMD9 G11
CA0_A VREFC
B14 H2 75 IN CA1_A
2
VSS_6 VDD_6
FBA_CMD8 G4
C10 VSS_7 VDD_7 L13 75 IN FBA_CMD32 H12
CA2_A
C12 VSS_8 VDD_8 L2 U50500

75 IN FBA_CMD7 H5
CA3_A
R50510
C3 P10 U50500 79 75 IN CA4_A
VSS_9 VDD_9
FBA_CMD11 H10 1K_1%_2
C5 VSS_10 VDD_10 P5 79 75 IN FBA_CMD15 J12
CA5_A
I
D1 V1 79 75 IN CA6_A
1
VSS_11 VDD_11
NORMAL NORMAL FBA_CMD14 J11
D12 VSS_12 VDD_12 V14 79 75 IN FBA_CMD3 J4
CA7_A
D14 VSS_13
79 75 IN FBA_CMD1 J3
CA8_A
D3 VSS_14 75 BI FBA_D4 B4 DQ1_A

x16 x8 79 75 IN FBA_CMD6 J5
CA9_A
E11 VSS_15 75 BI FBA_D7 A3 DQ4_A 75 BI FBA_D30 U4 DQ1_B

NC 79 75 IN FBA_CMD10_CKE G10
CABI_A
E4 P1V35S_FBVDDQ FBA_D1 B3 FBA_D29 V3 NC 79 75 IN CKE_A
F1
VSS_16 75 BI FBA_D5 B2
DQ7_A 75 BI FBA_D28 U3
DQ0_B
NC
F12
VSS_17 75 BI FBA_D3 E3
DQ3_B
NC TCK N5
F14
VSS_18
B10
75 BI FBA_D6 E2
DQ6_A 75 BI FBA_D25 P3
DQ2_B
NC TDI F10
F3
VSS_19 VDDQ_1
B5
75 BI FBA_D2 F2
DQ5_B
NC TDO N10
G1
VSS_20 VDDQ_2
C1
75 BI FBA_D0 G2
DQ3_A 75 BI FBA_D24 N2
DQ4_B
NC TMS F5
G12
VSS_21 VDDQ_3
C11
75 BI DQ0_A 75 BI FBA_D26 M2
DQ7_B
NC
G14
VSS_22 VDDQ_4
C14 FBA_EDC0 C2
75 BI DQ6_B
G3
VSS_23 VDDQ_5
C4
75 IN FBA_DBI0 D2
EDC0_A
FBA_EDC3 T2 GND 75 IN FBA_CMD4 L3 CA0_B
H11
VSS_24 VDDQ_6
E1
75 IN DBI0_A 75 IN FBA_DBI3 R2
EDC0_B
NC 75 IN FBA_CMD12 M11 CA1_B
H4
VSS_25 VDDQ_7
E14 FBA_WCK01 D4
75 IN DBI0_B
75 IN FBA_CMD5 M4 CA2_B
L11
VSS_26 VDDQ_8
F11
75 IN FBA_WCK01# D5
WCK0_A
FBA_WCKB23 R4 NC 75 IN FBA_CMD13 L12 CA3_B
L4
VSS_27 VDDQ_9
F4
75 IN WCK0_A* 75 IN FBA_WCKB23# R5
WCK0_B
NC 79 75 IN FBA_CMD7 L5 CA4_B
M1
VSS_28 VDDQ_10
H1
75 IN WCK0_B*
79 75 IN FBA_CMD11 L10 CA5_B
VSS_29 VDDQ_11
FBA_CMD15 K12
M12 VSS_30 VDDQ_12 H14 x16 x8
75 BI FBA_D23 U11 DQ9_B
79 75 IN FBA_CMD14
CA6_B
E M14 J13 FBA_D8 B11 NC FBA_D22 V12 79 75 IN K11 CA7_B E
M3
VSS_31 VDDQ_13
J2
75 BI FBA_D15 A12
DQ11_A
NC
75 BI FBA_D20 U12
DQ10_B
79 75 IN FBA_CMD3 K4 CA8_B
N1
VSS_32 VDDQ_14
K13
75 BI FBA_D13 B12
DQ14_A
NC
75 BI FBA_D17 U13
DQ13_B
79 75 IN FBA_CMD1 K3 CA9_B
N12
VSS_33 VDDQ_15
K2
75 BI FBA_D14 B13
DQ12_A
NC
75 BI FBA_D21 P12
DQ8_B
79 75 IN FBA_CMD6 K5 CABI_B R50500
N14
VSS_34 VDDQ_16
L1
75 BI FBA_D12 E12
DQ10_A
NC
75 BI FBA_D16 P13
DQ12_B
79 75 IN FBA_CMD10_CKE M10 CKE_B 121_1%_2
N3
VSS_35 VDDQ_17
L14
75 BI FBA_D10 E13
DQ13_A
NC
75 BI FBA_D19 N13
DQ11_B
ZQ_A J14 FBA_ZQ_1_A 1 2
P11
VSS_36 VDDQ_18
N11
75 BI FBA_D11 F13
DQ8_A
NC
75 BI FBA_D18 M13
DQ14_B
ZQ_B K14 FBA_ZQ_1_B 1 2
P4
VSS_37 VDDQ_19
N4
75 BI FBA_D9 G13
DQ9_A
NC
75 BI DQ15_B
VSS_38 VDDQ_20 75 BI DQ15_A 121_1%_2
R1 P1 FBA_EDC2 T13
R12
VSS_39 VDDQ_21
P14 FBA_EDC1 C13 GND
75 IN FBA_DBI2 R13
EDC1_B
R50501
R14
VSS_40 VDDQ_22
T1
75 IN FBA_DBI1 D13
EDC1_A 75 IN DBI1_B
79 75 IN FBA_CMD2_RST J1 RESET*
R3
VSS_41 VDDQ_23
T11
75 IN DBI1_A NC
FBA_WCK23 R11
T10
VSS_42 VDDQ_24
T14 FBA_WCKB01 D11 NC
75 IN FBA_WCK23# R10
WCK1_B
T12
VSS_43 VDDQ_25
T4
75 IN FBA_WCKB01# D10
WCK1_A
NC
75 IN WCK1_B*
T3
VSS_44 VDDQ_26
U10
75 IN WCK1_A*
75 IN FBA_CLK0# K10 CLK*
VSS_45 VDDQ_27
FBA_CLK0 J10
T5 VSS_46 VDDQ_28 U5 75 IN CLK
U1 VSS_47
U14 VSS_48 MICRON_MT61K256M32JE_14_A_FBGA_180P MICRON_MT61K256M32JE_14_A_FBGA_180P
RFU_A G5
V11 VSS_49
RFU_B M5
V13 VSS_50
V2 VSS_51
V4 VSS_52
P1V8S_AON1
SAMSUNG K4Z80325BC-HC14
VPP_1 A10
VPP_2 A5 6019B1847601
VPP_3 V10
VPP_4 V5
D MICRON MT61K256M32JE-14:A MICRON_MT61K256M32JE_14_A_FBGA_180P D
6019B1847701
MICRON_MT61K256M32JE_14_A_FBGA_180P
Vinafix.com
P1V35S_FBVDDQ P1V35S_FBVDDQ P1V35S_FBVDDQ
FBA_CMD10_CKE 1 R50505 2 FBA_CKE_L

79 75 BI
10K_1%_2
P1V8S_AON1
CLOSE TO VRAM CLOSE TO VRAM R50506 2
FBA_CMD2_RST 1
79 75 BI FBA_RST*
10K_1%_2
C50510 C50511 C50512 C50513 C50514 C50515
10UF_4V_3 10UF_4V_3 10UF_4V_3 10UF_4V_3
1
1
10UF_4V_3 10UF_4V_3
C P1V35S_FBVDDQ
P1V35S_FBVDDQ
C
2
2
22UF_4V_3
22UF_4V_3
22UF_4V_3
22UF_4V_3
22UF_4V_3
22UF_4V_3
1
1
1
C50521
C50516
C50517
C50518
C50519
C50520
OPTION
C50546 C50547 C50548 C50549 C50550
2
4.7UF_6.3V_2 1UF_6.3V_1 1UF_6.3V_1

2
1UF_6.3V_1 1UF_6.3V_1
AROUND UNDER VRAM AROUND UNDER VRAM
P1V35S_FBVDDQ P1V35S_FBVDDQ
P1V35S_FBVDDQ
1
1
1
B B
2
2
2
RIGHT UNDER VRAM RIGHT UNDER VRAM RIGHT UNDER VRAM CLOSE TO VRAM
C50551 C50552 C50553 C50554 C50555 C50556
C50522 C50523 C50524 C50525 C50526 C50527 C50528 C50529 C50530 C50531 C50532 C50533
1UF_6.3V_1 1UF_6.3V_1 1UF_6.3V_1
1UF_6.3V_1 1UF_6.3V_1 1UF_6.3V_1 1UF_6.3V_1 1UF_6.3V_1 1UF_6.3V_1
1UF_6.3V_1 1UF_6.3V_1 1UF_6.3V_1
P1V35S_FBVDDQ
P1V35S_FBVDDQ
P1V35S_FBVDDQ
1
1
1
1
1
2
2
2
2
CLOSE TO VRAM CLOSE TO VRAM

CLOSE TO VRAM
C50557 C50558 C50559 C50560 C50561 C50562
C50540 C50541 C50542 C50543 C50544 C50545
C50534 C50535 C50536 C50537 C50538 C50539 1UF_6.3V_1 1UF_6.3V_1 1UF_6.3V_1
1UF_6.3V_1 1UF_6.3V_1 1UF_6.3V_1
A 1UF_6.3V_1 1UF_6.3V_1 1UF_6.3V_1
1UF_6.3V_1 1UF_6.3V_1 1UF_6.3V_1 A
INVENTEC
Vinafix.com TITLE
Block Diagram

SIZE
A3
CODE
CS
DOC.NUMBER
1310xxxxx-0-0
REV
X01
6 5 4 3 2 1
6 5 4 3 2 1
U50600
P1V35S_FBVDDQ
U50600
F F
A11 VSS_1 VDD_1 A1
A13 VSS_2 VDD_2 A14
A2 VSS_3 VDD_3 E10
A4 VSS_4 VDD_4 E5
FBA_CMD20 H3 K1 FBA2_VREFC
CA0_A VREFC

CA1_A
C10 L13 U50600 U50600 75 IN CA2_A
2
VSS_7 VDD_7
FBA_CMD29 H12
C12 VSS_8 VDD_8 L2 75 IN FBA_CMD23 H5
CA3_A
C3 VSS_9 VDD_9 P10 80 75 IN FBA_CMD27 H10

CA4_A
R50610
C5 VSS_10 VDD_10 P5 80 75 IN FBA_CMD30 J12
CA5_A
D1 V1 80 75 IN CA6_A 1K_1%_2
VSS_11 VDD_11
FBA_CMD31 J11
I
D12 V14 NORMAL NORMAL 80 75 IN CA7_A
1
VSS_12 VDD_12
FBA_CMD19 J4
D14 VSS_13
80 75 IN FBA_CMD17 J3
CA8_A
D3 VSS_14 75 BI FBA_D39 B4 DQ1_A

x16 x8 80 75 IN FBA_CMD22 J5
CA9_A
E11 VSS_15 75 BI FBA_D35 A3 DQ4_A 75 BI FBA_D57 U4 DQ1_B

NC 80 75 IN FBA_CMD26_CKE G10
CABI_A
E4 P1V35S_FBVDDQ FBA_D32 B3 FBA_D56 V3 NC 80 75 IN CKE_A
F1
VSS_16 75 BI FBA_D38 B2
DQ0_B
NC
F12
VSS_17 75 BI FBA_D34 E3
DQ3_B
NC TCK N5
F14
VSS_18
B10
75 BI FBA_D33 E2
DQ2_B
NC TDI F10
F3
VSS_19 VDDQ_1
B5
75 BI FBA_D37 F2
DQ5_B
NC TDO N10
G1
VSS_20 VDDQ_2
C1
75 BI FBA_D36 G2
DQ3_A 75 BI FBA_D63 N2
DQ4_B
NC TMS F5
G12
VSS_21 VDDQ_3
C11
75 BI DQ0_A 75 BI FBA_D62 M2
DQ7_B
NC
G14
VSS_22 VDDQ_4
C14 FBA_EDC4 C2
75 BI DQ6_B
G3
VSS_23 VDDQ_5
C4
75 IN FBA_DBI4 D2
EDC0_A
FBA_EDC7 T2 GND 75 IN FBA_CMD16 L3 CA0_B
H11
VSS_24 VDDQ_6
E1
75 IN DBI0_A 75 IN FBA_DBI7 R2
EDC0_B
NC 75 IN FBA_CMD25 M11 CA1_B
H4
VSS_25 VDDQ_7
E14 FBA_WCK45 D4
75 IN DBI0_B
75 IN FBA_CMD24 M4 CA2_B
L11
VSS_26 VDDQ_8
F11
75 IN FBA_WCK45# D5
WCK0_A
FBA_WCKB67 R4 NC 75 IN FBA_CMD33 L12 CA3_B
L4
VSS_27 VDDQ_9
F4
75 IN WCK0_A* 75 IN FBA_WCKB67# R5
WCK0_B
NC 80 75 IN FBA_CMD23 L5 CA4_B
VSS_28 VDDQ_10 75 IN WCK0_B*
80 75 IN FBA_CMD27 L10 CA5_B
E M1 VSS_29 VDDQ_11 H1
FBA_CMD30 K12 E
M12 VSS_30 VDDQ_12 H14 x16 x8
80 75 IN FBA_CMD31 K11
CA6_B
M14 VSS_31 VDDQ_13 J13 75 BI FBA_D43 B11 DQ11_A

NC
75 BI FBA_D50 V12 DQ10_B
CA7_B
M3 VSS_32 VDDQ_14 J2 75 BI FBA_D46 A12 DQ14_A

NC
CA8_B
N1 VSS_33 VDDQ_15 K13 75 BI FBA_D44 B12 DQ12_A

NC
CA9_B
N12 VSS_34 VDDQ_16 K2 75 BI FBA_D42 B13 DQ10_A

NC
75 BI FBA_D52 P12 DQ12_B
80 75 IN FBA_CMD26_CKE M10
CABI_B
N14 L1 FBA_D45 E12 NC FBA_D51 P13 80 75 IN CKE_B R50600

VSS_35 VDDQ_17 75 BI DQ13_A 75 BI DQ11_B
ZQ_A J14 FBA_ZQ_2_A 1 121_1%_2 2
N3 L14 FBA_D40 E13 NC FBA_D54 N13
P11
VSS_36 VDDQ_18
N11
75 BI FBA_D41 F13
DQ8_A
NC
75 BI FBA_D55 M13
DQ14_B
ZQ_B K14 FBA_ZQ_2_B 1 2
P4
VSS_37 VDDQ_19
N4
75 BI FBA_D47 G13
DQ9_A
NC
75 BI DQ15_B
121_1%_2
R1
VSS_38 VDDQ_20
P1
75 BI DQ15_A
FBA_EDC6 T13 R50601
R12
VSS_39 VDDQ_21
P14 FBA_EDC5 C13 GND
75 IN FBA_DBI6 R13
EDC1_B
R14
VSS_40 VDDQ_22
T1
75 IN FBA_DBI5 D13
EDC1_A 75 IN DBI1_B
80 75 IN FBA_CMD18_RST J1 RESET*
R3
VSS_41 VDDQ_23
T11
75 IN DBI1_A NC
FBA_WCK67 R11
T10
VSS_42 VDDQ_24
T14 FBA_WCKB45 D11 NC
75 IN FBA_WCK67# R10
WCK1_B
T12
VSS_43 VDDQ_25
T4
75 IN FBA_WCKB45# D10
WCK1_A
NC
75 IN WCK1_B*
T3
VSS_44 VDDQ_26
U10
75 IN WCK1_A*
75 IN FBA_CLK1# K10 CLK*
VSS_45 VDDQ_27
FBA_CLK1 J10
U1 VSS_47
RFU_A G5
V11 VSS_49
RFU_B M5
V13 VSS_50
V2 VSS_51
V4 VSS_52
P1V8S_AON1
VPP_1 A10
VPP_2 A5
D VPP_3 V10 D
VPP_4 V5
Vinafix.com P1V35S_FBVDDQ
FBA_CKE_L
FBA_CMD26_CKE 1 R50605 2 FBA_CKE_H

80 75 BI
10K_1%_2
CLOSE TO VRAM CLOSE TO VRAM P1V8S_AON1

FBA_RST*
C50610 C50611 C50612 C50613 C50614 C50615
FBA_CMD18_RST 1 R50606 2
C 10UF_4V_3 10UF_4V_3 10UF_4V_3 10UF_4V_3
80 75 BI FBA_RST* C
1
10K_1%_2
10UF_4V_3 10UF_4V_3
P1V35S_FBVDDQ
P1V35S_FBVDDQ 2
2
22UF_4V_3
22UF_4V_3
22UF_4V_3
22UF_4V_3
22UF_4V_3
22UF_4V_3
1
1
C50621
C50616
C50617
C50618
C50619
C50620
OPTION
C50646 C50647 C50648 C50649 C50650
4.7UF_6.3V_2 1UF_6.3V_1 1UF_6.3V_1
2
1UF_6.3V_1 1UF_6.3V_1
P1V35S_FBVDDQ
1
1
1
B B
2
2
2
C50651 C50652 C50653 C50654 C50655 C50656
C50622 C50623 C50624 C50625 C50626 C50627 C50628 C50629 C50630 C50631 C50632 C50633
1UF_6.3V_1 1UF_6.3V_1 1UF_6.3V_1
1UF_6.3V_1 1UF_6.3V_1 1UF_6.3V_1
P1V35S_FBVDDQ
P1V35S_FBVDDQ
P1V35S_FBVDDQ
1
1
1
2
2

CLOSE TO VRAM
A C50634 C50635 C50636 C50637 C50638 C50639
C50657 C50658 C50659 C50660 C50661 C50662 A
1UF_6.3V_1 1UF_6.3V_1 1UF_6.3V_1
1UF_6.3V_1 1UF_6.3V_1
1UF_6.3V_1
1UF_6.3V_1
1UF_6.3V_1 1UF_6.3V_1
C50640
1UF_6.3V_1
C50641 C50642 C50643 C50644
1UF_6.3V_1 1UF_6.3V_1
C50645
1UF_6.3V_1 1UF_6.3V_1 1UF_6.3V_1
INVENTEC
Vinafix.com
1UF_6.3V_1 1UF_6.3V_1 1UF_6.3V_1
TITLE
Block Diagram

SIZE
A3
CODE
CS
DOC.NUMBER
1310xxxxx-0-0
REV
X01
6 5 4 3 2 1
6 5 4 3 2 1
U50700
P1V35S_FBVDDQ
U50700

A13 VSS_2 VDD_2 A14
A2 VSS_3 VDD_3 E10
A4 VSS_4 VDD_4 E5
FBB_CMD0 H3 K1 FBB1_VREFC
B1 VSS_5 VDD_5 H13 76 IN FBB_CMD9 G11
CA0_A VREFC

CA1_A
C10 VSS_7 VDD_7 L13 U50700 U50700 76 IN FBB_CMD32 H12

CA2_A
C12 L2 76 IN CA3_A
2
VSS_8 VDD_8
1K_1%_2
FBB_CMD7 H5
81 76 IN CA4_A
R50710
C3 VSS_9 VDD_9 P10
FBB_CMD11 H10
C5 VSS_10 VDD_10 P5 81 76 IN FBB_CMD15 J12
CA5_A
D1 VSS_11 VDD_11 V1 81 76 IN FBB_CMD14 J11

CA6_A

VSS_12 VDD_12
FBB_CMD3 J4
I
D14 81 76 IN CA8_A
1
VSS_13
FBB_CMD1 J3
D3 VSS_14 76 BI FBB_D1 B4 DQ1_A
x16 x8 81 76 IN FBB_CMD6 J5
CA9_A
E11 VSS_15 76 BI FBB_D6 A3 DQ4_A 76 BI FBB_D24 U4 DQ1_B

NC 81 76 IN FBB_CMD10_CKE G10
CABI_A
E4 VSS_16 P1V35S_FBVDDQ 76 BI FBB_D2 B3 DQ7_A 76 BI FBB_D30 V3 DQ0_B

NC 81 76 IN CKE_A
F1 FBB_D4 B2 FBB_D29 U3 NC
F12
VSS_17 76 BI FBB_D5 E3
DQ5_A 76 BI FBB_D31 U2
DQ3_B
NC TCK N5
F14
VSS_18
B10
76 BI FBB_D3 E2
DQ6_A 76 BI FBB_D25 P3
DQ2_B
NC TDI F10
F3
VSS_19 VDDQ_1
B5
76 BI FBB_D0 F2
DQ5_B
NC TDO N10
G1
VSS_20 VDDQ_2
C1
76 BI FBB_D7 G2
DQ3_A 76 BI FBB_D27 N2
DQ4_B
NC TMS F5
G12
VSS_21 VDDQ_3
C11
76 BI DQ0_A 76 BI FBB_D28 M2
DQ7_B
NC
G14
VSS_22 VDDQ_4
C14 FBB_EDC0 C2
76 BI DQ6_B
G3
VSS_23 VDDQ_5
C4
76 IN FBB_DBI0 D2
EDC0_A
FBB_EDC3 T2 GND 76 IN FBB_CMD4 L3 CA0_B
H11
VSS_24 VDDQ_6
E1
76 IN DBI0_A 76 IN FBB_DBI3 R2
EDC0_B
NC 76 IN FBB_CMD12 M11 CA1_B
H4
VSS_25 VDDQ_7
E14 FBB_WCK01 D4
76 IN DBI0_B
76 IN FBB_CMD5 M4 CA2_B
L11
VSS_26 VDDQ_8
F11
76 IN FBB_WCK01# D5
WCK0_A
FBB_WCKB23 R4 NC 76 IN FBB_CMD13 L12 CA3_B
L4
VSS_27 VDDQ_9
F4
76 IN WCK0_A* 76 IN FBB_WCKB23# R5
WCK0_B
NC 81 76 IN FBB_CMD7 L5 CA4_B
M1
VSS_28 VDDQ_10
H1
76 IN WCK0_B*
81 76 IN FBB_CMD11 L10 CA5_B
VSS_29 VDDQ_11
FBB_CMD15 K12
E M12 VSS_30 VDDQ_12 H14 x16 x8
76 BI FBB_D21 U11 DQ9_B
81 76 IN FBB_CMD14 K11
CA6_B
E
M14 VSS_31 VDDQ_13 J13 76 BI FBB_D13 B11 DQ11_A
NC
76 BI FBB_D16 V12 DQ10_B
CA7_B
M3 VSS_32 VDDQ_14 J2 76 BI FBB_D14 A12 DQ14_A

NC
CA8_B
N1 VSS_33 VDDQ_15 K13 76 BI FBB_D12 B12 DQ12_A

NC
CA9_B
N12 K2 FBB_D11 B13 NC FBB_D18 P12 81 76 IN CABI_B R50700

N14
VSS_34 VDDQ_16
L1
76 BI FBB_D15 E12
DQ10_A
NC
76 BI FBB_D22 P13
DQ12_B
81 76 IN FBB_CMD10_CKE M10 CKE_B
ZQ_A J14 FBB_ZQ_1_A 1 121_1%_2
2
N3 L14 FBB_D8 E13 NC FBB_D23 N13
P11
VSS_36 VDDQ_18
N11
76 BI FBB_D9 F13
DQ8_A
NC
76 BI FBB_D19 M13
DQ14_B
ZQ_B K14 FBB_ZQ_1_B 1 2
P4
VSS_37 VDDQ_19
N4
76 BI FBB_D10 G13
DQ9_A
NC
76 BI DQ15_B
121_1%_2
R1
VSS_38 VDDQ_20
P1
76 BI DQ15_A
FBB_EDC2 T13
VSS_39 VDDQ_21 76 IN EDC1_B R50701
R12 P14 FBB_EDC1 C13 GND FBB_DBI2 R13
R14
VSS_40 VDDQ_22
T1
76 IN FBB_DBI1 D13
EDC1_A 76 IN DBI1_B
81 76 IN FBB_CMD2_RST J1 RESET*
R3
VSS_41 VDDQ_23
T11
76 IN DBI1_A NC
FBB_WCK23 R11
T10
VSS_42 VDDQ_24
T14 FBB_WCKB01 D11 NC
76 IN FBB_WCK23# R10
WCK1_B
T12
VSS_43 VDDQ_25
T4
76 IN FBB_WCKB01# D10
WCK1_A
NC
76 IN WCK1_B*
T3
VSS_44 VDDQ_26
U10
76 IN WCK1_A*
76 IN FBB_CLK0# K10 CLK*
VSS_45 VDDQ_27
FBB_CLK0 J10
U1 VSS_47
RFU_A G5
V11 VSS_49
RFU_B M5
V13 VSS_50
V2 VSS_51
V4 VSS_52
P1V8S_AON1
VPP_1 A10
VPP_2 A5
VPP_3 V10
D VPP_4 V5
D
P1V35S_FBVDDQ
P1V35S_FBVDDQ
Vinafix.com 81 76 BI FBB_CMD10_CKE 1 R50705 2
10K_1%_2
P1V35S_FBVDDQ
FBB_CKE_L
FBB_CMD2_RST 1 R50706 2
81 76 BI FBB_RST*
10K_1%_2
C50710 C50711 C50712 C50713 C50714 C50715

C C
10UF_4V_3 10UF_4V_3 10UF_4V_3 10UF_4V_3 1
1
10UF_4V_3 10UF_4V_3
2
2
22UF_4V_3
22UF_4V_3
22UF_4V_3
22UF_4V_3
22UF_4V_3
22UF_4V_3
1
1
C50716
C50717
C50718
C50719
C50720
C50721
OPTION
C50746 C50747 C50748 C50749 C50750
4.7UF_6.3V_2 1UF_6.3V_1 1UF_6.3V_1
2
1UF_6.3V_1 1UF_6.3V_1
P1V35S_FBVDDQ
1
1
1
B B
2
2
2
C50751 C50752 C50753 C50754 C50755 C50756
C50722 C50723 C50724 C50725 C50726 C50727 C50728 C50729 C50730 C50731 C50732 C50733
1UF_6.3V_1 1UF_6.3V_1 1UF_6.3V_1
1UF_6.3V_1 1UF_6.3V_1 1UF_6.3V_1
P1V35S_FBVDDQ
P1V35S_FBVDDQ
P1V35S_FBVDDQ
1
1
1
2
2

A CLOSE TO VRAM A
C50757 C50758 C50759 C50760 C50761 C50762
C50734
1UF_6.3V_1
C50735 C50736 C50737
1UF_6.3V_1
C50738 C50739
1UF_6.3V_1 C50740 C50741 C50742 C50743 C50744 C50745
1UF_6.3V_1 1UF_6.3V_1
1UF_6.3V_1
1UF_6.3V_1
1UF_6.3V_1 1UF_6.3V_1 INVENTEC
Vinafix.com
1UF_6.3V_1 1UF_6.3V_1 1UF_6.3V_1 TITLE
Block Diagram

SIZE
A3
CODE
CS
DOC.NUMBER
1310xxxxx-0-0
REV
X01
6 5 4 3 2 1
6 5 4 3 2 1
U50800
P1V35S_FBVDDQ
U50800
A11 VSS_1 VDD_1 A1

A2 VSS_3 VDD_3 E10
A4 VSS_4 VDD_4 E5
FBB_CMD20 H3 K1 FBB2_VREFC
CA0_A VREFC

CA1_A
C10 L13 U50800 U50800 76 IN CA2_A
2
VSS_7 VDD_7
FBB_CMD29 H12
C12 VSS_8 VDD_8 L2 76 IN FBB_CMD23 H5
CA3_A
C3 VSS_9 VDD_9 P10 82 76 IN FBB_CMD27 H10

CA4_A
R50810
C5 VSS_10 VDD_10 P5 82 76 IN FBB_CMD30 J12
CA5_A
D1 V1 82 76 IN CA6_A 1K_1%_2
VSS_11 VDD_11
FBB_CMD31 J11
I
1
VSS_12 VDD_12
FBB_CMD19 J4
D14 VSS_13
82 76 IN FBB_CMD17 J3
CA8_A
D3 VSS_14 76 BI FBB_D35 B4 DQ1_A

x16 x8 82 76 IN FBB_CMD22 J5
CA9_A
E11 VSS_15 76 BI FBB_D33 A3 DQ4_A 76 BI FBB_D62 U4 DQ1_B

NC 82 76 IN FBB_CMD26_CKE G10
CABI_A
E4 VSS_16 P1V35S_FBVDDQ 76 BI FBB_D32 B3 DQ7_A 76 BI FBB_D59 V3 DQ0_B

NC 82 76 IN CKE_A
F1 FBB_D36 B2 FBB_D57 U3 NC
F12
VSS_17 76 BI FBB_D39 E3
DQ5_A 76 BI FBB_D63 U2
DQ3_B
NC TCK N5
F14
VSS_18
B10
76 BI FBB_D34 E2
DQ2_B
NC TDI F10
F3
VSS_19 VDDQ_1
B5
76 BI FBB_D37 F2
DQ5_B
NC TDO N10
G1
VSS_20 VDDQ_2
C1
76 BI FBB_D38 G2
DQ3_A 76 BI FBB_D60 N2
DQ4_B
NC TMS F5
G12
VSS_21 VDDQ_3
C11
76 BI DQ0_A 76 BI FBB_D58 M2
DQ7_B
NC
G14
VSS_22 VDDQ_4
C14 FBB_EDC4 C2
76 BI DQ6_B
G3
VSS_23 VDDQ_5
C4
76 IN FBB_DBI4 D2
EDC0_A
FBB_EDC7 T2 GND 76 IN FBB_CMD16 L3 CA0_B
H11
VSS_24 VDDQ_6
E1
76 IN DBI0_A 76 IN FBB_DBI7 R2
EDC0_B
NC 76 IN FBB_CMD25 M11 CA1_B
H4
VSS_25 VDDQ_7
E14 FBB_WCK45 D4
76 IN DBI0_B
76 IN FBB_CMD24 M4 CA2_B
L11
VSS_26 VDDQ_8
F11
76 IN FBB_WCK45# D5
WCK0_A
FBB_WCKB67 R4 NC 76 IN FBB_CMD33 L12 CA3_B
L4
VSS_27 VDDQ_9
F4
76 IN WCK0_A* 76 IN FBB_WCKB67# R5
WCK0_B
NC 82 76 IN FBB_CMD23 L5 CA4_B
M1
VSS_28 VDDQ_10
H1
76 IN WCK0_B*
82 76 IN FBB_CMD27 L10 CA5_B
VSS_29 VDDQ_11
FBB_CMD30 K12
M12 VSS_30 VDDQ_12 H14 x16 x8
82 76 IN FBB_CMD31
CA6_B
E M14 J13 FBB_D42 B11 NC FBB_D48 V12 82 76 IN K11 CA7_B E
M3
VSS_31 VDDQ_13
J2
76 BI FBB_D43 A12
DQ11_A
NC
76 BI FBB_D52 U12
DQ10_B
82 76 IN FBB_CMD19 K4 CA8_B
N1
VSS_32 VDDQ_14
K13
76 BI FBB_D40 B12
DQ14_A
NC
76 BI FBB_D50 U13
DQ13_B
82 76 IN FBB_CMD17 K3 CA9_B
N12
VSS_33 VDDQ_15
K2
76 BI FBB_D45 B13
DQ12_A
NC
76 BI FBB_D49 P12
DQ8_B
82 76 IN FBB_CMD22 K5 CABI_B
N14
VSS_34 VDDQ_16
L1
76 BI FBB_D41 E12
DQ10_A
NC
76 BI FBB_D51 P13
DQ12_B
82 76 IN FBB_CMD26_CKE M10 CKE_B R50800
ZQ_A J14 FBB_ZQ_2_A 1 121_1%_2 2
N3 L14 FBB_D44 E13 NC FBB_D53 N13
P11
VSS_36 VDDQ_18
N11
76 BI FBB_D46 F13
DQ8_A
NC
76 BI FBB_D54 M13
DQ14_B
ZQ_B K14 FBB_ZQ_2_B 1 2
P4
VSS_37 VDDQ_19
N4
76 BI FBB_D47 G13
DQ9_A
NC
76 BI DQ15_B
121_1%_2
R1
VSS_38 VDDQ_20
P1
76 BI DQ15_A
FBB_EDC6 T13 R50801
R12
VSS_39 VDDQ_21
P14 FBB_EDC5 C13 GND
76 IN FBB_DBI6 R13
EDC1_B
R14
VSS_40 VDDQ_22
T1
76 IN FBB_DBI5 D13
EDC1_A 76 IN DBI1_B
82 76 IN FBB_CMD18_RST J1 RESET*
R3
VSS_41 VDDQ_23
T11
76 IN DBI1_A NC
FBB_WCK67 R11
T10
VSS_42 VDDQ_24
T14 FBB_WCKB45 D11 NC
76 IN FBB_WCK67# R10
WCK1_B
T12
VSS_43 VDDQ_25
T4
76 IN FBB_WCKB45# D10
WCK1_A
NC
76 IN WCK1_B*
T3
VSS_44 VDDQ_26
U10
76 IN WCK1_A*
76 IN FBB_CLK1# K10 CLK*
VSS_45 VDDQ_27
FBB_CLK1 J10
U1 VSS_47
RFU_A G5
V11 VSS_49
RFU_B M5
V13 VSS_50
V2 VSS_51
V4 VSS_52
P1V8S_AON1
VPP_1 A10
VPP_2 A5
VPP_3 V10
VPP_4 V5
D MICRON_MT61K256M32JE_14_A_FBGA_180P D
P1V35S_FBVDDQ P1V35S_FBVDDQ Vinafix.com

P1V35S_FBVDDQ

FBB_CMD26_CKE 1 R50805 2 FBB_CKE_H
C C50810 C50811 C50812 C50813 C50814 C50815
82 76 BI C
10K_1%_2
10UF_4V_3 10UF_4V_3 10UF_4V_3 10UF_4V_3
1
1
10UF_4V_3 10UF_4V_3
2
2
FBB_CMD18_RST 1 R50806 2
82 76 BI FBB_RST*
22UF_4V_3
22UF_4V_3
22UF_4V_3
22UF_4V_3
22UF_4V_3
22UF_4V_3
1
10K_1%_2
C50821
C50816
C50817
C50818
C50819
C50820
OPTION
C50846 C50847 C50848 C50849 C50850
4.7UF_6.3V_2 1UF_6.3V_1 1UF_6.3V_1
2
1UF_6.3V_1 1UF_6.3V_1
P1V35S_FBVDDQ
1
B B
1
2
2
C50851 C50852 C50853 C50854 C50855 C50856
C50822 C50823 C50824 C50825 C50826 C50827 C50828 C50829 C50830 C50831 C50832 C50833
1UF_6.3V_1 1UF_6.3V_1 1UF_6.3V_1
1UF_6.3V_1 1UF_6.3V_1 1UF_6.3V_1
P1V35S_FBVDDQ
P1V35S_FBVDDQ
P1V35S_FBVDDQ
1
1
1
2
2
CLOSE TO VRAM
A CLOSE TO VRAM CLOSE TO VRAM A
C50834 C50835 C50836 C50837 C50838 C50839

C50840 C50841 C50842 C50843 C50844 C50845
C50857
1UF_6.3V_1
C50858 C50859 C50860 C50861
1UF_6.3V_1 1UF_6.3V_1
C50862
INVENTEC
Vinafix.com
1UF_6.3V_1 1UF_6.3V_1 1UF_6.3V_1
1UF_6.3V_1 1UF_6.3V_1 1UF_6.3V_1 TITLE
1UF_6.3V_1 1UF_6.3V_1 1UF_6.3V_1
Block Diagram
50800 - 50899 SIZE

A3
CODE
CS
DOC.NUMBER
1310xxxxx-0-0
REV
X01
6 5 4 3 2 1
6 5 4 3 2 1
U50900
P1V35S_FBVDDQ
U50900
A11 VSS_1 VDD_1 A1

A2 VSS_3 VDD_3 E10
A4 VSS_4 VDD_4 E5
FBC_CMD0 H3 K1 FBC1_VREFC
B1 VSS_5 VDD_5 H13 77 IN FBC_CMD9 G11
CA0_A VREFC

CA1_A
C10 VSS_7 VDD_7 L13 U50900 U50900 77 IN FBC_CMD32 H12

CA2_A
2
C12 VSS_8 VDD_8 L2 77 IN FBC_CMD7 H5
CA3_A
C3 VSS_9 VDD_9 P10 83 77 IN FBC_CMD11 H10

CA4_A
C5 VSS_10 VDD_10 P5 83 77 IN FBC_CMD15 J12

CA5_A
R50910
D1 VSS_11 VDD_11 V1 83 77 IN FBC_CMD14 J11
CA6_A
D12 V14 NORMAL NORMAL 83 77 IN CA7_A 1K_1%_2
I
VSS_12 VDD_12
FBC_CMD3 J4
IN
1
D14 83 77 CA8_A
VSS_13
FBC_CMD1 J3
D3 VSS_14 77 BI FBC_D1 B4 DQ1_A
x16 x8 83 77 IN FBC_CMD6 J5
CA9_A
E11 VSS_15 77 BI FBC_D7 A3 DQ4_A 77 BI FBC_D25 U4 DQ1_B

NC 83 77 IN FBC_CMD10_CKE G10
CABI_A
E4 P1V35S_FBVDDQ FBC_D5 B3 FBC_D29 V3 NC 83 77 IN CKE_A
F1
VSS_16 77 BI FBC_D4 B2
DQ7_A 77 BI FBC_D28 U3
DQ0_B
NC
F12
VSS_17 77 BI FBC_D6 E3
DQ3_B
NC TCK N5
F14
VSS_18
B10
77 BI FBC_D3 E2
DQ6_A 77 BI FBC_D26 P3
DQ2_B
NC TDI F10
F3
VSS_19 VDDQ_1
B5
77 BI FBC_D0 F2
DQ5_B
NC TDO N10
G1
VSS_20 VDDQ_2
C1
77 BI FBC_D2 G2
DQ3_A 77 BI FBC_D30 N2
DQ4_B
NC TMS F5
G12
VSS_21 VDDQ_3
C11
77 BI DQ0_A 77 BI FBC_D27 M2
DQ7_B
NC
G14
VSS_22 VDDQ_4
C14 FBC_EDC0 C2
77 BI DQ6_B
G3
VSS_23 VDDQ_5
C4
77 IN FBC_DBI0 D2
EDC0_A
FBC_EDC3 T2 GND 77 IN FBC_CMD4 L3 CA0_B
H11
VSS_24 VDDQ_6
E1
77 IN DBI0_A 77 IN FBC_DBI3 R2
EDC0_B
NC 77 IN FBC_CMD12 M11 CA1_B
H4
VSS_25 VDDQ_7
E14 FBC_WCK01 D4
77 IN DBI0_B
77 IN FBC_CMD5 M4 CA2_B
L11
VSS_26 VDDQ_8
F11
77 IN FBC_WCK01# D5
WCK0_A
FBC_WCKB23 R4 NC 77 IN FBC_CMD13 L12 CA3_B
L4
VSS_27 VDDQ_9
F4
77 IN WCK0_A* 77 IN FBC_WCKB23# R5
WCK0_B
NC 83 77 IN FBC_CMD7 L5 CA4_B
M1
VSS_28 VDDQ_10
H1
77 IN WCK0_B*
83 77 IN FBC_CMD11 L10 CA5_B
VSS_29 VDDQ_11
FBC_CMD15 K12
M12 VSS_30 VDDQ_12 H14 x16 x8
77 BI FBC_D23 U11 DQ9_B
83 77 IN FBC_CMD14
CA6_B
E M14 J13 FBC_D14 B11 NC FBC_D20 V12 83 77 IN K11 CA7_B E
M3
VSS_31 VDDQ_13
J2
77 BI FBC_D15 A12
DQ11_A
NC
77 BI FBC_D22 U12
DQ10_B
83 77 IN FBC_CMD3 K4 CA8_B
N1
VSS_32 VDDQ_14
K13
77 BI FBC_D8 B12
DQ14_A
NC
77 BI FBC_D21 U13
DQ13_B
83 77 IN FBC_CMD1 K3 CA9_B
FBC_CMD6 K5 R50900
N12 VSS_34 VDDQ_16 K2 77 BI FBC_D12 B13 DQ10_A
NC
77 BI FBC_D18 P12 DQ12_B
83 77 IN FBC_CMD10_CKE M10
CABI_B
121_1%_2
N14 VSS_35 VDDQ_17 L1 77 BI FBC_D13 E12 DQ13_A
NC
83 77 IN CKE_B
J14 FBC_ZQ_1_A 1 2
ZQ_A
N3 L14 FBC_D9 E13 NC FBC_D17 N13
P11
VSS_36 VDDQ_18
N11
77 BI FBC_D11 F13
DQ8_A
NC
77 BI FBC_D16 M13
DQ14_B
ZQ_B K14 FBC_ZQ_1_B 1 2
P4
VSS_37 VDDQ_19
N4
77 BI FBC_D10 G13
DQ9_A
NC
77 BI DQ15_B
VSS_38 VDDQ_20 77 BI DQ15_A R50901
R1 P1 FBC_EDC2 T13 121_1%_2
R12
VSS_39 VDDQ_21
P14 FBC_EDC1 C13 GND
77 IN FBC_DBI2 R13
EDC1_B
R14
VSS_40 VDDQ_22
T1
77 IN FBC_DBI1 D13
EDC1_A 77 IN DBI1_B
83 77 IN FBC_CMD2_RST J1 RESET*
R3
VSS_41 VDDQ_23
T11
77 IN DBI1_A NC
FBC_WCK23 R11
T10
VSS_42 VDDQ_24
T14 FBC_WCKB01 D11 NC
77 IN FBC_WCK23# R10
WCK1_B
T12
VSS_43 VDDQ_25
T4
77 IN FBC_WCKB01# D10
WCK1_A
NC
77 IN WCK1_B*
T3
VSS_44 VDDQ_26
U10
77 IN WCK1_A*
77 IN FBC_CLK0# K10 CLK*
VSS_45 VDDQ_27
FBC_CLK0 J10
U1 VSS_47
RFU_A G5
V11 VSS_49
RFU_B M5
V13 VSS_50
V2 VSS_51
V4 VSS_52
P1V8S_AON1
VPP_1 A10
VPP_2 A5
VPP_3 V10
VPP_4 V5
Vinafix.com
P1V35S_FBVDDQ
P1V35S_FBVDDQ
P1V35S_FBVDDQ FBC_CMD10_CKE 1 R50905 2 FBC_CKE_L
83 77 BI
10K_1%_2
FBC_CMD2_RST 1 R50906 2
83 77 BI FBC_RST*
10K_1%_2
C50910 C50911 C50912 C50913 C50914 C50915

C C
10UF_4V_3 10UF_4V_3 10UF_4V_3 10UF_4V_3
1
1
10UF_4V_3 10UF_4V_3
P1V35S_FBVDDQ
P1V35S_FBVDDQ
2
2
22UF_4V_3
22UF_4V_3
22UF_4V_3
22UF_4V_3
22UF_4V_3
22UF_4V_3
1
1
C50921
C50916
C50917
C50918
C50919
C50920
OPTION
C50946 C50947 C50948 C50949 C50950
4.7UF_6.3V_2 1UF_6.3V_1 1UF_6.3V_1
2
1UF_6.3V_1 1UF_6.3V_1
P1V35S_FBVDDQ
1
1
1
B B
2
2
2
C50951 C50952 C50953 C50954 C50955 C50956
C50922 C50923 C50924 C50925 C50926 C50927 C50928 C50929 C50930 C50931 C50932 C50933
1UF_6.3V_1 1UF_6.3V_1 1UF_6.3V_1
1UF_6.3V_1 1UF_6.3V_1 1UF_6.3V_1
P1V35S_FBVDDQ
P1V35S_FBVDDQ
P1V35S_FBVDDQ
1
1
1
1
1
2
2
2
2

A CLOSE TO VRAM A
C50957 C50958 C50959 C50960 C50961 C50962
C50934
1UF_6.3V_1
C50935 C50936 C50937 C50938
1UF_6.3V_1 1UF_6.3V_1
C50939
C50940
1UF_6.3V_1
C50941 C50942 C50943 C50944
1UF_6.3V_1 1UF_6.3V_1
C50945
1UF_6.3V_1 1UF_6.3V_1
1UF_6.3V_1
1UF_6.3V_1
1UF_6.3V_1 1UF_6.3V_1 INVENTEC
Vinafix.com
1UF_6.3V_1 1UF_6.3V_1 1UF_6.3V_1
1UF_6.3V_1 1UF_6.3V_1 1UF_6.3V_1
TITLE
Block Diagram
50900 - 50999 SIZE

A3
CODE
CS
DOC.NUMBER
1310xxxxx-0-0
REV
X01
6 5 4 3 2 1
6 5 4 3 2 1
U51000
P1V35S_FBVDDQ
U51000

A13 VSS_2 VDD_2 A14
A2 VSS_3 VDD_3 E10
A4 VSS_4 VDD_4 E5
FBC_CMD20 H3 K1 FBC2_VREFC
CA0_A VREFC

CA1_A
2
C10 VSS_7 VDD_7 L13 U51000 U51000 77 IN FBC_CMD29 H12
CA2_A
C12 VSS_8 VDD_8 L2 77 IN FBC_CMD23 H5

CA3_A
C3 P10 84 77 IN CA4_A R51010

VSS_9 VDD_9
FBC_CMD27 H10
C5 VSS_10 VDD_10 P5 84 77 IN FBC_CMD30 J12
CA5_A
1K_1%_2
D1 V1 84 77 IN CA6_A
I
VSS_11 VDD_11
NORMAL NORMAL FBC_CMD31 J11
IN
1
D12 V14 84 77 CA7_A
VSS_12 VDD_12
FBC_CMD19 J4
D14 VSS_13
84 77 IN FBC_CMD17 J3
CA8_A
D3 VSS_14 77 BI FBC_D38 B4 DQ1_A

x16 x8 84 77 IN FBC_CMD22 J5
CA9_A
E11 VSS_15 77 BI FBC_D34 A3 DQ4_A 77 BI FBC_D56 U4 DQ1_B

NC 84 77 IN FBC_CMD26_CKE G10
CABI_A
E4 P1V35S_FBVDDQ FBC_D36 B3 FBC_D57 V3 NC 84 77 IN CKE_A
F1
VSS_16 77 BI FBC_D39 B2
DQ0_B
NC
F12
VSS_17 77 BI FBC_D35 E3
DQ3_B
NC TCK N5
F14
VSS_18
B10
77 BI FBC_D32 E2
DQ2_B
NC TDI F10
F3
VSS_19 VDDQ_1
B5
77 BI FBC_D33 F2
DQ5_B
NC TDO N10
G1
VSS_20 VDDQ_2
C1
77 BI FBC_D37 G2
DQ3_A 77 BI FBC_D62 N2
DQ4_B
NC TMS F5
G12
VSS_21 VDDQ_3
C11
77 BI DQ0_A 77 BI FBC_D63 M2
DQ7_B
NC
G14
VSS_22 VDDQ_4
C14 FBC_EDC4 C2
77 BI DQ6_B
G3
VSS_23 VDDQ_5
C4
77 IN FBC_DBI4 D2
EDC0_A
FBC_EDC7 T2 GND 77 IN FBC_CMD16 L3 CA0_B
H11
VSS_24 VDDQ_6
E1
77 IN DBI0_A 77 IN FBC_DBI7 R2
EDC0_B
NC 77 IN FBC_CMD25 M11 CA1_B
H4
VSS_25 VDDQ_7
E14 FBC_WCK45 D4
77 IN DBI0_B
77 IN FBC_CMD24 M4 CA2_B
L11
VSS_26 VDDQ_8
F11
77 IN FBC_WCK45# D5
WCK0_A
FBC_WCKB67 R4 NC 77 IN FBC_CMD33 L12 CA3_B
L4
VSS_27 VDDQ_9
F4
77 IN WCK0_A* 77 IN FBC_WCKB67# R5
WCK0_B
NC 84 77 IN FBC_CMD23 L5 CA4_B
M1
VSS_28 VDDQ_10
H1
77 IN WCK0_B*
84 77 IN FBC_CMD27 L10 CA5_B
VSS_29 VDDQ_11
E FBC_CMD30 K12 E
M12 VSS_30 VDDQ_12 H14 x16 x8
84 77 IN FBC_CMD31 K11
CA6_B
M14 VSS_31 VDDQ_13 J13 77 BI FBC_D40 B11 DQ11_A

NC
77 BI FBC_D50 V12 DQ10_B
CA7_B
M3 VSS_32 VDDQ_14 J2 77 BI FBC_D43 A12 DQ14_A

NC
CA8_B

NC
CA9_B

NC
84 77 IN FBC_CMD26_CKE M10
CABI_B
N14 L1 FBC_D44 E12 NC FBC_D52 P13 84 77 IN CKE_B R51000

ZQ_A J14 FBC_ZQ_2_A 1 121_1%_2 2
N3 L14 FBC_D45 E13 NC FBC_D55 N13
P11
VSS_36 VDDQ_18
N11
77 BI FBC_D47 F13
DQ8_A
NC
77 BI FBC_D54 M13
DQ14_B
ZQ_B K14 FBC_ZQ_2_B 1 2
P4
VSS_37 VDDQ_19
N4
77 BI FBC_D41 G13
DQ9_A
NC
77 BI DQ15_B
121_1%_2
R1
VSS_38 VDDQ_20
P1
77 BI DQ15_A
FBC_EDC6 T13 R51001
R12
VSS_39 VDDQ_21
P14 FBC_EDC5 C13 GND
77 IN FBC_DBI6 R13
EDC1_B
R14
VSS_40 VDDQ_22
T1
77 IN FBC_DBI5 D13
EDC1_A 77 IN DBI1_B
84 77 IN FBC_CMD18_RST J1 RESET*
R3
VSS_41 VDDQ_23
T11
77 IN DBI1_A NC
FBC_WCK67 R11
T10
VSS_42 VDDQ_24
T14 FBC_WCKB45 D11 NC
77 IN FBC_WCK67# R10
WCK1_B
T12
VSS_43 VDDQ_25
T4
77 IN FBC_WCKB45# D10
WCK1_A
NC
77 IN WCK1_B*
T3
VSS_44 VDDQ_26
U10
77 IN WCK1_A*
77 IN FBC_CLK1# K10 CLK*
VSS_45 VDDQ_27
FBC_CLK1 J10
U1 VSS_47
RFU_A G5
V11 VSS_49
RFU_B M5
V13 VSS_50
V2 VSS_51
V4 VSS_52
P1V8S_AON1
VPP_1 A10
VPP_2 A5
VPP_3 V10
D VPP_4 V5 D
P1V35S_FBVDDQ
P1V35S_FBVDDQ Vinafix.com FBC_CMD26_CKE 1 R51005 2
P1V35S_FBVDDQ
FBC_CKE_H
84 77 BI
10K_1%_2
CLOSE TO VRAM CLOSE TO VRAM P1V8S_AON1 FBC_CMD18_RST 1 R51006 2

84 77 BI FBC_RST*
10K_1%_2
C C51010 C51011 C51012 C51013 C51014 C51015
C
10UF_4V_3 10UF_4V_3 10UF_4V_3 10UF_4V_3
1
1
10UF_4V_3 10UF_4V_3
P1V35S_FBVDDQ
P1V35S_FBVDDQ
2
2
22UF_4V_3
22UF_4V_3
22UF_4V_3
22UF_4V_3
22UF_4V_3
22UF_4V_3
1
1
C51021
C51016
C51017
C51018
C51019
C51020
OPTION
C51046 C51047 C51048 C51049 C51050
4.7UF_6.3V_2 1UF_6.3V_1 1UF_6.3V_1
2
1UF_6.3V_1 1UF_6.3V_1
P1V35S_FBVDDQ
P1V35S_FBVDDQ
P1V35S_FBVDDQ
B B
1
1
1
2
2
C51051 C51052 C51053 C51054 C51055 C51056
C51022 C51023 C51024 C51025 C51026 C51027 C51028 C51029 C51030 C51031 C51032 C51033
1UF_6.3V_1 1UF_6.3V_1 1UF_6.3V_1
1UF_6.3V_1 1UF_6.3V_1 1UF_6.3V_1
P1V35S_FBVDDQ
P1V35S_FBVDDQ
P1V35S_FBVDDQ
1
1
1
2
2
A CLOSE TO VRAM A
C51057
1UF_6.3V_1
C51058 C51059 C51060 C51061
1UF_6.3V_1 1UF_6.3V_1
C51062
INVENTEC
Vinafix.com
C51034 C51035 C51036 C51037 C51038 C51039 C51040 C51041 C51042 C51043 C51044 C51045
1UF_6.3V_1 1UF_6.3V_1 1UF_6.3V_1
1UF_6.3V_1 1UF_6.3V_1 1UF_6.3V_1 1UF_6.3V_1 1UF_6.3V_1 1UF_6.3V_1 TITLE
Block Diagram

SIZE
A3
CODE
CS
DOC.NUMBER
1310xxxxx-0-0
REV
X01
6 5 4 3 2 1
6 5 4 3 2 1
U51100
P1V35S_FBVDDQ
U51100

A13 VSS_2 VDD_2 A14
A2 VSS_3 VDD_3 E10
A4 VSS_4 VDD_4 E5
FBD_CMD0 H3 K1 FBD1_VREFC
B1 VSS_5 VDD_5 H13 78 IN FBD_CMD9 G11
CA0_A VREFC

CA1_A
C10 VSS_7 VDD_7 L13 U51100 U51100 78 IN FBD_CMD32 H12

CA2_A
2
78 IN CA3_A
1K_1%_2
C12 VSS_8 VDD_8 L2
R51110
FBD_CMD7 H5
C3 VSS_9 VDD_9 P10 85 78 IN FBD_CMD11 H10
CA4_A
C5 VSS_10 VDD_10 P5 85 78 IN FBD_CMD15 J12

CA5_A
D1 VSS_11 VDD_11 V1 85 78 IN FBD_CMD14 J11

CA6_A
I
VSS_12 VDD_12
FBD_CMD3 J4
IN
1
D14 85 78 CA8_A
VSS_13
FBD_CMD1 J3
D3 VSS_14 78 BI FBD_D5 B4 DQ1_A
x16 x8 85 78 IN FBD_CMD6 J5
CA9_A
E11 VSS_15 78 BI FBD_D1 A3 DQ4_A 78 BI FBD_D30 U4 DQ1_B

NC 85 78 IN FBD_CMD10_CKE G10
CABI_A
E4 VSS_16 P1V35S_FBVDDQ 78 BI FBD_D0 B3 DQ7_A 78 BI FBD_D28 V3 DQ0_B

NC 85 78 IN CKE_A
F1 FBD_D3 B2 FBD_D26 U3 NC
F12
VSS_17 78 BI FBD_D6 E3
DQ5_A 78 BI FBD_D31 U2
DQ3_B
NC TCK N5
F14
VSS_18
B10
78 BI FBD_D7 E2
DQ6_A 78 BI FBD_D25 P3
DQ2_B
NC TDI F10
F3
VSS_19 VDDQ_1
B5
78 BI FBD_D2 F2
DQ5_B
NC TDO N10
G1
VSS_20 VDDQ_2
C1
78 BI FBD_D4 G2
DQ3_A 78 BI FBD_D29 N2
DQ4_B
NC TMS F5
G12
VSS_21 VDDQ_3
C11
78 BI DQ0_A 78 BI FBD_D24 M2
DQ7_B
NC
G14
VSS_22 VDDQ_4
C14 FBD_EDC0 C2
78 BI DQ6_B
G3
VSS_23 VDDQ_5
C4
78 IN FBD_DBI0 D2
EDC0_A
FBD_EDC3 T2 GND 78 IN FBD_CMD4 L3 CA0_B
H11
VSS_24 VDDQ_6
E1
78 IN DBI0_A 78 IN FBD_DBI3 R2
EDC0_B
NC 78 IN FBD_CMD12 M11 CA1_B
H4
VSS_25 VDDQ_7
E14 FBD_WCK01 D4
78 IN DBI0_B
78 IN FBD_CMD5 M4 CA2_B
L11
VSS_26 VDDQ_8
F11
78 IN FBD_WCK01# D5
WCK0_A
FBD_WCKB23 R4 NC 78 IN FBD_CMD13 L12 CA3_B
L4
VSS_27 VDDQ_9
F4
78 IN WCK0_A* 78 IN FBD_WCKB23# R5
WCK0_B
NC 85 78 IN FBD_CMD7 L5 CA4_B
M1
VSS_28 VDDQ_10
H1
78 IN WCK0_B*
85 78 IN FBD_CMD11 L10 CA5_B
VSS_29 VDDQ_11
E FBD_CMD15 K12 E
M12 VSS_30 VDDQ_12 H14 x16 x8
78 BI FBD_D23 U11 DQ9_B
85 78 IN FBD_CMD14 K11
CA6_B
M14 VSS_31 VDDQ_13 J13 78 BI FBD_D13 B11 DQ11_A

NC
78 BI FBD_D21 V12 DQ10_B
CA7_B
M3 VSS_32 VDDQ_14 J2 78 BI FBD_D14 A12 DQ14_A

NC
CA8_B
N1 VSS_33 VDDQ_15 K13 78 BI FBD_D8 B12 DQ12_A

NC
CA9_B
N12 VSS_34 VDDQ_16 K2 78 BI FBD_D12 B13 DQ10_A

NC
78 BI FBD_D17 P12 DQ12_B
85 78 IN FBD_CMD10_CKE M10
CABI_B
N14 L1 FBD_D10 E12 NC FBD_D19 P13 85 78 IN CKE_B R51100

ZQ_A J14 FBD_ZQ_1_A 1 121_1%_2 2
N3 L14 FBD_D15 E13 NC FBD_D16 N13
P11
VSS_36 VDDQ_18
N11
78 BI FBD_D9 F13
DQ8_A
NC
78 BI FBD_D18 M13
DQ14_B
ZQ_B K14 FBD_ZQ_1_B 1 2
P4
VSS_37 VDDQ_19
N4
78 BI FBD_D11 G13
DQ9_A
NC
78 BI DQ15_B
121_1%_2
R1
VSS_38 VDDQ_20
P1
78 BI DQ15_A
FBD_EDC2 T13 R51101
R12
VSS_39 VDDQ_21
P14 FBD_EDC1 C13 GND
78 IN FBD_DBI2 R13
EDC1_B
R14
VSS_40 VDDQ_22
T1
78 IN FBD_DBI1 D13
EDC1_A 78 IN DBI1_B
85 78 IN FBD_CMD2_RST J1 RESET*
R3
VSS_41 VDDQ_23
T11
78 IN DBI1_A NC
FBD_WCK23 R11
T10
VSS_42 VDDQ_24
T14 FBD_WCKB01 D11 NC
78 IN FBD_WCK23# R10
WCK1_B
T12
VSS_43 VDDQ_25
T4
78 IN FBD_WCKB01# D10
WCK1_A
NC
78 IN WCK1_B*
T3
VSS_44 VDDQ_26
U10
78 IN WCK1_A*
78 IN FBD_CLK0# K10 CLK*
VSS_45 VDDQ_27
FBD_CLK0 J10
U1 VSS_47
RFU_A G5
V11 VSS_49
RFU_B M5
V13 VSS_50
V2 VSS_51
V4 VSS_52
P1V8S_AON1
VPP_1 A10
VPP_2 A5
VPP_3 V10
D VPP_4 V5 D
Vinafix.com
P1V35S_FBVDDQ
FBD_CMD10_CKE 1 R51105 2 FBD_CKE_L

P1V35S_FBVDDQ P1V35S_FBVDDQ 85 78 BI
10K_1%_2
FBD_CMD2_RST 1 R51106 2
85 78 BI FBD_RST*
10K_1%_2
C C51110 C51111 C51112 C51113 C51114 C51115 C

10UF_4V_3 10UF_4V_3 10UF_4V_3 10UF_4V_3
1
1
10UF_4V_3 10UF_4V_3
2
2
22UF_4V_3
22UF_4V_3
22UF_4V_3
22UF_4V_3
22UF_4V_3
22UF_4V_3
1
1
C51116
C51117
C51118
C51119
C51120
C51121
OPTION
C51146 C51147 C51148 C51149 C51150
4.7UF_6.3V_2 1UF_6.3V_1 1UF_6.3V_1
2
1UF_6.3V_1 1UF_6.3V_1
P1V35S_FBVDDQ
1
B B
1
2
2
C51151 C51152 C51153 C51154 C51155 C51156
C51122 C51123 C51124 C51125 C51126 C51127 C51128 C51129 C51130 C51131 C51132 C51133
1UF_6.3V_1 1UF_6.3V_1 1UF_6.3V_1
1UF_6.3V_1 1UF_6.3V_1 1UF_6.3V_1
P1V35S_FBVDDQ
1
1
1
2
2
CLOSE TO VRAM CLOSE TO VRAM CLOSE TO VRAM

A A
C51134
1UF_6.3V_1
C51135 C51136 C51137 C51138
1UF_6.3V_1 1UF_6.3V_1
C51139 C51140
1UF_6.3V_1
C51141 C51142 C51143 C51144
1UF_6.3V_1 1UF_6.3V_1
C51145
C51157
1UF_6.3V_1
C51158 C51159 C51160 C51161
1UF_6.3V_1 1UF_6.3V_1
C51162
INVENTEC
Vinafix.com
1UF_6.3V_1 1UF_6.3V_1 1UF_6.3V_1
TITLE
Block Diagram

SIZE
A3
CODE
CS
DOC.NUMBER
1310xxxxx-0-0
REV
X01
6 5 4 3 2 1
6 5 4 3 2 1
U51200
P1V35S_FBVDDQ
U51200
A11 VSS_1 VDD_1 A1

A2 VSS_3 VDD_3 E10
A4 VSS_4 VDD_4 E5
FBD_CMD20 H3 K1 FBD2_VREFC
CA0_A VREFC

CA1_A
2
C10 VSS_7 VDD_7 L13 U51200 U51200 78 IN FBD_CMD29 H12
CA2_A
C12 VSS_8 VDD_8 L2 78 IN FBD_CMD23 H5

CA3_A
C3 P10 86 78 IN CA4_A R51210

VSS_9 VDD_9
FBD_CMD27 H10
C5 VSS_10 VDD_10 P5 86 78 IN FBD_CMD30 J12
CA5_A
1K_1%_2
D1 V1 86 78 IN CA6_A
I
VSS_11 VDD_11
NORMAL NORMAL FBD_CMD31 J11
IN
1
D12 V14 86 78 CA7_A
VSS_12 VDD_12
FBD_CMD19 J4
D14 VSS_13
86 78 IN FBD_CMD17 J3
CA8_A
D3 VSS_14 78 BI FBD_D35 B4 DQ1_A

x16 x8 86 78 IN FBD_CMD22 J5
CA9_A
E11 VSS_15 78 BI FBD_D33 A3 DQ4_A 78 BI FBD_D56 U4 DQ1_B

NC 86 78 IN FBD_CMD26_CKE G10
CABI_A
E4 VSS_16 P1V35S_FBVDDQ 78 BI FBD_D32 B3 DQ7_A 78 BI FBD_D59 V3 DQ0_B

NC 86 78 IN CKE_A
F1 FBD_D37 B2 FBD_D58 U3 NC
F12
VSS_17 78 BI FBD_D34 E3
DQ5_A 78 BI FBD_D60 U2
DQ3_B
NC TCK N5
F14
VSS_18
B10
78 BI FBD_D39 E2
DQ2_B
NC TDI F10
F3
VSS_19 VDDQ_1
B5
78 BI FBD_D36 F2
DQ5_B
NC TDO N10
G1
VSS_20 VDDQ_2
C1
78 BI FBD_D38 G2
DQ3_A 78 BI FBD_D61 N2
DQ4_B
NC TMS F5
G12
VSS_21 VDDQ_3
C11
78 BI DQ0_A 78 BI FBD_D63 M2
DQ7_B
NC
G14
VSS_22 VDDQ_4
C14 FBD_EDC4 C2
78 BI DQ6_B
G3
VSS_23 VDDQ_5
C4
78 IN FBD_DBI4 D2
EDC0_A
FBD_EDC7 T2 GND 78 IN FBD_CMD16 L3 CA0_B
H11
VSS_24 VDDQ_6
E1
78 IN DBI0_A 78 IN FBD_DBI7 R2
EDC0_B
NC 78 IN FBD_CMD25 M11 CA1_B
H4
VSS_25 VDDQ_7
E14 FBD_WCK45 D4
78 IN DBI0_B
78 IN FBD_CMD24 M4 CA2_B
L11
VSS_26 VDDQ_8
F11
78 IN FBD_WCK45# D5
WCK0_A
FBD_WCKB67 R4 NC 78 IN FBD_CMD33 L12 CA3_B
L4
VSS_27 VDDQ_9
F4
78 IN WCK0_A* 78 IN FBD_WCKB67# R5
WCK0_B
NC 86 78 IN FBD_CMD23 L5 CA4_B
M1
VSS_28 VDDQ_10
H1
78 IN WCK0_B*
86 78 IN FBD_CMD27 L10 CA5_B
VSS_29 VDDQ_11
FBD_CMD30 K12
M12 VSS_30 VDDQ_12 H14 x16 x8
86 78 IN FBD_CMD31
CA6_B
E M14 J13 FBD_D43 B11 NC FBD_D48 V12 86 78 IN K11 CA7_B E
M3
VSS_31 VDDQ_13
J2
78 BI FBD_D41 A12
DQ11_A
NC
78 BI FBD_D52 U12
DQ10_B
86 78 IN FBD_CMD19 K4 CA8_B
N1
VSS_32 VDDQ_14
K13
78 BI FBD_D42 B12
DQ14_A
NC
78 BI FBD_D50 U13
DQ13_B
86 78 IN FBD_CMD17 K3 CA9_B
N12
VSS_33 VDDQ_15
K2
78 BI FBD_D40 B13
DQ12_A
NC
78 BI FBD_D55 P12
DQ8_B
86 78 IN FBD_CMD22 K5 CABI_B
N14
VSS_34 VDDQ_16
L1
78 BI FBD_D46 E12
DQ10_A
NC
78 BI FBD_D53 P13
DQ12_B
86 78 IN FBD_CMD26_CKE M10 CKE_B R51200
ZQ_A J14 FBD_ZQ_2_A 1 121_1%_2 2
N3 L14 FBD_D44 E13 NC FBD_D51 N13
P11
VSS_36 VDDQ_18
N11
78 BI FBD_D47 F13
DQ8_A
NC
78 BI FBD_D54 M13
DQ14_B
ZQ_B K14 FBD_ZQ_2_B 1 2
P4
VSS_37 VDDQ_19
N4
78 BI FBD_D45 G13
DQ9_A
NC
78 BI DQ15_B
121_1%_2
R1
VSS_38 VDDQ_20
P1
78 BI DQ15_A
FBD_EDC6 T13 R51201
R12
VSS_39 VDDQ_21
P14 FBD_EDC5 C13 GND
78 IN FBD_DBI6 R13
EDC1_B
R14
VSS_40 VDDQ_22
T1
78 IN FBD_DBI5 D13
EDC1_A 78 IN DBI1_B
86 78 IN FBD_CMD18_RST J1 RESET*
R3
VSS_41 VDDQ_23
T11
78 IN DBI1_A NC
FBD_WCK67 R11
T10
VSS_42 VDDQ_24
T14 FBD_WCKB45 D11 NC
78 IN FBD_WCK67# R10
WCK1_B
T12
VSS_43 VDDQ_25
T4
78 IN FBD_WCKB45# D10
WCK1_A
NC
78 IN WCK1_B*
T3
VSS_44 VDDQ_26
U10
78 IN WCK1_A*
78 IN FBD_CLK1# K10 CLK*
VSS_45 VDDQ_27
FBD_CLK1 J10
U1 VSS_47
RFU_A G5
V11 VSS_49
RFU_B M5
V13 VSS_50
V2 VSS_51
V4 VSS_52
P1V8S_AON1
VPP_1 A10
VPP_2 A5
VPP_3 V10
VPP_4 V5
P1V35S_FBVDDQ
P1V35S_FBVDDQ Vinafix.com
P1V35S_FBVDDQ
FBD_CMD26_CKE 1 R51205 2 FBD_CKE_H

86 78 BI
10K_1%_2
C C51210 C51211 C51212 C51213 C51214 C51215 C

10UF_4V_3 10UF_4V_3 10UF_4V_3 10UF_4V_3
1
1
10UF_4V_3 10UF_4V_3
P1V35S_FBVDDQ P1V35S_FBVDDQ R51206 2

86 78 BI FBD_CMD18_RST 1 FBD_RST*
10K_1%_2
2
2
22UF_4V_3
22UF_4V_3
22UF_4V_3
22UF_4V_3
22UF_4V_3
22UF_4V_3
1
1
C51221
C51216
C51217
C51218
C51219
C51220
OPTION
C51246 C51247 C51248 C51249 C51250
4.7UF_6.3V_2 1UF_6.3V_1 1UF_6.3V_1
2
1UF_6.3V_1 1UF_6.3V_1
P1V35S_FBVDDQ
1
B B
1
2
2
C51251 C51252 C51253 C51254 C51255 C51256
C51222 C51223 C51224 C51225 C51226 C51227 C51228 C51229 C51230 C51231 C51232 C51233
1UF_6.3V_1 1UF_6.3V_1 1UF_6.3V_1
1UF_6.3V_1 1UF_6.3V_1 1UF_6.3V_1
P1V35S_FBVDDQ
1
1
1
2
2
CLOSE TO VRAM CLOSE TO VRAM CLOSE TO VRAM

A A
C51234
1UF_6.3V_1
C51235 C51236 C51237 C51238
1UF_6.3V_1 1UF_6.3V_1
C51239 C51240
1UF_6.3V_1
C51241 C51242 C51243 C51244
1UF_6.3V_1 1UF_6.3V_1
C51245
C51257
1UF_6.3V_1
C51258 C51259 C51260 C51261
1UF_6.3V_1 1UF_6.3V_1
C51262
INVENTEC
Vinafix.com
1UF_6.3V_1 1UF_6.3V_1 1UF_6.3V_1
TITLE
Block Diagram

SIZE
A3
CODE
CS
DOC.NUMBER
1310xxxxx-0-0
REV
X01
6 5 4 3 2 1
8 7 6 5 4 3 2 1
27 MHZ XTAL
OUT 91 94
TP51300
P1V8S_MAIN1 1 U50000
13/22 XTAL/PLL
BEAD,30OHM,25%,1A,0.05OHM,0603INCH,100MHZ,C,TR
D
L51300 GPU_PLLVDD_XS_SP BD12 SP_PLLVDD D
1UF_6.3V_1
1
BC12 VID_PLLVDD
4.7UF_6.3V_2
22UF_4V_3
C51302
1
1UF_6.3V_1
C51300
C51301
C51303
2
2
2
CL=2*10-(5+3)=12 U42 GPCPLL_AVDD0
PLACE NEAR GPU AF11
1
1UF_6.3V_1
1UF_6.3V_1
1UF_6.3V_1
GPCPLL_AVDD1
C51304
C51305
C51306
BB24 XSN_PLLVDD
2
C PLACE UNDER GPU C
TP5631
1
DGPU_XTAL_SSIN BJ6 EXT_REFCLK_FL XTAL_OUTBUFF BK6 DGPU_XTAL_OUTBUFF
100K_1%_2
BL6 BM6
10K_1%_2
XTAL_IN XTAL_OUT
R51316
R51321
Vinafix.com
2
I
A
X51310
DGPU_XTAL_IN 1 3 DGPU_XTAL_OUT
4 2
10PF_50V_2
10PF_50V_2
1
1
27MHZ_10PF
C51310
C51311
6018B0057601
2
B B
A A
51300 - 51399
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
PCB P/N
XXX
60xxxxxxxxxx
DATE
PCB VER
21-OCT-2002
XXX
A3 CS
SHEET 87 of 139
8 7 6 5 4 3 2 1
6 5 4 3 2 1
GPU VBIOS, EXTERNAL STRAPS F
P1V8S_AON1
10K_1%_2_DY
U50000
R51424
14/22 MISC 2
BJ4 DGPU_ROM_CS#
ROM_CS* OUT 88
BK2 DGPU_ROM_SI
ROM_SI
BK4 DGPU_ROM_SO
OUT 88
DGPU_STRAP0 BL3
ROM_SO
BK3 DGPU_ROM_SCLK
IN 88
E 88 IN DGPU_STRAP1 BL4
STRAP0 ROM_SCLK OUT 88
E
88 IN STRAP1
100K_1%_2
100K_1%_2
DGPU_STRAP2 BM4
10K_1%_2
2
2
88 IN DGPU_STRAP3 BM5
STRAP2
88 IN STRAP3
R51421
R51422
R51423
DGPU_STRAP4 BK5
88 IN DGPU_STRAP5 BJ5
STRAP4
88 IN STRAP5
1
1
BUFRST* BF9
P1V8S_AON1
NVIDIA_N18E_G1_KD_QS_A1_BGA_2228P P1V8S_AON1
10K_1%_2
2
R51400
0.1UF_16V_2
1
C51400
1
D D
2
I U51400
DGPU_ROM_CS# 1 R51401 2 VBIOS_CS# 1 8
88 IN CS# VCC
33_1%_2
DGPU_ROM_SO 2 7
88 OUT SO HOLD#
3 6 VBIOS_SCLK 1 I R51402 2 DGPU_ROM_SCLK

WP# SCLK IN 88
33_1%_2
P1V8S_AON1 4 5 VBIOS_SI 1 2 DGPU_ROM_SI
IN
Vinafix.com
GND SI 88
R51403
WINBOND_W25Q80EWSNIG_SOP_8P 33_1%_2
100K_1%_2_DY
100K_1%_2_DY
100K_1%_2_DY
100K_1%_2_DY
100K_1%_2_DY
100K_1%_2
1
1
R51438
R51440
R51436
R51434
R51432
R51430
2
2
DGPU_STRAP5
OUT 88
DGPU_STRAP4
OUT 88
DGPU_STRAP3
OUT 88
DGPU_STRAP2
OUT 88
DGPU_STRAP1
OUT 88
100K_1%_2_DY
DGPU_STRAP0
OUT 88
100K_1%_2
100K_1%_2
100K_1%_2
100K_1%_2
100K_1%_2
1
2 R51433 1
2 R51431 1
C C
R51441
R51439
R51437
R51435
2
DEFAULT IS SAMSUNG
SAMSUNG K4Z80325BC-HC14 MICRON MT61K256M32JE-14:A

6019B1847601 6019B1847701
STRAP 0X0=000 STRAP 0X1=001
SAMSUNG:R51431 STUFF MICRON :R51430 STUFF
R51430 NOT STUFF R51431 NOT STUFF
B B
A A
INVENTEC
Vinafix.com TITLE
Block Diagram

6 5 4 3 2 1
6 5 4 3 2 1
GPU GPIO P1V8S_AON1
P1V8S_MAIN1
2.2K_5%_2
2.2K_5%_2
R51524 2
R51523 2
R51525
TP24
0_5%_2
TP51521
1 R51521
PEX_DGPU_RST# R51526 I2C_RST#
33_1%_2 IN OUT
1
89 74 89
I2CC_SCL_G 1I 2 I2CC_SCL_R_G 0_5%_2_DY
89 BI
F I2CC_SDA_G 1I 2 I2CC_SDA_R_G I2CC_SDA F
89 BI BI 108
1 R51522 I2CC_SCL
BI 108
6
3
4
TP24
33_1%_2
TP51522
S2
D2
S1
D1
Q51520 P1V8S_AON1
P1V8S_AON1
G1
G2
EM6K1GT2R
I2C_RST#
10K_1%_2
2
89 IN
G
R51545
P1V8S_AON1
TO PCH
G
I
A I
GPIO2_DGPU_EVENT# S S D D GPU_EVENT_PCH#
OUT IN
1
89 44 73
R51534 2
R51533 2
2.2K_5%_2
2.2K_5%_2
1
Q51545 TP24
TP24 PJA138K
TP51545
TP51531
1 R51531
1
33_1%_2
I2CS_SCL_G 1I 2 I2CS_SCL_R_G EC
89 BI
I2CS_SDA_G 1I 2 I2CS_SDA_R_G EC_SMBDATA0
89 BI BI 51 73
1 R51532 EC_SMBCLK0 P1V8S_AON1
BI 51 73
6
3
4
TP24
33_1%_2 P1V8S_AON1
TP51532
S2
D2
S1
D1
Q51530
10K_1%_2
2
G
E
R51550
E
G1
G2
EM6K1GT2R
I2C_RST# TO EC
G
89 IN
I
P3V3S P1V8S_AON1
A I
GPIO12_DGPU_PWRLEVEL S S D D DGPU_PWRLEVEL
OUT IN
1
89 51 73
1
10K_1%_2
U50000
2
Q51550 TP24
OVERT#
10K_1%_2
2
R51510
PJA138K
R51511
TP51550
3.3V LEVEL 1 12/22 MISC 1
TP24
I
Q51510
I
I A1
TP51511 PJA138K
1
73 51 OUT GPU_OVERT_EC# G_OVERT#BG5 BJ8 I2CS_SCL_G BI 89

HPD PULL UP
D S OVERT I2CS_SCL
BH8 I2CS_SDA_G P1V8S_AON1
D S I2CS_SDA
BI 89
3.3V LEVEL OVERHEAT TO EC BF12

G
TS_VREF I
GPIO14_IFPA_HPD R51560 1 2 10K_1%_2
I BG9 I2CC_SCL_G 89 OUT
2
BI
G
A I2CC_SCL 89
I
BH9 I2CC_SDA_G P1V8S_AON1 GPIO15_IFPB_HPD R51561 1 2 10K_1%_2
I2CC_SDA
BI 89 89 OUT
NC
I
GPIO27_IFPC_DP_HPD R51562 1 2 10K_1%_2
105 OUT GPU_OVERT_NVVDD#1 3 93 89 OUT
I
BG8 I2CB_SCL_G R51500 1 2 2K_1%_2 GPIO17_IFPD_HPD R51563 1 2 10K_1%_2
I2CB_SCL
BF8 I2CB_SDA_G
89 OUT
I2CB_SDA R51501 1 2 2K_1%_2
GPIO18_IFPE_HDMI_HPD I
95 89 OUT R51564 1 2 10K_1%_2
D51510
I
GPIO24_IFPF_HPD R51565 1 2 10K_1%_2
DIODE-BAT54-TAP-PHP BJ1
89 OUT
THERMDN
60110GA0367T
D BJ2 THERMDP D
R51512
I
PEX_DGPU_RST# 1 2 OVERT_RST#
89 74 IN
10K_1%_2
BD6 GPIO0_GPU_VID
GPIO PULL UP
GPIO0
BB5 GPIO1_GC6_FB_EN
OUT 89
GPIO4_1V8_MAIN_EN I
GPIO1
OUT 89 105 89 OUT R51566 1 2 10K_1%_2
BD1 GPIO2_DGPU_EVENT#
ADC_IN_P BJ9
GPIO2
BE4
OUT 89
89 OUT GPIO5_FRM_LCK# R51567 1
I 2 10K_1%_2
98 IN
Vinafix.com
ADC_IN GPIO3
I
ADC_IN_N BJ11 BE1 GPIO4_1V8_MAIN_EN GPIO9_GPU_THERMAL_ALERT# R51540 1 2 10K_1%_2
98 IN ADC_IN* GPIO4
BG2 GPIO5_FRM_LCK#
OUT 89 105 89 OUT
GPIO5
BD2 GPIO6_NVVDD_PSI#
IN 89
89 OUT GPIO22_GPU R51568 1 2 2.2K_5%_2
GPIO6
BD7 GPIO7_LCD_BL_PWM
OUT 89
GPIO28_ADC_MUX_SEL I
GPIO7
OUT 89 98 89 OUT R51569 1 2 10K_1%_2
BH4 GPIO8_FBVDD_SEL
GPIO8
BJ3 GPIO9_GPU_THERMAL_ALERT#
OUT 89
GPIO9
BD3 GPIO10_MEM_VREF_CTL
BI 89
OUT 89
GPIO PULL DOWN
GPIO10
BK24 BH3 GPIO11_LCD_VDD_EN
BL23
JTAG_TCK GPIO11
BE6 GPIO12_DGPU_PWRLEVEL
OUT 89
BM23
JTAG_TMS GPIO12
BB1
IN 89
GPIO1_GC6_FB_EN I
JTAG_TDI GPIO13 89 OUT R51570 1 2 10K_1%_2
R51507 BM24 BG4 GPIO14_IFPA_HPD
DGPU_JTAG_TRSTB BL24
JTAG_TDO GPIO14
BG1 GPIO15_IFPB_HPD
IN 89
GPIO7_LCD_BL_PWM
JTAG_TRST* GPIO15
IN 89 89 OUT R51571 1 2 100K_1%_2
10K_1%_2 GPIO16 BE2 I
BH1 GPIO17_IFPD_HPD GPIO10_MEM_VREF_CTL R51572 1 2 1K_1%_2
GPIO17
BE3 GPIO18_IFPE_HDMI_HPD
IN 89 89 OUT
R51508 GPIO18
IN 89 95
DGPU_JTAG_SEL BK23 NVJTAG_SEL GPIO19 BD4 89 OUT GPIO11_LCD_VDD_EN R51573 1
I 2 10K_1%_2
BE5 GPIO20_FL_SYNC_GPU_FGC6
10K_1%_2
GPIO20
BA5 GPIO21_GPU
OUT 89
GPIO20_FL_SYNC_GPU_FGC6 I
GPIO21
BI 89 89 OUT R51574 1 2 10K_1%_2
BB6 GPIO22_GPU
GPIO22
BG3 GPIO23_GPU
BI 89
GPIO21_GPU
C GPIO23
BI 89 89 OUT R51575 1 2 100K_1%_2 C
BD5 GPIO24_IFPF_HPD
GPIO24
BB2 GPIO25_FBVDD_PSI#
IN 89
GPIO23_GPU
GPIO25
OUT 89 89 OUT R51576 1 2 100K_1%_2
BE7 GPIO26_FP_FUSE
GPIO26
BA4 GPIO27_IFPC_DP_HPD
OUT 99
GPIO29_IDLE_IN_SW I
GPIO27
IN 89 93 89 OUT R51577 1 2 10K_1%_2
BB4 GPIO28_ADC_MUX_SEL
GPIO28
BA3 GPIO29_IDLE_IN_SW
IN 89 98
GPIO29
BB3
OUT 89
GPIO30
GPIO0_GPU_VID 1 R51579 2 NVVDD_PWMID

89 IN OUT 108
P3V3_NV_SEQ P3V3_NV_SEQ 0_5%_2
GC6_FB_EN I
89 IN GPIO8_FBVDD_SEL 1 R51580 2 VRAM_DGPU_PWMVID
0_5%_2
OUT 112
100K_1%_2
A
1
10K_1%_2
2
LEVEL SHIFTER
R51592
R51593 I
A
B Q51592 P1V8S_AON1 B
EM6K1GT2R
2
1
G1
S1 1 3.3V LEVEL
2
10K_1%_2
1.8V LEVEL 6 GC6_FB_EN_PCH
10K_1%_2
2
OUT 44 73 105
2
D1 3
R51583
D2
R51586
GPIO1_GC6_FB_EN 5 G2
89 IN 4
S2
I
1
I
TP24
1
R51582 2

Acer CN517-71 - Inventec Covini-Alphard Rev X01 - 6050A3087502 (DIAGRAMAS - com.BR)

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Acer CN517-71 - Inventec Covini-Alphard Rev X01 - 6050A3087502 (DIAGRAMAS - com.BR)

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6 5 4 3 2 1

THIS DRAWING AND SPECIFICATIONS,HEREIN,ARE THE PROPERTY OF INVENTEC

12.SYSTEM POWER(P3V3DS) 47.SYSTEM MEMORY(DIMM0)

I2C0 BC22 PCH_I2C_CLK TOUCH PANEL

115 EC_SMB1_CLK CHARGER

GPU POWER BLOCK

9 OUT ACDRV 1 2 VADPBL OUT 9 0.1UF_16V_2

PMON PHASE VRPCHG_PH

SHORT_0402_15 C60024 R60012 10_5%_2

D60002 R60020 R60019

C60112 1 VIN BST 8

9 VRPVDDQ_PH 1 L60300 2 VRPVDDQ

CLOSE TO 3V3 & AGND

1 2 VRPVCCIO_VIN 1 9 0.1UF_16V_2 VRPVCCIO

1 R66112 2 1 2 VRACPU_CSCOMP 8 U66000 32 VRAGT_ILIM 1 R66305 2 I

93.1K_1%_2 75K_1%_2 NI I VRACPU_CSSUM CSSUM_4PH CSCOMP_2PH VRAGT_CSCOMP VRAGT_CSCOMP1 R66412 2 VRAGT_CSP1 20

VRACPU_CSP2 I VRACPU_CSREF CSREF_4PH CSSUM_2PH VRAGT_CSSUM

I VRACPU_CSP4 R66413 VRAGT_CSN1

VRACPU_CSN3 R66133 19 18 1 R66124 2

CHANGE by XXX DATE 21-OCT-2002

220_1%_2 12 PGND SW 26 VRACPU_PH4 1 2

SIZE CODE DOC.NUMBER REV

P1V05A P5V0DS 22UF_6.3V_3

R7030 VIN1 VOUT1

SIZE CODE DOC.NUMBER REV

1. P3V3DS / P5V0DS 3. P1V2 / P1V8 / VCCSFR(PVCCST)

P5VDS_EN R6901 D7000

C 2. P1V0A / P1V8A / P3V3A DIODE-BAT54-TAP-PHP 100_5%_2

P3V3A_5A_PWEN 1 I R7003 2 EN_1V05A 0.1uF_16V_2

R7014 1 R7021 2 3V3DS_PG

P5V0S TP24 P5V0S TP24

PAD4300 P5V0S_FAN1 PAD4301

1 ACES_50279_00401_Q01_4P TP4303 ACES_50279_00401_Q01_4P

REFERENCE 0~49(PCB SCREW)

FIX_MASK FIX_MASK SCREW420_700_1P

FIX_MASK FIX_MASK SCREW420_700_1P

FIX_MASK FIX_MASK SCREW420_700_1P

K36 D29 EDP_TX0_DP 62

39 30 H_PWRGD BT31 R4508

PLACE IN BACK SIDE PVCORE

AA13 AH13 U4555

A A A A A A A A A A AA36 AJ14 VCC5 VCC68

A A A A A A A A A A A AF29 AN33 VCC45

VCC47 VCC110 U35

AF31 AN35 VCC47

A A A AG33 AP38 VCC58

VCC60 VCC123 W14

J30 VCCSA1 VDDQ1 AA6

L35 VCCSA11 VDDQ11 AR12

J17 I I RSVD29 RSVD22

VCCIO18 VCCSA_SENSE OUT 18 BR35 BP1 1

PLACE IN TOP SIDE

2 1 C4709 10UF_6.3V_2 10UF_6.3V_2

C4726 C4708 10UF_6.3V_2

PLACE U4555 PIN BH13,BJ13,G11

PLACE IN BACK SIDE

PLACE IN BACK SIDE 1UF_6.3V_2 C4701

1UF_6.3V_2_DY 1UF_6.3V_2 22UF_6.3V_3

INTEL_J43242_BGA_1440P AH37 VGT_VSSSENSE 18 35

54 HDA_BCLK R4972 1 2 A 33_5%_2 HDA_R_BCLK BD11 BF36 10K_5%_2_DY

23 IN PCH_PWROK AY42 PCH_PWROK GPD2/LAN_WAKE# BG44

61 BI USB3_TX3P G12 USB31_3_TXP