ECE 221 – AC Circuit and System Lab

Lab 8: Pulse Amplitude Modulation (PAM) and Pulse Code Modulation (PCM)

Objective: In this lab, PAM and PCM signals will be generated through a sample & hold circuit.
An FPGA-based system will be used for data acquisition.

Introduction:
In digital communication systems, an analog signal, w (t), can be periodically sampled by a pulse
train, p ( t ) before transmission. The varying amplitude in the sampled discrete-time signal, w s (t) ,
reflects the information of w (t). This type of communication scheme is called as pulse-amplitude
modulation (PAM). The PAM signal, w s (t) , can be further processed by holding and quantizing
signal amplitude into N binary bits are used to represent the amplitude level of quantized signal,
w sh (t). After all the processes shown in Figure 1, a digital signal, w (n), is obtained for digital
communication. This type of signal is also called a pulse-code modulation (PCM) signal.

w (t) w s (t) w sh (t) w (n)

Hold Quantization
Sampler
Circuit N

p(t )
Figure 8.1 PAM and PCM signal generation
 Part A: PAM signal and sample-and-hold circuit

A circuit will be built to sample and hold an analog signal. Figure 8.2 shows the block diagram of
system, where w (t) is a signal generated by a signal generator, p(t) is a pulse signal generated from
a FPGA board.
w (t) w s (t) w sh (t)
Hold
Sampler
Circuit

p(t)
Figure 8.2 PAM signal and sampler circuit

Prelab (20 points)

1. Suppose an analog signal w ( t )=cos ( 2 π f w t ). p ( t ) is a sampling pulse train

p ( t ) =∑ δ ( t−nT s )
n
here the sampling frequency f S = 1 kHz ( the sampling period T S = 1 ms )
The sampled signal w s ( t ) =w ( t ) p(t ).
fS
Assuming there is an ideal low-pass filter (LPF) with cut-off frequency f cutoff = and unity
2
gain.

Sketch amplitude spectra corresponding to the input signal w ( t ), the sampling pulse train p ( t ) ,
the sampled signal w s ( t ) , the output signal at the output of the LPF, w out ( t )

(1) f w =200 Hz , f S =1kHz , f cutoff =500 Hz

(2) f w =400 Hz , f S =1kHz , f cutoff =500 Hz

(3) f w =800 Hz , f S =1kHz , f cutoff =500 Hz

Lab work (70 points)

1. Construct a sampling circuit using an analog switch, cd74hc4053.

 The pin layout of cd74hc4053 is shown below (see data sheet for details).

Figure 8.3 Pin layout of an analog switch

The connections of sampling circuit are described below.

V CC : +3.3 V ( from a power supply)
V EE : - 3.3 V ( from a power supply)
GND : Ground
E : Ground
A1 : Analog input, w ( t ), from a signal generator
A0 : Ground
S0 : Pulse train, p ( t ) , (i.e., pwm_sig from a source)
S1 : Ground
S2 : Ground
AN : PAM signal,w s (t) (to an oscilloscope)
Note: Be sure the source and the power supply of IC share a common ground.
The pwm_sig could be generated by a function generator, an FPGA board, or a MCU board.

2. Test the sampler circuit with the following conditions and record your observations.
Step #1 : Use a signal generator to apply an analog signal, w ( t )= A cos (2 πft )
where A=3V and f =200 Hz , to the sampling circuit (Pin #13, A1, of the
analog switch)
Step #2 : Apply a 20% duty-cycle pulse train, p ( t ) , to the sampling
circuit (Pin #11, S0 , of the analog switch)

Step #3: Record w( t ) , p ( t ) , and w s (t) in time and frequency domains.

Step #4: Change the frequency of w ( t ) to different cases: f =400 Hz and f =800 Hz .
Record w s (t) in frequency domain.
Note: There is no much changes on p ( t ) ∧w ( t ) .
3. Test the sampler circuit with the following conditions and record your observations.

Step #1 : Use a signal generator to apply an analog signal, w ( t )= A cos (2 πft )

where A=3V and f =200 Hz , to the sampling circuit (Pin #13, A1, of the
analog switch)

Step #2 : Apply a 10% duty-cycle pulse train, p ( t ) , to the sampling

circuit (Pin #11, S0 , of the analog switch)

Step #3: Record p ( t ) and w s (t) in frequency domain.

 Discuss your observations with the lab instructor.

4. Construct a sample&hold circuit using an analog switch (cd74hc4053) and an operational

amplifier (LMC6482).

1) The wiring information of cd74hc4053 is listed below. (Pay attention to the changes in
RED)
V CC : +3.3 V ( from a power supply)
V EE : - 3.3 V ( from a power supply)
GND : Ground
E : Inverted pulse train (i.e., pwm_sig_bar from a source)
A1 : Analog input, w ( t ), from a signal generator
A0 : Ground
S0 : +3.3 V (from a power supply)
S1 : Ground
 S2 : Ground
AN : A signal fed to LMC6482
Note: Be sure the source and the power supply of IC share a common ground.

2) The sample-and-hold circuit is shown below.

Figure 8.4 Sample-and-hold circuit

5. Test the sample-and-hold circuit with the following conditions and record your observations.

Step #1 : Use a signal generator to apply an analog signal, w ( t )= A cos (2 πft )

where A=3V and f =200 Hz , to the sampling circuit (Pin #13, A1, of the
analog switch)
Step #2 : Apply an 10% duty-cycle inverted pulse train, pwm_sig_bar,
to the sample-and-hold circuit (Pin #6, E , of the analog switch)

Step #3: Record the time-domain plot of w sh (t).

Post lab discussion (10 points)

Discuss your observation in the lab.
It was observed that time domain plot could be produced through the steps provided by
the lab.
Appendix[1]

Figure 8.5 below shows the sampling process to generate a PAM signal, where w s ( t ) is the sampled
signal, T s is the sampling period, and τ is the pulse width.

Figure 8.5. PAM signal and sampling process

It can be seen that

w s ( t ) =w ( t ) p(t ) (1)

where p ( t ) =∑ ∏
n
( t−nτ T )=¿ ∑ ∏( tτ )∗δ (t−n T ) ¿
s

n
s (2)

{
τ
∏( t
τ )
=
1∧|t|≤
2 (Rectangular function)
0∧others
 {
δ (t )= +∞ ∧t=0
0∧others
(Dirac delta function, δ function)

¿ is the convolution operator

To obtain Fourier transform of the sampled signal, first take Fourier transform of the sampling
function .

The spectrum of the sampled signal is then

For your reference:

1. PAM circuit

2. PAM circuit outputs

 3. Sample-and-hold circuit outputs

Part B: FPGA-based Data Acquisition System through SPI (serial peripheral interface)

Objective: the primary objective of part B is to learn how to interface analog-to-digital

(A/D) converter through a serial peripheral interface (SPI) bus, and how to synchronize
multiple systems from different clock domain in a digital design. Secondary objectives are
to gain experience in FPGA design implementation and verification.

An A/D converter daughter board (PmodAD1) is used to interface with an FPGA kit. The
circuit diagram of PmodAD1 is shown in Figure 1. It includes two ADCS7476 12-bit A/D
converter chips, two anti-alias filters and two connectors (J1 and J2). The ADCS7476 is a
low power, monolithic CMOS 12-bit A/D converter. Based on successive approximation
register architecture with internal track-and-hold, the device provides a digital serial
output. The serial interface is a compatible SPI bus.
 Figure 8.6 PmodAD1 circuit diagram

Design requirements:

(1) Input signal: unipolar, [0, 3.3 V]

(2) Converted data: LEDs [Optional: use 7-segment displays instead]
(3) At least 500 k samples per second
Prelab (week#2) :

1. Go through the ADC datasheet and design requirements, then answer the following
questions:
(1) What’s the maximum frequency of SCLK to the A/D device?
20 MHz
(2) How many cycles of SCLK are needed for each data sample?
1 MPSPS
(3) Show the timing diagram of data conversion

(4) List the I/O information of your VHDL design

iRESET => '0',
iCLK => clk_12_5M,
iEN_ADC => EN_ADC,
 iSDATA_ADC => ADC_DATA_IN,
oCS_L => CS_L,
oSCLK_ADC => clk_12_5M,
oADC_DATA_V => ADC_DATA_LEDS_OUT,
oDONE_ADC => DONE_ADC,
oBUSY_ADC => BUSY_ADC
(5) What’s the frequency of SCLK in your VHDL design
100MHz
(6) Show the block diagram of your VHDL design

2. Write VHDL codes for the data acquisition system

Lab work (week #2) :

Debug your VHDL codes and implement the ADC data acquisition system on an FPGA board.

(1) Record your results and complete the table below:

Input (Volt) LED result Theoretical result (Calculated)

3.3 V

2V

1.6 V

0.8 V

(2) Capture SCLK, CS and SDATA using a scope