Journal of VLSI Signal Processing 31, 77–89, 2002

c 2002 Kluwer Academic Publishers. Manufactured in The Netherlands.

A 16-Bit by 16-Bit MAC Design Using Fast 5:3 Compressor Cells

OHSANG KWON∗
SUN Microsystems Inc., Palo Alto, CA 94303, USA

KEVIN NOWKA
IBM Austin Research Lab, Texas 78758, USA

EARL E. SWARTZLANDER, JR.

Department of Electrical and Computer Engineering, University of Texas at Austin, Texas 78712, USA

Received October 17, 2000; Revised October 8, 2001

Abstract. 3:2 counters and 4:2 compressors have been widely used for multiplier implementations. In this paper,
a fast 5:3 compressor is derived for high-speed multiplier implementations. The fast 5:3 compression is obtained
by applying two rows of fast 2-bit adder cells to five rows in a partial product matrix. As a design example, a 16-bit
by 16-bit MAC (Multiply and Accumulate) design is investigated both in a purely logical gate implementation and
in a highly customized design. For the partial product reduction, the use of the new 5:3 compression leads to 14.3%
speed improvement in terms of XOR gate delay. In a dynamic CMOS circuit implementation using 0.225 µm bulk
CMOS technology, 11.7% speed improvement is observed with 8.1% less power consumption for the reduction
tree.

Keywords: 3:2 counter, 4:2 compressor, 5:3 compressor, 5:2 compressor, multiplier, MAC

1. Introduction are basic elements that are frequently used to reduce a

Multiplication is one of the most frequently encoun-
tered arithmetic operations in microprocessors and sig-
nal processors. Due to the delay and complexity of
multipliers, efficient designs have been pursued over
the last several decades. In this paper, a new design
method is proposed for multiplier, multiple adders and
fused MAC (Multiply and Accumulate) designs.
The fast multiplication process consists of three
steps [1, 2]: partial product generation, partial product
reduction and final carry-propagating addition. To
reduce the number of partial products, recoding tech-
niques have been widely used [3–5]. In the partial prod-
uct reduction step, 3:2 counters and 4:2 compressors
∗ Thiswork was done when the author was with the Department of
Electrical and Computer Engineering, University of Texas at Austin.
partial product matrix into two rows [1, 2, 6, 7]. The re-
duction process is performed with a CSA (Carry-Save-
Adder) array using the basic elements. A high-speed
carry-propagating adder is used to produce the final
result from the two rows.
In this paper, a new fast 5:3 compressor is proposed
for high-performance multiplier implementation. The
new fast 5:3 compressor is obtained by applying 2-bit
adder cells in parallel and a new logical decomposition
is used for fast implementation of the 2-bit adder. In
the new logical decomposition, the 2-bit adder cell has
2 XOR delays on the critical path. A 16-bit by 16-bit
MAC (Multiply and Accumulate) design is presented
using the fast 5:3 compressors and a radix-4 Booth
recoding technique.
In the MAC design, for high throughput operation,
the result of partial product reduction can be fed back
78 Kwon, Nowka and Swartzlander
directly to the next cycle in a redundant form (carry-
save). In this case, a new method can be used to elim-
inate one row of the partial product matrix before the
actual reduction process begins, which can eliminate
one 3:2 counter delay for some specific operand sizes.
Overall, the new design is 14.3% faster in terms of XOR
delays for the partial product reduction. In a highly cus-
tomized dynamic CMOS circuit implementation, it is
observed that the new method provides 11.7% speed
improvement while it consumes 8.1% less power in
the reduction tree.
In this paper, the new 5:3 compressor design is pre-
sented in Section 2. Section 3 presents a 16-bit by
16-bit two’s complement MAC implementation exam-
ple and compares the performance to a conventional
design. Section 4 discusses possible extensions of the
new method. Finally, a conclusion is given in Section 5.
2. New Compressors
2.1. 3:2 Counters and 4:2 Compressors
Figure 1 shows two block diagrams of a 3:2 counter.
3:2 counters have been widely used in fast multiplier
implementations from the earliest efforts [1, 2] to more
recent works in CMOS circuits [8–10]. A 3:2 counter
has three input bits of equal weight and two output bits,
sum and carry, of the same and one greater binary bit
weight, respectively. The sum output of a 3:2 counter
takes two XOR delays (an XOR delay is denoted xor ,
hereafter).
Figure 2 shows two logical decompositions of a
4:2 compressor [7, 10–12]. The 4:2 compressor has
Figure 1. 3:2 counters.
five input bits including a carry-in from the neighbor-
ing less significant cell and three outputs including a
carry-out to the more significant neighboring cell. Both
designs shown in Fig. 2 have 3xor on their longest
path.
2.2. A 5:3 Compressor
A fast 5:3 compressor can be constructed with 2-bit
adder cells. Figure 3 shows the block diagrams of two
fast 2-bit adder cells. To minimize the delay, two differ-
ent logical decompositions of a full adder are combined
to form the 2-bit adder. The first full adder (Type-I) has
three input bits in the less significant bit position and
calculates an output carry in a fast manner. The second
full adder (Type-II) accepts the carry input in the mid-
dle of its calculation. Through combining the different
full adder styles for the 2-bit adder configuration, the
overall delay of the 2-bit adder is only 2xor which is
the same as that of a 1-bit full adder’s sum bit delay.
Figure 4 shows a fast 5:3 compression that is im-
plemented using the fast 2-bit adder cells. By applying
two rows of 2-bit adder cells in parallel, five rows are
reduced to three rows as shown in the figure.
Using the new fast 5:3 compression, the speed of
multipliers and fused multiply-adders can be improved
as will be explained in Sections 3 and 4. Here, XOR
delay is used as the speed measure of 3:2 counters,
4:2 compressors and the new 5:3 compressors since
all of their logical decompositions employ a series of
XORs. In this way, the speed comparison can be made
independent of specific technologies though actual rel-
ative delays may be slightly different depending on
specific circuit families and fabrication technologies
employed. Many multiplier designs use specially de-
signed counters and compressors depending on their
processing technology. Section 3 gives an example of
the fast 2-bit adder cell design using a fully customized
dynamic CMOS circuit.
2.3. 5:2 Compressors
The 5:3 compressor can be used to build other com-
pressors. Figure 5 shows a 5:2 compressor cell using
the fast 5:3 compressor and a 3:2 counter. It has five di-
rect input bits (a, b, c, d, e) and two additional carry-in
bits (x1 in, x2 in) from a neighboring less significant
cell. Among four output bits, two are carry-out bits
(x1 out, x2 out) to the neighboring more significant
 A 16-Bit by 16-Bit MAC Design 79

Figure 2. 4:2 compressors.

Figure 3. Two logical decompositions of a fast 2-bit adder. (a) type-I; (b) type-II.

cell and one carry bit (carry) of one-greater signifi- carry, sum are output bits in Fig. 6. Then,
cance and a sum bit (sum). It has a sum delay of 4xor
on the critical path. a + b + c + d + e + x1 in + x2 in
Figure 6 shows another 5:2 compressor cell which = (x1 out + x2 out + carry) · 2 + sum. (1)
also has a sum delay of 4xor [13]. Its carry output has
the same delay as the sum output while the carry output Proof : From the definition in Table 1, the following
is faster than the sum in the block diagram shown in holds true.
Fig. 5.
The following theorem proves the correctness of x1 out = ((a ∨ b) ∧ (c ∨ d)) (2)
the 5:2 compressor in Fig. 6.
s1 = ((a ∧ b) ∨ (c ∧ d)) (3)
Theorem 1. a, b, c, d, e, x1 in, x2 in are input bits (s1 ⊕ n) = ((a ⊕ b) ⊕ (c ⊕ d)) (4)
of the 5:2 compressors in Fig. 6 and x1 out, x2 out, a + b + c + d = x1 out · 2 + s1 + n. (5)
80 Kwon, Nowka and Swartzlander

Figure 4. 5:3 compression using 2-bit adder cells.

Figure 6. A direct 5:2 compressor logical decomposition.

s2 ≡ ((s1 ⊕ n) ⊕ x1 in) (7)

Figure 5. A 5:2 compressor cell using a 5:3 compressor and a 3:2
counter. s1 + n + x1 in = x2 out · 2 + s2 . (8)

Let x2 out and s2 represent the carry and save terms In a similar manner, let carry and sum be carry and
of (s1 + n + x1 in), respectively. Then, sum of (s2 + e + x2 in), respectively. Then,

x2 out ≡ (s1 ∧ n) ∨ (s1 ∧ x1 in) ∨ (n ∧ x1 in) carry ≡ (((s2 ⊕ e) ∧ e) ∨ ((s2 ⊕ e) ∧ x2 in)) (9)
= (s1 ∧ n) ∨ (x1 in ∧ (s1 in ∨ n)) sum ≡ ((s2 ⊕ e) ⊕ x2 in) (10)
= (((s1 ⊕ n) ∧ s1 ) ∨ ((s1 ⊕ n) ∧ x1 in)) (6) s2 + e + x2 in = carry · 2 + sum. (11)
 A 16-Bit by 16-Bit MAC Design 81

Table 1. A redundant representation of (a + b + c + d). high-throughput operation, the accumulator stores an

a+b+c+d Other conditions x1 out
0 0
1 0
2 ((a ∧ b) ∨ (c ∧ d)) 0 1
((a ∨ b) ∧ (c ∨ d)) 1 0
3 1
4 1
From Eqs. (5), (8) and (11),
a + b + c + d + e + x1 in + x2 in
= x1 out · 2 + s1 + n + e + x1 in + x2 in
= x1 out · 2 + x2 out · 2 + s2 + e + x2 in
= (x1 out + x2 out + carry) · 2 + sum.
It is readily seen that the block diagram of Fig. 6 gen-
erates x1 out, x2 out, carry and sum according to their
definitions in Eqs. (2), (6), (9) and (10) respectively.
3. A Design Example: 16-bit × 16-bit
MAC Design
3.1. A Logical Architecture of a MAC Using
the New 5:3 Compressor
Figure 7 shows a block diagram of a 16-bit by 16-bit
2’s complement MAC design. To reduce the number of
partial products, radix-4 Booth recoding is used. For
n s1 intermediate result in a carry-save form and the accu-
mulator output is fed back for the next accumulation
0 0 operation. In this manner, carry propagating addition
1 0 is separated from the critical path in MAC operation.
1 The partial products and accumulator output are com-
0 bined to form a partial product matrix and undergo 11:2
0 1 reduction process. The final two rows after the final
1 1 reduction process are added in the carry-propagating
adder.
Figure 8 shows the necessary 11:2 reduction tree ob-
tained using two 5:3 compressors, three 3:2 counters
and a 4:2 compressor. Figure 9 shows the reduction
process starting from the partial product matrix. In the
partial product matrix, the sign bits of partial products
are shown as white dots and carry-ins of partial prod-
ucts are shown as grey dots. A bar above a dot means
(12)
the logical inverse of the dot. When a recoded digit is
negative, the corresponding partial product has a carry-
in. The method of handling two’s complement partial
products in the partial product matrix is well discussed
in [14, 15].
The partial product matrix consists of eight partial
products obtained through radix-4 Booth recoding and
two rows from the accumulator output. The maximum
height of bit slice is eleven since there are carry-ins
with partial products due to the possible negative re-
coded digits in the Booth recoding process. However,
the accumulator output bits are available at the begin-
ning of the cycle. The carry-in bit of the partial prod-
uct and constant one’s are also available without any
delay in the cycle. Therefore, the bottom three rows

Figure 7. A block diagram of 16-bit by 16-bit MAC. Figure 8. A reduction tree for 11:2 compression.
82 Kwon, Nowka and Swartzlander
Figure 9. A dot diagram of 11:2 reduction process.
in the partial product matrix can be reduced to two
rows using a row of full adders simultaneously dur-
ing the partial product generation. The partial product
generation requires one Booth encoding delay and one
Booth decoding (5:1 MUX) delay which is longer than
one full adder delay. With the pre-reduction row of full
adders, there are only ten rows to be reduced in the main
reduction process.
Figure 9 shows the detailed view of the reduc-
tion process using the new reduction tree. Overall,
the design using the new 5:3 compressor takes 7xor
compared to the 8xor required by a conventional
 A 16-Bit by 16-Bit MAC Design 83

design using 4:2 compressors and 3:2 counters, which Table 2. A new booth encoding.
is 14.3% speed improvement. X 2i+1 X 2i X 2i−1 Pi Mi Xi 2X i

0 0 0 0 0 1 1
3.2. Circuit Implementation
0 0 1 1 0 1 0
0 1 0 1 0 1 0
The radix-4 Booth recoding technique has been widely
0 1 1 1 0 0 1
used since it reduces the number of partial products by
approximately half [3–6, 16]. There are well-known 1 0 0 0 1 0 1
Booth encoding methods and the corresponding static 1 0 1 0 1 1 0
CMOS circuits in previous works [6, 16]. However, for 1 1 0 0 1 1 0
dynamic CMOS circuit implementation, dual-rail sig- 1 1 1 0 0 1 1
nals are required at the output of the Booth decoders.
This entails at least five control signals for single-stage
Booth decoder implementation using direct implemen- decoder circuit, for the complementary signal genera-
tation of previous encoding methods. tion, a control signal is needed to indicate a recoded
In this paper, a new encoding method is used and it value of zero. Using the new encoding method, this
will be shown that four control signals are enough with event can be represented when both X and 2X are high
a carefully designed Booth decoder circuit. This will be and the circuit can be configured to take advantage of
helpful in large multiplier designs where interconnec- it. Note that some of the NMOS devices are shared
tion complexity is one of design bottlenecks. Table 2 between adjacent Booth decoder cells to minimize the
shows the new encoding method. Figure 10 shows its cell area of the Booth decoder.
dynamic CMOS implementation and Fig. 11 shows the Figure 12 shows a dynamic implementation of the
accompanying Booth decoder circuits. In the Booth fast 2-bit adder cells. To minimize the number of

Figure 10. A booth encoding circuit.

84 Kwon, Nowka and Swartzlander

Table 3. Performance comparison of reduction trees.

Conventional
New scheme scheme [10]

No. of domino stages 4 5

Delay 149 ps (5:3) 209 ps (4:2-I)
118 ps (3:2) 112 ps (3:2)
187 ps (4:2) 186 ps (4:2-II)
Total: 454 ps 507 ps
No. of TRs used/bit slice 382 426
Power consumption/bit slice 4.19 mW 4.56 mW

eliminates one xor in the partial product reduction.

Figure 11. A booth decoding circuit.
devices and to get fast operation, the 2-bit adder cell is
designed using multiple output domino logic (MODL)
where some intermediate nodes in the evaluation paths
are used as outputs as well. In Fig. 3, two XOR stages
are needed for fast implementation of the 2-bit adder
cell. The 2 stages are logically combined in a 1-stage
domino implementation instead of separate 2-stage
domino implementation for faster operation.
3.3. Performance Comparison
In the 16-bit by 16-bit MAC design, the new 5:3 com-
pressor was applied and it was shown that it effectively
That is, it takes 7xor instead of 8xor in a conven-
tional design, which is 14.3% speed improvement.
Table 3 shows a circuit simulation result using highly
customized dynamic CMOS circuit implementation in
0.225 µm bulk CMOS technology [17]. The conven-
tional design uses only 4:2 compressors and/or 3:2
counters in the reduction tree [10]. The new design uses
the new 5:3 compressors as well as the 4:2 compres-
sors and 3:2 counters as seen in Fig. 8. In fast dynamic
CMOS implementations, a 3:2 counter is implemented
with 1-stage domino logic and a 4:2 compressor is im-
plemented with two cascaded domino full adders. The
new 5:3 compressor in Fig. 12 is implemented using
only 1-stage domino logic and thus is much faster than
the 4:2 compressor. In the reduction tree, the new de-
sign requires only four domino stages while the conven-
tional scheme has five domino stages. In domino logic
implementation, it is important to reduce the number of
stages since each domino stage has an output inverter

Figure 12. A fast 2-bit adder implementation using MODL.


as well as a NMOS pull-down path. Overall, the new
design has an 11.7% speed improvement over the con-
ventional design with less number of devices and less
power comsumption as seen in Table 3. The advantage
mainly comes from the use of the new efficient 5:3
compression using the fast 2-bit adder cell.
In the circuit implementation, dynamic CMOS cir-
cuits are exclusively used for maximum performance.
In general, CMOS circuits are classified into static
CMOS and dynamic CMOS circuits. Static CMOS
circuits are good for moderate performance and low
power consumption. For high performance operation,
dynamic circuits are often used at the cost of overhead
for precharge clock distribution and relatively large
power consumption. Nonetheless, the use of dynamic
CMOS circuits have been reported in many high-end
processor designs where circuit speed is more impor-
tant than other design factors [18–20]. For static circuit
implementation, it should be noted that the dynamic
CMOS circuit topology in this paper can be directly ap-
plied to DCVS (Differential Cascode Voltage Switch)
circuits since their topology is quite similar. The logi-
cal decompositions in Section 2 can be implemented in
popular CPL (Complementary Pass-gate Logic), DPL
(Differential Pass-gate Logic) and static CMOS circuits
as well.
4. Discussion
4.1. 5:3 Compressor
In this paper, a new 5:3 compressor is applied to
a 16-bit by 16-bit MAC design. In general, the 5:3 com-
pressor can be used for other multiplication or multiply-
addition applications.
Figure 13 shows a 5:3 compressor tree example for
21:2 reduction. For maximum performance, 3:2 coun-
ters are used whenever 3 or 4 rows are left even after
the application of 5:3 compressors. The delay is given
as follows.
A 16-Bit by 16-Bit MAC Design 85
Figure 13. 5:3 Compressor tree architecture for 21:2 reduction.
performance is mainly determined by compressor cell
design. In addition, the performance can be different
depending on specific operand sizes because the use of
a specific compressor leads to a specific sequence of
maximum numbers of rows to be handled. Figure 14
shows delay comparison for various number of input
rows in dynamic CMOS circuit implementation. The
Wallace tree performs especially well when the num-
ber of rows is 6, 9, 37–42 and 59–63. The binary tree is
good when the number of rows is 4, 14–16 and 59–64.
The 5:3 compressor is best when the number of rows
is 5, 10–13, 17–21, 33–35, 43–58 and 65–70.
So far, the use of the new 5:3 compressor was
compared with conventional partial product reduction
methods using 3:2 counters and 4:2 compressors. In
these methods, the reduction architecture and its delay
is determined by the tallest vertical bit slice in a PPM
(partial product matrix). The logic elements and their
interconnections in the vertical slice is replicated to dif-
ferent bit positions. This approach has been widely used
in fully customized circuit implementations of large
multipliers where interconnection complexity and de-
sign modularity are major design bottlenecks. One of
recent works on partial product reduction is to use an al-
gorithmic approach utilizing delay difference of carry
and sum outputs to attain maximal performance [7].
delay = log5/3 (n/3) · 5:3 +  F A
The maximum number of rows which the 5:3 compres-
sor tree architecture can handle is
5, 8, 13, 21, 35, . . .
starting from tree height of 2. Since the delay
is O(log n) as in Wallace/Dadda tree, the relative
(13) The basic idea of this method (called TDM (Three
Dimensional Minimization)) is to make proper con-
nections globally over entire vertical bit slices so that
the delay throughout each path is approximately the
same. The long delay path originating from the previ-
ous compressor should be connected to the short delay
path of the next one, and so on. This method is effective
and known to be optimal when there is a distinct de-
lay difference among logic paths inside a compressor
86 Kwon, Nowka and Swartzlander
Figure 14. Delay comparison: Tree architectures with dynamic CMOS circuit implementation.
cell as in Fig. 1. However, in fully customized circuit
implementations, compressors and/or counters are de-
signed to minimize overall delay and transistor counts.
The distinct delay difference is not usually found in
many customized circuit implementations. In addition,
the algorithmic approach leads to different intercon-
nections on different bit slices which is a major design
bottleneck in large multipliers where interconnection
complexity is a dominant design factor as well as area
and power consumption.
The 5:3 compressor has a similarity with the algo-
rithmic approach in the viewpoint that it utilizes the
delay difference on paths from inputs to outputs dur-
ing logic derivation. However, in the 5:3 compressor,
connections are optimized within a local area (the 5:3
compressor itself which spans over only 2 consecu-
tive bit positions) and the resulting cell has equal de-
lay on outputs from the viewpoint of logical analysis.
Thus, the conventional partial product reduction meth-
ods can be applied in a similar manner and the ben-
efit of interconnection regularity and design modular-
ity of conventional reduction methods are preserved.
Simultaneously, delay and area can be improved by
circuit optimization in the cell itself as shown in the
circuit implementation example of Section 3.2.
4.2. Booth Encoding and Pre-Reduction Technique
In multiplier designs, radix-4 Booth recoding technique
has been widely used for partial product generation
though the recoding entails Booth encoder and Booth
decoders to compress the original partial products into
half. In fact, the similar compression can be done using
one 4:2 compression stage. The advantage of the Booth
recoding technique comes from the following aspects:
speed, area and power consumption.
In terms of delay, the recoding involves encoder and
decoder delay while non-Booth recoding takes one
2-input AND gate and a 4:2 compressor delay. It should
be noted that delay comparison depends on specific im-
plementation styles and its investigation is beyond the
scope of this paper. Nonetheless, it is seen that radix-4
recoding is preferred especially in many custom circuit
implementation since encoding and decoding can be
implemented in one custom logic gate, respectively.
Specifically, in dynamic CMOS circuit implementa-
tion, radix-4 recoding involves only two domino stages
while non-Booth recoding takes 2 domino stages for
4:2 compressor delay and another for 2-input AND
gate. In terms of area, one Booth decoder performs the
role of one 4:2 compressor if the relatively small Booth
encoding logic is ignored. In custom circuit designs,
the Booth decoder is easily implemented as one custom
logic gate and its area can be minimized by sharing
some transistors with adjacent cells just as in a dynamic
CMOS circuit implementation of Fig. 11 while a 4:2
compressor requires two 3:2 counters. The less area and
fewer logic stage leads to less power consumption, too.
Radix-4 Booth recoding is used in the implementation
example of this paper to reflect these advantages.
In addition, in the MAC design example, a row of
full adders was used for 3:2 reduction for three rows
not driven by the Booth recoder in the partial product

Figure 15. Partial product matrix for a 13-bit by 13-bit 2’s complement MAC.
matrix prior to the main reduction process. The delay of
the full adder row is smaller than that of partial product
generation when radix-4 or higher radix recoding tech-
niques are used. In these recoding techniques, Booth
encoding and Booth multiplexing are needed for the
partial product generation.
If the delay of partial product generation is greater
than that of a 4:2 compressor, 4:2 compression can
be used for the early available 4 rows in the partial
product matrix. Figure 15 shows an example of this
case, which is useful to reduce one more row in the
partial product matrix before partial product reduction
process begins. The example is for a 13-bit by 13-bit
2’s complement MAC design. Using this method, the
delay become 6 xor for 8:2 reduction instead of 7 xor
for 10:2 reduction. This method is applicable when the
operand width of the MAC is an odd number.
5. Conclusions
In this paper, a new fast 5:3 compression method is
derived from a fast 2-bit adder cell. The 2-bit adder
cell has the delay of 2 xor when a new logical de-
composition is used. In addition, its one-stage dynamic
CMOS circuit is proposed for highly customized de-
sign methodology. For the partial product reduction of a
16-bit by 16-bit MAC, the use of the new 5:3 compres-
sor cell leads to 14.3% speed improvement in terms of
XOR delay. In highly customized dynamic CMOS cir-
A 16-Bit by 16-Bit MAC Design 87
cuit implementation, 11.7% speed improvement is ob-
served with 8.1% less power consumption in 0.225 µm
bulk CMOS technology.
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Ohsang Kwon is a member of technical staff at SUN Microsys-
tems, Inc., Palo Alto, California, where he is involved in developing
Ultra-Sparc III, IV microprocessors for high-end servers. His re-
search interests are in computer arithmetic, high-speed CMOS circuit
implementation. He obtained Ph.D. in electrical and computer engi-
neering at The University of Texas at Austin in 2000. His dissertation
research was in the field of computer arithmetic and its high-speed
CMOS circuit implementation. He received M.S. and B.S. in elec-
tronics engineering at Seoul National University, Seoul, Korea in
1992 and 1990, respectively. From 1992 to 1997, he worked for Dae-
woo Electronics Co. Ltd., Seoul, Korea as research engineer. During
this period, he developed image decoder, demodulator and channel
decoder for a prototype digital HDTV and worked on their VLSI
implementations. From 1998 to 2000, he worked for IBM Austin
Research Laboratory, where he was engaged in 1 GHz PowerPC
prototype development and then explored high-speed CMOS
circuit implementation of 64-bit multipliers and adders. He has been
with Microelectronics Division at SUN Microsystems since 2000.
He published 7 papers in several international conferences and is an
inventor or co-inventor of 10 U.S. patents.
ohsang.kwon@eng.sun.com
Kevin J. Nowka received his B.S. degree in computer engineering
from Iowa State University in 1986 and his M.S. and Ph.D. degrees
in electrical engineering from Stanford University in 1988 and 1995,
respectively. He joined the IBM Austin Research Laboratory in
1996 where he has conducted research on CMOS VLSI circuits and
arithmetic functions for application to the design of high-frequency
and low-power CMOS processors. He developed circuits for two
gigahertz microprocessors and for an ultralow-power embedded
PowerPC processor. He holds fourteen patents related to processor
design.
nowka@us.ibm.com
Earl E. Swartzlander, Jr. is a Professor of Electrical and Computer
Engineering at the University of Texas at Austin, where he holds the
Schlumberger Centennial Chair in Engineering. Previously he held
a variety of engineering and technical management positions with
TRW Defense and Space Systems from 1975 to 1990. His research
interests are in application specific processing and the interaction

between computer architecture and VLSI technology. This involves
computer arithmetic, VLSI development and digital signal processor
implementation. He is currently the hardware area editor for ACM
Computing Reviews, the computer arithmetic editor for the Journal
of Systems Architecture. He has been the Editor-in-Chief of the IEEE
Transactions on Computers, the IEEE Transactions on Signal Pro-
cessing and was the founding Editor-in-Chief of the Journal of VLSI
Signal Processing. He has been a member of the Board of Governors
of the IEEE Computer Society (1987 to 1991), the ADCOM/Board of
Governors of the IEEE Signal Processing Society (1992 to 1994) and
a member of the IEEE Solid-State Circuits Council/Society (1986
to 1991). He was the Secretary of the IEEE Solid-State Circuits
Council (1992 to 1993) and Treasurer of the IEEE Solid-State Cir-
cuits Council/Society (1994 to 1998). He has been a member of the
IEEE History Committee since 1996. He has chaired or co-chaired
many conferences including the following: the IEEE Workshop
on Signal Processing Systems (SiPS) Design and Implementation
A 16-Bit by 16-Bit MAC Design 89
(Lafayette, LA, October 11–13, 2000), the IEEE International
Conference on Application-Specific Systems, Architectures, and
Processors (Boston, MA, July 10–12, 2000), the 31st Asilomar Con-
ference on Signals, Systems & Computers (Monterey, CA, 1997),
the 1994 International Conference on Application Specific Array
Processors (San Francisco), the 1993 International Conference on
Parallel and Distributed Systems, Taiwan, and the 11th Symposium
on Computer Arithmetic (Windsor, Canada, 1993). He obtained his
doctorate in computer design with the support of a Howard Hughes
Doctoral Fellowship. He is a Fellow of the IEEE and is a regis-
tered professional engineer in four states. He has been recognized as
an Outstanding Electrical Engineer and a Distinguished Engineer-
ing Alumnus of Purdue University and has received a Distinguished
Engineering Alumnus Award from the University of Colorado. He is
also a member of the IEEE Computer Society Golden Core and the
recipient of an IEEE Third Millennium Medal.
eswartzla@aol.com