Energy Efficient Multiplier for

Reconfigurable Digital filter

Dr.S.Karthick Dr.C.Kamalanathan Dr.Sunita Panda

Department of Electronics and
Communication Engineering
Koneru Lakshmaiah Education
Foundation
Vaddeswaram,Andra Pradesh,India
karthickapplied@gmail.com
Department of Electrical,Electronics
and Communication Engineering
GITAM School of Technology
GITAM Deemed to be University
Bengaluru,India
kamalanadhan@gmail.com
Department of Electrical,Electronics
and Communication Engineering
GITAM School of Technology
GITAM Deemed to be University
Bengaluru,India
sunita.nano@gmail.com

Abstract— The growth of personal computing devices as
portable desktops, personal digital assistants, multimedia and
personal computers demands a complex functionality with
efficient computations. Digital systems with present day
technologies possess a very high computing capability that makes
powerful workstations. The demand for low power consumption
is prominently increasing as the device feature size shrinks into
submicron dimensions. Power dissipation can become the
bottleneck for the current designs because of battery life and
cooling requirements of portable equipment’s. Excessive power
consumption degrades the reliability and limits the transistor
integration on a chip. With, ever increasing quest for higher
computing power on battery operated devices, design emphasis
on optimizing area, power with high performance. The total
power dissipation of the proposed compressor is found to be
11.796 µW and 5.168 µW with the corresponding delay of 0.649
ns and 0.437 ns for 180 nm and 90 nm technologies respectively.
It reveals a PDP reduction of the proposed compressor to be
5.50% to 15.83% for 180 nm technology, 4.48% to 14.89% for 90
nm technology compared with other state-of-the-art designs.
This suggests the suitability of the proposed compressor design
for portable applications. An 8-bit Wallace tree multiplier is
designed using the proposed compressor and other state-of-the-
art designs. From the comparison, it is seen that the multiplier
design using proposed compressor architecture achieves better
performance in terms of PDP compared to other state-of-the- art
designs.
Keywords—Multiplier, Digital filter, Compressor
I. INTRODUCTION
Digital signal processing includes filtering, averaging,
correlation and modulating the signals in digital form to
estimate the characteristic parameters of a signal.
Advancements in DSP have permitted many applications
with unprecedented growth capabilities. Digital computers
and special purpose digital hardware performs complex
signal processing tasks. Even though the VLSI technology
has rapid exponential growth characterized by Moore’s law,
there is a boon in low power design parallel to technology
scaling. Complex sensor and monitoring systems in
biomedical applications implemented in general purpose
computing are highly sensitized to power consumption due
to the scaling of technologies. Hence designers are forced
towards power constrained designs for the development of
low power biomedical monitoring systems.
Many digital signal processing applications uses filtering
as the underlying component. Adders and multipliers form the
basic processing elements of the digital filters. The partial
product accumulation stage of the multiplier occupies a high
fraction of silicon area and consumes significant amount of
power. Therefore, increasing the speed of partial product stage
and reducing its power dissipation are crucial to improve the
performance of the multiplier. Chang et al. (2004) proposed
the low power compressors capable of improving the
performance of multiplier circuits. Aliparast et al. (2013)
presented the ultra high speed 4-2 compressor for fast digital
arithmetic circuits. Low power circuits can be obtained by
minimizing the number of inverter (Shams & Bayoumi 1997).
Systolic array architecture increases the throughput and
maintains regularity & modularity cells of VLSI system
designs (Parhi 2001). Vinoth et al. (2011) uses Sklansky adder
to implement 4:2 and 5:2 compressor architectures. The
proposed architecture consumes 1.436 mW power with the
reduction of 4.57% compared to conventional Wallace tree
multiplier. Ghasemzadeh et al. (2014) designed a novel 4:2
compressor structure to reduce the glitches at the output
waveform. The speed is enhanced by faster production of
intermediate carry. Jamshidi et al. (2015) proposed magnetic
tunnel junction and complementary metal oxide
semiconductor based architecture for 4:2 compressor designs.
The proposed architecture reduces the number of elements and
interconnections in the compressor cell. Howard et al. (2005)
compared standard CMOS, hybrid CMOS and pass transistor
logic based compressors. The compressors are selected based
on power, area and speed requirements. Kandasamy et
al.(2018) presents the high-speed adder circuit design based
on 18 transistor (18T) full swing gate diffusion input based
logic gates and transmission based techniques to compute the
sum and carry bits. Nehru et al.(2017)incorporate a different
kinds of adders and the performance was determined by the
trade-offs between power delay and area parameters. (Huang
et al. 2012) proposed systolic array based digital filter for the
QRS detector of ECG analysis to increase the throughput of
the digital filter. Gavaberet.al.(2019) proposed architecture
uses a low-power three-input XOR gate to reduce area, delay
and power consumption. Energy efficient compressor is
proposed in this work. The performance of the proposed
compressor is verified by implementing in systolic array based
digital filter.
II. SYSTOLIC ARRAY BASED DIGITAL FILTER
Digital filters are used in the pre-processing stage of QRS
detection algorithm. Band pass filters are used to reduce the
wave interference, noise and baseline wanders in QRS
preprocessing stage. The low pass and high pass filters are
cascaded to form the band pass filter. The amplitude response

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of the band pass filter is designed to approximate the spectrum
of the average QRS complex and effectively passes the
characteristic frequencies by attenuating higher and lower
frequencies.
Fig. 1. Digital Filter with Systolic Array Architecture
Systolic array architecture contains a set of interconnected
cells called processing elements each capable of performing
simple operations. Systolic array architecture computes and
passes the data using a network of Processing Elements (PEs).
These processing elements maintain the regular flow of data
in and out of the system. All the processing elements in a
systolic array are uniform and pipelined. Replacing a single
processing element with array of processing elements
increases the computational throughput without increasing the
memory bandwidth. Figure 1 shows the systolic array
architecture for digital filters. The systolic array architecture
is used to build the digital filter to achieve the tradeoff
between throughput and hardware required. The systolic array
architecture shown in Figure 1 consists of delay elements,
adders and multipliers. Adder and multiplier form the basic
processing element shown within the dotted area in Figure 1.
The processing elements can be connected in an array
structure to implement the digital filter (Huang et al. 2012).
Multiplier efficiency determines the performance of digital
filter when power consumption and throughput are considered
as the limiting factor.
the partial product terms. The second stage is the reduction of
partial product terms using accumulator. Carry propagate
adders are used at the last stage to obtain the final product
terms. The second stage of partial product accumulation called
as carry save adder tree which determines the area, throughput
and power consumption of the multiplier. The reduction of
these partial products involves the parallel application of
compressors
III. PROPOSED 4:2 COMPRESSOR
In proposed 4:2 compressor gate level optimization is done
to improve the energy efficiency of the compressor. The 4:2
compressor consists of five inputs and three outputs. The
arithmetic functionality of 4:2 compressor is represented by
the equation (1).
Z1 + Z2 + Z3 + Z4 + Cin = 2 x (Cout + Cox) + Sout (1)
The sum output (Sout) of the proposed compressor is
expressed by the equation (2). From the equation (2)
if Cin = 0 and odd number of inputs are high, the sum output
will be high. For Cin = 1, the Sout will be high if even number
of inputs are high.
Sout = (Z1 ⨁ Z2) ⨁ (Z3 ⨁ Z4) ⨁ Cin (2)
The carry outputs Cox and Cout of the proposed 4:2
compressor is represented by equations (3) to (7).
Cox = (Z1 ⨁ Z2 ) Cin + Z1Z2 (3)
= Z1Z2’Cin + Z1’Z2Cin + Z1Z2 (4)
= Z1Z2’Cin + Z1Z2 + Z2Cin (5)
= Z1Cin + Z1Z2 + Z2Cin (6)
Cout =(Z1 ⨁ Z2 ⨁ Cin) Z3 + (Z1 ⨁ Z2 ⨁ Cin) Z4 + Z3Z4 (7)
TABLE I. TRUTH TABLE OF PROPOSED 4:2 COMPRESSOR
ARCHITECTURE

No of High
Cin Cox Cout Sout
Logic (Z*)
0 0 0 0 0
1 0 0 0 1
2 0 1 0 0
3 0 1 0 1
4 0 1 1 0
0 1 0 0 1
1 1 0 1 0
2 1 1 0 1
3 1 1 1 0
4 1 1 1 1

The truth table of the proposed 4:2 compressor is

Fig. 2. Z × Z Multiplier Processing Stages
A fast tree multiplier involves three processing stages as
shown in Figure 2. The first processing stage is to generate
illustrated in Table 1, where Z* is the number of logic high
inputs. Figure 3 shows the proposed 4:2 compressor
architecture. Based on And-Or-Invert (AOI) logic it can be
seen that 8 NOT gate + 12 AND gate + 6 OR gate make up
the conventional compressor design using full adders. The
proposed compressor design shown in Figure 3 is made by 7
NOT gate + 14 AND gate + 7 OR gates. The area count is
evaluated by counting the total number of NAND gates that
make the circuit. The NAND equivalent of NOT gate is taken

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as 1 unit, AND gate is taken as 2 units and OR gate is taken as TABLE III PERFORMANCE COMPARISONS OF PROPOSED AND
3 units for calculating the area count of the proposed EXISTING COMPRESSOR ARCHITECTURES
compressor and other state-of-the-art designs. The delay of the Performance Metrics Area Delay Power PDP
proposed compressor design shown in Figure 3 is 2* ∆xor + Compressors
(µm)2 (ns) (µW) (µW-
1* ∆and + 2* ∆or + 1* ∆not. Table 2 gives the gate count in ns)
NAND equivalent and delay of the proposed compressor and Conventional
other state-of-the-art designs. The proposed logic has Compressor

125.19

11.116
0.796

8.848
minimum number of inverter in the critical path. The proposed Using Full
compressor reduces the number of gates required, which Adders
minimizes the interconnect delays and the associated glitches. Logic Level
Optimized

159.03

13.177
0.633

8.341
Compressor
(Chang et al.
2004)
High Speed

168.56

14.601
0.623

9.096
Compressor
(Baran et al.2010)
180
nm Logical
Decomposed
Compressor

154.51

12.836
0.642

8.241
(Pishvaie et al.
2013)

Ultra High Speed

Compressor

164.48

13.526
0.599

8.102
(Aliparast et. al.
2010)
Fig. 3. Proposed 4:2 Compressor
Proposed
Compressor

140.49

11.796
0.649

7.656
TABLE II NAND EQUIVALENT GATE COUNT AND DELAY OF
THE PROPOSED COMPRESSOR AND OTHER STATE-OF-THE-ART
DESIGN
Conventional
4:2 NAND Equivalent Delay Compressor

65.41

0.534

4.833

2.581
Compressor Using Full
NOT AND OR Adders
Conventional 8 24 18 4*Δxor
Compressor Logic Level
Optimized
Logic Level 14 24 27 2*Δxor+1*Δand +1*Δnor Compressor
81.89

0.425

5.729

2.435
Optimized +1*Δnot (Chang et al.
Compressor 2004)

High Speed 18 36 15 1*Δnand+2*Δxor+1*Δxnor

Compressor High Speed
Compressor
86.37

0.418

6.348

Logical 13 14 36 3*Δand+3*Δnor+1*Δnand (Baran et al.2010) 2.653

Decomposed +1*Δnot 90 nm
Compressor
Logical
Ultra High 18 30 18 1*Δxor+2*Δxnor Decomposed
Compressor
79.56

0.431

5.581

2.405

Speed (Pishvaie et al.

Compressor 2013)
Proposed 7 28 21 2*Δxor+1*Δand+2*Δor
Compressor +1*Δnot Ultra High Speed
Compressor
84.22

0.402

5.881

2.364

(Aliparast et. al.

2010)
The energy efficient compressor is described using structural
Verilog-HDL to produce gate level netlist and synthesized Proposed
using Cadence RTL compiler with respect to 180 nm and 90 Compressor
72.42

0.437

5.168

2.258

nm technologies. Conventional compressor, logic level

optimized compressor (Chang et. al. 2004), high speed
compressor (Baran et. al. 2010), logical decomposed
compressor (Pishave et. al. 2013) and ultra high speed
compressor (Aliparast et. al. 2013) are used for comparison.
The designs used for comparison are also described using
structural Verilog-HDL. The area, power and PDP of the
proposed and previous designs are shown in Table 3.
The total power dissipation of the proposed compressor is
declined by 10.48%, 19.21%, 8.10% and 12.79%
for 180 nm technology, 9.79%, 18.59%, 7.40% and 12.12%
for 90 nm technology compared to logic level optimized
compressor, high speed compressor, logical decomposed

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compressor and ultra high speed compressor respectively. Using High
Delay of the proposed compressor is 18.47% and 18.16% less Speed

11.383
9.729

1.170
9989
Compressor
for 180 nm and 90 nm technologies compared to conventional (Baran et
compressor architecture. The PDP of the proposed compressor al.2010)
is reducing by 13.47%, 8.21%, 15.83%, 7.10% and 5.50% Using Logical
for 180 nm technology, 12.51%, 7.27%, 14.89%, 6.11% and Decomposed
4.48% for 90 nm technology compared with other state-of- Compressor

10.048

10.269
1.022
9245
90 nm
the-art-designs. (Pishvaie et al.
2013)

Using Ultra High

IV. IMPLEMENTATION OF PROPOSED COMPRESSOR IN Speed Compressor

10.117
9.342

1.083
9752
SYSTOLIC ARRAY BASED DIGITAL FILTER (Aliparast et al.
2013)
To verify the performance of the proposed compressor an
implementation of processing element in systolic array based
digital filter shown in Figure 1 is done. The processing Using Proposed

10.446

0.901

9.412
7934
element is constructed using 16-bit carry look ahead adder and Compressor
8-bit Wallace tree multiplier with proposed compressor and
other state-of-the-art designs Table 4 shows the performance
estimates of the digital filter in terms of area, delay and power
dissipation. From Table 4 it can be seen that the digital filter
implemented with proposed compressor exhibits a PDP
reductions of at least 8.67% for 180 nm technology and 6.98%
for 90 nm technology respectively compared with other
state- of-the-art designs. A plot of PDP for the digital filter
with proposed and other compressor designs for 180 nm and
90 nm technologies is shown in Figures 4 and 5.
TABLE IV AREA, DELAY AND POWER COMPARISONS OF DIGITAL FILTER
IMPLEMENTED WITH PROPOSED AND OTHER STATE-0F-THE-ART
COMPRESSOR DESIGNS

Performance Metrics Area Delay Power PDP

Compressors
(µm) (ns) (µW) (µW-
2
ns) Fig. 4. PDP of the Digital Filter Implemented with Proposed Compressor and
Using Conventional State-of-the-Art Designs for 180nm Technology
21.103

39.083
13567

1.852

Compressor
Using Logic Level
14.924

36.146
18736

2.422

Optimized
Compressor
(Chang et al.2004)
Using High Speed
14.691

39.695
19679

2.702

Compressor
(Baran et al. 2010)

Using Logical
Decomposed
15.172

35.806
18212

2.360

180 Compressor
nm (Pishvaie et
al.2013)
Using Ultra High
Speed Compressor
14.107

34.647
19212

2.456

(Aliparast et al.
2013)
Fig. 5. PDP of the Digital Filter Implemented with Proposed Compressor and
State-of-the-Art Designs for 90nm Technology
Using Proposed
Compressor
15.573

31.644
15530

2.032

V.CONCLUSION
Using Conventional Energy efficient compressor architecture for systolic array
Compressor
13.976

11.209

based filter is proposed. The total power dissipation of the

0.802
6887

proposed compressor is found to be 11.796 µW and 5.168

µW with the corresponding delay of 0.649 ns and 0.437 ns for
Using Logic Level 180 nm and 90 nm technologies, respectively. It reveals a PDP
Optimized
10.368
9.884

1.049

reduction of the proposed compressor to be 5.50% to 15.83%

9511

Compressor
(Chang et al.2004) for 180 nm technology, 4.48% to 14.89% for 90 nm
technology compared with other state-of-the-art designs. This
suggests the suitability of the proposed compressor design for

Authorized licensed use limited to: Middlesex University. Downloaded on November 03,2020 at 08:53:20 UTC from IEEE Xplore. Restrictions apply.
portable applications. An 8- bit Wallace tree multiplier is
designed using the proposed compressor and other state-of-
the-art designs. From the comparison, it is seen that the
multiplier design using proposed compressor architecture
achieves better performance in terms of PDP compared to
other state-of-the- art designs. An implementation of the
proposed compressor in the processing element of systolic
array based digital filter is done to evaluate its performance.
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