Design and Stability Analysis of CNTFET based
SRAM Cell
Mohita, Tannu Newar, Tista Roy
School of Electronics Engineering
KIIT University
Bhubaneswar, India
mohita.22singh@gmail.com, newartanu@gmail.com
tistaroy222@gmail.com
Abstract—Static Random Access Memory (SRAM) is one of
the most crucial and critical memory devices used in today's
technological environment. The continuous scaling of CMOS
technology significantly limits the performance of 6T SRAM cell
in terms of leakage power and stability. With remote chances to
further improve the MOSFET technology in future, Carbon
Nanotube Field Effect Transistors (CNTFETs) are being widely
studied as the possible alternatives. In this paper, the conventional
6T SRAM cell is compared with CNTFET based SRAM cell. The
conventional 6T SRAM cell is designed using Cadence Virtuoso
Tool in 180nm and 45nm Technology. The Verilog-A code of
CNTFET for replacing nMOS and pMOS are separately
simulated in Cadence Virtuoso Tool. The CNTFET based SRAM
cell is technology independent. The performances are evaluated in
terms of leakage power, delay and stability to show that the
CNTFET based SRAM cell can successfully replace the CMOS
based SRAM cell.
Keywords- CNTFET, N-curve, SRAM, Stability Analysis.
I. INTRODUCTION
The cache memory in a microprocessor occupies more than
50% of chip area. In today’s processors, the leakage power of
cache is a major source of power dissipation. Supply voltage is
scaled down basically to reduce the power dissipation. But for
high performance the threshold voltage should also be scaled
down which exponentially increases the sub threshold leakage
current and thus leads to increment in the leakage power [1].
Due to MOS scaling, stability of SRAM has become a major
concern for future technology. In the conventional 6T cell, it is
difficult to find an optimum design because the both read
stability and write margin must be considered. At low supply
voltage, 6T cell worsen in read stability[2].
The scaling down of transistors and increase in speed has
been the driving force in technological advances in order to
meet the density and sustain the IC predicted by Moore’s law.
However, as noted by ITRS 2009 edition, further scaling down
to sub-22nm range has faced serious limits related to fabrication
technology and device performances. [3]. As the size shrinks,
the thickness of the insulators within the transistor, reduces. The
Joy Chowdhury, J.K.Das
Lecturer, School of Electronics Engineering
KIIT University
Bhubaneswar, India
joychowdhury87@yahoo.in ,
jkdas12@gmail.com
result is a short circuit allowing current to flow directly from
source to drain, drain to the body, and even through the thin gate
oxide, that separates the gate from the channel. Also, doping
becomes a problem[4]. These limits can be overcome to some
extent by modifying the channel material in the traditional bulk
MOSFET structure with a single carbon nanotube or an array of
carbon nanotubes.
The rest of this paper is organized as follows. In Section II,
the background of 6T SRAM cell, carbon nanotube and carbon
nanotube field effect transistor is explained. In Section III, the
proposed SRAM cell is described. Section IV provides the
simulation result. Finally Section V gives the conclusion of this
paper.
II. BACKGROUND
A. Conventional 6T SRAM Cell
In Conventional 6T SRAM cell each bit is stored on four
transistors that form two cross coupled inventor. This storage
cell has two stable states used to denote 0 and 1. Two
additional access transistors serve to control access to storage
cell during read and write operation. Access to the cell is
enabled by the word line WL which controls the two access
transistor which in term control, whether the cell should be
connected to the bit line BL and BLB. They are used to transfer
data for both read and write operations. An SRAM cell has
three different states it can be in: standby where the circuit is
idle, reading when the data has been requested and writing
when updating the contents. The SRAM to operate in read
mode and write mode should have "read stability" and "write
ability" respectively [5]. The 6-T SRAM cell shown in Fig.1
operates as follows:
For a Standby Operation, the word line is not asserted, the
access transistors M5 and M6 disconnect the cell from the bit
lines. For a read operation, condition is that the strength (drive
current) of the pull-down transistor to that of the pass-gate
transistor should be sufficiently large. It is called cell Beta
ratio. For a write operation, the condition is that the ratio of the
strength of the pass-gate transistor to that of the pull-up
transistor should be sufficiently large. It is called cell gamma current. CS, CD, CG, CSUB, is capacitance of source, drain, gate
ratio.[6] and substrate respectively.
Fig. 1. Conventional 6T SRAM cell
B. Carbon Nano Tube (CNT)
Carbon nanotubes are hexagonal sheets of graphene, which
are single layers of graphite atoms, which are rolled up into
hollow cylinder. Depending on their chirality (i.e., the direction
in which the graphite sheet is rolled), the single-walled carbon
nanotubes can either be metallic or semiconducting. The
circumference of such nanotube can be expressed in terms of a
chiral vector. The structure of any carbon nanotube can be
described by an index with a pair of integers(n,m) that define
its chiral vector. The chiral angle θ is given by (1):
(1)
For a CNT with (n, m) as chirality and a as lattice (that is
carbon to carbon atom distance) the diameter d is given by (2):
(2)
A carbon nanotube’s bandgap is directly affected by its
chirality and diameter. Since the nanotube has ballistic
conductance, the charge carriers do not collide, reducing
resistance to negligible levels. Electrical properties of carbon
nanotubes arise from the unique electronic structure of
graphene itself.
C. Carbon Nanotube Field Effect Transistor (CNTFET)
A carbon nanotube field-effect transistor (CNTFET) refers to
a field-effect transistor that utilizes a single carbon nanotube or
an array of carbon nanotubes as the channel material instead of
bulk silicon in the traditional MOSFET structure. CNFETs
require three terminals, source, drain, and gate. The gate is used
to control the current across the source and drain terminal.
When the gate is on current is able to flow across the source
and drain through a channel. Like CMOS CNTFETs also has
complimentary devices, the p-type and n-type. The p-type
transistor conducts holes, where as the n-type conducts
electrons[4]. CNFET works on the principle of direct tunneling
through a Schottky barrier at the source–channel junction.
Applied voltage to the gate can control the electrical
conductance of the CNTFET by changing electron density in
the channel. By using appropriate diameter suitable threshold
voltage for CNFET can be achieved. Its threshold voltage is
proportional to the inverse of the diameter of CNT [7]. Figure 2
shows the internal view of CNTFET. Here IDS is drain to source
Fig. 2. Internal view of CNTFET
III. PROPOSED SRAM CELL
The inverter is the fundamental part of SRAM cell design. A
CNFET-based inverter circuit is shown in Fig 3(a).The pull-up
network (PUN) is implemented using p-type CNTFET and the
pull-down network (PDN) is implemented using n-type
CNTFET. They are coupled together in series between a high
supply voltage (VDD) and ground, as shown in figure. The
proposed CNTFET based SRAM cell replaces CMOS 6T cell
with CNTFET. It has 6 transistors like the conventional 6T cell.
It is given in Fig.3(b). It is constructed using two inverters each
having one n-type CNTFET and one p-type CNTFET. The
source terminals of p-type CNTFETs (P1,P2) are connected to
supply. The two n-type CNTFETs (N1,N2) of inverters have
their source connected to ground. The drain terminals of these
transistors are connected to storage nodes Q and QB and the
gates are cross-coupled. Another two n-type CNTFETs (A1,A2)
are used as access transistors which are controlled by wordline
WL through gate. They connect the bitlines (BL,BLB) to the
inverter outputs. A value(0 or 1) is loaded or accessed from cell
through bitlines(BL and BLB).
IV. SIMULATION AND RESULT
The code for n-type CNTFET and p-type CNTFET is written
in Verilog-A format. This code is stored as symbol or block in
a separate library of cadence. This symbol is used to draw the
schematic diagram. The schematic of inverter is drawn and
VTC curve of the circuit is obtained by performing dc analysis
in analog environment. Also the gain curve is plotted. It is
shown in fig.4. The noise margin of the CNTFET based
inverter is obtained and given in (3) and (4).
Fig. 3. CNTFET based inverter and SRAM cell
 Fig. 4. VTC curve of CNTFET based inverter
(3)
(4)
The threshold voltage of the CNTFET based inverter is 0.5V
as obtained from the VTC curve. The input (Vin) to output
(Vout) delay of the inverter is 12.29E-12V. The proposed
SRAM cell schematic is drawn. The schematic is shown in fig.
5. The dc analysis and transient analysis is done using spectre
simulator at supply voltage VDD=1. The input-output waveforms
of the transient analysis of the circuit is shown in fig. 6. When
WL is high, Q and QB changes according to BL and BLB.
When WL is low Q and QB retain their states. The performance
of the cell is analysed. Then CMOS 6T SRAM
Fig. 5. Schematic of CNTFET based SRAM cell
Fig. 6. Output waveform of CNTFET based SRAM cell
Fig. 7. 6T SRAM cell Schematic
cell is designed in 180nm and 45nm technology. The fig.7.
shows 6T SRAM cell schematic. The supply voltage VDD used
for 180nm technology is 1.8V and for 45nm technology is 1V.
The leakage power and delay of 6T SRAM cell and proposed
SRAM cell is calculated. The stability of the SRAM cell is an
important performance parameter. The stability of the cell is
determined from static noise margin(SNM). The SNM is the
maximum noise voltage introduced at the output of the two
inverters of cell such that the cell can sustain its state. The
SNM is the length of the side of the largest square that can be
inscribed in the lobe of butterfly curve. For stability analysis,
two dc noise voltage sources are placed in series with the cross-
coupled inverters. The butterfly curve is obtained by plotting
the VTC curve of the inverter of the cell and overlapping its
inverse. The butterfly curve of 6T cell in 45nm and CNTFET
based cell is shown in fig.8. and fig.9 respectively. The
Table1gives performance comparison of 6T in 45nm and
180nm and proposed cell in terms of leakage power and delay.
Fig. 8. Butterfly curve of 6T SRAM cell in 180nm
 Fig. 9. N-curve of 6T SRAM cell in 180nm for read 0 and write 0. Fig. 12. N-curve of CNTFET for read 0 and write 0.

Fig. 10. N-curve of 6T SRAM cell in 180nm for read 1 and write 1.

Fig. 13. N-curve of CNTFET for read 1 and write 1.

TABLE I. PERFORMANCE COMPARISON

CNTFET
Performance 6T SRAM 6T SRAM
Based SRAM
parameters Cell in 180nm Cell in 45nm
Cell
`Leakage Power
48.3×10-10 1.165×10-13 454.11×10-18
(Watts)

Delay in psec 12.578 9.9971 5.502

TABLE II. STABILITY ANALYSIS USING BUTTERFLY

CURVE
Fig. 11. Butterfly curve of CNTFET based SRAM cell
6T Cell in CNTFET Based
6T Cell in 45nm
Parameter 180nm Cell

SNM 721.3mV 261.04mV 154.85mV

 TABLE III. STABILITY ANALYSIS USING N - CURVE REFERENCES
6T Cell in 6T Cell in CNTFET
Conditions Parameter
180nm 45nm Based Cell [1] M. Powell, Se-Hyun Yung, B. Falsafi, K. Roy and T.N. Vijaykumar,
“Reducing Leakage in a High-Performance Deep-Submicron Instriction
READ 0 SVNM 407.62mV 265.99mV 259.74mV Cache,” IEEE Trans. on VLSI Systems, vol. 9, No.1., Feb 2001.
[2] Sanjeev. K. Jain and Pankaj Aggrawal, " A Low Leakage and SNM Free
READ 0 SINM 513.24µA 35.08µA 15.89µA
SRAM cell Design in Deep sub micron CMOS technology," Proceeding
of the 19th International Conference on VLSI Design (VLSID'06), IEEE
WRITE 0 WTV 1.069V 474.85mV 397.69mV
2006.
WRITE 0 WTI -175.80µA -8.4457µA -14.36µA [3] International Technology Roadmap for Semiconductors 2009 Edition.
[4] Alokik Kanwal, “A Review of Carbon Nanotube Field Effect
READ 1 SVNM 664.95mV 270.17mV 261.88mV Transistors,” version 2.0, alokik@eden.rutgers.edu, 4/28/2003
[5] K. Dhanumjaya, M. Sudhu, Dr. MN. Giri Prasad and Dr. K. Padmaraju
READ 1 SINM 592.507µA 34.78µA 15.89µA “Cell Stability Analysis Of Conventional 6t Dynamic 8t Sram Cell In
45nm Technology,” International Journal of VLSI Design and
WRITE 1 WTV 808.43mV 467.84mV 396.53mV Communication Systems," Vol.3, No.2, April 2012.
[6] Sagar Joshi and Sarman Hadia, “Design and Analysis for Low power
WRITE 1 WTI -95.16µA -8.447µA -14.403µA CMOS Sram cell in 90nm technology using cadence tool,” IJARCCE,
vol. 2, pp. Issue 4, April 2013.
[7] Aparna Anand and S.R.P. Sinha, " Performance Evaluation of Logic
Gates Based On Carbon Nano Tube Field Effect Transistor," International
V. CONCLUSION Journal of Recent Technology and Engineering, Vol-2, Issue-5,
November 2013.
In this paper we have proposed the CNTFET-based SRAM
cell. It is compared with the CMOS-based 6T SRAM cell in
180nm and 45nm technology. All simulations are carried out in
to cover the different aspects of SRAM cell stability analysis
using Butterfly curve and N-curve method. Three different
technologies were consider and a comparative analytical
performance overview has been presented. Improved results was
exhibited by CNTFET based designs in all aspects except noise
margin which can be further enhanced by using more optimized
CNTFET models.