IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO.
3, MARCH 2009
Modeling and Parameter Extraction for the Series
Resistance in Thin-Film Transistors
Keum-Dong Jung, Student Member, IEEE, Yoo Chul Kim, Student Member, IEEE,
Byung-Gook Park, Member, IEEE, Hyungcheol Shin, Senior Member, IEEE, and Jong Duk Lee, Member, IEEE
Abstract—A new parameter extraction method is proposed for
the series resistance of thin-film transistors (TFTs). By analyz-
ing the gate–source overlap region of staggered structure TFTs,
the model for the series resistance is derived and utilized for
the parameter extraction. To verify the extraction method, the
characteristics of amorphous silicon TFTs obtained from TCAD
simulation are used. For the devices with different overlap lengths,
the extracted parameters are identical to each other, although
the series resistances are different due to the narrow overlap
length. When the actual channel length is different from the mask-
specified length, the offset length can be effectively corrected by
the new method, so that accurate parameters can be obtained. Be-
cause the new method has several advantages such as the accuracy
and generality over the conventional method, it can be used for
further analysis of TFT characteristics.
Index Terms—Channel length offset, contact resistance,
modeling, overlap length, parasitic resistance, series resistance,
thin-film transistors (TFTs), transfer length.
I. INTRODUCTION
T HIN-FILM transistors (TFTs) had been considered to be
suitable for large-area switching devices because of their
low fabricating cost compared to the single-crystalline metal–
oxide–semiconductor field-effect transistors (MOSFETs). The
potential capacities of TFTs are recently proven by the success
of amorphous silicon (a-Si) TFTs in the liquid crystal displays.
Nowadays, the superb uniformity of a-Si TFTs enables more
than 80-in panel [1], and even the driving circuits using a-Si
TFTs are commercially integrated into the panel. Following the
success of a-Si TFTs, many novel TFTs are being developed for
usage in new applications such as active-matrix organic light-
emitting diodes and flexible displays [2]–[9].
Concerning the characteristics of TFTs, it is well known
that not only the mobility of the material but also the series
(parasitic) resistance is very important. Contact-limited behav-
ior of TFTs has been reported continuously regardless of the
semiconductor materials [10]–[12], so that reducing the series
resistance is one of the important topics in this area [13]–[16].
Various experiments have been conducted to analyze the origin
and properties of the series resistance [17]–[21], and several
physical models for the series resistance have been suggested
Manuscript received August 12, 2008. Current version published February 25,
2009. This work was supported by the Brain Korea 21 (BK21) program. The
review of this paper was arranged by Editor C. McAndrew.
The authors are with the Inter-University Semiconductor Research Center
and School of Electrical Engineering, Seoul National University, Seoul 151-
742, Korea (e-mail: windbit@naver.com).
Digital Object Identifier 10.1109/TED.2008.2010579
0018-9383/$25.00 © 2009 IEEE
431
[10], [27], [28], [31]–[33]. In addition, in the TFT compact
models, the series resistances are always included because their
effects are not negligible for the modeling of I–V charac-
teristics [22]–[25].
For the extraction of the series resistance, the total resistance
versus the channel length plot, which is similar to the channel
resistance method for silicon MOSFETs [38], has been widely
used. The advantage of the method is that the principle is
simple, the fabrication is not hard, yet it gives a lot of useful
information. However, looking into the method in detail, the
explanations for the extracted parameters have been slightly dif-
ferent from one researcher to another, so it is hard to understand
the physical meaning of the extracted parameters. Moreover,
the change of the channel length during the fabrication has
been rarely considered for TFTs, while it is closely related to
the extraction of the series resistance. Therefore, the extraction
method and related models need to be reconsidered to obtain
more accurate series resistance and more physically meaningful
parameters.
In this paper, a new series resistance model and related para-
meter extraction method are proposed. First, in Section II, the
conventional extraction method is reviewed and its limitations
are examined. The new model for the series resistance is pro-
posed in Section III, and the extraction method for the modeling
parameters is described in Section IV. For the verification of the
method, some extraction examples with the amorphous silicon
TFTs are provided in Section V, and finally, the conclusion is
given in Section VI.
II. CONVENTIONAL METHOD
For the conventional method, the total resistance Rtot is
plotted as a function of the TFT channel length L, and the
series resistance Rsd is found at the point of L = 0 as shown
in Fig. 1 [12], [14], [17]–[19], [23], [26]–[30]. The value of
Rsd changes with the gate voltage VG , which is typical for
TFTs. From the common crossing point which usually exists
in the second quadrant, the modeling parameters, such as the
empirical parasitic resistance Rp and empirical channel length
offset ΔLp , are obtained. From the slope of the graph, the
intrinsic semiconductor parameters, such as intrinsic mobility
μi and intrinsic threshold voltage VTHi , can be obtained. For the
modeling of Rsd , the following equation [17], [26], [28], [29]
or its derivatives [14], [23] are used in various publications:
ΔLp
Rsd = Rp + (1)
μi Ci W (VG − VTHi )
432 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 3, MARCH 2009

Fig. 1. Typical Rtot −L plot from the conventional parameter extraction

method.

where W and Ci represent the TFT channel width and the

insulator capacitance per unit area, respectively.
One major limitation of the conventional method is that there
should be a crossing point in the second quadrant. Although,
in many publications, a common crossing point is shown in
their Rtot −L plots [17], [18], [23], [26], [28], [29], lots of other
Rtot −L plots seem not to have the common crossing point [12],
[27], [30], [36]–[37]. If there is no crossing point, (1) is not
applicable, so that another more complex equation should be
used for the modeling of the series resistance.
Even if the common crossing point can be found, the physical
meaning of the point is not clear, particularly for the empirical
channel length offset ΔLp . Kanicki et al. insist that ΔLp is
associated with the effective channel length longer than the
mask-specified channel length in [35], while Luan and Neudeck
[26] explain that ΔLp is an empirical parameter which can be
considered as the length of the accumulation channel resistance
Fig. 2. (a) Inverted-staggered TFT is composed of one channel region and
in series with Rp . In the a-Si TFT modeling by Servati et al. two overlap regions. Bias conditions for the source, drain, and gate electrodes
[23], the obtained ΔLp for TFT set II is observed to be larger are VS = 0 V, VD = 0.1 V, and VG > VTH , respectively. (b) In the overlap
than the total overlap length, so the authors explain that the region, Ix (x) flows through the accumulation layer and Jy (x) flows from the
accumulation layer to the source electrode.
phenomenon is possibly due to the expansion of channel by
virtue of a highly resistive contact layer. Gundlach et al. [30]
comment that ΔLp is twice the transfer length which gives an Under this bias condition, the accumulation layer is induced
estimate of the contact area participating in charge injection. not only in the channel but also at the bottom of the overlap
In summary, the meaning of ΔLp is uncertain and has been region. Because of the small VD , the accumulation layer is
interpreted as the mixture of the effective channel length, the almost uniform, so that the sheet resistance Rsh (in ohms per
channel length offset during the fabrication, and the transfer square) along the accumulation layer can be considered as a
length. constant. The relation between Rsh and VG is approximately
given as
III. ANALYSIS OF SERIES RESISTANCE
1
Rsh ≈ (2)
Previous analyses on the gate–source overlap region have μi Ci (VG − VTHi )
derived the analytic equations for the series resistance [27],
[35]. This section briefly revises the equation and expands it where the intrinsic mobility μi is also a function of VG in
to describe the I–V characteristics of the TFTs. TFTs [22].
The cross section of an inverted-staggered TFT, also known The series resistance Rsd is related to the overlap region in
as a top-contact TFT, is shown in Fig. 2(a). An n-type TFT is Fig. 2(b). Ix (x) and V (x) represent the x-direction current and
assumed because a-Si TFTs are n-type. However, the following electric potential of the accumulation layer, respectively. Out-
analysis can be applied to any kind of TFTs, such as organic side of the accumulation layer, the current is assumed to flow
TFTs or amorphous oxide TFTs, as far as it has the staggered only in y-direction, which can be represented by the current
structure. The TFT consists of one channel region at the center density Jy (x). Ry represents the apparent y-direction resistance
and two overlap regions at each side. It is assumed that the normalized with the area (in ohms square centimeter), and it
source voltage VS is zero while the gate voltage VG is larger includes all resistive components existing in the contact and
than the threshold voltage VTH . Not to break the symmetry bulk semiconductor. By using this apparent resistance Ry , the
of the device, the drain voltage VD is assumed very small, following analysis becomes more simple and intuitive without
e.g., 0.1 V. losing the generality.
JUNG et al.: MODELING AND PARAMETER EXTRACTION FOR THE SERIES RESISTANCE IN TFTs 433

By using these quantities and assumptions, one can obtain the

following expressions for Jy (x), Ix (x), and V (x), respectively:
      
x Lov x
Jy (x) = Jy0 cosh − + tanh sinh − (3)
L0 L0 L0
      
x Lov x
Ix (x) = W L0 Jy0 sinh − + tanh cosh −
L0 L0 L0
       (4)
x Lov x
V (x) = Ry Jy0 cosh − + tanh sinh − (5)
L0 L0 L0
 Fig. 3. For the parameter extraction, x-intercept, slope, and triangular area are
Ry used from the Rtot −L plot.
L0 = (6)
Rsh
TABLE I
where Jy0 is the maximum current density at x = 0, Lov is the PARAMETERS FROM THE Rtot −L PLOT ARE EXPRESSED WITH Rsh , L0 ,
length of the overlap region, and L0 is the effective overlap Ry , AND Lov . WHEN Lov  L0 , THE EXPRESSIONS ARE MUCH SIMPLER
length given by (6). Here, L0 has the same physical meaning
with the transfer length [34] or the characteristic length [27],
[35] in the literature. A detailed derivation procedure is sum-
marized in Appendix A.
With the aforementioned equations, Rsd can be derived from
the total resistance of the overlap region by dividing the total
potential drop V (x = 0) by the total current Ix (x = 0)
V (x = 0) 2Ry
Rsd = 2Rs = 2 = (7)
Ix (x = 0) W L0 tanh(Lov /L0 )
where the source resistance Rs is the half of Rsd due to the
symmetry. Equation (7) well explains the characteristics of the
series resistance of TFTs. First, Rsd is a function of VG because
L0 is dependent on VG . Usually, Rsd decreases with larger difference is that the x-intercepts are used for the new method
VG because L0 increases with larger VG . Second, the equation instead of the common crossing point in the conventional
can account for the effects of the narrow overlap length which method. To derive the relation of Rtot and L, (8) is converted to
are known to increase Rsd [10], [17]. If Lov  L0 , the hyper-
bolic tangent term becomes one, so Rsd becomes its minimum VD Rsh 2Ry
Rtot = = L+
value. For Lov comparable to L0 , Rsd increases because the IDS W W L0 tanh(Lov /L0 )
hyperbolic tangent term becomes less than one. If Lov  L0 ,  
Rsh 2L0
L0 is canceled in the denominator because tanh(Lov /L0 ) ≈ = L+ . (10)
Lov /L0 , so Rsd is determined only by Lov . Third, as Rsd is W tanh(Lov /L0 )
proportional to Ry , it can be directly deduced that the bad
In Fig. 3, the relation of Rtot and L is plotted, which becomes
contact or thick bulk semiconductor would increase Rsd .
a straight line with the slope of Rsh /W and the y-intercept of
Since the current should be continuous at the boundary of the
Rsd . In Table I, the x-intercept, y-intercept, and the triangular
channel and the overlap region, one can find the following I–V
area are expressed with Rsh , L0 , Ry , and Lov . Therefore, by
equation:
comparing the Rtot −L plot with Table I, the parameters such
VD as Rsd , Rsh , L0 , and Ry can be extracted.
IDS = W . (8)
LRsh +
2Ry If Lov  L0 , it is quite easy to extract the parameters. L0
L0 tanh(Lov /L0 )
can be directly obtained from the x-intercept because L0 =
In addition, the equation of Jy0 is given by |x-intercept|/2. Rsh can be found from the slope, and Ry also
VD can be obtained with (6). It is interesting to notice that the area
Jy0 = . (9) of the triangle in the second quadrant corresponds to the Ry
Rsh L0 L tanh(Lov /L0 ) + 2Ry
value.
Therefore, all the electrical quantities in (3)–(9) can be de- However, in most of the cases, the relation between L0 and
termined analytically if L0 , Rsh , and Ry are obtained. A Lov is unknown. Therefore, the following equation should be
detailed derivation procedure for IDS and Jy0 is summarized solved for L0 :
in Appendix B.
2L0
|x-intercept| = . (11)
IV. PARAMETER EXTRACTION METHOD tanh (Lov /L0 )

Similar to the conventional method, the Rtot −L plot is used It is not so difficult to numerically solve (11) for L0 , but in
for the new parameter extraction method. However, the major this paper, a graphical solving method is introduced for more
434
Fig. 4. (a) X−Y plot from (13) gives L0 value at intersection of the straight
line and the curve. (b) If the x-intercept increases for the fixed Lov , L0
increases continuously. (c) If Lov increases for the fixed x-intercept, L0
converges to |x-intercept|/2.
qualitative understanding. Equation (11) can be converted to
 
|x-intercept| Lov
L0 = tanh (12)
2 L0
so that L0 can be considered as the intersection of the following
two graphs:
Y =X
 
|x-intercept| Lov
Y = tanh . (13)
2 X
Therefore, by drawing a χ-shaped X−Y plot as shown in
Fig. 4(a), one can obtain the value of L0 . While the former
graph in (13) is a straight line, the latter graph is a curve
which yields |x-intercept|/2 for small X and decreases when
X > Lov /2. Fig. 4(b) and (c) shows the effect of x-intercepts
and Lov on the extraction of L0 , respectively. If x-intercept
becomes larger while Lov is fixed, the values of the curve
increase so that the L0 increases. On the other hand, if Lov
becomes larger while x-intercept is fixed, the bending point of
the curve increases as shown in Fig. 4(c), so that L0 converges
to |x-intercept|/2. This observation corresponds to the previous
discussion that L0 = |x-intercept|/2 when Lov  L0 . Once L0
is found, it is not difficult to find Rsh and Ry . In summary,
the parameter extraction procedure is composed of three steps:
1) L0 is obtained from the x-intercept using the X−Y graphical
method; 2) Rsh is found from the slope; and 3) Ry is obtained
either by (6) or by the triangular area.
For the new method mentioned earlier, the actual electrical
channel length considering the channel length offset should be
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 3, MARCH 2009
Fig. 5. Cross section of the simulated BCE a-Si TFTs. The channel length
offset ΔL affects both the channel length L and the overlap length Lov .
used instead of the mask-specified channel length. In addition,
for Lov , the effects of the channel length offset should be
considered. Otherwise, extracted Rsd , L0 , and Ry may include
a significant error due to the inaccurate L and Lov .
To obtain the channel length offset ΔL, the following method
can be used. Because L0 in (3) is independent on Lov , extracted
L0 should be the same for the devices which have different Lov .
However, if the mask-specified L and Lov are used without
considering ΔL, the obtained L0 would be different at the
first extraction. Then, until the same L0 is derived for different
Lov , ΔL can be found by guessing ΔL and recalculating L0 .
Although this method requires additional devices with different
Lov , the accuracy is much better than the previously reported
method [40] or direct measurement of the actual channel
length.
The external resistance Rext , which exists outside of the
source and drain contacts, should also be considered. For
Rtot −L plot, Rext increases Rtot by its amount, so that wrong
parameters can be obtained due to the increased x-intercept and
y-intercept values. However, in most TFTs, Rext (∼Ω) is much
smaller than Rtot (∼M Ω), so the effect is negligible. Even
though the external resistance is not negligible, the measure-
ment of Rext is not difficult if the dedicated dummy patterns for
Rext measurement are fabricated. Once Rext value is found, the
effects can easily be eliminated by subtracting Rext from Rtot .
V. VERIFICATION AND DISCUSSION
For the verification of the described method, I–V charac-
teristics are obtained from the simulation on the a-Si TFTs
using SILVACO TCAD simulator. The TCAD simulation has
two advantages in this case. First, the channel length offset
can be virtually controlled from zero to a finite value, so the
extraction method can be verified in various conditions. Second,
not only I–V characteristics but also the internal parameters
in the overlap region such as Jy (x) in (3) can be obtained, so
the series resistance model can be verified more in detail. The
simulated TFT is a back-channel-etched (BCE) a-Si TFT shown
in Fig. 5. For the simulation, the basic a-Si TFT models and the
default parameter values are used [39].
Assuming that ΔL is zero, the series resistance and related
parameters are extracted. The channel lengths L’s are changed
JUNG et al.: MODELING AND PARAMETER EXTRACTION FOR THE SERIES RESISTANCE IN TFTs
Fig. 6. (a) I–V characteristics of TFT set A with different L. (b) I–V
characteristics of TFT set B with different L. Due to the large series resistance,
the current of TFT set B is smaller than that of TFT set A.
from 2 to 10 μm, and the overlap lengths Lov ’s are changed
from 0.5 to 10 μm. Fig. 6 shows the linear region I–V char-
acteristics of two sets of TFTs. TFT set A and B have Lov of
10 and 0.5 μm, respectively, so that the current of TFT set B
is smaller than that of TFT set A due to the narrow Lov . For
the parameter extraction, the Rtot −L plots are shown in Fig. 7.
Because ΔL and Rext are assumed to be zero, the x-intercepts
in the plot can be directly used for further analysis. In Fig. 8,
the χ-shaped graphical solving method is applied to obtain the
effective overlap length L0 . The obtained L0 is exactly the
same for the two TFT sets, although the x-intercepts and y-
intercepts are different from each other. This confirms that L0
is determined only by Rsh and Ry , as shown in (5), and not
related to either Lov or Rsd . Fig. 9(a) shows the obtained L0
as a function of VG . Next, the sheet resistance Rsh is obtained
from the slopes of Rtot −L plots, and the results are shown in
Fig. 9(b). There is no difference between the extracted Rsh for
different Lov , because Rsh is not related to Lov . Finally, the
y-direction apparent resistance Ry is obtained in Fig. 9(c). Ry
can be obtained from either the triangular area in Rtot −L plot
or (6), and the obtained Ry ’s are identical to each other for
different Lov . In conclusion, L0 , Rsh , and Ry are sequentially
obtained from the new extraction method and are the same for
different Lov . However, if the conventional extraction method
is used, the two Rtot −L plots in Fig. 7 would be analyzed
differently because of the different common crossing points,
i.e., different Rp and ΔLp .
For the verification of the extracted parameters, Jy (x) at
VG = 20 V is calculated using (3) for the two sets of TFTs in
Fig. 10. The calculated Jy (x) fits very well with the simulation
435
Fig. 7. (a) Rtot −L plot for TFT set A. (b) Rtot −L plot for TFT set B. The
x-intercepts, the y-intercepts, and the triangular area are different for the two
sets of TFTs. Also, the common crossing points in the second quadrant are
different.
Fig. 8. X−Y plot to obtain L0 . The same L0 is obtained for different overlap
lengths. For different VG , L0 changes.
result, so that it can be considered that the model for the
overlap region is correctly derived. In addition, in Fig. 11, the
I–V characteristics of L = 0.5, 1, and 2 μm devices, which
are more affected by the series resistance, are calculated with
(8). The calculation results also show good agreement with the
simulation results, confirming the usefulness of the extracted
parameters for the modeling of the series resistance.
Until now, ΔL is thought to be zero. However, for the real
case, positive or negative ΔL originated from various reasons
always exists. Therefore, the same simulation and parameter
extraction are done again assuming nonzero ΔL. For example,
in the case of ΔL = −0.2 μm, the channel length L decreases
from 10 to 9.8 μm while the overlap length Lov increases from
2 to 2.2 μm. However, for the parameter extraction, the mask-
specified L and Lov should be used because ΔL is not known
436 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 3, MARCH 2009

Fig. 10. (a) Jy (x) for TFT set A decays exponentially with x. (b) Jy (x)
for TFT set B. Due to the narrow overlap, less current flows than TFT set A
while the peak value of Jy (x) is larger. In both graphs, solid line represents the
calculation results with (3) using L0 , Rsh , and Ry of 0.684 μm, 1.01 MΩ/sq.,
and 470 kΩ · μm2 , respectively.

Fig. 9. Parameters are obtained from the Rtot −L plot as a function of VG .

(a) L0 is obtained from the x-intercepts. (b) Rsh is obtained from the slope.
(c) Ry is obtained from the triangular area.

prior to the parameter extraction. Fig. 12 shows the χ-shaped

X−Y plot without considering ΔL, where L0 is not the same
for different Lov due to the incorrect L and Lov . Then, ΔL
is guessed from -0.5 to 0.1 μm to revise L and Lov , and the
same extraction process is done again. In Fig. 13, the obtained
L0 curves for different Lov are shown with the presumed ΔL
values, and the standard deviations of the obtained L0 are also
Fig. 11. Comparison of I–V characteristics from the TCAD simulation and
presented for each VG . Finally, from Fig. 14, one can obtain the calculation with (8) using the extracted parameters.
the assumed ΔL of -0.2 μm from the point which gives the
minimum relative error for the obtained L0 curves. In this
paper, the sum of the standard deviation is used for the relative
error estimation. After the accurate ΔL is obtained, L0 and Ry
can be derived with the accurate L and Lov , and the result would
be the same with that of Fig. 9.
The new parameter extraction method is applied to the previ-
ous experimental I–V curves obtained by Servati et al. [23].
The modeling done by Servati et al. is adequate for the
comparison because it uses two device sets ( TFT set I and
TFT set II ) which have different series resistance. However,
ΔL cannot be obtained because there is no device which
has different Lov , so that ΔL is assumed to be zero for the Fig. 12. X−Y plot to obtain L0 using the mask-specified L and Lov . The
following discussion. By applying the new method to the I–V obtained L0 ’s are different for two Lov ’s due to the nonzero ΔL.
JUNG et al.: MODELING AND PARAMETER EXTRACTION FOR THE SERIES RESISTANCE IN TFTs
Fig. 13. Using the presumed ΔL, L0 and standard deviations are ob-
tained for four different Lov ’s. (a) ΔL = −0.5 μm. (b) ΔL = −0.2 μm.
(c) ΔL = 0 μm. (d) ΔL = 0.1 μm.
Fig. 14. By plotting the relative error of L0 curves, the assumed ΔL of
−0.2 μm can be obtained from the minimum relative error point. For the
relative error, the summation of the standard deviation in Fig. 13 is used.
characteristics in [23], the X−Y plot can be obtained for the
two sets of TFTs as shown in Fig. 15. For TFT set I, the obtained
L0 ’s are always smaller than the overlap length Lov (≈2.5 μm),
so that the series resistance is not affected by Lov . However, for
TFT set II, the obtained L0 ’s are relatively larger than Lov , so
that the series resistance becomes larger due to the insufficient
overlap length. In Table II, the obtained L0 ’s, as well as Ry
and Rsh , are summarized for two different gate voltages. From
the obtained parameters, it can be recognized that there are two
reasons for the large series resistance of TFT set II: One is Ry ,
which is 13 times larger for TFT set II, and the other is in-
sufficient Lov . Overall, the series resistance of TFT set II is
16 times larger than that of TFT set I at VG of 20 V.
VI. CONCLUSION
A new parameter extraction method is proposed for the
series resistance of staggered structure TFTs and applied for the
analysis of a-Si TFTs. Compared to the conventional method,
437
Fig. 15. X−Y plot obtained by the new method using the I–V characteristics
in [23]. (a) For TFT set I, L0 is obtained for two different VG ’s. (b) For TFT
set II, larger L0 is obtained for the same VG than TFT set I.
TABLE II
WITH THE CONVENTIONAL METHOD, Rp AND ΔLp COMPARISON OF THE
PARAMETERS OBTAINED IN [23], AND BY THE NEW METHOD.
FOR DIFFERENT GATE VOLTAGES, THE NEW METHOD
DERIVES DIFFERENT PARAMETERS
the new method has the following advantages. First, the method
gives more physically meaningful parameters such as the ef-
fective overlap length L0 and apparent resistance Ry . Second,
the method can derive the channel length offset ΔL which
has been hard to obtain. Third, not only the effect of narrow
overlap can be predicted but also the current density and electric
potential inside the overlap region can be calculated. Due to
the aforementioned advantages and the ease of usage, the new
method and the series resistance model can be useful for the
design, evaluation, and modeling of TFTs.
A PPENDIX
A. Derivation of Jy (x), Ix (x), and V (x)
The derivation of Jy (x), Ix (x), and V (x) is almost the same
to the transmission-line model [38]. By using the assumptions
438 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 3, MARCH 2009

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Keum-Dong Jung (S’06) was born in Korea on
November 1, 1978. He received the B.S. degree in
electrical engineering and the Ph.D. degree in elec-
trical engineering and computer science from Seoul
National University, Seoul, Korea, in 2001 and 2009,
respectively.
From 2001 to 2003, he was with Ahnlab, Inc.,
where he developed the network server using the
C++ programming language. He is currently with
the Inter-University Semiconductor Research Center
and School of Electrical Engineering, Seoul National
University. His previous research interest was the display devices. His current
research interest includes the fabrication, characterization, and modeling of
TFTs, including a-Si and organic TFTs.
439
Yoo Chul Kim (S’07) was born in Seoul, Korea, in
1980. He received the B.S. and M.S. degrees in elec-
trical engineering from Seoul National University,
Seoul, in 2006 and 2008, respectively.
He is currently with the Inter-University Semi-
conductor Research Center and School of Electrical
Engineering, Seoul National University. His current
research interests include modeling, measurement,
and fabrication of organic thin-film transistors.
Byung-Gook Park (M’90) received the B.S. and
M.S. degrees in electronics engineering from Seoul
National University (SNU), Seoul, Korea, in 1982
and 1984, respectively, and the Ph.D. degree in
electrical engineering from Stanford University,
Stanford, CA, in 1990.
From 1990 to 1993, he was with the AT&T Bell
Laboratories, where he contributed to the develop-
ment of 0.1-μm CMOS and its characterization.
From 1993 to 1994, he was with Texas Instruments,
developing 0.25-μm CMOS. Since 1994, he has been
with the School of Electrical Engineering (SoEE), SNU, where he was first an
Assistant Professor and is currently a Professor. In 2002, he was with Stanford
University as a Visiting Professor, on his sabbatical leave from SNU. He
has been leading the Inter-university Semiconductor Research Center (ISRC),
SNU, as the Director since June 2008. His current research interests include the
design and fabrication of nanoscale CMOS, flash memories, silicon quantum
devices, and organic thin-film transistors. He has authored and coauthored over
580 research papers in journals and conferences and currently holds 34 Korean
and 7 U.S. patents.
Prof. Park has served as a committee member on several international con-
ferences, including Microprocesses and Nanotechnology, IEEE International
Electron Devices Meeting, International Conference on Solid State Devices and
Materials, and IEEE Silicon Nanoelectronics Workshop (Technical Program
Chair in 2005 and General Chair in 2007). He is currently serving as an
Executive Director of the Institute of Electronics Engineers of Korea (IEEK)
and a Board Member of IEEE Seoul Section. He received “Best Teacher”
Award from SoEE in 1997, Doyeon Award for Creative Research from ISRC in
2003, Haedong Paper Award from IEEK in 2005, and Educational Award from
College of Engineering, SNU, in 2006.
Hyungcheol Shin (S’92–M’93–SM’00) received the
B.S. (magna cum laude) and M.S. degrees in elec-
tronics engineering from Seoul National University,
Seoul, Korea, in 1985 and 1987, respectively, and
the Ph.D. degree in electrical engineering from the
University of California, Berkeley, in 1993.
From 1994 to 1996, he was a Senior Device
Engineer with Motorola Advanced Custom Tech-
nologies. In 1996, he was with the Department
of Electrical Engineering and Computer Sciences,
Korea Advanced Institute of Science and Technology
(KAIST), Daejeon, Korea. During his sabbatical leave from 2001 to 2002,
he was a Staff Scientist with Berkana Wireless, Inc., San Jose, CA, where
he was in charge of CMOS RF modeling. Since 2003, he has been with
the School of Electrical Engineering and Computer Science, Seoul National
University. He has published over 300 technical papers in international journals
and conference proceedings. He also wrote a chapter in a Japanese book
on plasma charging damage and semiconductor device physics. His current
research interests include nano-CMOS, Flash memory, DRAM cell transistors,
CMOS RF, and noise.
Prof. Shin is a lifetime member of the Institute of Electronics Engineers
of Korea (IEEK). He was a committee member of the International Electron
Devices Meeting. He has also served as a committee member of several
international conferences, including the International Workshop on Compact
Modeling, and as a committee member of the IEEE EDS Graduate Student
Fellowship. He received the Second Best Paper Award from the American
Vacuum Society in 1991, the Excellent Teaching Award from the Department of
Electrical Engineering and Computer Sciences, KAIST, in 1998, The Haedong
Paper Award from IEEK in 1999, and the Excellent Teaching Award from Seoul
National University in 2005 and 2007. He is listed in Who’s Who in the World.
440 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 3, MARCH 2009

Jong Duk Lee (M’79) was born in Youngchun,

Kyungpook, Korea. He received the B.S. degree
in physics from Seoul National University (SNU),
Seoul, Korea, in 1966, and the Ph.D. degree from
the Department of Physics, University of North
Carolina, Chapel Hill, in 1975.
He was with the Department of Applied Physics,
College of Engineering, SNU, as a Teaching As-
sistant until 1970. From 1975 to 1978, he was an
Assistant Professor with the Department of Electron-
ics Engineering, Kyungpook National University,
Gyeongbuk, Korea. In 1978, he studied microelectric technology in HP-ICL,
Palo Alto, CA. Afterward, he was with the Korea Institute of Electronic Tech-
nology (KIET) as the Director of the semiconductor division. He established
the KIET Kumi Facility and introduced the first polysilicon gate technology
in Korea by developing 4K SRAM, 32K and 64K Mask ROM’s, and one-chip
8-b microcomputer. In July 1983, he moved to the Department of Electronics
Engineering, SNU, which has been merged to School of Electrical Engineering,
in 1992, where he is currently a Professor. He started to establish the Inter-
University Semiconductor Research Center, SNU, in 1985, where he served as
the Director from 1987 to 1989. He served as the Chairman of the Electronics
Engineering Department, SNU, from 1994 to 1996. He worked for Samsung
SDI Company, Ltd., as the Head of Display R&D Center for a year on the
leave of SNU in 1996. Since 1985, he has been concentrating his study on the
image sensors such as Vidicon type, MOS type, and also CCD to help Samsung
SDI Co. and Samsung Electronics Co. His current research interests include
sub-0.1-μm CMOS structure and technology, CMOS image sensors and field
emission display, and organic TFTs.
Dr. Lee is a member of KPS, KVS, IEEK, and KIDS. He is also a lifetime
member of CAST (Korean Academy of Science and Technology). He was
a member of IEEE (M’78), SID, AVS, and ECS. He was also a member of
the steering committee for International Vacuum Microelectronics Conference
(IVMC) from 1997 to 2001 and Korean Conference on Semiconductors (KCS)
from 1998 to 2008. He was the Conference Chairman of IVMC’97 and KCS’98
who led the IVMC’97 and the KCS’98 successfully. He was also a member of
International Electron Devices Meeting Subcommittee on Detectors, Sensors
and Displays operated by IEEE Electron Devices Society from 1998 to 1999.
He was the first President of the Korean Information Display Society from
June 1999 to December 31, 2001. He initiated the International Meeting on
Information Display for KIDS activity and served as the first Organization
Chairman in 2001.