Verilog-HDL Based Implementation of a Fuzzy Logic Controller for Embedded

Systems

M. D. Baldania1, A. B. Patki2, A. M. Sapkal3

1
Electronics & Telecommunication Department, College of Engineering, Pune, India
2
Professor Emeritus, Electronics & Telecommunication Department, College of Engineering, Pune, India
3
Professor & HOD, Electronics & Telecommunication Department, College of Engineering, Pune, India

(1baldaniamd12.extc@coep.ac.in, 2abpatki.extc@coep.ac.in, 3ams.sapkal@coep.ac.in)

Abstract - Fuzzy logic has the advantage of modelling processor which is embedded in Xilinx ISE design suite
complex, non-linear problems linguistically rather than 14.2). Fuzzy controller is realized using ISE design suite
mathematically with satisfying increasing demand of higher after complete code compilation and cross checking
performance and sophistication of embedded systems. This results. It works as a co-processor with Microblaze soft
paper describes design of a fuzzy logic controller using core on Kintex 7 KC705 board. In practice, outputs of
Verilog-HDL language with different approaches showing
sensors or external devices are converted into digital form
which elements of language should be used for most
optimized synthesis. Different algorithms for defuzzification (binary representation) for further calculation. The
process are also implemented and synthesized to check which complete design process calculations are performed in
method is most efficient and uses less hardware with higher hexadecimal representation which are further converted
computational speed. The development of a controller is into analog form [3]. This paper is organized into sections
carried out using ISE Design Suite 14.2 of Xilinx. on fuzzification, fuzzy inference module, rule inference
module and defuzzification with the Verilog-HDL
Keywords - Defuzzification, Fuzzification, ISE Design constructs.
Suite 14.2, Rule Evaluation, Verilog-HDL (Hardware
Description Language),
II. FUZZIFICATION
I. INTRODUCTION Fig. 1 shows four input signals of fuzzy controller.
Among them distance_input[7:0] and speed_input[7:0]
As compared to general purpose embedded are 8-bits distance (current distance of the vehicle from
controllers, application specific controllers have the object ahead of it) and speed (current speed of the
advantages of higher computational speed, less power, vehicle) inputs respectively. Fuzzification is the process of
less silicon area. While Verilog-HDL and VHDL assigning specific values to input variables based on
languages are widely used for hardware design, Verilog- expertise, which is also known as membership
HDL supports few keyword elements which are assignment. For example, distance_input[7:0] can take
synthesizable. Fuzzy logic has the capability of inferring any value from 00H to FFH (H represents Hex number).
under the situations associated with uncertainty and So distance is divided into different intervals and
imprecision by assigning membership function values to appropriate linguistic labels are given to them i.e., from
different linguistic variables [1, 2]. In the past, fuzzy 0m to 240m is divided equally into hex range 00H to FFH.
logic controllers have been deployed as an add-on Fig. 2 shows assignment of linguistic terms to distance
hardware module on PCB based hard core processor
and/or purely software based solutions. The embedded
systems with dedicated IP soft core processors like
Microblaze do not support Instruction Set Architecture
(ISA) for Fuzzy Logic applications and hence a need for
IP Core realization is on rise. This paper brings out
various issues using Verilog-HDL based design
implementation for an automatic brake control system.
Different types of language elements and various
defuzzification methods are experimented in ISE design
suite 14.2 to evaluate the method that is best suited for
optimum hardware and high speed performance.
Simulations result are also shown with the help of ISim
which is also a part of Xilinx ISE design suite 14.2.
Fig. 1 shows the block diagram of an automatic brake
control mechanism taken as an example connected with
Microblaze soft core processor (Microblaze is an soft core Fig. 1. Fuzzy logic controller block of Automatic brake system.

978-1-4799-1597-2/13/$31.00 ©2013 IEEE

 2013 IEEE International Conference on Computational Intelligence and Computing Research

Whether the given input falls into a particular range or

not is very important step for membership assignment.
Verilog-HDL implementation code for membership
assignment for a typical input is as follows:

if (distance_input < =dvcpoint1)

Fig 2. Fuzzification of distance_input [7:0].
input i.e., VeryClose, Close, Normal, Far, VeryFar are
labels given to distance input according to its appropriate
range. For these class of applications, Triangular and
trapezoidal membership functions are deployed, and
trapezoidal representation is resorted in practice.
Whenever distance input is to be processed, its
membership function value to any one of the defined
ranges or two adjacent ranges is to be computed. Verilog-
HDL does not support synthesizable type definition. So
each range labels are defined using parameter keyword,
which is the only synthesizable supported structure for
defining constants.
In our representation, total 6 parameters are required
for one linguistic label of any variable. So
distance_input[7:0] has total 30 parameters declared and
speed_input[7:0] has total 30 parameters declared.
Verilog-HDL does not impose restriction on number of
parameters declaration; however, it has adverse impact on
computational speed and chip area.
Table 1 shows different linguistic variable
assignments to distance and speed inputs.
In Verilog-HDL code, label VeryClose is stored as
follows (dvcpoint1 stands for DistanceVeryClosePoint1).
parameter dvcpoint1= 8'h00, dvcslope1= 8'hFF,
dvcpoint2 = 8’h00, dvcpoint3 = 8’h21, dvcslope2= 8'h0B,
dvcpoint4 = 8'h2C;
mem_distance_vc = 8’h00;
else if ((distance_input>dvcpoint2) &
(distance_input<dvcpoint2))
mem_distance_vc = (distance_input – dvcpoint1) *
dvcslope1;
else if ((distance_input > dvcpoint2) &
(distance_input<dvcpoint3))
mem_distance_vc =48’hFF – ((distance_input –
dvcpoint2) * dvcslope2;
else
mem_distance_vc = 8’h00;
As shown in Fig. 2, point1, point2, point3and point4
are very useful to check in which range particular input
belongs and based on that, with the help of slope1 and
slope2, membership value is assigned. Total no. of
membership assignments are equal to the total no. of
linguistic labels given for a particular input. So
distance_input[7:0] has got 5 and speed_input[7:0] has
got 5 membership value assignments and at a time of a
particular input, maximum two assignments have non-zero
value.
For instance, distance_input[7:0] is 8’h45 and
speed_input[7:0] is 8’h24, which are 62m and 23kmph
respectively. So input distance falls into Close and Normal
ranges and gets 8’hBA and 8’h21 membership values
respectively (based on fuzzification code written above)
and input speed falls into VeryLow and Low ranges and
gets 8’hE3 and 8’h1C of membership values respectively.
III. FUZZY CONTROL OUTPUT
The output membership functions of the fuzzy brake
controller are singletons. Five different linguistic terms of
the singleton output i.e., VeryLow, Low, Medium, High
and VeryHigh are used to describe the brake control
output variation. The assignment to the output
membership function in Verilog-HDL is declared as an 8-
bit long parameter types.

TABLE I parameter bvl= 8'h27, bl= 8'h50, bm= 8'h78, bhigh=

DISTANCE & SPEED INPUTS LINGUISTIC VARIABLES AND THEIR 8'hA2, bvhigh= 8'hE0;
RANGES

Distance Distance Speed Speed Range

Fuzzy Set Range (m) Fuzzy Set (kmph) IV. RULE INFERENCE MODULE
VeryClose 0 to 40 VeryLow 0 to 20
Close 30 to 70 Low 10 to 40 After the degree of membership function have been
Normal 60 to 140 Average 30 to 50 determined in the fuzzification stage, the next step is to
Far 120 to 200 Fast 40 to 70 use linguistic rules to decide an action to be taken in
VeryFar 180 onwards VeryFast 60 onwards response to a given set of degrees of membership
functions. The numerical results from this calculation are
called as fuzzy outputs. Various rules that can be fired for
 2013 IEEE International Conference on Computational Intelligence and Computing Research
different degrees of membership function variation,
introduced composite results.
In our case, inputs distance_input[7:0] and
speed_input[7:0], both have 5 linguistic terms and has a
total of 5*5 = 25 different rules, which can be used to
describe the complete fuzzy control strategy [5].
The IF part of the rule gets the degree of the input
membership function and the THEN part has the degree of
membership function that is determined by the result of
the rule evaluation. Since the input grades are connected
by a logical ‘AND’ operator, one input is dependent upon
the other, selecting the minimum value will satisfy both
conditions. Therefore, taking the minimum of the two
variables will be used as the output grade of membership
function in each rule.
In Verilog-HDL, reg [7:0] brake[24:0] defines array
of brake variables which is 8-bits wide and got 25 array
elements and it is used for storing output value of each
rule. For instance, rule 1 can be described in Verilog-HDL
as follows:
always @(speed_input or distance_input or reset or
clock)
begin
if (reset == 1)
brake[0] = 00;
else if (mem_distance_vc != 0 & mem_speed_vl != 0)
minimum (brake[0], mem_distance_vc, mem_speed_vl);
else
brake[0] = 8’h00;
end
Similarly, all other 24 rules are defined in Verilog-
HDL. It uses Verilog-HDL task named as minimum to
calculate minimum value of the mem_distance_vc and
mem_speed_vl, which are membership degree of
DistanceVeryClose and SpeedVeryLow. Further, minimum
is used because it is an equivalent of AND logical
operator which is used in rule description.
At any instance of time, for a particular
distance_input[7:0] and speed_input[7:0], maximum any
4 brake reg values are non-zero which are used for further
defuzzification process.
In the example described in section III, we have 4
different degrees of membership values which are non-
zero, i.e., mem_distance_c (stands for Close range of
distance input), mem_distance_n (stands for Normal range
of distance input), mem_speed_vl (stands for VeryLow
range of speed input), mem_speed_l (stands for Low range
of speed input) and they all activate 4 different rules, i.e.,
rule 6, 7, 11 and 12 which has brake[6], brake[7],
brake[11] and brake[12] as register values with non-zero
values respectively.
V. DEFUZZIFICATION
After the output grade of each rule has been
determined, the next step is to combine all the output
grades into a single value that can be used to control the
brake operation. In the defuzzifier process, Center-of-
Gravity (COG) [9, 10, 11] defuzzification technique will
be used to obtain the final system output. In this
application, singleton variables are used as the output
membership functions. Defuzzification involves taking the
weighted average of all the fuzzy outputs. Each fuzzy
output is multiplied by its corresponding singleton value,
then the sum of these products divided by the sum of all
the fuzzy outputs to obtain the final single output variable
[8, 9, 10].
A. Center-Of-Gravity (COG)
In Verilog-HDL, the support for loop structure is
limited i.e., right-hand side of the expression must be
constant (and same is the case with while loop), we have
to add every brake elements separately using if keyword.
COG in Verilog-HDL is implemented as follows.
always @(distance_input or speed_input or clock or
reset)
begin
if (reset ==1)
begin
sum = 0;
product = 0;
brake_op = 0;
end
else if
begin
sum = brake[0] + brake[1] + brake[2] + brake[3] +
brake[4] + brake[5] + brake[6] + brake[7] + brake[8] +
brake[9] + brake[10] + brake[11] + brake[12] + brake[13]
+ brake[14] + brake[15] + brake[16] + brake[17] +
brake[18] + brake[19] + brake[20] + brake[21] +
brake[22] + brake[23] + brake[24];
product = ((brake[15] + brake[20] + brake[21] +
brake[22]) * bvl) + ((brake[5] + brake[10] + brake[11] +
brake[16] + brake[17]) * bl) +((brake[0] + brake[1] +
brake[6] + brake[12] + brake[18] + brake[19] +brake[23]
+ brake[24]) * bm) + ((brake[2] + brake[7] + brake[13] +
brake[14]) * bhigh) +((brake[3] + brake[4] + brake[8] +
brake[9]) * bvhigh);
brake_op = product/sum;
end
end
brake_op is the final output of the hardware block
shown in Fig. 1. The simulation results obtained in ISim
simulator for example taken in section III are depicted in
Fig. 3.
 2013 IEEE International Conference on Computational Intelligence and Computing Research

The automatic brake controller is designed by taking

care of only front condition and avoiding situations at the
rear part of a vehicle. The controller is designed and
synthesized in ISE Design Suite 14.2. It used 22
multipliers, 121 adders/subtractors, 98 comparators and
1390 multiplexers (every generated component has
different number of bits dealing capacity). The design is
generated considering Kintex 7 KC705 as a targeted
device and controller utilizes only 5% of its slice LUTs
(2121 out of 41000), 11% of bonded Input Output Bus
(IOB) (33 out of 300) and other parts being unused which
shows very less area required by controller.
Fig. 4. COG & Sum-average method comparison
B. Sum-Average Method.
In view of the previous results, authors have brought
Rather than using singleton values of control output, out chip area (component utilization) as an approach to
sum of all non-zero membership values are calculated and select defuzzification over the conventional practice. So it
divided by total number of non-zero values. Continuing depends upon the manufacturer requirement which
with the input values taken previously, brake_op will be method to choose for defuzzification. In practice, COG is
8’h44 and with the same input values COD gets 8’h54. most widely used method as compare to others.
The sum-average method takes 10 multipliers, 17
adders/subtractors, 1 adder tree, 70 comparators and 837
multiplexers. It takes only 2% of slice LUTs (1002 out of ACKNOWLEDGMENT
41000) of Kintex 7 KC705. So it is a choice of a designer
The authors would like to thank to the College of
which method to adopt based on its speed and chip area
Engineering, Pune for the infrastructure support. We
requirement for defuzzification process.
acknowledge the fruitful discussion with Prof. (Mrs.) V. V.
Fig. 4 shows comparison of COG and sum-average
Ingale and are grateful for technical interaction with Prof.
method based on used components. As COG requires
(Mrs.) Vanita Agarwal. The support from Mr. Himanshu
more number of components and thus consumes more
B., Mr. Avinash K., Mr. Dinesh Sawant is appreciated.
power and fabrication area and it is a less preferable
method for defuzzification where higher accuracy is not
required.
REFERENCES
Typically, fuzzy system designer have to deploy
either COG or sum-average method for defuzzification [1] Zadeh, L.A., "Fuzzy Sets," Information and Control,
based on the experts feedback. In the past, there were no 8, 338-353, 1965.
guiding principles to select a particular defuzzification [2] Madni Asad M, Wan L. A, Hansen, Robert K, Vuong
method. Jim B, “Adaptive Fuzzy Logic Based Control System
for Rifle Stabilization”, Proceedings, 1998 World
Automation Congress (WAC ’98), Anchorage,
Alaska, May 10-14, 1998, pp.103-112.
[3] Brubaker, David I., "Fuzzy Logic Basics: Intuitive
Rules Replace Complex Math," EDN, June 18, 1992,
pp.111.
[4] Samir Palnitkar, “Veirlog HDL A Guide to Digital
Design and Synthesis”, 3rd reprint, Pearson
EducatonCypress Semiconductor, Addison-Wesley
Publishing., Inc. 2003.
[5] Mukesh D. Baldania, “Design of a Fuzzy Logic
Controller for Automatic Robotic Application”,
Project Report, EXTC Department, COEP, 2012-
2014.

Fig. 3. ISim generated result of COG method.