2065-16

Advanced Training Course on FPGA Design and VHDL for Hardware

Simulation and Synthesis

26 October - 20 November, 2009

VHDL & FPGA Architecturs

Synthesis III - Advanced VHDL

Nizar Abdallah
ACTEL Corp. 2061 Stierlin Court Mountain View
CA 94043-4655
U.S.A.
Lectures:
VHDL & FPGA Architectures
Outline
 Introduction to FPGA & FPGA Design Flow
 Synthesis I – Introduction
 Synthesis II - Introduction to VHDL
 Synthesis III - Advanced VHDL
 Design verification & timing concepts
 Programmable logic & FPGA architectures
 Actel ProASIC3 FPGA architecture

VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 2

Inferring Latches and Flip-Flops
 A latch or flip-flop is inferred if all branches of
an IF statement are not assigned
 Latch is inferred when if statement includes
level value
 Flip-Flop is inferred when if statement detects
an edge
 Simulator needs to hold previous output under
certain conditions if no else statement is
included

VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 3

Inferring Latches
 Latch is inferred when if statement detects a
level (0 or 1) and all branches of an IF
statement are not assigned

process
process (SEL,
(SEL, A)
A)
begin
begin A latch Y
if
if (SEL
(SEL == ‘1’)
‘1’) then
then YY <=
<= A;
A;
end
end if
if ;; SEL
end
end process;
process;

To avoid unwanted latches, include an ELSE condition

VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 4

Inferring Latches (cont’d)
 CASE statements using “when others => null”
can infer latches if type is std_logic or
std_logic_vector

--
-- sel,
sel, A,
A, BB are
are std_logic
std_logic SEL[1]
process
process (SEL,
(SEL, A,
A, B)
B)
begin
begin A
case
case SEL
SEL is
is latch Y
when
when “00”
“00” =>
=> YY <=
<= A;
A; B
when
when “10”
“10” =>
=> YY <=
<= B;
B;
when
when others
others =>
=> null;
null; SEL[0]
end
end case;
case;
end
end process;
process;

To avoid unwanted latches, actually define Y for the “others” condition, for example:
when others => Y <= ‘0’;

VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 5

Inferring Flip-Flops
 Use Processes and IF statements to describe
sequential logic
 IF statement detects clock edge
rising edge = if (CLK’event and CLK=‘1’)
falling edge = if (CLK’event and CLK=‘0’)

architecture
architecture BEHAVE
BEHAVE of
of DF
DF is
is
begin
begin
INFER:
INFER: process
process (CLK)
(CLK) begin
begin D Q
if
if (CLK’event
(CLK’event and
and CLK
CLK =‘1’)
=‘1’) then
then
QQ <=
<= D;
D;
end
end if
if ;;
end
end process
process INFER;
INFER; CLK
end
end BEHAVE;
BEHAVE;

VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 6

Sequential Logic: Example 1

D flip-flop with
asynchronous low
reset and active high
architecture
architecture FLOPFLOP of
of DFCLR
DFCLR is
is clock edge
begin
begin
INFER:
INFER: process
process (CLK,
(CLK, RST)
RST)
begin
begin
if D Q
if (RST
(RST =‘0’)
=‘0’) then
then
QQ <=
<= ‘0’;
‘0’;
elsif
elsif (CLK’event
(CLK’event and
and CLK
CLK =‘1’)
=‘1’) then
then
QQ <=
<= D;
D; CLK
end
end if
if ;; RST
end
end process
process INFER;
INFER;
end
end FLOP;
FLOP;

VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 7

Sequential Logic: Example 2

D flip-flop with
synchronous low reset,
architecture
architecture FLOPFLOP of
of DFSLRHE
DFSLRHE is
is active high enable and
begin
begin rising edge clock
INFER:
INFER: process
process (CLK)
(CLK)
begin
begin
if
if (CLK’event
(CLK’event and and CLK
CLK =‘1’)
=‘1’) then
then
if
if (SRST
(SRST == ‘0’)
‘0’) then
then D Q
QQ <=
<= ‘0’;
‘0’; EN
elsif
elsif (EN(EN == ‘1’)
‘1’) then
then
CLK
QQ <=
<= D;
D;
end SRST
end ifif ;;
end
end if
if ;;
end
end process
process INFER;
INFER;
end
end FLOP;
FLOP;

VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 8

Sequential Logic: Example 3

architecture
architecture FLOPFLOP of
of EN_FLOP
EN_FLOP is
is
begin
begin
INFER:process
INFER:process (CLK)(CLK) begin
begin
if
if (CLK’event
(CLK’event and and CLK
CLK =‘0’)
=‘0’) then
then
if
if (EN
(EN == ‘0’)
‘0’) then
then
QQ <=
<= D;D;
end
end ifif ;;
end
end ifif ;;
end
end process
process INFER;
INFER;
end
end FLOP;
FLOP;

Will this model a positive edge or negative edge triggered flip-flop?

Is the enable synchronous or asynchronous?

Is the enable active high or active low?

VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 9

Sequential Logic: Example 4

library
library ieee;
ieee; 4-bit register
use
use ieee.std_logic_1164.all;
ieee.std_logic_1164.all; using WAIT
entity
entity DF_4
DF_4 isis statement
port
port (D:
(D: inin std_logic_vector(3
std_logic_vector(3 downto
downto 0);0);
CLK:
CLK: inin std_logic;
std_logic;
Q:
Q: out
out std_logic_vector(3
std_logic_vector(3 downto
downto 0));
0));
end
end DF_4
DF_4 ;; D[3:0] Q[3:0]
architecture
architecture FLOPFLOP of
of DF_4
DF_4 is
is
begin
begin
INFER:
INFER: process
process Where’s the sensitivity list?
begin
begin
CLK
wait
wait until
until (CLK’event
(CLK’event and
and CLK
CLK =‘1’);
=‘1’);
QQ <=
<= D;
D;
end
end process
process INFER;
INFER;
end
end FLOP;
FLOP;

VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 10

8-bit Counter Example

CNT

8
8 2x1 8 D Q 8
MUX Q
+ 8

incrementor CNT-EN CLK CLR

NOTE: The output, Q, must be copied to an

internal signal, CNT, since an output port can not
appear on the right-hand side of an assignment
operator

VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 11

8-bit Counter Example (cont’d)
library
library ieee;
ieee; useuse ieee.std_logic_1164.all;
ieee.std_logic_1164.all;
use
use ieee.std_logic_unsigned.all;
ieee.std_logic_unsigned.all;
entity
entity COUNTER
COUNTER is is
port
port (CLK,CNT_EN,CLR:in
(CLK,CNT_EN,CLR:in std_logic;
std_logic;
QQ :out
:out std_logic_vector(7
std_logic_vector(7 downto
downto 0));
0));
end
end COUNTER;
COUNTER;
architecture
architecture BEHAVEBEHAVE of
of COUNTER
COUNTER is
is
signal
signal CNT:std_logic_vector(7
CNT:std_logic_vector(7 downto
downto 0);
0);
begin
begin
FIRST:
FIRST: process
process (CLK,
(CLK, CLR)
CLR)
begin
begin
if
if (CLR
(CLR == ‘0’)
‘0’) then
then
CNT
CNT <=<= ""00000000";
00000000";
elsif
elsif (CLK'event
(CLK'event andand CLK
CLK == ‘1’)
‘1’) then
then
if
if (CNT_EN
(CNT_EN == ‘0’)
‘0’) then
then
CNT
CNT <=<= CNT
CNT ++ ‘1’;
‘1’;
end
end ifif ;;
end
end ifif ;;
end
end process
process FIRST;
FIRST;
QQ <=
<= CNT;
CNT;
end
end BEHAVE;
BEHAVE;

VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 12

8-bit Shift Register

library
library ieee;
ieee;
use
use ieee.std_logic_1164.all;
ieee.std_logic_1164.all;
entity
entity SHIFTER
SHIFTER is
is
port(CLK,
port(CLK, DIN:
DIN: in
in std_logic;
std_logic;
Z:
Z: out
out std_logic_vector(7
std_logic_vector(7 downto
downto 0));
0)); A[6:0]
end
end SHIFTER;
SHIFTER;
architecture
architecture RTL
RTL of
of SHIFTER
SHIFTER is
is
DIN
signal
signal A:A: std_logic_vector(7
std_logic_vector(7 downto
downto 0);
0); D[7:0] Z[7:0]
begin
begin
process
process (CLK)
(CLK)
begin
begin
if
if (CLK'event
(CLK'event and
and CLK='1')
CLK='1') then
then
AA <=
<= AA (6
(6 downto
downto 0)
0) && DIN;
DIN; --
-- shift
shift left
left CLK
end
end if;
if;
end
end process;
process;
ZZ <=
<= A;
A;
end
end RTL
RTL

VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 13

State Machine Overview
 Typically include:
At least 2 process statements (one MUST control the clocking)
IF-THEN-ELSE statements
CASE statements
User defined types to hold current state and next state

 Transitions depend on current state and

optionally, the inputs
 Outputs depend on:
Current state (Moore machine)
Current state & inputs (Mealy machine)

 Definition:
State (t+1) <= F(i1,...,in,State(t))
Output <= F(i1,...,in,State(t))
VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 14
FSM: Two Machine Types

Moore
Moore Trans. Gen. O
Machine
Machine I
Func.
Func Func.

ck

Mealey
Mealey Trans. Gen. O
Machine
Machine I
Func.
Func Func.

ck

VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 15

Common FSM Structure in VHDL
Next state

Second process First process

Inputs
Next State Current State
Logic Register
(combinational) (sequential)
Clock

Current state

Asynchronous
reset
Third process
Output Outputs
Logic
(combinational)

VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 16

FSM Example: 4 Consecutive Ones
Counter

0
E0 1

0
E1
0 0
1 0 1
E4
E2

1 E3
1

VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 17

FSM Example: 4 Consecutive Ones
Counter (cont’d)
--
--
Entity
Entity counter
counter is
is port
port (ck,
(ck, I,
I, reset:
reset: in
in bit;
bit; O:
O: out
out bit);
bit);
End
End counter;
counter;

Architecture
Architecture automate
automate of
of counter
counter is
is
type
type STATE_TYPE
STATE_TYPE is
is (E0,
(E0, E1,
E1, E2,
E2, E3,
E3, E4);
E4);
signal
signal CURRENT_STATE,
CURRENT_STATE, NEXT_STATE:
NEXT_STATE: STATE_TYPE;
STATE_TYPE;
--
-- pragma
pragma CUR_STATE
CUR_STATE CURRENT_STATE;
CURRENT_STATE;
--
-- pragma
pragma NEX_STATE
NEX_STATE NEXT_STATE;
NEXT_STATE;
--
-- pragma
pragma CLOCK
CLOCK ck;
ck;

begin
begin
Process(CURRENT_STATE,
Process(CURRENT_STATE, I, I, reset)
reset)
begin
begin
if
if (reset
(reset == '1')
'1') then
then
NEXT_STATE
NEXT_STATE <=
<= E0;
E0;
OO <=
<= '0';
'0';
else
else

VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 18

FSM Example: 4 Consecutive Ones
Counter (cont’d)
case
case CURRENT_STATE
CURRENT_STATE is is
WHEN
WHEN E0
E0 =>
=>
if
if (I='1')
(I='1') then
then
NEXT_STATE
NEXT_STATE <=
<= E1;
E1;
else
else
NEXT_STATE
NEXT_STATE <=
<= E0;
E0;
end
end if;
if;
OO <=
<= '0';
'0';

WHEN
WHEN E1
E1 =>
=>
if
if (I='1')
(I='1') then
then
NEXT_STATE
NEXT_STATE <=
<= E2;
E2;
else
else
NEXT_STATE
NEXT_STATE <=
<= E0;
E0;
end
end if;
if;
OO <=
<= '0';
'0';

VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 19

FSM Example: 4 Consecutive Ones
Counter (cont’d)
WHEN
WHEN E2
E2 =>
=>
if
if (I='1')
(I='1') then
then
NEXT_STATE
NEXT_STATE <=
<= E3;
E3;
else
else
NEXT_STATE
NEXT_STATE <=
<= E0;
E0;
end
end if;
if;
OO <=
<= '0';
'0';

WHEN
WHEN E3
E3 =>
=>
if
if (I='1')
(I='1') then
then
NEXT_STATE
NEXT_STATE <=
<= E4;
E4;
else
else
NEXT_STATE
NEXT_STATE <=
<= E0;
E0;
end
end if;
if;
OO <=
<= '0';
'0';

VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 20

FSM Example: 4 Consecutive Ones
Counter (cont’d)
WHEN
WHEN E4
E4 =>
=>
if
if (I='1')
(I='1') then
then
NEXT_STATE
NEXT_STATE <=
<= E4;
E4;
else
else
NEXT_STATE
NEXT_STATE <=
<= E0;
E0;
end
end if;
if;
OO <=
<= '1';
'1';

WHEN
WHEN others
others =>
=>
assert
assert ('1')
('1')
report
report "Illegal
"Illegal State";
State";

end
end case;
case;
end
end if;
if;
end
end process;
process;

VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 21

FSM Example: 4 Consecutive Ones
Counter (cont’d)
Process
Process (ck)
(ck)
begin
begin
if
if (ck
(ck == '0'
'0' and
and not
not ck'stable)
ck'stable) then
then
CURRENT_STATE
CURRENT_STATE <=
<= NEXT_STATE;
NEXT_STATE;
end
end if;
if;
end
end process;
process;
end
end counter;
counter;

VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 22

FSM Example: 4 Consecutive Ones
Counter (cont’d)

CK
CK

II

O
O

Current
Current E0 E1 E2 E3 E4

Next
Next E1 E2 E3 E4 E4

What happens if a glitch occurs on the input I ?

VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 23

FSM Warnings

 All Signals which are Assigned to within a

Clocked Process Have Registers on their
Outputs

 Signal Assignments within a Process are

Effective only before the wait (implicit or
explicit) Statement

VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 24

Design Verification
 Three step process:
Simulate RTL vs. specification
Simulate structural (using VITAL) vs. RTL
Simulate structural (using VITAL) with back-annotated timing

 Procedure
Use testbench or manually apply stimulus
Check for correct results and produce a trace file

 Choices
Use vendor-specific stimulus file (non-portable)
Write generic VHDL testbench

VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 25

Generic VHDL Testbench
 Written by designer using standard VHDL
Portable to any VHDL simulator

 Creates a new level of design hierarchy

Component instantiation of design under test
VHDL processes to apply stimulus and record outputs

 Uses VHDL textio package

Read or write to ASCII data files
Input test vectors (times and values)
Tabular trace, print-on-change, strobe

VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 26

Assert Statement
 Writes out text messages during simulation
 Useful for timing checks, out of range
conditions, etc.
 Four levels
Failure
Error
Warning
Note

assert
assert (Y
(Y >> 2)
2)
report
report “SETUP
“SETUP VIOLATION”
VIOLATION”
severity
severity Warning;
Warning;

VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 27

Wait Statement
 Suspends execution of the process or sub-
program
 Usage:
wait
wait for
for 10
10 NS;
NS;
wait
wait for <time> wait
wait until
until XX >> 10;
10;
wait until <condition>
wait on <signals>

 Remember!
Processes with a sensitivity list cannot have a
WAIT statement

VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 28

Generating Waveforms
 A sequential waveform can be generated using
Multiple signal assignments in a single concurrent signal
assignment ENABLE
ENABLE <=
<= ‘0’,
‘0’, ‘1’
‘1’ after
after 100
100 ns,
ns,
‘0’
‘0’ after
after 180
180 ns,
ns, ‘1’
‘1’ after
after 210
210 ns;
ns;
sequential signal assignments in a process
.. .. ..
process
process
begin
begin
ENABLE
ENABLE <=
<= ‘0’;
‘0’;
wait
wait for
for 100
100 ns;
ns;
ENABLE
ENABLE <=
<= ‘1’;
‘1’;
wait
wait for
for 80
80 ns;
ns;
ENABLE
ENABLE <=
<= ‘0’;
‘0’;
wait
wait for
for 30
30 ns;
ns;
ENABLE
ENABLE <=
<= ‘1’;
‘1’;
wait;
wait;
end
end process;
process;
.. .. ..

VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 29

Generating Repetitive Waveforms
 Waveforms with .. .. ..
AA <=
<= not
not AA after
after 20
20 ns;
ns;
Constant 50% duty cycle .. .. ..
can be created with a
single concurrent signal
assignment or in a process A A
20 40 60 80 100 120

Varying on-off delays can .. .. ..

be created using a CLK:
CLK: process
process
process statement constant
constant OFF_PERIOD:
OFF_PERIOD: TIME:=
TIME:= 30
30 ns;
ns;
constant
constant ON_PERIOD:
ON_PERIOD: TIME:=
TIME:= 20
20 ns;
ns;
begin
begin
wait
wait for
for OFF_PERIOD;
OFF_PERIOD;
D_CLK
D_CLK <=
<= ‘1’;
‘1’;
wait
wait for
for ON_PERIOD;
ON_PERIOD;
D_CLK
D_CLK <=
<= ‘0’;
‘0’;
end
end process;
process;
.. .. ..

D_CLK
30 50 80 100

VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 30

Testbench Example:
8-Bit Counter
library
library ieee;
ieee; use
use ieee.std_logic_1164.all;
ieee.std_logic_1164.all;
use
use ieee.std_logic_arith.all;
ieee.std_logic_arith.all;

entity
entity TESTBENCH
TESTBENCH is
is Testbench entity does
not include ports
end
end TESTBENCH;
TESTBENCH;

architecture
architecture BEHAVE
BEHAVE of
of TESTBENCH
TESTBENCH is
is

Counter declared
component
component COUNTER
within testbench
COUNTER
port
port (CLK,CNT_EN,CLR:in
(CLK,CNT_EN,CLR:in std_logic;
std_logic;
Q:out
Q:out std_logic_vector(7
std_logic_vector(7 downto
downto 0));
0));
end
end component;
component;
signal
signal CLKIN,ENABLE,RESET:std_logic;
CLKIN,ENABLE,RESET:std_logic;
signal
signal Qout:std_logic_vector(7
Qout:std_logic_vector(7 downto
downto 0);
0);

begin
Counter instantiated
begin --
-- Instantiate
Instantiate Counter
Counter
U1:COUNTER
U1:COUNTER port
port map(CLK=>CLKIN,
map(CLK=>CLKIN, CNT_EN=>ENABLE,
CNT_EN=>ENABLE,
within testbench
CLR=>RESET,
CLR=>RESET, Q=>Qout);
Q=>Qout);

VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 31

Testbench Example:
8-Bit Counter (cont.)

--
-- initialize
initialize inputs,
inputs, and
and toggle
toggle the
the reset
reset line
line
INIT:
INIT: process
process begin
begin
ENABLE
ENABLE <=
<= '1';
'1';
RESET
RESET <=<= '1';
'1';
wait
wait for
for 250
250 ns;
ns;
RESET
RESET <=<= '0';
'0';
wait
wait for
for 250
250 ns;
ns;
RESET
RESET <=<= '1';
'1';
wait;
wait; --
-- this
this instruction
instruction suspends
suspends the
the init
init process
process
end
end process
process INIT;
INIT;
--
-- process
process to
to cause
cause clock
clock to
to toggle
toggle (20
(20 MHz)
MHz)
CLK_TOG:
CLK_TOG: process
process begin
begin
CLKIN
CLKIN <=<= '0';
'0';
wait
wait for
for 25
25 ns;
ns;
CLKIN
CLKIN <=<= '1';
'1';
wait
wait for
for 25
25 ns;
ns;
end
end process
process CLK_TOG;
CLK_TOG;
end
end BEHAVE;
BEHAVE;

VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 32

Testbench Example:
8-Bit Counter (cont.)

VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 33

Common Issues:
Combinational Processes

process
process (A,
(A, B,
B, SEL)
SEL)
begin
begin
if
if (SEL=‘1’)
(SEL=‘1’) then
then
OUT
OUT <=
<= A;
A;
else
else
OUT
OUT <=
<= B;
B;
end
end if;
if;
end
end process;
process;

 Sensitivity list must consist of all signals that

are read inside the process
Synthesis tools often ignore sensitivity list, but simulation
tools do not…
A forgotten signal will lead to difference in behavior of the
simulated model and the synthesized design

VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 34

Common Issues:
Combinational Processes

process
process (A,
(A, B,
B, SEL)
SEL) process
process
begin
begin begin
begin
if
if (SEL=‘1’)
(SEL=‘1’) then
then OUT
OUT <=
<= A;
A; if
if (SEL=‘1’)
(SEL=‘1’) then
then
else
else OUT
OUT <=
<= B;
B; OUT
OUT <=
<= A;
A;
end
end if;
if; else
else
end
end process;
process; OUT
OUT <=
<= B;
B;
end
end if;
if;
wait
wait on
on A,
A, B,
B, SEL;
SEL;
end
end process;
process;

 Can use WAIT ON instead of sensitivity list

 But not both!

VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 35

Common Issues:
Wait-free Paths

process
process
begin
begin
if
if (condition)
(condition)
wait
wait on
on CLK’event
CLK’event and
and CLK=1;
CLK=1;
end
end if;
if;
end
end process;
process;

 Every path through a process body without

sensitivity list must have a wait
Otherwise the process can hang

VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 36

Common Issues:
Mistakenly Inferences Latches
process
process (A,
(A, B)
B)
begin
begin
if
if (condition_1)
(condition_1)
XX <=
<= AA ++ B;
B;
elsif
elsif (condition_2)
(condition_2)
XX <=
<= XX –– B;
B;
end
end if;
if;
end
end process;
process;

 Remember, incomplete assignments imply

latches
In the above example, if neither condition_1 nor condition_2 is
true then X will retain its value … basically, X is stored in a
latch
If you are writing combinational logic, make sure that every
output gets assigned a value along each path (e.g. if
statements, case statements) through the process body
In general, latches are not recommended anyway in
synchronous designs (not testable via scan paths)
VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 37
Common Issues:
The Problem with Latches
 Most EDA software tools have difficulty with
latches because of transparency
Timing analysis must consider both open and closed cases
Test vector generation is complicated
Latches are not scan testable

 Good design practice:

ASICs and FPGAs are a flip-flop’s world
Don’t use latches unless you absolutely have to

 Poorly coded if and case statements can yield

unintended latches

VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 38

Common Issues:
Implicit Register Inference

process
process (A,
(A, B)
B)
begin
begin
wait
wait until
until CLK’event
CLK’event and
and CLK=1;
CLK=1;
if
if (COUNT
(COUNT >=
>= 9)
9) then
then
COUNT
COUNT <=
<= 0;
0;
else
else
COUNT
COUNT <=
<= COUNT
COUNT +1;
+1;
end
end if;
if;
end
end process;
process;

 Storage registers are synthesized for all signals

that are driven within a clocked process
 Storage registers are also synthesized for all
variables that are read before being updated

VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 39

Common Issues:
Reset (or Set) in Synthesis

process
process Process
Process (CLK,
(CLK, RST)
RST)
begin
begin begin
begin
wait
wait until
until CLK’event
CLK’event and
and CLK=1;
CLK=1; if
if (RST=‘1’)
(RST=‘1’) then
then
if
if (RST=‘1’)
(RST=‘1’) then
then --
-- asynchronous
asynchronous reset
reset
--
-- synchronous
synchronous reset
reset elsif
elsif (CLK’event
(CLK’event and
and
else
else CLK=1)
CLK=1) then
then
--
-- combinational
combinational code
code --
-- combinational
combinational code
code
end
end if;
if; end
end if;
if;
end
end process;
process; end
end process;
process;

 Must reset all registers, otherwise synthesized

chip won’t work
Unlike simulation, you can’t set initial values in synthesis!

 Asynchronous reset possible only with a

process that has a sensitivity list
VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 40
Common Issues:
Coding Style Influence

process(A,
process(A, B, B, C,C, SEL)
SEL) Process
Process (A,(A, B,
B, C,
C, SEL)
SEL)
begin
begin variable
variable tmp:
tmp: bit;
bit;
if
if (SEL=‘1’)
(SEL=‘1’) thenthen begin
begin
ZZ <= SEL
<= AA ++ B;
B; if
if (SEL=‘1’)
(SEL=‘1’) then
then
else
else C tmp
tmp :=
:= B;
B;
+ SEL
ZZ <=
<= AA ++ CC A else
else
end if;
end if; + tmp
tmp :=
:= C;
C; B
end
end process;
process; B end
end if;
if;
ZZ <= C
<= AA ++ tmp;
tmp; +
end
end process;
process; A

 Structure of initially generated hardware is

determined by the VHDL code itself
Synthesis optimizes that initially generated hardware, but
cannot do dramatic changes
Therefore, coding style matters!

VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 41

Common Issues:
IF vs. CASE
 IF-THEN-ELSIF-THEN-…-ELSE maps to a chain of
2-to-1 multiplexers
if
if (COND1)
(COND1) then
then OUT
OUT <=
<= X1;
X1;
elsif
elsif (COND2)
(COND2) then
then OUT
OUT <=
<= X2;
X2;
……
else
else OUT
OUT <=
<= Xn;
Xn;

 CASE maps to a single N-to-1 multiplexer

……
case
case EXPRESSION
EXPRESSION is
is
when
when VALUE1
VALUE1 =>
=>
OUT
OUT <=
<= X1;
X1;
when
when VALUE2
VALUE2 =>
=>
OUT
OUT <=
<= X2;
X2;
……
when
when others
others =>
=>
OUT
OUT <=
<= Xn;
Xn;
end
end case;
case;
……

VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 42

Common Issues:
Let the tool do the Synthesis
 Don’t do synthesis by hand!
Do not come up with Boolean functions for outputs of
arithmetic operator
Let Synthesis tool decide which adder, multiplier to use
You will only restrict the synthesis process

 Let synthesis tool decide the numeric encoding

of the FSM states
Use enumerated type for state

 Split into multiple simpler processes

 Keep module outputs registered
Simplifies timing constraints

VHDL & FPGA Architectures © 2005 Nizar Abdallah November, 2005 43