C2000™ Piccolo™ F28004X Series Launchpad™ Development Kit: User'S Guide

User's Guide
SPRUII7B – June 2018 – Revised April 2020
C2000™ Piccolo™ F28004x Series LaunchPad™

Development Kit
The C2000 LAUNCHXL-F280049C a low-cost development board for the Texas Instruments Piccolo
F28004x series of microcontrollers (MCUs). It is designed around the TMS320F280049C MCU and
highlights the control, analog, and communications peripherals, as well as the integrated nonvolatile
memory. The LaunchPad also features two independent BoosterPack XL expansion connectors, on-board
Controller Area Network (CAN) transceiver, 5 V encoder connectors, FSI connector, and an on-board
XDS110 debug probe.
Figure 1 highlights the key features of the Piccolo F28004x LaunchPad.
Figure 1. Piccolo F28004x Series LaunchPad Development Kit
SPRUII7B – June 2018 – Revised April 2020 C2000™ Piccolo™ F28004x Series LaunchPad™ Development Kit 1
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Copyright © 2018–2020, Texas Instruments Incorporated
www.ti.com
Contents
1 Board Overview .............................................................................................................. 3
2 Hardware Description ....................................................................................................... 6
3 Software Development .................................................................................................... 12
4 Board Design ............................................................................................................... 14
5 References .................................................................................................................. 23
Appendix A ....................................................................................................................... 24
List of Figures
1 Piccolo F28004x Series LaunchPad Development Kit .................................................................. 1
2 Piccolo F28004x LaunchPad Development Kit Block Diagram ........................................................ 6
3 BoosterPack Pin Map ....................................................................................................... 8
4 MCU025B_Block_Diagram.SchDoc ..................................................................................... 14
5 MCU025B_Connectors.SchDoc .......................................................................................... 15
6 MCU025B_AltRouting_Misc.SchDoc .................................................................................... 16
7 MCU025B_F280049C_Device.SchDoc ................................................................................. 17
8 MCU025B_XDS110_Target_Interface.SchDoc ........................................................................ 18
9 MCU025B_XDS110_USB_Power.SchDoc ............................................................................. 19
10 MCU025B_XDS110_MCU.SchDoc ...................................................................................... 20
11 MCU025B_Hardware.SchDoc ............................................................................................ 21
12 F28004x LaunchPad Dimensions and Component Locations ....................................................... 22
13 Target Configuration Advanced Options ................................................................................ 25
14 Target Configuration included in the demo project .................................................................... 25
List of Tables
1 LAUNCHXL-F280049C Specifications .................................................................................... 3
2 Boot Select Switch Settings ................................................................................................ 7
3 PGA Signals and Associated Connections ............................................................................. 10
4 Alternate Function Switch Settings ...................................................................................... 11
5 FSI to BoosterPack Isolation Resistors ................................................................................. 12
Trademarks
C2000, Piccolo, LaunchPad, InstaSPIN-FOC, InstaPIN-FOC, FAST, Code Composer Studio are
trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
2 C2000™ Piccolo™ F28004x Series LaunchPad™ Development Kit SPRUII7B – June 2018 – Revised April 2020
www.ti.com Board Overview
1 Board Overview
1.1 Kit Contents

The Piccolo F28004x Series LaunchPad Development Kit contains these items:
• C2000 Piccolo F28004x Series LaunchPad development board (LAUNCHXL-F280049C)
• USB micro-B plug to USB-A plug cable
• Two LaunchPad Stickers
1.2 Features
The F28004x LaunchPad has these features:
• C2000 Piccolo Series F280049CPZS microcontroller:
– Enabled for InstaSPIN-FOC™ motor control and Configurable Logic Block (CLB) capability
• On-board XDS110 debug probe
• Two user-controlled LEDs
• One microcontroller reset switch
• Selectable power domains:
– USB (isolated)
– BoosterPack
– External power supply
• CAN connectivity with on-board CAN transceiver
• Two independent Enhanced Quadrature Encoder Pulse (QEP)-based encoder connectors
• Separate FSI connector
• Two independent BoosterPack XL standard connectors featuring stackable headers to maximize
expansion through the BoosterPack ecosystem
1.3 Specifications
Table 1 summarizes the F28004x LaunchPad specifications.
Table 1. LAUNCHXL-F280049C Specifications

Parameter Value
5 VDC from one of the following sources:
• Debug USB (USB101) USB Micro-B cable connected to PC or other compatible
power source.
Board Supply Voltage
• BoosterPack 1
• BoosterPack 2
• Auxiliary power connectors
Dimensions 6.15 in x 2.3 in x .425 in (15.62 cm x 5.84 cm x 10.8 mm) (L x W x H)
• Optional 5 VDC to BoosterPacks, current limited by LMR62421. Nominal rating 2.1
Amps. Board input power supply limitations may also apply.
Break-out Power Output • 3.3 VDC to BoosterPacks, limited by output of TPS79601 LDO. This 3.3-V plane is
shared with on-board components. Total output power limit of TPS79601 is 1
Amp.
This kit is assumed to run at standard room conditions. The EVM should run at
Assumed Operating Conditions approximately standard ambient temperature and pressure (SATP) with moderate-to-
low humidity.
Board Overview www.ti.com
1.4 Using the F28004x LaunchPad

The recommended steps for using the F28004x LaunchPad are:
1. Follow the README First document included in the kit. The README First document helps you
run the LaunchPad. Within just a few minutes, you can control and monitor the F28004x LaunchPad
with the pre-programmed quick start application. Additionally, Section A.1, the FAQ section included in
this document can be helpful if there are any issues that might quickly be addressed.
2. Experiment with BoosterPacks. This development kit conforms to the latest revision of the
BoosterPack pinout standard. It has two independent BoosterPack connections to enable a variety of
expansion opportunities. For more information about the TI LaunchPad and BoosterPack standard, see
the TI LaunchPad web page at http://www.ti.com/launchpad.
3. Take the first step towards developing your own control applications. The F28004x LaunchPad is
supported by the C2000Ware development package. After C2000Ware is installed, look for
f28004x\examples\launchpad in the installation directory. You can find pre-configured example
applications for this board as well as for this board with selected BoosterPacks. Any of the other
examples found withing the f28004x\examples directory can be used with minor modifications to run on
the LaunchPad as well. For more details about software development, see Section 3.
4. Customize and integrate the hardware to suit your end application. This development kit can be
used as a reference for building your own custom circuits based on C2000 Piccolo Series
microcontrollers or as a foundation for expansion with your custom BoosterPack or other circuits. This
document can serve as a starting point for this endeavor.
5. Get Trained. You can also download hours of written and video training materials on this and related
LaunchPads. For more information, visit the C2000 Real-Time Control MCUs - Support & Training
page.
1.5 BoosterPacks
The LAUNCHXL-F280049C provides an easy and inexpensive way to develop applications with the
F28004x Series microcontroller. BoosterPacks are add-on boards that follow a pin-out standard created by
Texas Instruments. The TI and third-party ecosystem of BoosterPacks greatly expands the peripherals
and potential applications that you can easily explore with the F28004x LaunchPad.
You can also build your own BoosterPack by following the design guidelines on TI’s website. Texas
Instruments even helps you promote your BoosterPack to other members of the community. TI offers a
variety of avenues for you to reach potential customers with your solutions.
1.6 InstaPIN-FOC™
The LAUNCHXL-F280049C includes the Piccolo TMS320F280049C that has the superset configuration of
features enabled, including InstaSPIN-FOC sensorless motor control technology. A library is included in
on-chip ROM that can be accessed by a set of software APIs as demonstrated by projects included in
C2000Ware MotorControl Software Development Kit (available 2018Q4).
InstaSPIN-FOC technology identifies motor parameters, self-tunes the sensorless FAST™ observer, sets
stable tuning for the current controllers, and allows you to quickly control your own three-phase motors
under advanced, high-performance field oriented vector control (FOC) without the need for mechanical
rotor sensors.
1.7 Hardware Revisions

This section contains an abbreviated revision history of the EVM as well as known issues with each
revision.
www.ti.com Board Overview
1.7.1 Revision A
The first production revision of the LAUNCHXL-F280049C was released in July 2018. This revision can be
identified by the "MCU025A" silkscreen labeling on the back side of the EVM between the BoosterPack
Connector site 1 towards the top of the board.
Various issues and concerns have been Identified on the EVM as listed below:
Known issues:
• There is contention on the primary side power of the USB Isolation IC, ADUM3160 (U3). As VBUS1 is
connected to a 5 V supply (USB_VBUS), the internal regulator of the ADUM3160 will provide 3.3 V
internally, with the VDD1 pin being an output. In this revision, USB_VCC, a 3.3 V supply, is connected
to VDD1 leading to the contention. Any fluctuation of either 3.3 V supply (USB_VCC and ADUM3160
VDD1) may cause currents to be sourced or drawn from either supply. This is a long term reliability
concern for both U3 and U101.
• On the PCB, the J6 and J8 labeling is swapped on the silkscreen. J6 is marked as the inner row (pins
71-80) and J8 is marked as the outer row (pins 51-60). This is incorrect and J6 should be on the outer
row with (pins 51-60) and J8 is the inner row (pins 71-80).
• Similar to the above, on the MCU025A_Connectors.SchDoc, J6 and J8 should be swapped. In the
schematic symbol J8 should be above Pins 31-40, while J6 should be above pins 11-20.
• Similar to the PCB silkscreen and the schematic, the Quick Start Guide insert has the pin numbers for
51-60 listed as J8 and 71-80 listed as J6. This is incorrect; the pin numbers should be swapped.
Special notes and considerations to be aware of:
• A precision reference (U11) is connected to VREFA+ (pin 9) of the TM4C129x device (U2 - the
XDS110 MCU). This is not necessary for the operation of the debug probe. VREFA+ (pin 9) can be
safely connected directly to VDDA (pin 8). There are no issues with the current configuration; it is an
opportunity for BOM cost/simplification for those seeking to replicate this design on their own.
• The EMU package 8.0.903.4 has a firmware update for the XDS110 Debug probe. This update breaks
the cJTAG function of the XDS110. Refer to Section A.1, the FAQs, for more information on how to
resolve this issue if encountered.
1.7.2 Revision B
The second production revision of the LAUNCHXL-F280049C was released in x. This revision can be
identified by the "MCU025B" silkscreen labeling on the back side of the EVM. The fixed issues and added
enhancements from the first revision (A) are described below.
Fixed issues:
• Fixed primary side power contention issue on USB Isolation IC, ADUM3160 (U3). See Section 1.7.1 for
description of issue.
• Fixed J6 and J8 header errors described in Section 1.7.1
Enhancements:
• FSITXD1, FSIRXD1, and 3.3V power signals have been added to the expanded 2x5 connector J11
• XDS110 MCU (U2) TM4C129x device replaced with MSP432E401 device. Form and function have not
been changed with this in any way.
• Precision reference (U11) connected to the XDS110 MCU (U2) has been removed and VREFA+ (pin
9) has been directly connected to VDDA (pin 8)
Hardware Description www.ti.com
2 Hardware Description
The F28004x LaunchPad includes a F280049CPZS MCU. This MCU is well suited for advanced real-time
control systems in cost-sensitive applications. A large number of these peripherals are made available to
users via the on-board accessories and the BoosterPack connectors. This section explains how those
peripherals operate and interface to the MCU
Figure 2 shows a high-level block diagram of the F28004x LaunchPad:
Figure 2. Piccolo F28004x LaunchPad Development Kit Block Diagram
2.1 Functional Description and Connections
2.1.1 Microcontroller
The F280049CPZS is a 32-bit floating-point microcontroller with 256KB Flash memory, 100KB RAM, and
operates at 100 MHz. It includes advanced control peripherals, differentiated analog, and various
communications peripherals. The devices has been optimized for high-performance applications and
provides a low-cost system solution. For more details, see the TMS320F28004x Piccolo microcontrollers
data sheet.
Most of the microcontroller's signals are routed to 0.1 inch (2.54 mm) pitch headers laid out to comply with
the TI BoosterPack standards with a few exceptions. An internal multiplexer allows different peripheral
functions to be assigned to each of the General-Purpose Input/Output (GPIO) pads. The multiplexing
options can be found in the device-specific data sheet. When adding external circuitry, consider the
additional load on the development board power rails.
The F28004x LaunchPad is factory-programmed with a quick start demo program. The quick start
program resides in the on-chip Flash memory and executes each time power is applied, unless the
application has been replaced with a user program. The quick start application utilizes the integrated
Analog-to-Digital Converter (ADC) module to sample the voltage on a pin, then output the results with the
Serial Communications Interface (SCI) Universal Asynchronous Receiver/Transmitter (UART) through the
Virtual COM port (VCP) of the XDS110 debug probe to a PC with a serial monitor running.
www.ti.com Hardware Description
2.1.2 LEDs
Two power indicator LEDs are included on the board: LED0 indicates when the 3.3 V is available on the
USB side of the isolation barrier and LED1 indicates when 3.3 V is available on the device side of the
isolation. LED1 indicates that there is power supplied to the F28004x device as well as the XDS110
debugger.
Two user LEDs are provided on the board: LED4 (red) and LED5 (green). These user LEDs are
connected to GPIO23 and GPIO34, respectively. These are connected to the SN74LVC2G07DBVR LED
driver IC and are connected in an active low configuration; that is, drive the GPIO low to turn on the LED
and high to turn it off. These LEDs are dedicated for use by the software application.
Two blue LEDs, LED2 and LED3, are connected to the XDS110 debug probe. These indicate debugger
activity and are not controllable by any application software.
2.1.3 Encoder Connectors

The F28004x LaunchPad includes two headers, J12 and J13, which are used for connecting linear or
rotary incremental encoders. These headers take 5 V signals that are down-converted to 3.3 V and wired
to the F280049C MCU. These signals are connected to the eQEP modules on the device. Each header
has the EQEPA, EQEPB, and EQEPI signals available for each eQEP module as well as pins for GND
and 5 V.
2.1.4 FSI
The F28004x MCU features the industry first Fast Serial Interface (FSI). The FSI enables robust high-
speed communications and is intended to increase the amount of information transmitted while reducing
the costs to communicate over an isolation barrier. Though no isolator is included on this LaunchPad, the
TXCLK, TXD0, TXD1, RXCLK, RXD0, and RXD1 signals are available on J11. This header is set up in
such a way that adding jumpers on the pins will connect the TX to RX channels for external loopback and
evaluation. Additionally, there are two GND signals on the connector that can be used for a wrapped-pair
connection to an external board with FSI. The GPIOs connected to this header are also routed to the
BoosterPack connectors through 0Ω resistors. As the FSI can toggle at up to 100 MHz rates, the longer
traces to the BoosterPack headers can create unintentional noise on the signal due to reflection.
Eliminating these extended traces by removing the in-circuit resistors will help to limit any noise or
reflections.
2.1.5 CAN
The F28004x LaunchPad includes a connector for a CAN network through J14. GPIO32 and GPIO33 are
routed from the F280049CPZS to J14 through the on-board CAN Transceiver. GPIO33 is also wired to the
FSI connector.
2.1.6 Boot Modes

The F280049C boot ROM contains bootloading software that executes every time the devices is powered
on or reset. Two pins, GPIO24 and GPIO32, are wired to the Boot Select switch (S2). Note that S2 is
placed upside down, so the OFF (open) position corresponds to a logic 1 and the ON (closed) position
corresponds to 0. By default, both pins are set to the OFF position so the device will boot from Flash. For
more information on the F28004x boot modes, see the TMS320F28004x Piccolo microcontrollers data
sheet.
Table 2. Boot Select Switch Settings

BOOT MODE GPIO32 (Position 1) GPIO24 (Position 2)
Boot from Parallel GPIO ON (0) ON (0)
Boot from SCI / Wait boot OFF (1) ON (0)
Boot from CAN ON (0) OFF (1)
Boot from Flash (default) OFF (1) OFF (1)
2.1.7 BoosterPack Headers
Figure 3. BoosterPack Pin Map
2.1.7.1 BoosterPack Sites

The F28004x LaunchPad features two fully independent BoosterPack XL connectors. BoosterPack site #1,
located above the F28004x MCU and below the XDS110 debugger, is compliant with the BoosterPack
standard with a few exceptions as noted in Figure 3. BoosterPack site #2, located under the F28004x
MCU, is compliant with the BoosterPack standard with a few exceptions as well, noted in Figure 3. To
expand the functions available to the user on this LaunchPad, some signals are also routed to alternate
locations on the board. These alternate routes can be selected by manipulating the onboard switches or
adding or removing 0 Ω resistors. This is described in Section 2.3.
The GPIO pin number as well as the BoosterPack compliant features are listed in Figure 3. Each GPIO
has multiple functions available through the GPIO mux. A few special functions have also been listed
above; the full GPIO mux table can be found in theTMS320F28004x Piccolo microcontrollers data sheet.
2.1.8 Analog Voltage Reference Header

The analog subsystem of the F28004x allows for flexible voltage reference sources. The ADC and DAC
modules are referenced to the VREFHIx and VREFLOx pin voltages. VREFHIx can either be driven
externally or can be generated by an internal bandgap voltage reference. An external voltage can be
supplied to header J15 as an external voltage source for VREFHIx. Note that there is no signal
conditioning circuitry in place for the voltage reference. For best performance, some additional circuitry
may be required.
2.1.9 Other Headers and Jumpers

The Piccolo LaunchPad has multiple jumpers to select different power sources for the board. This
LaunchPad also provides a way to isolate the connected USB from the device, allowing for safe operation
and debugging in high-voltage applications.
2.1.9.1 USB Isolation Block

JP1, JP2, and JP3 are provided to enable isolation between the device and the connected USB in high-
voltage applications. The area of isolation is defined by the white outline in the upper-left corner of the
LaunchPad. JP1 separates the GND of USB region and the MCU region of the LaunchPad. JP2 separates
3.3 V, and JP3 separates 5 V. By default, all three jumpers are shorted and the power is supplied by the
connected USB, meaning that the USB is NOT isolated from the MCU region. If power isolation is desired,
remove the supplied shunts from JP1, JP2, and JP3. In this configuration, a 3.3 V supply must be
connected to the MCU region to power the F280049C MCU and the other on-board circuitry, including the
XDS110 debug probe. Some applications may not require 5 V to be supplied to the MCU region. In an
isolated power application with JP3 removed, supplying 5 V to the MCU region is optional.
2.1.9.2 BoosterPack Site 2 Power Isolation

JP8 is included to isolate 3.3 V and 5 V from the BoosterPack 2 headers. This might be required if two
BoosterPacks are simultaneously connected to the LaunchPad and both provide power to the LaunchPad.
If this is the case, power can be isolated by removing the shunts on JP8 and there will be no contention
between the two BoosterPacks.
2.1.9.3 Alternate Power

Additional jumpers are provided outside of the BoosterPack connector for additional external power
connections for 3.3 V or 5 V. These can be used to supply an external board or for powering the
LaunchPad with an external supply. When using these connection points, ensure that no other power
supplies are connected.
JP4 and JP6 are provided as extra connection points for a 3.3 V supply to be connected to the
LaunchPad.
JP5 and JP7 are provided as extra connection points for a 5 V supply to be connected to the LaunchPad.
2.1.9.4 5 V Step-up Converter

JP9 isolates the output of the LMR2421 Simple Switcher step-up voltage regulator(U3) from the 5 V power
domain of the LaunchPad. This voltage regulator can step up 3.3 V to 5 V if no other 5 V supply is
connected. Do not place a shunt on J9 unless JP3 is open and no other 5 V supply is connected to the
LaunchPad.
2.1.10 PGA
The F28004x MCU features on-chip Programmable Gain Amplifiers (PGA) to amplify an input voltage for
increasing the dynamic range of the downstream ADC and CMPSS modules. The integrated PGA helps to
reduce the cost and design effort for many control applications that traditionally require external, stand-
alone amplifiers. On-chip integration ensures that the PGA is compatible with the downstream ADC and
CMPSS modules. Software selectable gain and filter settings make the PGA adaptable to various
performance needs. For more information on the PGAs, see the device-specific data sheet and TRM.
The F28004x LaunchPad was designed to optimize the routing of certain PGA signals to the BoosterPack
connectors. This design choice allows for the evaluation of the on-chip PGA, if desired. Three PGA
modules are routed each BoosterPack Connector. An RC filter can be placed on each of these signals to
provide additional filtering of the input signal. By default, 0 Ω series resistor and pads for a decoupling
capacitor are placed on each PGA input signal. These values can be modified based on application
requirements.
In addition to the PGA input signals, BoosterPack site 2 has the associated output filter signals routed.
Each output filter signal has two components: a 0 Ω series resistor and a decoupling capacitor. If the PGA
output filters are used, remove the 0 Ω series resistor to isolate it from the BoosterPack connector, and
place an appropriate filter capacitor. By default, a 330 pF capacitor is populated. An isolated ground plane
for the PGAs has been created to help limit outside noise coupling onto the PGA signals. By default, this
ground plane is shorted to the ground plane of the PCB through a resistor. If isolation between
PGAx_GND and the PCB ground is needed the resistor can be removed.
Wherever a PGA signal is brought to the BoosterPack connector, an ADC input is also provided.
Depending on the signal, the ADC is connected by either a short on the board or through on-chip
connections. Other than PGA4_IN and PGA6_IN, each PGA input signal can be isolated from the
connected ADC signal by removing the 0 Ω resistor that is part of the input RC filter.
Table 3 summarizes the available PGA signals and connections. For the full connection details, see Sheet
4 of the board schematic.
Table 3. PGA Signals and Associated Connections

BoosterPack Pin
PGA Signal ADC Input Signal Note
Site Position
J3.27 PGA1_IN ADCINB2 Populate RC filter if required
J3.28 PGA3_IN ADCINC0 Populate RC filter if required
1 J3.29 PGA5_IN ADCINA9 Populate RC filter if required
Connected to PCB GND by default. Remove R26 is
J1.2 PGA1/3/5_GND –
PGA_GND isolation is required
J7.29 (69) PGA2_IN ADCINA3 Populate RC filter if required
J5.6 (46) PGA2_OF ADCINA4 Remove R19 if PGA output filter is required
J7.27 (67) PGA4_IN ADCINC3 Populate RC filter if required
J5.5 (45) PGA4_OF ADCINB4 Remove R25 if PGA output filter is required
2
J7.28 (68) PGA6_IN ADCINC5 Populate RC filter if required
J5.8 (48) PGA6_OF ADCINA8 Remove R22 if PGA output filter is required
Connected to PCB GND by default. Remove R27 is
J5.2 (42) PGA2/4/6_GND –
PGA_GND isolation is required
2.2 Debug Interface
2.2.1 XDS110 Debug Probe

The F28004x LaunchPad includes an on-board XDS110 Debug Probe. The XDS110 allows for the
programming and debugging of the F280049C using Code Composer Studio™ or any other supported tool
chains. In the current configuration, the XDS110 is only wired to support 2-pin cJTAG mode. This uses
only the TMS and TCK JTAG pins and allows for TDI and TDO to be reallocated for application needs.
TDI and TDO are available on GPIO35 and GPIO37. Though these pins are not routed to the debug
probe, by default, they are available at the BoosterPack connector. GPIO35 and GPIO37 can also be
routed to J101 using a combination of S3 and S4. For the proper configuration, see Section 2.3.
2.2.2 XDS110 Output

The connector J102 is provided to debug an external target with the on-board XDS110 debug probe. This
connector allows the LaunchPad to be used as a stand-alone XDS110 debug probe. If the LaunchPad is
being used in this manner, ensure that all of the shunts are removed from J101. This isolates the JTAG
signals from going to the F280049C MCU.
2.2.3 Virtual COM Port

When plugged into a USB host, the XDS110 enumerates as both a debugger and a virtual COM port.
J101 allows the user to connect the SCI UART from the F280049C to the debug probe to be passed on to
the USB host. By default, SCIA maps to the virtual COM port of the XDS110 using GPIO28 and GPIO29.
Alternately, GPIO35 and GPIO37 can be used for SCIA. This is accomplished by manipulating S3, S4,
and S8. For the appropriate switch settings, see the Section 2.3.
2.3 Alternate Routing
2.3.1 Overview
The F280049C MCU is a very versatile device in a small package. To balance compatibility with
BoosterPack standards as well as showcasing the versatility of the F280049C, some complexity was
added to the design. Most features aligning with the BoosterPack standard are available by default. The
additional functions are selected using a switches, or static resistors which can be added or removed. This
section covers the alternate functions and how to enable them. Note that by enabling certain alternate
features, standard BoosterPack functionality may be lost. The switches are configured such that it is not
possible to connect multiple functions to the same header.
Table 4 is a master list of all of the possible functions controlled by the alternate routing switches:
Table 4. Alternate Function Switch Settings

Pins S3.1 S3.2 S4 S6 S8 S9 Function Note
x x x 0 0 x SCIA to virtual COM port Default configuration
GPIO28/GPIO29
x x x 1 x x SCIA to BoosterPack Site 2
1 x 1 x 1 x SCIA to virtual COM port
GPIO35/GPIO37 1 x 0 x x x I2C on BoosterPack Site 1 Default configuration
0 x 1 x x x QEP1 on J12
0 x x x x x QEP1 on J12
GPIO59
1 x x x x x GPIO on BoosterPack Site 1 Default configuration
GPIO14/GPIO15/ x 0 x x x x QEP2 on J13
GPIO26 x 1 x x x x GPIO on BoosterPack Site 2 Default configuration
GPIO32/GPIO33 x x x x x 0 CAN on J14
(2)
x x x x x 1 GPIO on BoosterPack Site 2 Default configuration
(1) Cells marked with 'x' indicate that the state of that switch has no impact on the function of that particular signal.
(2) GPIO33 is also connected to the FSIRXCLK pin on J11 through a 0 Ω resistor R46. If CAN functionality is required, ensure that
R46 is populated.
2.3.2 UART
This LaunchPad allows for one of two sets of pins to be used for the SCIA UART routed to the virtual
COM port of the XDS110. By default, GPIO28 and GPIO29 are routed to the virtual COM port and not
available on the BoosterPack connector. Alternately, GPIO35 and GPIO37 can be routed to the virtual
COM port.
When UART functionality is not needed at the virtual COM port, the GPIOs can be routed to the
BoosterPack connectors for BoosterPack standard functions.
2.3.3 eQEP
The LaunchPad has the ability to connect to two independent linear or rotary encoders through the
F28004x on-chip eQEP interfaces: Header J12 is connected to eQEP1 and header J13 is connected to
eQEP2. By default, this connection is not active and the GPIOs are routed to the BoosterPack connectors.
The eQEP signals are routed through TI SN74LV4053A Triple 2-Channel Analog
Multiplexer/Demultiplexer ICs (U8/U9) to select the functions. Once the eQEP signals have been selected
through U8/U9, the 3.3 V signals are stepped up through a TI TXB0106PWR Level Translator (U7) to 5 V
at the connectors.
2.3.3.1 EQEP1
GPIO35, GPIO37, and GPIO59 are routed to J12 through U9. By setting position 2 (LEFT) of S3 to 0
(DOWN), the eQEP signals are routed to J12. GPIO35 and GPIO37 also require that S4 is set to 1 (UP).
In addition to configuring the switches, ensure that the EQEP1 function is selected in the GPIO Mux.
Software Development www.ti.com
2.3.3.2 EQEP2
GPIO14. GPIO15, and GPIO26 are routed to J13 through U8. By setting position 1 (RIGHT) of S3 to 0
(DOWN), the eQEP signals are routed to J13. In addition to configuring the switches, ensure that the
EQEP2 function is selected in the GPIO Mux.
2.3.4 CAN
The LaunchPad can be connected to a CAN bus through J14. GPIO32 and GPIO33 are routed to the on-
board TI SN65HVD234 3.3 V CAN Transceiver, U10. By setting S9 to 0, GPIO32 and GPIO33 are routed
to the transceiver. If S9 is set to 1, the GPIOs are routed to the BoosterPack connectors. As GPIO33 is
also used by the FSI, ensure that R46 is populated with a 0-Ω resistor to connect GPIO33 to the CAN
transceiver.
2.3.5 FSI
One set of GPIOs with available FSI functionality is directly connected to both the BoosterPack connectors
as well as the FSI header, J11. To simplify the layout of the LaunchPad, 0-Ω resistors are placed on the
signal trace to remove the BoosterPack Connection from the circuit. The mapping between the GPIOs, the
resistors, and the FSI signal is listed in Table 5. R46 also connects GPIO33 to S9, which selects the route
to the BoosterPack connector or the CAN transceiver.
Table 5. FSI to BoosterPack Isolation Resistors

GPIO Resistor FSI Signal
GPIO25 R72 FSITXAD1
GPIO6 R44 FSITXAD0
GPIO7 R45 FSITXACLK
GPIO2 R71 FSIRXAD1
GPIO12 R47 FSIRXAD0
GPIO33 R46 FSIRXACLK
2.3.6 GPIO18/X2
The F280049C oscillator clock output signal, X2, is multiplexed with GPIO18. By default, the Launchpad
uses an on-board crystal oscillator, Y2, as the clock source for the on-chip Phase-Locked Loop (PLL) that
requires both X1 and X2 signals of the MCU. To balance the requirement of having cleanly routed
oscillator signals and bringing all possible GPIOs to the BoosterPack connectors, GPIO18/X2 can be
routed to the BoosterPack connectors through a 0 Ω resistor. If GPIO18 is needed at the BoosterPack
connector, the on-chip zero-pin oscillators must be used as the clock source for the on-chip PLL. For more
information on the X1/X2 configurations, see the device-specific data sheet.
If GPIO18 functionality is needed at the BoosterPack Connector:
1. Remove R31 to separate GPIO18 from Y2.
2. Populate R28 to connect GPIO18 to the BoosterPack connector.
3. Populate R35 to connect X1 to Ground.
3 Software Development
This section provides general information about software development, as well as instructions for
programming the LaunchPad.
3.1 Software Description

C2000Ware includes a set of example applications that use the C2000Ware Peripheral Driver Library.
These applications demonstrate the capabilities of the F28004x series MCU, as well as provide a starting
point for the development of the final application for use on the F28004x LaunchPad development board.
Example applications are also provided for the F28004x LaunchPad when paired with selected
BoosterPacks.
www.ti.com Software Development
3.2 Source Code

The complete source code including the source code installation instructions are provided at
http://www.ti.com/tool/c2000ware. The source code and binary files are installed in the C2000Ware
software tree.
3.3 Tool Options

The source code installation includes directories containing projects, makefiles, and binaries for Texas
Instruments' Code Composer Studio IDE.
Download evaluation versions of these tools from the Tools & Software section of www.ti.com/c2000. CCS
provides the application debug environment for developing, programming, and debugging code on the
C2000 family of microcontrollers.
3.4 Programming the F28004x LaunchPad

The F28004x LaunchPad software package includes pre-built binaries for each of the example
applications. If you installed the C2000Ware software to the default installation path of
C:\ti\c2000\C2000Ware_<version>, you can find the example applications in
C:\ti\c2000\C2000Ware_<version>\examples. The on-board XDS110 is used with the On-Chip Flash
Programmer tool to program applications on the F28004x LaunchPad.
Follow these steps to program example applications into the F28004x LaunchPad development kit using
the on-board XDS110 debug probe:
1. Install CCS on a PC running Microsoft Windows.
2. Connect the USB-A cable plug in to an available USB port on the PC and plug the Micro-B plug to the
port (USB101) on the F28004x LaunchPad.
3. Verify that LED0, at the top of the board is illuminated indicating USB power as well as LED1, which
indicates the target and debugger are powered.
4. Install Windows XDS110 and Virtual COM Port drivers if prompted. Installation instructions can be
found at http://processors.wiki.ti.com/index.php/XDS110.
5. Run CCS on the PC.
6. Launch the Target Configuration included in the project. Ensure that the Target Configuration
configured to use the 2-pin cJTAG advanced configuration.
7. Click Load Program and select the program to load.
Board Design www.ti.com
4 Board Design
4.1 Schematic
This section contains the complete schematics for the F28004x LaunchPad, as shown in Figure 4 to Figure 11.
The source files for the schematic are provided inC2000Ware_<version>\boards\LaunchPads\LAUNCHXL_F280049C\A\design files
microUSB XDS110 cJTAG SCIA
Power
Management LEDs
BoosterPack
F280049CPZ Connector 1
BoosterPack
FSI TX/RX Connector 2
Connector
CAN Connector EQEP Connectors
Figure 4. MCU025B_Block_Diagram.SchDoc
www.ti.com Board Design
+3V3 J1 J3 +5V0 J4 J2
1 +3.3V +5V 21 GPIO10 40 PWM/GPIO ! GND 20

PGA135_GND 2 Analog_In GND 22 GPIO11 39 PWM/GPIO ! PWM/GPIO ! 19 GPIO57
GPIO13 3 LP_UART_RX Analog_In 23 ADCINA5 GPIO8 38 PWM/GPIO ! GPIO ! 18
GPIO40 4 LP_UART_TX Analog_In 24 ADCINB0 GPIO9 37 PWM/GPIO ! GPIO 17
5 GPIO ! Analog_In 25 ADCINC2 GPIO4 36 Timer_Cap/GPIO ! RST 16 XRSn
ADCINB3 6 Analog In Analog_In 26 ADCINB1 GPIO5 35 Timer_Cap/GPIO ! SPI_MOSI 15 GPIO16
GPIO56 7 SPI_CLK Analog_In/I2S_WS 27 ADCINB2_P1I GPIO58 34 GPIO ! SPI_MISO 14 GPIO17
ADCINC4 8 GPIO ! Analog_In/I2S_SCLK 28 ADCINC0_P3I GPIO30 33 GPIO ! SPI_CS/GPIO ! 13 GPIO39
GPIO37_BP 9 I2C_SCL Analog_Out/I2S_SDout 29 ADCINA9_P5I GPIO18_BP 32 GPIO ! SPI_CS/GPIO ! 12 GPIO23
GPIO35_BP 10 I2C_SDA Analog_Out/I2S_SDin 30 ADCINA1 GPIO25_BP 31 GPIO ! GPIO ! 11 GPIO59_BP
GND GND
Booste rPack Headers Site 1 (Top)
J5 - J8 are labeled on the PCB. The

Pin numbers listed on these +3V3 +5V0
schematic components should be
offset by 40. i.e. pin 1 on J5 is labeled JP8
as pin 40 on the PCB. 1 2
3 4
J5 J7 J8 J6
1 +3.3V +5V 21 GPIO0 40 PWM/GPIO ! GND 20

PGA246_GND 2 Analog_In GND 22 GPIO1 39 PWM/GPIO ! PWM/GPIO ! 19 GPIO27
GPIO28_BP 3 LP_UART_RX Analog_In 23 ADCINA6 GPIO6_BP 38 PWM/GPIO ! GPIO ! 18
GPIO29_BP 4 LP_UART_TX Analog_In 24 ADCINA2 GPIO7_BP 37 PWM/GPIO ! GPIO 17
ADCINB4_P4OF 5 GPIO ! Analog_In 25 ADCINC14 GPIO2_BP 36 Timer_Cap/GPIO ! RST 16 XRSn
ADCINA4_P2OF 6 Analog In Analog_In 26 ADCINC1 GPIO3 35 Timer_Cap/GPIO ! SPI_MOSI 15 GPIO24
GPIO22 7 SPI_CLK Analog_In/I2S_WS 27 ADCINC3_P4I GPIO26_BP 34 GPIO ! SPI_MISO 14 GPIO31
ADCINA8_P6OF 8 GPIO ! Analog_In/I2S_SCLK 28 ADCINC5_P6I GPIO15_BP 33 GPIO ! SPI_CS/GPIO ! 13 GPIO33_BP
9 I2C_SCL Analog_Out/I2S_SDout 29 ADCINA3_P2I GPIO14_BP 32 GPIO ! SPI_CS/GPIO ! 12 GPIO34
10 I2C_SDA Analog_Out/I2S_SDin 30 ADCINA0 GPIO32_BP 31 GPIO ! GPIO ! 11 GPIO12_BP
GND GND
Booste rPack Headers Site 2 (Bottom)
EQEP Connect ors

+5V0 +5V0
+5V0 +5V0 CAN Connect or
+3V3
+3V3
FSI Connect or
R48 R49 R50 R51 R52 R53 R54
1.00k 1.00k 1.00k 1.00k 1.00k 1.00k U10 10.0k
J12 1% 1% 1% J13 1% 1% 1% J11 GPIO32_CANTX
1 EQEP1A 1 EQEP2A GPIO33_FSIRXCLK 1 2 GPIO7_FSITXCLK 1 D CANH 7 J14
2 EQEP1B 2 EQEP2B 3 4 4 6 R55 1
R CANL
3 EQEP1I 3 EQEP2I GPIO12_FSIRXD0 5 6 GPIO6_FSITXD0 GPIO33_CANRX 120 2
4 4 GPIO2_FSIRXD1 7 8 GPIO25_FSITXD1 8 RS EN 5 3
5 5 9 10
C43 C44 C45 C46 C47 C48 +3V3 GND 3 2
VCC GND
1000pF 1000pF 1000pF 1000pF 1000pF 1000pF
R56 SN65HVD234DR
GND 10.0k C49
0.1uF
GND GND GND
GND GND
GND GND GND
Figure 5. MCU025B_Connectors.SchDoc
User LEDs +3V3 +3V3 Oscillator Route cleanly and place near U1
GPIO18_X2
+3V3 Boot Mode Select GPIO18_BP R28
+3V3
DNP
0 X1 Reset Button +3V3
R29 R30
680 680 R31
0 R32
R33 R34 1 2 2.2k
R36 R37 56k 56k Selected Boot Mode Chart R35
DNP
1
10M 10M LED4 LED5 0 3 4 XRSn
1
3
S2 placed upside-down (so UP is open (1), DOWN is closed (0))
GPIO24
S1
Red Green GPIO32 Y2 GND C37
Mode # GPIO24 GPIO32 Boot Mode
2
0.1uF
C38 C39
G
G
2
1
00 0 0 Boot from Parallel GPIO 15pF 15pF
U6
R38
2
4
GPIO23 1 1A 1Y 6 +3V3
01 0 1 Boot from SCI / Wait Mode
0 S2 GND GND
2 GND VCC 5
02 1 0 Boot from CAN
3
4
GPIO34 R39 3 4 GND GND GND
2A 2Y 03 1 1 Boot from Flash
0 C40
SN74LVC2G07DBVR 0.1uF
By default:
R40 R41 - Crystal Y2 is connected between X1 and X2.
GND 2.2k 2.2k - GPIO18_BP is not connected to the BoosterPack EQEP Level Shifter
GND header.
+3V3 +5V0
If GPIO18 is needed at the Boosterpack Headers: C41 C42
- Remove R35
- Place 0ohm resistors on both R31 and R28 U7
0.1uF 0.1uF
GND 2 VCCA VCCB 15
GND GND
GPIO35_Q1A 1 A1 B1 16 EQEP1A
GPIO37_Q1B 3 A2 B2 14 EQEP1B
GPIO59_Q1I 4 A3 B3 13 EQEP1I
GPIO14_Q2A 5 A4 B4 12 EQEP2A
GPIO15_Q2B 6 A5 B5 11 EQEP2B
+3V3 GPIO26_Q2I 7 A6 B6 10 EQEP2I
R42 8 9
OE GND
2.2k
R43 TXB0106PWR
DNP
0
GND
To disable the Level Shifter:

1. De-populate R42
GND 2. Place a 0-ohm resistor on R43 to ground OE
UART Routing
EQEP Routing
GPIO37_ALT 1 4 GPIO35_ALT FSI and CAN Routing
+3V3
U8 GPIO37 2 5 GPIO35 GPIO33_FSIRXCLK R46 GPIO33_ALT GPIO7_FSITXCLK R45 GPIO7_BP
0 0
16 VCC 1Y0 12 GPIO14_Q2A GPIO37_BP 3 6 GPIO35_BP
1Y1 13 GPIO14_BP
QEP2_SEL 11 A
10 2 GPIO15_Q2B S4 GPIO12_FSIRXD0 R47 GPIO12_BP GPIO6_FSITXD0 R44 GPIO6_BP
B 2Y0
9 C 2Y1 1 GPIO15_BP 0 0
6 INH 3Y0 5 GPIO26_Q2I +3V3
3Y1 3 GPIO26_BP GPIO28_BP 1 4 GPIO29_BP
GPIO14 14 GPIO2_FSIRXD1 R71 GPIO2_BP GPIO25_FSITXD1 R72 GPIO25_BP
1-COM
GPIO15 15 2-COM GND 7 GPIO28 2 5 GPIO29 0 0
GPIO26 4 8 BP 6 3 BP
3-COM GND
GPIO28_SCIRX 3 6 GPIO29_SCITX
QEP1_SEL 5 2 QEP2_SEL
SN74LV4053ATPWRQ1 If needed, depopulate the resistors to isolate the BP headers
4 1 S6 from the FSI Headers. By default all are connected.
GND GND J12 J13
S3 FSI routing will be as clean as possible to FSI header. BP
+3V3 resistors will be branches with short stubs off of main branch to
U9 GPIO37_SCITX 1 4 GPIO35_SCIRX reduce noise on high speed lines
16 VCC 1Y0 12 GPIO35_Q1A GND TXD_TO_XDS 2 5 RXD_FROM_XDS

1Y1 13 GPIO35_SCIRX
QEP1_SEL 11 A
S3 (1, UP): QEP signals are routed to the BoosterPack GPIO29_SCITX 3 6 GPIO28_SCIRX
10 2 GPIO37_Q1B Headers (default) GPIO33_CANRX 1 4 GPIO32_CANTX
B 2Y0
9 1 GPIO37_SCITX S3 (0, DOWN): QEP signals are routed to the QEP If CAN functionality is desired, ensure
C 2Y1
Headers S8 GPIO33_ALT 2 5 GPIO32 that R46 is populated with a 0-ohm
6 5 GPIO59_Q1I resistor.
INH 3Y0
3Y1 3 GPIO59_BP S8 is placed upside-down so the 0 position is 'up' GPIO33_BP 3 6 GPIO32_BP
GPIO35_ALT 14 towards the debug probe
1-COM
GPIO37_ALT 15 2-COM GND 7
GPIO59 4 3-COM GND 8 S9
SN74LV4053ATPWRQ1
GND GND
Figure 6. MCU025B_AltRouting_Misc.SchDoc
Place near U1
+3V3
GND
C9 C10 C11 C12 C13 C14 R10 +3V3
VDD 10uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF 2.2k
R11
DNP
U1E 0
4 VDD VSS 5 U1D
46 VDD VSS 45
71 72 TCK 60 73 VREGENZ R12
VDD VSS TCK VREGENZ
+3V3 VDDA 87 VDD VSS 86 0
TMS 62 TMS FLT1 49
L2 11 12
VDDA VSSA
60 ohm 34 VDDA VSSA 33 XRSn 2 XRS FLT2 48
GND
3 VDDIO
X1 69 X1
C15 C16 C17 C18 47 VDDIO
2.2uF 2.2uF 2.2uF 2.2uF 70 VDDIO
+3V3 VDDIO 88 VDDIO
F280049CPZS
L3 80 82
VDDIO_SW VSS_SW
GND 220 ohm
GND F280049CPZS
C19 C20 C21 C22 C23 C24 C25
Place near U1 10uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF GND
GND
GND
Place near U1
U1B
GPIO32 64 GPIO32
GPIO33_FSIRXCLK 53 GPIO33
GPIO34 94 DNPC26 DNPC27 DNPC28 DNPC29 DNPC30 DNPC31
GPIO34
GPIO35 63 A 0ohm series resistor has been placed GND 330pF 330pF 330pF 330pF 330pF 330pF
GPIO35/TDI
GPIO37 61 on each DAC out pin. If there is not
GPIO37/TDO
GPIO39 91 enough output resistance for the DAC,
GPIO39
GPIO40 85 replace the 0ohm resistor with an
GPIO40
GPIO56 65 appropriate value
GPIO56
GPIO57 66 GPIO57
GPIO58 67 GPIO58
U1C
GPIO59 92 GPIO59
ADCINA0 R13 0 23 A0/B15/C15/DACA_OUT PGA1_IN 18 R14 0 ADCINB2_P1I
ADCINA1 R15 0 22 A1/DACB_OUT PGA2_IN 30 R16 0 ADCINA3_P2I
F280049CPZS ADCINA2 9 A2/B6/PGA1_OF PGA3_IN 20 R17 0 ADCINC0_P3I
ADCINA3_P2I 10 A3 C3/PGA4_IN 31 R18 0 ADCINC3_P4I
ADCINA4_P2OF R19 36 A4/B8/PGA2_OF PGA5_IN 16 R20 0 ADCINA9_P5I
0 ADCINA5 35 A5 C5/PGA6_IN 28 R21 0 ADCINC5_P6I
U1A ADCINA6 6 A6/PGA5_OF PGA7_IN 43
ADCINA8_P6OF R22 37 A8/PGA6_OF
GPIO0 79 GPIO00 0 ADCINA9_P5I 38 A9
GPIO1 78 GPIO01
GPIO2_FSIRXD1 77 14 R23 PGA135_GND
GPIO02 PGA1_GND
GPIO3 76 GPIO03 ADCINB0 41 B0 PGA3_GND 15 0
GPIO4 75 GPIO04 ADCINB1 40 B1/A10/C10/PGA7_OF PGA5_GND 13
GPIO5 89 ADCINB2_P1I 7 32 R24 PGA246_GND
GPIO05 B2/C6/PGA3_OF PGA2_GND/PGA4_GND/PGA6_GND
GPIO6_FSITXD0 97 GPIO06 ADCINB3 8 B3/VDAC PGA7_GND 42 0
GPIO7_FSITXCLK 84 GPIO07 ADCINB4_P4OF R25 39 B4/C8/PGA4_OF
GPIO8 74 GPIO08 0
GPIO9 90 25 R26 R27
GPIO09 VREFHIA
GPIO10 93 ADCINC0_P3I 19 24 0 0
GPIO10 C0 VREFHIB/VREFHIC
GPIO11 52 GPIO11 ADCINC1 29 C1
GPIO12_FSIRXD0 51 GPIO12 ADCINC2 21 C2
GPIO13 50 GPIO13 ADCINC4 17 C4 VREFLOA 27
GPIO14 96 GPIO14 ADCINC14 44 C14 VREFLOB/VREFLOC 26
GPIO15 95 GPIO15
GND J15
GPIO16 54 GPIO16
GPIO17 55 GPIO17
F280049CPZS
GPIO18_X2 68 C32 C33 C34
GPIO18_X2
GPIO22 83 330pF 330pF 330pF When using PGA output filters:
GPIO22_SW
GPIO23 81 - Remove the Resistors
GPIO23_SW
GPIO24 56 - Place Capacitors required for PGA
GPIO24
GPIO25_FSITXD1 57 filtering
GPIO25
GPIO26 58 C35 C36
GPIO26
GPIO27 59 GND When not using PGA output filters: 2.2uF 2.2uF
GPIO27
GPIO28 1 - Place 0ohm Resistors
GPIO28
GPIO29 100 - Default capacitor values allow for
GPIO29
GPIO30 98 reasonable ACQPS
GPIO30
GPIO31 99 GPIO31
GND
F280049CPZS
Figure 7. MCU025B_F280049C_Device.SchDoc
XDS110 Side Target Side
+3V3
R57
3.3k
XDS_TXD
XDS_RXD J101
1 2 RXD_FROM_XDS
XDS_RESET_OUT 3 4 TXD_TO_XDS
XDS_TMS_SWDIO 5 6 TMS
XDS_TCK_SWDCLK 7 8 TCK
XDS_TDO_SWO
XDS_TDI
To debug the F280049C, ensure that the jumpers on J101

are connected to pass the TMS and TCK signals to the
+3V3 J102
1 2 MCU. RXD and TXD are optional. These are for Channel
3 4 B of the Debugger to enable a serial interface to the
5 6
7 8 connected PC.
9 10
If debugging an external target, remove the jumpers from

GND J101 and connect the external target to J102.
U12
1 IO1 IO4 5
2 IO2 IO5 6
3 IO3 IO6 7
8 VCC GND 4
TPD6E004RSER
GND
Figure 8. MCU025B_XDS110_Target_Interface.SchDoc
USB & XDS Power Isolation Boundary +3V3

8 U3
7
6 USB_VBUS 1 16
VBUS1 VBUS2
5
L100 3 14
GND VDD1 VDD2
742792620
4 USB_ID C105 C106 4 13 C1 C2
ID PDEN SPD
0.1uF 0.1uF 0.1uF 0.1uF
D+ 3 USB_DP USB_GND 5 SPU PIN 12
D- 2 USB_DM USB_DM R103 24.3 6 UD- DD- 11 R1 24.3 XDS_DM

USB101
1
L101 USB_VBUS USB_GND USB_DP R104 24.3 7 10 R2 24.3 XDS_DP GND
VBUS UD+ DD+
742792620
C100 2 9
GND1 GND2
2.2uF 8 15
GND1 GND2
11
10
9
USB_GND
U100 USB_GND GND
1 IO1 IO3 4 USB_DP

USB_ID 2 IO2 IO4 5 USB_DM
C101 R100 +5V0 +3V3
3300pF 1.00M USB_VBUS 6 3 USB_VBUS
VCC GND
TPD4E004DRYR
R3
USB_GND USB_GND 680
JP3
+3V3
U101 USB_VCC
2
1 IN OUT 3 USB_VCC LED1
2 IN OUT 4
R101 C102 C103
8 5 51k 15pF 2.2uF Red
EN
1
FB
NC 7 JP2
R105
GND R102 USB_GND 680
TPS79601DRBR 30.0k GND
1
2
6
2
LED0
USB_GND USB_GND JP1 GND
USB_GND Red
1
C104
USB_GND
0.01uF
USB_GND GND
3.3V to 5V Boost System Supervisory Circuit

XRSn
+3V3 +3V3 +3V3 +5V0
L1 JP4 JP5
1 1
+3V3 +3V3 2 2
3.3uH R4 3 3 VDD
U4 2.2k
U5 +5V0 TP1
D1 5 1 R5 R6 VDDIO
VDD OUTA
5 1 0 2.2k GND GND
VIN SW
TP2
1N5819HW-7-F R7 C3 3 6 VDDA
R8 SENSE OUTB
4 30.1k 820pF +3V3 +5V0
EN
10k FB 3 JP6 JP7 TP3
C4 JP9 4 2 1 1 +3V3
SET GND
2 10uF 2 2
GND
R9 3 3 TP4
C5 10k C6 TPS3702CX33DDCR C7 C8 +5V0
4.7uF LMR62421XMFX/NOPB 0.1uF 0.01uF 0.01uF
TP5
GND GND
If +5V0 is supplied from elsewhere,
disconnect this jumper to prevent GND GND GND
contention GND TP6
GND GND
+5V0 is always connected to the GND
XDS110.
Figure 9. MCU025B_XDS110_USB_Power.SchDoc
U2A +3V3 U2B
XDS_RXD 33 PA0 81 PL0

XDS_TXD 34 PA1 PK0 18 82 PL1
XDS_TCK_SWDCLK 35 19 R58 R59 R60 R61 83
PA2 PK1 PL2
XDS_TMS_SWDIO 36 20 1.0k 1.0k 1.0k 1.0k 84
PA3 PK2 PL3
XDS_TDO_SWO 37 PA4 PK3 21 85 PL4
XDS_TDI 38 PA5 PK4 63 DEBUG_ID4 86 PL5
+5V0 XDS_RESET_OUT 40 PA6 PK5 62 DEBUG_ID5 XDS_DP 94 PL6 PQ0 5
41 PA7 PK6 61 DEBUG_ID6 XDS_DM 93 PL7 PQ1 6
R62 60 DEBUG_ID7 11
PK7 PQ2
100 95 PB0 78 PM0 PQ3 27
96 PB1 PJ0 116 77 PM1 PQ4 102
C50 91 117 76
PB2 PJ1 PM2
0.01uF 92 75 118
PB3 PM3 PP0
121 PB4 PH0 29 74 PM4 PP1 119
120 PB5 PH1 30 73 PM5 PP2 103
GND PH2 31 72 PM6 PP3 104
ITCK 100 PC0/TCK/SWCLK PH3 32 71 PM7 PP4 105
ITMS 99 PC1/TMS/SWDIO PP5 106
ITDI 98 PC2/TDI PG0 49 107 PN0
J10 ITDO 97 50 108
PC3/TDO/SWO PG1 PN1
+3V3 25 PC4 109 PN2
1 10 24 PC5 PF0 42 110 PN3
2 9 23 PC6 PF1 43 111 PN4
3 DNP 8 22 44 112
PC7 PF2 PN5
4 7 PF3 45
5 6 1 PD0 PF4 46 MSP432E401YTPDT
2 PD1
3 PD2 PE0 15
4 PD3 PE1 14
125 PD4 PE2 13
GND GND 126 PD5 PE3 12
127 PD6 PE4 123
R63 R64 128 124
PD7 PE5
470 470
MSP432E401YTPDT
1
LED2 LED3
Blue Blue
2
U2D
+3V3
GND GND 7 VDD
16 VDD
26 VDD GND 17
C51 C52 C53 C54 C55 C56 28 48
VDD GND
0.01uF 0.01uF 0.01uF 0.1uF 0.1uF 1uF 39 55
VDD GND
+3V3 47 VDD GND 58
U2C 51 VDD GND 80
52 VDD GND 114
R65 64 65 69
WAKE HIB VDD
10k GND 79 10
R66 VDD GNDA
70 RST RBIAS 59 90 VDD
100 101 VDD
R67 R68 +3V3 113
DNP VDD
10k 53 4.87k 122
EN0RXIN VDD
GND
54 C57 C58 8
EN0RXIP VDDA
66 1uF 0.01uF
XOSC0
GND GND GND 87 VDDC
XOSC1 67 115 VDDC
56 EN0TXON
GND
GND C59 C60 C61 9 VREFA+
57 Y1 2.2uF 0.1uF 1uF
EN0TXOP
OSC0 88 1 2 68 VBAT
G
3 4
G
OSC1 89
GND MSP432E401YTPDT
C62
MSP432E401YTPDT C63 12pF +3V3
12pF R70
GND 51
GND
GND
C66
0.1uF
GND
Figure 10. MCU025B_XDS110_MCU.SchDoc
DNP DNP DNP MH1 MH2
FID1 FID2 FID3
DNP DNP DNP

MH3 MH4
FID4 FID5 FID6
Logo1
PCB Number: MCU025 PCB
PCB Rev: B LOGO
Texas Instruments CE Logo1 Logo4
PCB
LOGO
Logo3 Logo2 INSTASPIN_FOC_LOGO
PCB PCB
H1 LOGO LOGO
MECH FCC disclaimer WEEE logo
AK67421-0.3
M1 M2 M3 M4 M5 M6 M7 M8 M9
ZZ2
Assembly Note
These assemblies are ESD sensitive, ESD precautions shall be observed.
ZZ3
Assembly Note
These assemblies must be clean and free from flux and all contaminants. Use of no clean flux is not acceptable.
ZZ4
Assembly Note
These assemblies must comply with workmanship standards IPC-A-610 Class 2, unless otherwise specified.
Figure 11. MCU025B_Hardware.SchDoc
4.2 Layout
The layout source files for the LAUNCHXL-F280049C are provided in
C2000Ware_<version>\boards\LaunchPads\LAUNCHXL_F280049C\MCU025\design files. The F28004x
LaunchPad was created using Altium Designer 17. The gerber files are also provided in the same
directory.
4.3 BOM
The BOM for the LAUNCHXL-F280049C is provided in
C2000Ware_<version>\boards\LaunchPads\LAUNCHXL_F280049C\MCU025.
4.4 LAUNCHXL-F280049C Board Dimensions

Figure 12 is a dimensional drawing of the F28004x LaunchPad that shows the location of selected
features of the board as well as the component locations.
Figure 12. F28004x LaunchPad Dimensions and Component Locations
www.ti.com References
5 References
5.1 Reference Documents

In addition to this document, the following references are available for download at www.ti.com.
• TMS320F280049C Piccolo™ Microcontrollers
• TMS320F28004x Piccolo™ Microcontrollers Data Sheet
• TMS320F28004x Piccolo™ Microcontrollers Technical Reference Manual
• TMS320C48004x Piccolo™ Microcontrollers Silicon Errata
• LAUNCHXL-F280049C LaunchPad Quick Start Guide
• C2000Ware for C2000 MCUs
• C2000Ware Quick Start Guide
• Texas Instruments Code Composer Studio
• Texas Instruments LaunchPad Development Environment
5.2 Other TI Components Used in This Design

This LaunchPad uses various other TI components for its functions. A consolidated list of these
components with links to their TI product pages is shown below.
• TM4C129ENCPDT IoT Enabled High Performance 32-Bit Arm® Cortex®-M4F
• LM4040 Precision Micropower Shunt Voltage Reference
• LMR62421 Simple Switcher 2.7 V to 5.5 V, 2.1 A Step-Up Regulator
• SN65HVD234 3.3 V CAN Transceiver
• SN74LV4053A Triple 2-Channel Analog Multiplexer/Demultiplexer IC
• SN74LVC2G07 Dual Buffer/Driver With Open-Drain Output
• TPD4E004 4-Channel ESD Protection Array for High-Speed Data Interfaces
• TPD6E004 Low-Capacitance 6-Channel +/-15 kV ESD Protection Array for High-Speed Data Interfaces
• TPS3702 High-Accuracy, Fixed-Threshold OV/UV Monitor
• TPS796 Ultralow-Noise, High PSRR, Fast, RF, 1-A Low-Dropout Linear Regulator
• TXB0106PWR 6-Bit Bidirectional Voltage-Level Translator
Appendix A
SPRUII7B – June 2018 – Revised April 2020
A.1 Frequently Asked Questions

1. Can other programming and debug tools (such as an XDS200 debug probe) be used with the F28004x
LaunchPad?
The F28004x LaunchPad utilizes an on-board XDS110 debug probe in a 2-pin cJTAG
configuration. cJTAG only uses the TMS and TCK pins of the debug probe. TDI and TDO are
present on the BoosterPack connectors and can be connected to a debug probe through jumper
wires, if necessary.
2. What versions of Code Composer Studio can be used to develop software for the F28004x
LaunchPad?
The on-board XDS110 debug probe is compatible with Code Composer Studio development
environment version 6.1.0 and later.
3. Why can't I connect to the LaunchPad in Code Composer Studio?
a. Are shunts present on J101 for TCK and TMS?
b. Is the XDS110 and the F280049C MCU powered? Is LED1 illuminated?
If JP1, JP2, and JP3 are disconnected, the power provided through the USB is isolated from
the rest of the board. Ensure that 3.3 V is supplied to any of the available connectors on the
target side of the isolation.
c. Is the micro-USB connected to the PCB and is the USB region receiving power? Is LED0
illuminated?
The USB region must be powered with the 5 V from the USB cable. LED0 will illuminate when
the 5V is stepped down to 3.3 V for the USB isolation chip to operate and pass the signals
across the isolation barrier.
d. Ensure that the target configuration is set up to use cJTAG in 2-pin advanced mode.
Open the Target Configuration file (.ccxml) in Code Composer Studio. Click on the Advanced
tab and select cJTAG (1149.7) 2-pin advanced modes from the drop-down labeled
JTAG/SWD/cJTAG Mode. Leave the Target Scan Format as OSCAN2 format.
Alternately, a working Target configuration file is included in the launcxl_ex1_f280049c_demo
project "TMS320F280049C_LaunchPad.ccxml". You can use this without modifications.
24 SPRUII7B – June 2018 – Revised April 2020

www.ti.com Frequently Asked Questions
Figure 13. Target Configuration Advanced Options
Figure 14. Target Configuration included in the demo project
SPRUII7B – June 2018 – Revised April 2020 25

Frequently Asked Questions www.ti.com
4. Is XDS110 firmware version 2.3.0.16 installed? This is contained in Emulation Package 8.0.903.4. If
so, this version of the XDS110 firmware breaks the cJTAG connection. To confirm which XDS110
firmware is used, and update the firmware, follow these steps:
a. Verify current XDS110 firmware version by connecting the LaunchPad to the PC through the USB
cable and executing "xdsdfu -e" in the command prompt.
If the current version is not v2.3.0.16, move on to other methods to resolve the connection
issues. Else, continue this procedure
b. Install the Emulation Package 8.1.0.00005 which contains the previous XDS110 v2.3.0.17 firmware
using the instructions found HERE. Alternatively, you can install the older Emulation Package
8.0.803.0 which contains XDS firmware version 2.3.0.15.
c. In a command prompt, navigate to the emulation driver within your CCS installation and execute
the following commands. e.g. C:\ti\ccsv8\ccs_base\common\uscif\xds110\
• xdsdfu -m
• xdsdfu -f firmware.bin -r
d. Power cycle the LaunchPad.
e. Verify new XDS110 firmware version by again executing "xdsdfu -e" in the command prompt.
Ensure that v2.3.0.16 is not installed.
NOTE: Prior to XDS110 version 2.3.0.14, the cJTAG connection with the F28004x MCU was not
working. Ensure that version 2.3.0.14 or newer, with the exception of firmware version
2.3.0.16, is running on the XDS110. Any older versions of the XDS110 firmware will not
operate as expected.
5. Why is the serial connection not working?

a. Are shunts present on J101 for TXD and RXD?
b. Are you using the correct COM port?
Right click on My Computer and select Properties. Navigate to the Hardware tab in the dialog
box and open the device manager. Scroll to Ports (COM & LPT) and expand this entry. Is
XDS110 Class Application/User UART listed? If so, read the COM number to the right of the
entry; this is the COM number you should be using.
c. Are you using the correct baud rate?
Most, if not all, of the examples are configured for a baud rate of 115200 when the CPU is
running at 100 MHz. If you have changed the PLL settings or developed your own code you
may have to recalculate the baud rate for your specific application. For information on how to
do this, see theTMS320F28004x Piccolo™ Microcontrollers Technical Reference Manual.
d. Does the UART channel wired to the debug probe match the UART channel configured in your
software?
The F28004x LaunchPad provides an option for one of two possible UART channels to be
routed to the debug probe through J101. Ensure that S3, S4, S6, and S8 are configured to the
appropriate UART channel for your application. ,For more information about the Alternate
Routing possibilities, see Section 2.3.
26 SPRUII7B – June 2018 – Revised April 2020

www.ti.com Revision History
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from A Revision (March 2019) to B Revision .................................................................................................. Page
• Updated Figure 1. ......................................................................................................................... 1

• Added new Section 1.7.2. ................................................................................................................ 5
• Updated Section 2.1.4. ................................................................................................................... 7
• Updated Figure 3. ......................................................................................................................... 8
• Updated Section 2.1.7.1. ................................................................................................................. 8
• Updated Section 2.3.5. .................................................................................................................. 12
• Updated Section 4.1. .................................................................................................................... 14
SPRUII7B – June 2018 – Revised April 2020 Revision History 27

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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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C2000™ Piccolo™ F28004X Series Launchpad™ Development Kit: User'S Guide

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C2000™ Piccolo™ F28004X Series Launchpad™ Development Kit: User'S Guide

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User's Guide

SPRUII7B – June 2018 – Revised April 2020

C2000™ Piccolo™ F28004x Series LaunchPad™

Figure 1. Piccolo F28004x Series LaunchPad Development Kit

1.1 Kit Contents

Table 1. LAUNCHXL-F280049C Specifications

1.4 Using the F28004x LaunchPad

1.7 Hardware Revisions

Figure 2. Piccolo F28004x LaunchPad Development Kit Block Diagram

2.1 Functional Description and Connections

2.1.3 Encoder Connectors

2.1.6 Boot Modes

Table 2. Boot Select Switch Settings

2.1.7 BoosterPack Headers

Figure 3. BoosterPack Pin Map

2.1.7.1 BoosterPack Sites

2.1.8 Analog Voltage Reference Header

2.1.9 Other Headers and Jumpers

2.1.9.1 USB Isolation Block

2.1.9.2 BoosterPack Site 2 Power Isolation

2.1.9.3 Alternate Power

2.1.9.4 5 V Step-up Converter

Table 3. PGA Signals and Associated Connections

2.2 Debug Interface

2.2.1 XDS110 Debug Probe

2.2.2 XDS110 Output

2.2.3 Virtual COM Port

2.3 Alternate Routing

Table 4. Alternate Function Switch Settings

Table 5. FSI to BoosterPack Isolation Resistors

3.1 Software Description

3.2 Source Code

3.3 Tool Options

3.4 Programming the F28004x LaunchPad

microUSB XDS110 cJTAG SCIA

CAN Connector EQEP Connectors

1 +3.3V +5V 21 GPIO10 40 PWM/GPIO ! GND 20

J5 - J8 are labeled on the PCB. The

1 +3.3V +5V 21 GPIO0 40 PWM/GPIO ! GND 20

EQEP Connect ors

GND GND GND

To disable the Level Shifter:

16 VCC 1Y0 12 GPIO35_Q1A GND TXD_TO_XDS 2 5 RXD_FROM_XDS

XDS110 Side Target Side

To debug the F280049C, ensure that the jumpers on J101

If debugging an external target, remove the jumpers from

USB & XDS Power Isolation Boundary +3V3

D- 2 USB_DM USB_DM R103 24.3 6 UD- DD- 11 R1 24.3 XDS_DM

U100 USB_GND GND

1 IO1 IO3 4 USB_DP

3.3V to 5V Boost System Supervisory Circuit

U2A +3V3 U2B

XDS_RXD 33 PA0 81 PL0

Figure 10. MCU025B_XDS110_MCU.SchDoc

DNP DNP DNP MH1 MH2

FID1 FID2 FID3

DNP DNP DNP

Figure 11. MCU025B_Hardware.SchDoc

4.4 LAUNCHXL-F280049C Board Dimensions

Figure 12. F28004x LaunchPad Dimensions and Component Locations

5.1 Reference Documents

5.2 Other TI Components Used in This Design

A.1 Frequently Asked Questions