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A tutorial on incremental design using FPGAs from Actel

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Regardless of the amount of time and energy FPGA designers invest attempting to create “right-first-
time” designs, the functional complexities, performance requirements, and high gate counts of large
complex designs frequently require changes to correct logic problems or to provide further
optimization. Compared with a traditional flow, an “incremental” design flow for design/synthesis and
place-and-route physical implementation is highly desirable with regard to repairing or optimizing
specific parts of the design without disturbing other portions that have met their design
requirements.

When a top-down design approach is difficult due to system memory limitations or extensive run
times, an incremental design flow also enables designers to process large designs. Other design
strategies involve freezing sections of a completed design while other parts of the design are
continuing development independently.

Traditional design creation and physical implementation

The common flow for FPGA development is to:

– Create the design in HDL.

– Run pre-synthesis simulation.
– Set constraints.
– Synthesize the design.
– Run post-synthesis simulation.
– Run place and route.
– Analyze the design's timing performance.

If functional and timing performance requirements are met, a programming file is generated and the
device is programmed. Using tools from Actel and its partners, the Libero IDE Platinum toolset is well
equipped to successfully manage a “right-first-time” design. For performance improvements, the
Actel SmartTime timing analysis and constraints management tool provides features for identifying
and resolving critical paths within the design. Additionally, the Magma PALACE physical synthesis
tool can generally improve the overall performance of Actel's Fusion Programmable System Chips
and ProASIC3 devices by a significant margin.

But what if further optimization on segments of the design need to be managed after the initial
layout? What if performance is still marginal, or some of the blocks still contain functional problems?
Incremental design flow overview
The design flow (Fig 1 ) closely resembles a traditional synthesis/physical implementation flow, with
the addition of “compile points” after the initial synthesis project setup and compile. Compile points
are parts of a design that act as relatively independent synthesis units: they have their own constraint
files and are optimized individually. They are re-synthesized only as needed, based on an analysis of
design dependencies and the nature of design changes. Compile points are locked, to ensure stability
in incremental design and to permit hierarchical place and route with multiple output netlists (one for
each compile point and one for the top level of the design). A “locked” compile point means that,
during synthesis of its parent, it is not re-optimized, its hierarchical interface is unchanged, and no
boundary optimizations are made. This implies that all instantiations of the same locked compile
point have the same implementation and are treated identically during synthesis.

1. Incremental flow using Synplify Pro and Libero IDE.

(Click this image to view a larger, more detailed version)

Alternatively, design teams can work on individual compile points simultaneously and independently.
Each compile point is treated as an individual block for incremental and individual mapping. Any
number of compile points can be identified and nested into the design. Using compile points, design
modifications can be managed without disturbing other parts of the design.

A “difference-based” incremental synthesis process keeps track of design changes and

dependencies. Re-synthesis occurs only on those parts of the design that are directly affected by the
incremental change. The process also ensures that the incremental changes made are identifiable in
the netlist to the corresponding netlist import and compile function. Keeping the original place and
route as golden as possible is ensured by running the updated netlist using an “Incremental Mode”
and “Lock Existing Layout' option in a Layout Options menu. Updates and modifications will occur to
only those parts of the layout that are directly related to the compile point changes made by the
synthesis tool.

The Synplify Pro MultiPoint synthesis and the Actel Libero Integrated Design Environment (IDE)
together provide an efficient incremental design flow methodology for managing true engineering
change order (ECO) requirements. This combination allows modular changes to the original design,
whereby only those parts of the design that need to change will change. This flow minimized the
impact on previously proven segments of the design, thus saving time and resources.

For example, the MultiPoint synthesis solution allows you to establish a multiple of “compile points”
that are preserved in Synplify Pro as future design or redesign areas. You may also partition a design
into small synthesis blocks for modification while leaving the remainder untouched. For very large
designs, MultiPoint allows designing and synthesizing in incremental blocks in order to avoid system
memory or runtime issues.Actel Libero easily accepts the updated netlists created by Synplify Pro's
MultiPoint synthesis process. The “incremental” place and route flow found in Libero provides an ECO
methodology, whereby only the parts of the layout that need to be updated will be, leaving selected
parts of the original layout undisturbed. Clearly, layout occurs much faster with the incremental layout
process than having to re-layout the entire design.
In many cases, you may have to revert back to the original design to make the functional and
performance modifications to meet requirements. An efficient incremental ECO-mode approach is
available to designers using MultiPoint synthesis within Synplify Pro and place-and-route options
within the Libero IDE. This allows designers to update the design in minimal time without disturbing
valuable design and development work that has already been completed and signed off.

Furthermore, the design “views” in the Libero IDE allow versions of the design to be saved
independently within the same design project. This feature saves prior constraint and place/route
files, enabling a comparison of the incremental design layout to previous layouts. You can easily
determine if a subsequent incremental fix meets the design objective, or if the previous solution
might be the better choice. With these design views, you can easily make variations each stemming
from the original layout, or serially from each subsequent layout, and compare the results of each
iteration.

The benefits to this incremental design flow are as follows:

– Large designs can be broken down into smaller blocks, reducing overall
synthesis and place-and-route run times and system memory
requirements.
– Areas of interest in a netlist or layout can be marked in Synplify Pro and
incrementally modified while only minimally affecting the original layout,
and saving re-synthesis and layout run time.
– Traditional bottom-up design requires designers to write and maintain
time-consuming and error-prone scripts that direct the synthesis and
keep track of design dependencies. A difference-based incremental
synthesis eliminates the need for these scripts.

Design Tutorial

Prepare your design for an incremental flow

After creating the design, the first step in using Synplify Pro MultiPoint synthesis is to create an
“implementation option” when launching Synplify Pro. This option contains device, speed grade,
global frequency, and other design and optimization parameters. Additional implementation options
using different parameters or design changes can subsequently be created to test variations of the
design. Create (for example) “implementation 1” for the initial set of parameters and HDL design.

The Synplify Pro “Compile Only” function helps Synplify Pro's SCOPE constraints editor understand
the hierarchy of the design. The SCOPE constraints editor in Synplify Pro manages the design
constraints for synthesis and place-and-route, and it is also used to define compile points and their
respective constraints. Compile points and constraints are both saved in a constraint file as part of
the implementation, the constraints having been set as part of the compile point definition. Compile
points are defined in a new top level constraint file, or, the definitions can be added to an existing top
level .sdc file.

Next, launch SCOPE from the Synplify Pro toolbar and select “Top Level Module” from the “Select File
Type” dialog. From this menu you can create compile points from a list of modules identified in the
design. Modules or blocks of interest can be “locked” which then identifies them to Synplify Pro as a
compile point. Set other top-level constraints at this time, such as input/output delays, clock
frequencies, or multi-cycle paths.

Constraints must be specified for each compile point within individual .sdc files, and separate top-
level constraints must be added for the entire design by a top level .sdc file. The “Create SCOPE File”
dialogs make it easy to establish compile points and constraint files.
After the compile points and constraints have been set up in SCOPE, the top-level design is ready for
synthesis.

A design is synthesized in three phases:

– Compile points are synthesized from the bottom up, starting with the
compile point at the lowest level of the hierarchy in the design. Each
compile point is synthesized independently. For each compile point,
Synplify Pro creates a subdirectory named after the compile point,
where it stores intermediate files for the compile point such as the RTL
netlist, the mapped netlist, and a model file. The model file contains the
hierarchical interface timing and resource information that is used to
synthesize the next level. Once generated, the model file is not updated
unless there is an interface design change or it is specifically requested
for update by the user.
– After all compile points are synthesized, Synplify Pro synthesizes the
design from the top down, using the model information for each
compile point.
– Synplify Pro then writes out a single netlist and one constraint file for
the entire design.

Analyzing the results in Synplify Pro

There are multiple ways by which you can evaluate the synthesis results. Synplify Pro writes timing
and area to a log file in the implementation directory. The design can be evaluated in the Synplify
Pro's HDL Analyst RTL and Technology schematic views to determine if your design has met the
design goals. You can also view and isolate critical paths, search for and highlight design objects,
and cross-probe between source files. Any errors identified at this level should be fixed.

Synthesize or re-synthesize incrementally

Synplify Pro allows you synthesize incrementally or entirely. If a compile point has not changed from
its original configuration, the model file from the previous synthesis run is used. You can choose to
“run incrementally” which synthesizes only the compile points, and only those that have had a source
code, constraint, or implementation change. Alternatively, the entire design can be re-synthesized
using a “re-synthesize all” command. Typically, to save time, you would choose to synthesize
incrementally.Physical implementation: import the updated netlist into Libero
Once Synplify Pro has generated the netlist, the netlist is automatically part of Libero IDE's File
Manager and is available for place-and-route (layout). The design flow and file manager user interface
with Libero make it easy to identify and select the netlist implementation options created by Synplify
Pro (Fig 2 ).

2. Libero IDE netlist identification and selection.

(Click this image to view a larger, more detailed version)
Assuming the netlist is an updated netlist containing the incremental changes made in the design
and synthesis process, you may first want to take care to preserve the original layout generated by
Libero's initial place-and-route process. Libero easily allows saving the original layout as a physical
design “view” (also called “implementation”), which can be named for convenience such as
“Design_Layout_1”. Rather than overwrite the “Design_Layout_1” file with the updated netlist results,
Libero allows creation of a new “view” within the same project. “Design_Layout_2”, for example, might
be used for implementation and testing of the updated netlist. This feature allows you to compare the
results of the “before and after” incremental netlist change created by Synplify Pro.

Next, open Actel Designer, the physical implementation tool within Libero, and import the updated
netlist into Libero using the new implementation name, and compile the design (Fig 3 ).

3. Compile the design.

(Click this image to view a larger, more detailed version)

After compile, Libero's layout menu provides options for the layout process. The default selection in
the layout menu would completely re-place and re-route the entire layout. For netlists that include
incremental updates using the MultiPoint process, Actel recommends using full place-and-route.
Using full place and route will provide the most efficient layout, however all timing will have to be re-
verified. Depending on your strategy for the incremental changes however, it may be advantageous to
only re-place and re-route those parts of the entire layout that in fact are directly affected by the
incremental changes in the design.

The layout options include “Place Incrementally”, “Lock Existing Placement (Fix)”, and “Route
Incrementally” options. “Place Incrementally” (without locking) uses the existing placement as a
reference starting point, but the result will be a different layout in most cases. An advanced
placement algorithm for Place Incrementally attempts to ensure timing performance is met. Locking
the existing layout with “Lock Existing Placement (Fix)” increases the predictability of the outcome
due to the incremental changes, because all fixed (unchanged) macros are untouched by Libero's
layout process.

When incorporating incremental changes into the design, you must be sure there is sufficient room in
the FPGA array to accommodate the incremental changes. If the incremental changes are
substantial, and if the design is already tight, the placement may not be successful. Knowing in
advance that incremental changes are coming, you could use Libero IDE's floor-planning tool to
reserve regions on the die to allow room for the changes. This in combination with locking the initial
layout can provide a quick and efficient way of incorporating the incremental changes while
preserving the desired parts of the original layout.

Incremental routing attempts to preserve the existing routing of the design, but is not guaranteed as it
depends on the nature of the netlist changes.

Evaluate the updated layout

After layout, use Libero's SmartTime static timing analysis tool to verify the overall device
performance of the new view, analyzing critical paths if necessary. Compare the performance results
of the pre-incremental flow run in Design_Layout_1 to Design_Layout_2 and determine if the
incremental update has accomplished the design goal.

Device programming and debug

Having met the design goals utilizing the ECO flow, Libero IDE provides FlashPro in-system
programming (ISP) and Silicon Sculptor programming tools plus Synplicity Identify' and Actel Silicon
Explorer device debugging and verification tools.

Summary
The Synplify Pro MultiPoint synthesis and Libero IDE development tools provide an efficient
incremental design flow for true ECO requirements. This combination allows modular changes to an
existing base design whereby only those parts of the design that need to change will change. This
flow minimizes effects on already proven parts of the design and saves time by not requiring an
entire re-layout of the design. With the “Implementation Options and Views” of Synplify and Libero,
one can easily set up design alternatives for analysis and selection of the best performance options.

Fred Wickersham is Product Marketing Manager for Software Tools at Actel. Fred has
over 25 years experience in semiconductor marketing and product management
coming from National Semiconductor, Philips Semiconductor, and LSI Logic. In his
current role, he is involved with tactical and strategic support of development tools
for Actel FPGA products. Fred obtained his electronics education at Oregon Institute
of Technology and has a BS from University of Phoenix.

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