Computer Function and

Interconnection
BACS 1113 Computer Organization and
Architecture
Overview

● Computer Components
○ Computer Components
○ CPU Components
● Computer Function
○ Instruction Fetch & Execute
● Bus Interconnection
○ Bus Structure
○ Multiple-Bus Hierarchies
● CISC and RISC 2
Computer Components

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Computer Components - Top Level

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Computer Components

● Central Processing unit (CPU) : Controls the operation of the

computer and performs its data
processing functions.
● Main memory : Temporary storage of code & data.
● I/O : Moves data between the computer and its external environment.
● System interconnection : Mechanism that provides for communication
among CPU, main memory, and I/O.
○ E.g. System bus
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CPU Components

● Control Unit (CU): Controls the operation of the CPU and hence the
computer.
● Arithmetic and Logic Unit (ALU) : Performs the computer’s data
processing functions.
● Registers:Provides storage internal to the CPU.
● CPU interconnection: mechanism that provides for communication
among the control unit, ALU, and registers.
○ E.g. CPU Internal bus
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Computer
components:

Top-level View

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CPU Components: Function of Registers

● PC: Stores the address of the next instruction.

● IR : Stores the instruction to execute.
● Accumulator : Temporary storage for ALU operations.
● MAR : specifies the memory address for the next read or write.
● MDR : Stores the data to be written into memory or the data read from
the memory

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Computer Components: Top-Level View

● Memory module
○ Consists of a set of locations, defined by sequentially numbered
addresses.
○ Stores a binary number (instruction or data).
● I/O module
○ Transfers data from external devices to CPU & memory, and vice
versa.
○ Contains internal buffers for temporarily holding
data until they can be sent on. 9
Computer Functions

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Instruction Fetch and Execute

● Fetch-Execute Instruction Cycle / Machine Cycle

● The steps performed by CPU for each machine language instruction
received.
● A 4 steps cycle

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Instruction Fetch and Execute

● Fetch - Retrieve an instruction from the memory.

● Decode - Translate the retrieved instruction Fetch Phase
into a series of computer commands.
● Execute - Execute the computer commands.
● Store - Send and write the results back in memory. Execute Phase

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Instruction Cycle (Fetch Phase)

● Processor fetches instruction from memory location pointed by PC.

○ PC : holds the address of next instruction to fetch.

● Instruction loaded into IR.

○ The instruction contains bits that specify the action to be taken.
○ Increment PC.

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Instruction Cycle (Execute Phase)

● Processor decodes / interprets the instruction and performs the

required action.
● Actual execution of operation:
○ Processor-memory : data transfer between CPU and main
memory.
○ Processor-I/O : Data transfer between CPU and I/O Module
○ Data processing : Arithmetic or logical operations
○ Control : Alteration of sequence of execution.
■ E.g. JMP 14
 Address of the data
to be loaded

Example of program Execution

Memory
● The LOAD instruction fetch-execute steps.
300 1940 (L)
1. PC → MAR ; MAR = 300
301 5941 (A)
2. MDR → IR ; IR = instruction 1940
Indicate the LOAD
3. PC + 1 → PC ; PC = 301 instruction 302 2941(S)
4. IR[address] → MAR .

; MAR = 940 (data location) .

940 0003
5. MDR → A ; A = 0003
941 0002
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 Address of the data
to be loaded

Example of program Execution

Memory
● The ADD instruction fetch-execute steps.
300 1940 (L)
1. PC → MAR ; MAR = 301
301 5941 (A)
2. MDR → IR ; IR = 5941
Indicate the ADD
3. PC + 1 → PC ; PC = 302 instruction 302 2941(S)
4. IR[address] → MAR .

; MAR = 941 (data location) .

940 0003
5. A + MDR → A ; A = 0005
941 0002
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 Address of the data
to be loaded

Example of program Execution

Memory
● The STORE instruction fetch-execute steps.
300 1940 (L)
1. PC → MAR ; MAR = 302
301 5941 (A)
2. MDR → IR ; IR = 2941
Indicate the
3. PC + 1 → PC ; PC = 303 STORE instruction 302 2941(S)
4. IR[address] → MAR .

; MAR = 941 (data location) .

940 0003
5. A → MDR ; Address 941 store 0005
941 0002 0005
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Bus Interconnection

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Bus

● A communication pathway connecting two or more devices.

● A shared transmission medium
● A signal transmitted by one device is broadcast to all other devices
attached to the bus.
● Signal will overlap and become garbled if two devices transmit in the
same time.
● Only one device at a time can successfully transmit

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Bus

● A bus consists of multiple communication pathways, known as lines.

● Memory to processor, processor to memory, I/O to processor,
processor to I/O, and I/O to or from memory.
● Line : transmit binary signals.
● Serial bus: Transmit a sequence of
binary digits across a single line.
● Parallel bus: Transmit binary digits
simultaneously across several line.
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Bus Structure

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Data bus

● Carries the “data” among system modules.

● May consist of 32, 64, 128, or more separate lines.
○ Number of lines = width of data bus
● Ea ch line carry one bit at a time.
○ The number of lines determine how many bits can be transmitted
at one time.
● Width is a key determinant of system performance.
○ E.g. 32bits data bus and 64 bits instruction. Processor must access
the memory twice for each instruction cycle. 22
Address bus

● Identifies the source or destination of the data on the data bus.

○ E.g. To read the data from memory, puts the address on the
address lines.
● Bus width (number of address lines) determines the maximum memory
capacity of the system.
○ E.g. n bits address bus giving 2n memory locations.
In 8086, 16 bits address bus giving 216 spaces (64K)

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Control bus

● Provides control for the proper synchronization and operation of the

bus and the module.
● Transmit both command and timing information among system
modules.
● Timing signals :
○ indicate the validity of data and address information.
● Command signals :
○ specify operations to be performed
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Control bus: Typical control bus

● Memory write : causes data on the bus to be written into the

addressed location.
● Memory read : causes data from the addressed location to be placed on
the bus.
● I/O write : causes data on the bus to be output to the addressed I/O
port.
● I/O read : causes data from the addressed I/O port
to be placed on the bus.
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Control bus: Typical control bus

● Interrupt request :
○ indicates that an interrupt is pending.
● Reset :
○ initializes all modules.
● Clock:
○ is used to synchronize operations.

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Bandwidth/Data Transfer Rate

● The transfer rate or bandwidth of a particular system bus can be

calculated from the number of cycles required for transfer, the length
of the cycle and the number of data lines.
● For example, if a bus has 8 data lines, requires 4 cycles to transfer data,
and each cycle is 250 nsecs then the bandwidth of the bus is 1 byte per
1000 nsecs. This is equivalent to 1 byte per microsecond or 1
Megabyte /second.

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Question

In order to execute a program instructions must be transferred from

memory along a bus to the CPU. If the bus has 8 data lines, at most one 8 bit
byte can be transferred at a time. How many memory access would be
needed in this case to transfer a 32 bit instruction from memory to the CPU.

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Bus: Direction of Transmission
A B
● Simplex
○ unidirectional
● Half duplex OR
A B
○ bidirectional, one direction at a time
● Full duplex
○ bidirectional simultaneously
A AND B

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Interconnection Method: Point to Point

● A bus carry signals

from a specific source
to a specific destination.
● E.g. : The cable that
connects the computer’s
serial port to a printer.

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Multipoint Bus

● A bus that connect several points together.

● The signals produced by a source
on the bus are “broadcasts” to
every other point on the bus.
● E.g. : Ethernet

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Bus Legacy
● Different types of buses:
a. External CPU bus = expansion bus
b. ISA bus (Industry Standard Architecture) – Sound Card
c. AGP bus (Advanced Graphic Port) – 2-4 times faster than PCI and used for
Video Card.
d. IDE bus (Intelligent Drive Electronics)– Disk Drives
e. PCI bus (Peripheral Component Interconnect) – 32-64b bit and slow
replacing ISA bus.
f. PCI Express
g. USB bus (Universal Serial Bus) – hot swap, plug and unplug and is slowly
wiping out PS/2 port.
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The chipset

● A chipset : component which routes data between the computer's

buses.
● Two components:
○ NorthBridge (memory controller)
In charge of controlling transfers between the processor and
the RAM, which is way it is located physically near the
Processor.
○ SouthBridge (I/O controller or expansion controller)
handles communications between peripheral devices. 33
The chipset

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Problems found for a single bus

● The more devices attached to the bus, the greater the bus length.
○ Propagation delays : determines the time it takes for devices to
coordinate the use of bus.
○ Affect performance.
● Aggregate data transfer demand approaches the bus capacity.
○ Wider buses can no longer overcome this problem.
○ Multiple buses are used.

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Traditional bus
architecture

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Modern bus
architecture

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CISC and RISC architecture

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RISC & CISC

● CPU architectures is defined as its basic characteristics and major

features of the CPU.
● Those characteristics include :
○ The number and the types of registers.
○ Methods of addressing memory.
○ Basic design and layout of the instruction set.

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RISC & CISC

● There are several different CPU architectures. The TWO(2) most

important approaches are known as :
○ Complex Instruction Set Computer (CISC)
○ Reduced Instruction Set Computer (RISC)

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CISC

● Characterized by :
○ Few general-purpose registers.
○ Many addressing techniques.
○ Large number of specialized, complex instructions.
○ Instruction are of varying sizes.
● Exp : zSeries, Intel x86 family

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RISC

● Characterized by :
○ 32 general-purpose registers.
○ Limited addressing modes
○ Limited and simple instruction set.
○ Fixed 4-byte instruction word size.
● Exp : Power PC

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RISC

● Attempt to produce more CPU power by eliminating TWO (2) major

bottlenecks to instruction execution speed.
○ Reducing the number of data memory accesses by using register
more effectively.
○ Simplifying the instruction set by eliminating rarely used
instructions.

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Instruction Format - CISC & RISC
CISC RISC

● Consists of many instructions that not ● Simplifying the instructions set of

frequently used CPU.
● Requires additional complex ● Emphasizing on frequently used
hardware. instructions. Exp. branch, load
● Longer execution time ● Shorter execution time

● For a simple instruction: ● For a simple instruction:

CISC requires more steps to RISC supposed to be executed within
complete the same clock interval

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CISC vs RISC Processing

CISC

RISC

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FIVE (5) main features of RISC over CISC

● Limited and simple instruction set.

○ Execute faster at high clock speed
○ Do not require complex hardware
● Registers-oriented instructions.
○ Reduce memory access
○ Use registers to operate/hold frequently us instruction (except for
LOAD and STORE)

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FIVE (5) main features of RISC over CISC

● A fixed length/format instruction word.

○ Easy to identify
○ Can be fetched and decoded independently → pipelining
● Limited addressing mode.
○ Provide single address mode
○ Speed up instruction executions

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FIVE (5) main features of RISC over CISC

● A large bank of registers.

○ Registers are applied widely
○ Reduce memory access

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