Compal Cdl50 La-D707p Rev 0.2

B C D E
Model Name : BDL50

File Name : LA-D707P
1 1
2 2
Kabylake-U M/B Schematics Document

Intel ULV Processor with DDR4 SODIMMx2
2016-05-11
3 REV:0.2 3
Project : Diner_Crepe1.1(15") (PV phase)

(Modified Source:LA-D704PR20_2016-04-20)
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
RepairLap.com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom v0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D707P
Date: Wednesday, May 11, 2016 Sheet 1 of 60
A B C D E
A B C D E
UC1
U666
VRAM AMD PCIex4
gDDR3 x4pcs Port #1~#4
R16M-M1-70 D3(R7)
256Mbx16(4Gb) 1Ch 64bits 1.5V R16M-M1-30 D3(R5) PCIe 2.0:5Gb/s
512Mbx16(8Gb) PCIe 3.0:8Gb/s
1
P.40~42 P.36~40 DDR4-SO-DIMM X 2
1
Dual Channel Interleaved

P.17~18
LVDS@ UT1
JLVDS1 DDR4 2133MHz 1.2V
eDP/LVDS eDP to LVDS Transmitter eDP x1Lane
CONN P.20 RTD2132N P.19
2.7Gb/s
Kabylake-U
SATA 3.0 Port 0 JHDD
eDP@ Skylake-U 2.5" SATA HDD P.30
FHD eDPx2Lane GEN1 1.5Gb/s
GEN2 3Gb/s Port 1 JODD
eDP@ 2.7Gb/s GEN3 6Gb/s ODD P.30
JCRT1 U4104 1356P BGA
CRT CONN DP to VGA Transmitter DDI x2Lane Port 2
P.22 CRT
RTD2168 P.22 KBL-U 15W 2+2 USB3.0
JHDMI1 DDI x4Lane Port 1 5Gb/s
HDMI CONN HDMI
SKL-U 15W 2+2 USB2.0 Port 1 JUSB1 Port 1
P.21 297MHz USB3.0 port
UL1 480Mb/s (onboard-1) P.31
2 2
LAN
RTL8111HSH(Giga) PCIex1 Port #5 Port 2 JUSB2
RTL8166EH(10/100)P.23 PCIe Gen1:2.5Gb/s USB2.0 port P.31
(onboard-2)
PCIe Gen2:5Gb/s
Port 3 JIO1
USB2.0 Port P.33
JWLAN1 (sub board)
NGFF WLAN+BT PCIex1 Port #6
PCIe 1.0:2.5Gb/s Port 4 JWLAN1
(Key E) P.32 Bluetooth
PCIe 2.0:5Gb/s P.32
Port 5 JLVDS1
Camera P.20
Port 6 JLVDS1
Touch Screen P.20
3 JIO1 3
Port 7 Card reader

SMbus RTS5141
(sub board) P.33
1MHz
JKB1 UK1
Int.KBD P.27 EC ENE LPC UA1
JTP1
KB9022QD 33MHz JSPK1
PS2 HDA 24MHz HDA Aduio codec
TouchPad P.26 Internal SPK
P.27 ALC3227
U4 P.24
FAN P.34 TPM JHP
SLB9665TT2.0 Combo Jack

JPWR P.28
Lid switch *default FWTPM
(sub board) P.33 SPI
UC3 50MHz
4 4
Thermal sensor UC2
NCT7718W P.10 SPI ROM

8MBytes P.07
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom v0.2
RepairLap.com
A B C D E
A B C D E
Power rail Control (EC) Source (CPU)

SOC SMBUS Address Table (TBC) EC SMBUS Address Table (TBC)
+RTCVCC X X
VIN X X Address (8bit)
SOC_SMBUS Net Name Power Rail Device Address (7 bit) EC_SMBUS Port Power Rail Device Address (7 bit)
BATT+ X X Write Read
B+ X X SMBCLK DIMM1 TBC TBC 0xA2 BAT 0x16
+VL X X SMBDATA +3VS
SMBUS Port 1 +3VL_EC
+3VL X X Touch PAD TBC TBC TBC
CHGR 0x12
+5VALW EC_ON X SML0CLK
+3VALW EC_ON X SML0DATA +3VS ME FW 0x48/0x49 TBC 0x90/0x92
dGPU TBC
1
+3VALW_EC EC_ON X 1
+3V_PCH PCH_PWR_EN X EC TBC TBC TBC Thermal 0x4C

SML1CLK SMBUS Port 2 +3VS Sensor
+1.2V_VDDQ SYSON PM_SLP_S5#/PM_SLP_S4# SML1DATA +3VS
DGPU TBC TBC TBC
+5VS SUSP# PM_SLP_S3# PCH TBC
+3VS SUSP# PM_SLP_S3# PCH TBC TBC TBC
+1.5VS SUSP# PM_SLP_S3#
DAX DAX
+1.05VS SUSP# PM_SLP_S3#
+0.6V_0.6VS SUSP#
+VCC_CORE X VR12.5_VR_ON Power State
KBL SKL SIGNAL
Part Number = DA6001LS000
PCB 1RU LA-D707P REV0 M/B 6
Part Number = DAZ1O200301
PCB BDL50 LA-D704P LS-C701P/C703P 02 STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
SKL@
S0 (Full ON) HIGH HIGH HIGH ON ON ON ON
BOM Structure Table (1/2) 45@
Part Number
ROYALTY HDMI W/LOGO
Description
S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF
Funct i on Stuf f Un-Stuf f RO0000002HM HDMI W/Logo:RO0000002HM
RO0000003HM S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF

DGPU SKU PX@
UMA SKU UMA@ QKKS@ QKJW@ SKLPV2@
R30R1@
U666
R70R1@
U666
S5 (Sof t OFF) LOW LOW LOW ON OFF OFF OFF
ES@ UC1 UC1 UC1
SPI_IO3(MOW36)
Crystal (DIS) XTALPX@
Crystal XTAL@ SA000092P60
<USB2.0 port>
R16M-M1-30 FCBGA R16M-M1-70 FCBGA
Green CLK(UMA) GCLK@ ES_QKKS SA00009PJ10 ES_QKJW SA00009UR00 SKY_i7_6500U_SR2EZ SA000087TC0 SA000098V30
DESTINATION
S IC A32 FJ8067702739720 QKKS G0 2.4G S IC A32 FJ8067702739718 QKJW G0 2.6G S IC FJ8066201930408 SR2EZ D1 2.5G BGA S IC A32 216-0867-071 R16M-M1-30 FCBGA S IC A32 216-0864-032 R16M-M1-70 FCBGA
USB2.0 port
Green CLK(DIS) GCLKPX@ R30R3@ R70R3@ UMA Dis
QS_i3@ QS_i5@ QS_i7@ U666 U666
2 TPM TPM@ UC1 UC1 UC1 1 USB 2.0/3.0 USB 2.0/3.0 2
2 USB 2.0/3.0 USB 2.0/3.0

3 USB 2.0 OFF BOARD USB 2.0 OFF BOARD
R16M-M1-30 FCBGA R16M-M1-70 FCBGA 4 WLAN WLAN
i3_7100U_QS_QLDP i5_7200U_QLDM i7_7500U_QLDN SA000087TB0 SA000098V40
SA0000A3810 SA0000A3710 SA0000A3420 S IC A32 216-0867-071 R16M-M1-30 FCBGA S IC A32 216-0864-032 R16M-M1-70 FCBGA
S IC A32 FJ8067702739738 QLDP H0 2.4G S IC A32 FJ8067702739739 QLDM H0 2.5G S IC A32 FJ8067702739740 QLDN H0 2.7G 5 Camera Camera
i3R1@ i5R1@ i7R1@ 6 TOUCH SCREEN TOUCH SCREEN
R30@ R70@ UC1 UC1 UC1
U666 U666 7 CR CR
8
9
ES_QKKS SA000092N70 ES_QKKS SA000092O70 ES_QKKS SA000092P60 10
R16M-M1-30 FCBGA R16M-M1-70 FCBGA S IC A32 FJ8067702739720 QKKS G0 2.4G S IC A32 FJ8067702739720 QKKS G0 2.4G S IC A32 FJ8067702739720 QKKS G0 2.4G
SA000087T90 SA000098V10
S IC A32 216-0867-071 R16M-M1-30 FCBGA S IC A32 216-0864-032 R16M-M1-70 FCBGA i3R3@ i5R3@ i7R3@
UC1 UC1 UC1 <PCI-E,SATA,USB3.0/CLK>
DESTINATION
Lane# PCI-E SATA USB3.0 CLK
ES_QKKS SA000092N80 ES_QKKS SA000092O80 ES_QKKS SA000092P70
UMA Dis
S IC A32 FJ8067702739720 QKKS G0 2.4G S IC A32 FJ8067702739720 QKKS G0 2.4G S IC A32 FJ8067702739720 QKKS G0 2.4G
1 1 USB3.0 USB3.0 X
UCPU1
+3VS 2 2 USB3.0 USB3.0 X
+3VS +3VS R=10K
3 3 USB3.0(Charger)USB3.0(Charger) X
PCH_SMBCLK 4 4 USB3.0(IO Board)USB3.0(IO Board) X
2N7002 PCH_SMBDATA
SMBCLK
R=1K SO-DIMM B 5 1 5 X GPU(DIS only)
R7 SMBDATA ZZZ ZZZ ZZZ ZZZ ZZZ 6 2 6 X GPU(DIS only)
R8 +3VALW CLK0
7 3 X GPU(DIS only)
3
+3VS +3VS 3
CPU SML0CLK
R=499 2N7002
R=2.2K
TP_SMBCLK
TP_SMBDAT
Touch Pad HY2@
2G HYNIX
X7667032L01
MIC2@ SAM2@
2G MICRON 2G SAMSUNG
X7667032L02 X7667032L05
HY4@
4G Hynix
X7667032L03
MIC4@
4G Micron
X7667032L04
8
9
10
4
5
6
X
LAN
WLAN
GPU(DIS only)
LAN
WLAN
CLK1
CLK2
R9 SML0DATA
W2 11 7 0 2.5"HDD 2.5"HDD X
ZZZ ZZZ ZZZ ZZZ ZZZ
+3VS +3VS +3VS 12 8 1 ODD ODD X
DGPU_PEX_RST# 13 9 Card reader(PCI-E) Card reader(PCI-E) CLK3
SML1CLK
R=1K R=2.2K 14 10 X X X
R3HY2@ R3MIC2@ R3SAM2@ R3HY4@ R3MIC4@
W3 SML1DATA +3VGS_AON 2G HYNIX 2G MICRON 2G SAMSUNG 4G Hynix 4G Micron 15 11 1* X X X
V3 2N7002 X7667032L23 X7667032L24 X7667032L25 X7667032L21 X7667032L22
EC_SMB_CK2 16 12 2 X
EC_SMB_DA2
R=2.2K
I2C_0_SCL
I2C_0_SDA
U6 2N7002 dGPU
U7 I2CS_SCL
I2CS_SDA
+3VS
I2C_1_SCL R=1K
I2C_1_SDA
U9 Thermal Sensor :NCT7718W_MSOP8
U8 Touch Screen Address : 0x4C
Load BOM Opt i on Tabl e
UK1:+3VALW_EC (+3VL)
EC_SMB_CK2
BOM Number Load BOM Opt i on
4 EC_SMB_DA2 4
79
80 4519YN32L01(UMA)
EC +3VL_EC
R=2.2K
4519YN32L02(DIS)
EC_SMB_CK1
77 EC_SMB_DA1
78 R=100 BAT Security Classification Compal Secret Data Compal Electronics, Inc.
Notes List
Charger THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RepairLap.com
Custom v0.2
A B C D E
5 4 3 2 1
[Diner-PWR Sequence_SKL-U22_DDR3L_Volume_NON CS]
G3->S0 S0->S3/DS3 S0/ DS3 ->S0 S0->S5

+3VL_RTC +3VL_RTC
tPCH01_Min : 9 ms
SOC_RTCRST# SOC_RTCRST#
+19VB +19VB
D +3VLP/+5VLP +3VLP/+5VLP D
EC_ON EC_ON
tPCH04_Min : 9 ms
+5VALW/+3VALW/+3VALW_DSW +5VALW/+3VALW/+3VALW_DSW
Pull-up to DSW well if not implemented.
PM_BATLOW# PM_BATLOW#
PCH_PWR_EN (SLP_SUS#) PCH_PWR_EN (SLP_SUS#)
+3V_PRIM +3V_PRIM
+1.8V_PRIM +1.8V_PRIM
EXT_PWR_GATE# If EXT_PWR_GATE# Toffmin is too small, Pwr EXT_PWR_GATE#

gate may choose to completely ignore it
+1.0V_MPHYPLL +1.0V_MPHYPLL
+1.0V_PRIM_CORE +1.0V_PRIM_CORE
tPCH34_Max : 20 ms
+1.0V_PRIM tPCH06_Min : 200 us +1.0V_PRIM
SUSACK# SUSACK#
tPCH02_Min : 10 ms
PCH_DPWROK PCH_DPWROK
tPCH03_Min : 10 ms
EC_RSMRST# EC_RSMRST#
tPLT02_Min : 0 ms Max : 90 ms
C AC_PRESENT AC_PRESENT C
ON/OFF ON/OFF
PBTN_OUT# PBTN_OUT#
Minimum duration of PWRBTN# assertion = 16mS. PWRBTN# can assert before or after RSMRST#
PM_SLP_S5# PM_SLP_S5#
tPCH18_Min : 90 us
ESPI_RST# ESPI_RST#
SYSON SYSON
+1.0V_VCCST/+1.0V_VCCSFR +1.0V_VCCST/+1.0V_VCCSFR
+1.35V_VDDQ/+1.35V_VCCSFR_OC +1.35V_VDDQ/+1.35V_VCCSFR_OC
SUSP# SUSP#
tCPU04 Min : 100 ns
+1.0VS_VCCSTG +1.0VS_VCCSTG
tCPU10 Min : 1 ms
B +1.0VS_VCCIO +1.0VS_VCCIO B
+5VS/+3VS/+1.5VS/+1.05VS
+5VS/+3VS/+1.5VS/+1.05VS
T4 = Min : 20ms Max : 30ms(EC Control)
EC_VCCST_PG EC_VCCST_PG
VR_ON VR_ON
tCPU19 Max : 100 ns
SM_PG_CTRL SM_PG_CTRL
tCPU18 Max : 35 us
+0.675VS_VTT +0.675VS_VTT
tCPU09 Min : 1 ms
+VCC_SA +VCC_SA
+VCC_CORE +VCC_CORE
+VCC_GT +VCC_GT
VR_PWRGD VR_PWRGD
tCPU16 Min : 0 ns
PCH_PWROK PCH_PWROK
H_CPUPWRGD H_CPUPWRGD
SYS_PWROK SYS_PWROK
A A
SUS_STAT# SUS_STAT#
SOC_PLTRST#
SOC_PLTRST#
RepairLap.com
Issued Date Title
Deciphered Date
HW Reserve
Custom v0.2
5 4 3 2 1
A B C D E
UC1A SKL-U
Rev_0.53
<21> PCH_DPB_N2 E55 C47
DDI1_TXN[0] EDP_TXN[0] EDP_CPU_LANE_N0_C <19>
<21> PCH_DPB_P2 F55 C46
DDI1_TXP[0] EDP_TXP[0] EDP_CPU_LANE_P0_C <19>
<21> PCH_DPB_N1 E58 D46
DDI1_TXN[1] EDP_TXN[1] EDP_CPU_LANE_N1_C <19>
<HDMI> <21> PCH_DPB_P1 F58 C45
DDI1_TXP[1] EDP_TXP[1] EDP_CPU_LANE_P1_C <19>
SOC_DP1_CTRL_DATA(Internal Pull Down): <21> PCH_DPB_N0 F53 A45 <eDP>
G53 DDI1_TXN[2] EDP_TXN[2] B45
<21> PCH_DPB_P0 DDI1_TXP[2] EDP_TXP[2]
<21> PCH_DPB_N3 F56 A47
DDI1_TXN[3] EDP_TXN[3]
Display Port B Detected <21> PCH_DPB_P3 G56
DDI1_TXP[3] EDP_TXP[3]
B47
<22> PCH_DPC_N0 C50 E45

0 = Port B is not detected. <eDP to CRT> D50 DDI2_TXN[0] DDI EDP EDP_AUXN F45
EDP_CPU_AUX#_C <19>
1
<22> PCH_DPC_P0 DDI2_TXP[0] EDP_AUXP EDP_CPU_AUX_C <19> 1
<22> PCH_DPC_N1 C52
D52 DDI2_TXN[1] B52
1 = Port B is detected. <22> PCH_DPC_P1
A50 DDI2_TXP[1] EDP_DISP_UTIL TP@ T228
B50 DDI2_TXN[2] G50
D51 DDI2_TXP[2] DDI1_AUXN F50
C51 DDI2_TXN[3] DDI1_AUXP E48 DDI2_AUX_DN
SOC_DP2_CTRL_DATA(Internal Pull Down): DDI2_TXP[3] DDI2_AUXN F48 DDI2_AUX_DP
DDI2_AUX_DN <22>
DDI2_AUXP G46
DDI2_AUX_DP <22> <DB> Check
DDI3_AUXN
Display Port C Detected DISPLAY SIDEBANDS
DDI3_AUXP
F46
PCH_DDPB_CLK L13
<21> PCH_DDPB_CLK GPP_E18/DDPB_CTRLCLK
PCH_DDPB_DAT PCH_DDPB_HPD From HDMI
0 = Port C is not detected. HDMI DDC (Port B)
L12 L9 PCH_DDPB_HPD <21>
<21> PCH_DDPB_DAT GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 L7 DDI2_HPD DDI2_HPD <22>
From eDP to CRT
@ RC200 1 2 2.2K_0402_5% N7 GPP_E14/DDPC_HPD1 L6 NMI_DBG#_CPU
GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 NMI_DBG#_CPU <10,26>
RC199 1 2 2.2K_0402_5% N8 N9 EC_SCI#
1 = Port C is detected. +3VS
CRT@ GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 L10 EDP_HPD
EC_SCI# <10,26> From eDP
GPP_E17/EDP_HPD EDP_HPD <19>
<DB> DP port C enable N11
N12 GPP_E22/DDPD_CTRLCLK R12 ENBKL
GPP_E23/DDPD_CTRLDATA EDP_BKLTEN ENBKL <26>
R11
EDP_BKLTCTL BKL_PWM_CPU <20>
EDP_COMP E52 1 OF 20 U13 ENVDD_CPU
EDP_RCOMP EDP_VDDEN ENVDD_CPU <20>
SKL-U_BGA1356
+1.0V_VCCST
+1.0VS_VCCIO RC123 1 @ 2 100K_0402_5% ENVDD_CPU
1
1 2 H_THERMTRIP#
RC2 1K_0402_5% RC3 UC1D SKL-U RC124 1 2 100K_0402_5% ENBKL
1K_0402_5% Rev_0.53
T248 TP@ D63
2 H_PECI A54 CATERR# 2
<26> H_PECI
2
1 2 H_PROCHOT#_R C65 PECI
<26> PROCHOT# PROCHOT# JTAG
COMPENSATION PU FOR eDP RC4 499_0402_1% H_THERMTRIP# C63
SOC_OCC# A65 THERMTRIP# B61 CPU_XDP_TCK0
+1.0VS_VCCIO T25 TP@ SKTOCC# PROC_TCK TP@ T259
CPU MISC D60 SOC_XDP_TDI
PROC_TDI TP@ T260
1
T270 TP@ XDP_BPM#0 C55 A61 SOC_XDP_TDO
DS11 XDP_BPM#1 D55 BPM#[0] PROC_TDO C60 SOC_XDP_TMS TP@ T261
T271 TP@ BPM#[1] PROC_TMS TP@ T262
RC1 1 2 EDP_COMP CK0402101V05_0402-2 T250 TP@ B54 B59 SOC_XDP_TRST#
24.9_0402_1% C56 BPM#[2] PROC_TRST# TP@ T263
ESD@ T249 TP@ BPM#[3]
CAD note: B56 PCH_JTAG_TCK1
SCV00001K00 SOC_GPIOE3 A6 PCH_JTAG_TCK D59 SOC_XDP_TDI TP@ T264
Trace width=20 mils,Spacing=25mil,Max length=100mils T30 TP@
2
A7 GPP_E3/CPU_GP0 PCH_JTAG_TDI A56 SOC_XDP_TDO TP@ T265

BA5 GPP_E7/CPU_GP1 PCH_JTAG_TDO C59 SOC_XDP_TMS TP@ T266
SOC_GPIOB4 AY5 GPP_B3/CPU_GP2 PCH_JTAG_TMS C61 SOC_XDP_TRST# TP@ T267
T40 TP@ GPP_B4/CPU_GP3 PCH_TRST# TP@ T268
A59 CPU_XDP_TCK0
RC5 2 1 49.9_0402_1% CPU_POPIRCOMP AT16 JTAGX TP@ T269
RC6 2 1 49.9_0402_1% PCH_OPIRCOMP AU16 PROC_POPIRCOMP
RC7 2 1 49.9_0402_1% EDRAM_OPIO_RCOMP H66 PCH_OPIRCOMP
RC8 2 1 49.9_0402_1% EOPIO_RCOMP H65 OPCE_RCOMP
OPC_RCOMP
4 OF 20
SKL-U_BGA1356
XDP CONN
3 3
+1.0VS_VCCIO
RC11 2 @ 1 51_0402_5% SOC_XDP_TMS
RC13 2 @ 1 51_0402_5% SOC_XDP_TDI
RC15 2 1 51 +-1% 0402 SOC_XDP_TDO SD000008H80
RC364 2 @ 1 51_0402_5% CPU_XDP_TCK0
+1.0V_PRIM
RC14 2 @ 1 51_0402_5% XDP_PREQ# XDP_PREQ# <11>
RC31 1 @ 2 1K_0402_5% XDP_ITP_PMODE XDP_ITP_PMODE <16>
4 RC365 2 @ 1 51_0402_1% SOC_XDP_TRST# 4
RC35 2 1 51_0402_1% CPU_XDP_TCK0 SD000008H80
RC37 2 @ 1 51_0402_5% PCH_JTAG_TCK1
RC366 1 @ 2 0_0402_5% CFG3 CFG3 <16> Security Classification

2014/05/19
Compal Secret Data
2015/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
SKL-U(1/12)DDI,MSIC,XDP,EDP
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom v0.2
A B C D E
5 4 3 2 1
Interleaved Memory Interleaved Memory

D
<Cocoa_1020> D
PDG#543016, ODT: CPU side no connect, DRAM side connect to VDDQ(Memory down); FET+R(SO-DIMM)
SKL-U
UC1B SKL-U UC1C
Rev_0.53 Rev_0.53
AU53 DDR_A_CLK#0
<17> DDR_A_D[0..15] DDR0_CKN[0] DDR_A_CLK#0 <17> <18> DDR_B_D[0..15]
DDR_A_D0 AL71 AT53 DDR_A_CLK0 DDR_B_D0 AF65 AN45 DDR_B_CLK#0
DDR0_DQ[0] DDR0_CKP[0] DDR_A_CLK0 <17> DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] DDR_B_CLK#0 <18>
DDR_A_D1 AL68 AU55 DDR_A_CLK#1 DDR_B_D1 AF64 AN46 DDR_B_CLK#1
DDR0_DQ[1] DDR0_CKN[1] DDR_A_CLK#1 <17> DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1] DDR_B_CLK#1 <18>
DDR_A_D2 AN68 AT55 DDR_A_CLK1 DDR_B_D2 AK65 AP45 DDR_B_CLK0
DDR0_DQ[2] DDR0_CKP[1] DDR_A_CLK1 <17> DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] DDR_B_CLK0 <18>
DDR_A_D3 AN69 DDR_B_D3 AK64 AP46 DDR_B_CLK1
DDR0_DQ[3] DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] DDR_B_CLK1 <18>
DDR_A_D4 AL70 BA56 DDR_A_CKE0 DDR_B_D4 AF66
DDR0_DQ[4] DDR0_CKE[0] DDR_A_CKE0 <17> DDR1_DQ[4]/DDR0_DQ[20]
DDR_A_D5 AL69 BB56 DDR_A_CKE1 DDR_B_D5 AF67 AN56 DDR_B_CKE0
DDR0_DQ[5] DDR0_CKE[1] DDR_A_CKE1 <17> DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] DDR_B_CKE0 <18>
DDR_A_D6 AN70 AW56 DDR_B_D6 AK67 AP55 DDR_B_CKE1
DDR0_DQ[6] DDR0_CKE[2] TP@ T14 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] DDR_B_CKE1 <18>
DDR_A_D7 AN71 AY56 DDR_B_D7 AK66 AN55
DDR0_DQ[7] DDR0_CKE[3] TP@ T15 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] TP@ T17
DDR_A_D8 AR70 DDR_B_D8 AF70 AP53
DDR0_DQ[8] DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3] TP@ T18
DDR_A_D9 AR68 AU45 DDR_A_CS#0 DDR_B_D9 AF68
DDR0_DQ[9] DDR0_CS#[0] DDR_A_CS#0 <17> DDR1_DQ[9]/DDR0_DQ[25]
DDR_A_D10 AU71 AU43 DDR_A_CS#1 DDR_B_D10 AH71 BB42 DDR_B_CS#0
DDR0_DQ[10] DDR0_CS#[1] DDR_A_CS#1 <17> DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0] DDR_B_CS#0 <18>
DDR_A_D11 AU68 AT45 DDR_A_ODT0 DDR_B_D11 AH68 AY42 DDR_B_CS#1
DDR0_DQ[11] DDR0_ODT[0] DDR_A_ODT0 <17> DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] DDR_B_CS#1 <18>
DDR_A_D12 AR71 AT43 DDR_A_ODT1 DDR_B_D12 AF71 BA42 DDR_B_ODT0
DDR0_DQ[12] DDR0_ODT[1] DDR_A_ODT1 <17> DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] DDR_B_ODT0 <18>
DDR_A_D13 AR69 DDR_B_D13 AF69 AW42 DDR_B_ODT1
DDR0_DQ[13] DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1] DDR_B_ODT1 <18>
DDR_A_D14 AU70 BA51 DDR_A_MA5 DDR_B_D14 AH70
DDR0_DQ[14] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR_A_MA5 <17> DDR1_DQ[14]/DDR0_DQ[30]
DDR_A_D15 AU69 BB54 DDR_A_MA9 DDR_B_D15 AH69 AY48 DDR_B_MA5
<17> DDR_A_D[16..31] DDR0_DQ[15] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR_A_MA9 <17> <18> DDR_B_D[16..31] DDR1_DQ[15]/DDR0_DQ[31] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR_B_MA5 <18>
DDR_A_D16 BB65 BA52 DDR_A_MA6 DDR_B_D16 AT66 AP50 DDR_B_MA9
DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR_A_MA6 <17> DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR_B_MA9 <18>
DDR_A_D17 AW65 AY52 DDR_A_MA8 DDR_B_D17 AU66 BA48 DDR_B_MA6
DDR_A_D18 AW63 AW52 DDR_A_MA7 DDR_B_D18 AP65 BB48 DDR_B_MA8
DDR_A_D19 AY63 AY55 DDR_A_BG0 DDR_B_D19 AN65 AP48 DDR_B_MA7
DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR_A_BG0 <17> DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] DDR_B_MA7 <18>
DDR_A_D20 BA65 AW54 DDR_A_MA12 DDR_B_D20 AN66 AP52 DDR_B_BG0
DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR_A_MA12 <17> DDR1_DQ[20]/DDR0_DQ[52] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR_B_BG0 <18>
DDR_A_D21 AY65 BA54 DDR_A_MA11 DDR_B_D21 AP66 AN50 DDR_B_MA12
DDR_A_D22 BA63 BA55 DDR_A_ACT# DDR_B_D22 AT65 AN48 DDR_B_MA11 8/10 Modify for DDR4
DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR_A_ACT# <17> DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] DDR_B_MA11 <18>
DDR_A_D23 BB63 AY54 DDR_A_BG1 DDR_B_D23 AU65 AN53 DDR_B_ACT#
DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR_A_BG1 <17> DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR_B_ACT# <18>
DDR_A_D24 BA61 DDR_B_D24 AT61 AN52 DDR_B_BG1
DDR0_DQ[24]/DDR0_DQ[40] DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR_B_BG1 <18>
DDR_A_D25 AW61 AU46 DDR_A_MA13 DDR_B_D25 AU61 8/10 Modify for DDR4
C DDR0_DQ[25]/DDR0_DQ[41] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] DDR_A_MA13 <17> DDR1_DQ[25]/DDR0_DQ[57] C
DDR_A_D26 BB59 AU48 DDR_A_MA15_CAS# DDR_B_D26 AP60 BA43 DDR_B_MA13
DDR0_DQ[26]/DDR0_DQ[42] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] DDR_A_MA15_CAS# <17> DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] DDR_B_MA13 <18>
DDR_A_D27 AW59 AT46 DDR_A_MA14_WE# DDR_B_D27 AN60 AY43 DDR_B_MA15_CAS#
DDR0_DQ[27]/DDR0_DQ[43] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] DDR_A_MA14_WE# <17> DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] DDR_B_MA15_CAS# <18>
DDR_A_D28 BB61 AU50 DDR_A_MA16_RAS# DDR_B_D28 AN61 AY44 DDR_B_MA14_WE# 9/8 Modify
DDR0_DQ[28]/DDR0_DQ[44] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] DDR_A_MA16_RAS# <17> DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] DDR_B_MA14_WE# <18>
DDR_A_D29 AY61 AU52 DDR_A_BA0 DDR_B_D29 AP61 AW44 DDR_B_MA16_RAS#
DDR0_DQ[29]/DDR0_DQ[45] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDR_A_BA0 <17> DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] DDR_B_MA16_RAS# <18>
DDR_A_D30 BA59 AY51 DDR_A_MA2 DDR_B_D30 AT60 BB44 DDR_B_BA0
DDR0_DQ[30]/DDR0_DQ[46] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] DDR_A_MA2 <17> DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] DDR_B_BA0 <18>
DDR_A_D31 AY59 AT48 DDR_A_BA1 DDR_B_D31 AU60 AY47 DDR_B_MA2
<17> DDR_A_D[32..47] DDR0_DQ[31]/DDR0_DQ[47] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR_A_BA1 <17> <18> DDR_B_D[32..47] DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] DDR_B_MA2 <18>
DDR_A_D32 AY39 AT50 DDR_A_MA10 DDR_B_D32 AU40 BA44 DDR_B_BA1 8/10 Modify for DDR4
DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDR_A_MA10 <17> DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR_B_BA1 <18>
DDR_A_D33 AW39 BB50 DDR_A_MA1 DDR_B_D33 AT40 AW46 DDR_B_MA10
DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR_A_MA1 <17> DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] DDR_B_MA10 <18>
DDR_A_D34 AY37 AY50 DDR_A_MA0 DDR_B_D34 AT37 AY46 DDR_B_MA1
DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] DDR_A_MA0 <17> DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR_B_MA1 <18>
DDR_A_D35 AW37 BA50 DDR_A_MA3 DDR_B_D35 AU37 BA46 DDR_B_MA0
DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] DDR_A_MA3 <17> DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] DDR_B_MA0 <18>
DDR_A_D36 BB39 BB52 DDR_A_MA4 DDR_B_D36 AR40 BB46 DDR_B_MA3
DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] DDR_A_MA4 <17> DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[3] DDR_B_MA3 <18>
DDR_A_D37 BA39 DDR_B_D37 AP40 BA47 DDR_B_MA4
DDR0_DQ[37]/DDR1_DQ[5] DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[4] DDR_B_MA4 <18>
DDR_A_D38 BA37 AM70 DDR_A_DQS#0 DDR_B_D38 AP37
DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSN[0] DDR_A_DQS#0 <17> DDR1_DQ[38]/DDR1_DQ[22]
DDR_A_D39 BB37 AM69 DDR_A_DQS0 DDR_B_D39 AR37 AH66 DDR_B_DQS#0
DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSP[0] DDR_A_DQS0 <17> DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQSN[0]/DDR0_DQSN[2] DDR_B_DQS#0 <18>
DDR_A_D40 AY35 AT69 DDR_A_DQS#1 DDR_B_D40 AT33 AH65 DDR_B_DQS0
DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSN[1] DDR_A_DQS#1 <17> DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQSP[0]/DDR0_DQSP[2] DDR_B_DQS0 <18>
DDR_A_D41 AW35 AT70 DDR_A_DQS1 DDR_B_D41 AU33 AG69 DDR_B_DQS#1
DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQSP[1] DDR_A_DQS1 <17> DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[1]/DDR0_DQSN[3] DDR_B_DQS#1 <18>
DDR_A_D42 AY33 BA64 DDR_A_DQS#2 DDR_B_D42 AU30 AG70 DDR_B_DQS1
DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQSN[2]/DDR0_DQSN[4] DDR_A_DQS#2 <17> DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[1]/DDR0_DQSP[3] DDR_B_DQS1 <18>
DDR_A_D43 AW33 AY64 DDR_A_DQS2 DDR_B_D43 AT30 AR66 DDR_B_DQS#2
DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSP[2]/DDR0_DQSP[4] DDR_A_DQS2 <17> DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[2]/DDR0_DQSN[6] DDR_B_DQS#2 <18>
DDR_A_D44 BB35 AY60 DDR_A_DQS#3 DDR_B_D44 AR33 AR65 DDR_B_DQS2
DDR_A_D45 BA35 BA60 DDR_A_DQS3 DDR_B_D45 AP33 AR61 DDR_B_DQS#3
DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSP[3]/DDR0_DQSP[5] DDR_A_DQS3 <17> DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[3]/DDR0_DQSN[7] DDR_B_DQS#3 <18>
DDR_A_D46 BA33 BA38 DDR_A_DQS#4 DDR_B_D46 AR30 AR60 DDR_B_DQS3
DDR_A_D47 BB33 AY38 DDR_A_DQS4 DDR_B_D47 AP30 AT38 DDR_B_DQS#4
<17> DDR_A_D[48..63] DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSP[4]/DDR1_DQSP[0] DDR_A_DQS4 <17> <18> DDR_B_D[48..63] DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[4]/DDR1_DQSN[2] DDR_B_DQS#4 <18>
DDR_A_D48 AY31 AY34 DDR_A_DQS#5 DDR_B_D48 AU27 AR38 DDR_B_DQS4
DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSN[5]/DDR1_DQSN[1] DDR_A_DQS#5 <17> DDR1_DQ[48] DDR1_DQSP[4]/DDR1_DQSP[2] DDR_B_DQS4 <18>
DDR_A_D49 AW31 BA34 DDR_A_DQS5 DDR_B_D49 AT27 AT32 DDR_B_DQS#5
DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSP[5]/DDR1_DQSP[1] DDR_A_DQS5 <17> DDR1_DQ[49] DDR1_DQSN[5]/DDR1_DQSN[3] DDR_B_DQS#5 <18>
DDR_A_D50 AY29 BA30 DDR_A_DQS#6 DDR_B_D50 AT25 AR32 DDR_B_DQS5
DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSN[6]/DDR1_DQSN[4] DDR_A_DQS#6 <17> DDR1_DQ[50] DDR1_DQSP[5]/DDR1_DQSP[3] DDR_B_DQS5 <18>
DDR_A_D51 AW29 AY30 DDR_A_DQS6 DDR_B_D51 AU25 AR25 DDR_B_DQS#6
DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSP[6]/DDR1_DQSP[4] DDR_A_DQS6 <17> DDR1_DQ[51] DDR1_DQSN[6] DDR_B_DQS#6 <18>
DDR_A_D52 BB31 AY26 DDR_A_DQS#7 DDR_B_D52 AP27 AR27 DDR_B_DQS6
DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSN[7]/DDR1_DQSN[5] DDR_A_DQS#7 <17> DDR1_DQ[52] DDR1_DQSP[6] DDR_B_DQS6 <18>
DDR_A_D53 BA31 BA26 DDR_A_DQS7 DDR_B_D53 AN27 AR22 DDR_B_DQS#7
DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSP[7]/DDR1_DQSP[5] DDR_A_DQS7 <17> DDR1_DQ[53] DDR1_DQSN[7] DDR_B_DQS#7 <18>
DDR_A_D54 BA29 DDR_B_D54 AN25 AR21 DDR_B_DQS7
DDR0_DQ[54]/DDR1_DQ[38] DDR1_DQ[54] DDR1_DQSP[7] DDR_B_DQS7 <18>
DDR_A_D55 BB29 AW50 DDR_A_ALERT# DDR_B_D55 AP25
DDR0_DQ[55]/DDR1_DQ[39] DDR0_ALERT# DDR_A_ALERT# <17> DDR1_DQ[55]
DDR_A_D56 AY27 AT52 DDR_A_PAR DDR_B_D56 AT22 AN43 DDR_B_ALERT#
DDR0_DQ[56]/DDR1_DQ[40] DDR0_PAR DDR_A_PAR <17> DDR1_DQ[56] DDR1_ALERT# DDR_B_ALERT# <18>
DDR_A_D57 AW27 DDR_B_D57 AU22 AP43 DDR_B_PAR
DDR0_DQ[57]/DDR1_DQ[41] DDR1_DQ[57] DDR1_PAR DDR_B_PAR <18>
DDR_A_D58 AY25 AY67 +0.6V_VREFCA DDR_B_D58 AU21 AT13 DDR_DRAMRST#
DDR0_DQ[58]/DDR1_DQ[42] DDR_VREF_CA +0.6V_VREFCA DDR1_DQ[58] DRAM_RESET#
DDR_A_D59 AW25 AY68 DDR_B_D59 AT21 AR18 SM_RCOMP0 RC38 1 2 121_0402_1%
DDR_A_D60 BB27 DDR0_DQ[59]/DDR1_DQ[43] DDR CH - A
DDR0_VREF_DQ BA67 +0.6V_B_VREFDQ DDR_B_D60 AN22 DDR1_DQ[59] DDR_RCOMP[0] AT18 SM_RCOMP1 RC39 1 2 80.6_0402_1%
DDR0_DQ[60]/DDR1_DQ[44] DDR1_VREF_DQ +0.6V_B_VREFDQ DDR1_DQ[60] DDR_RCOMP[1]
B DDR_A_D61 BA27 DDR_B_D61 AP22 DDR CH - B AU18 SM_RCOMP2 RC40 1 2 100_0402_1% B
DDR_A_D62 BA25 DDR0_DQ[61]/DDR1_DQ[45] AW67 DDR_PG_CTRL DDR_B_D62 AP21 DDR1_DQ[61] DDR_RCOMP[2]
DDR_A_D63 BB25 DDR0_DQ[62]/DDR1_DQ[46] DDR_VTT_CNTL DDR_B_D63 AN21 DDR1_DQ[62]
DDR0_DQ[63]/DDR1_DQ[47] 2 OF 20 DDR1_DQ[63] 3 OF 20
SKL-U_BGA1356 SKL-U_BGA1356
+1.2V_VDDQ
For VTT power control
+1.2V_VDDQ
1
+3VS
1
RC904 0.1U_0201_10V6K 2 1 CC57

1
RC905 @ 100K_0402_5%
100K_0402_5% UC7 RC394
@ 1 5 100K_0402_5%
2
NC VCC
2
DDR_PG_CTRL 2
2
A
1
4 SM_PG_CTRL <49>
Y
2
RC906 3 +1.2V_VDDQ
100K_0402_5% GND @ESD@
@ SN74AUP1G07DCKR_SC70-5 DDR_PG_CTRL 1 2
SA00007UR00 CC70 100P_0402_50V8J
2
1
DDR_PG_CTRL 3 1 SM_PG_CTRL
RC32 From ESD Team Request
470_0402_5%
@
2
UC9 SB000008E10
MMBT3904WH NPN SOT323-3 DDR_DRAMRST# 1 2 DDR_DRAMRST#_R DDR_DRAMRST#_R <17,18>
SB00000QJ00,S TR DRC5115E0L NPN SOT323-3 RC33 0_0402_5%
1
CC155
0.1U_0201_10V6K
@ESD@
2 9/8 Modify base on ESD Request
A A
PLACE NEAR TO SoC

SKL-U(2/12)DDRIII
RepairLap.com
5 4 3 2 1
5 4 3 2 1
SML0ALERT# (Internal Pull Down):

eSPI or LPC
SKL-U
UC1E 0 = LPC is selected for EC --> For KB9022/9032 Use
Rev_0.53
SPI - FLASH 1 = eSPI is selected for EC --> For KB9032 Only.
SMBUS, SMLINK
PCH_SPI_CLK AV2
PCH_SPI_SO AW3 SPI0_CLK R7 SMBCLK SML0ALERT#
PCH_SPI_SI AV3 SPI0_MISO GPP_C0/SMBCLK R8 SMBDATA
SMB
PCH_SPI_SIO2 AW2 SPI0_MOSI GPP_C1/SMBDATA R10 SMBALERT# (Link to XDP, DDR, TP)
SPI0_IO2 GPP_C2/SMBALERT# TP@ T239
1
PCH_SPI_SIO3 AU4
PCH_SPI_CS0# AU3 SPI0_IO3 R9 SML0CLK RC218
AU2 SPI0_CS0# GPP_C3/SML0CLK W2 SML0DATA
SPI0_CS1# GPP_C4/SML0DATA 1K_0402_1%
AU1 W1 SML0ALERT#
SPI0_CS2# GPP_C5/SML0ALERT#
2
D W3 SML1CLK D
SPI - TOUCH GPP_C6/SML1CLK V3 SML1DATA
SML1
M2 GPP_C7/SML1DATA AM7 GPP_B23 1 2 SML1ALERT# (Link to EC,DGPU, LAN, Thermal Sensor)
M3 GPP_D1/SPI1_CLK GPP_B23/SML1ALERT#/PCHHOT# RC902 @ +3V_PRIM
J4 GPP_D2/SPI1_MISO 0_0201_5% RC903
V1 GPP_D3/SPI1_MOSI SML1ALERT# 2 @ 1
GPP_D21/SPI1_IO2 TP@ T234
V2 150K_0402_1%
M1 GPP_D22/SPI1_IO3
LPC
GPP_D0/SPI1_CS# AY13 LPC_AD0 SML0ALERT# RC3602 @ 1 10K_0402_5%
GPP_A1/LAD0/ESPI_IO0 LPC_AD0 <26,28> +3VS
BA13 LPC_AD1
C LINK GPP_A2/LAD1/ESPI_IO1 LPC_AD1 <26,28>
BB13 LPC_AD2
GPP_A3/LAD2/ESPI_IO2 LPC_AD2 <26,28>
G3 AY12 LPC_AD3 SMBALERT# 8 1
CL_CLK GPP_A4/LAD3/ESPI_IO3 LPC_AD3 <26,28>
12/11_Delete TP G2 BA12 LPC_FRAME# 7 2
CL_DATA GPP_A5/LFRAME#/ESPI_CS# LPC_FRAME# <26,28>
G1 BA11 SUS_STAT# TP@ T242 EC_KBRST# 6 3
CL_RST# GPP_A14/SUS_STAT#/ESPI_RESET# 5 4
<26> EC_KBRST# EC_KBRST# AW13 AW9 CLK_PCI0 RC387 1 2 22_0402_5% RPC19 10K_0804_8P4R_5%
GPP_A0/RCIN# GPP_A9/CLKOUT_LPC0/ESPI_CLK CLK_PCI_LPC <26>
AY9 CLK_PCI1 RC53 1 TPM@2 22_0402_5% To EC
GPP_A10/CLKOUT_LPC1 CLK_PCI_TPM <28>
To TPM <26,28> SERIRQ SERIRQ AY11 AW11 PM_CLKRUN#
GPP_A6/SERIRQ GPP_A8/CLKRUN# PM_CLKRUN# <26>
5 OF 20 11/28_Follow Intel check list, add PU res
LPC Mode
SKL-U_BGA1356 <SI>un-mount RC53
11/28 CPU side delete EC_PCIE_WAKE#
+3VS +3VS
to SPI ROM UC2 Source From
2
RPH11
C PCH_SPI_CS0#_R 1 8 EC_SPI_CS0# RC216 RC215 C
EC_SPI_CS0# <26>
PCH_SPI_CS0#_R 2 7 PCH_SPI_CS0# 10K_0402_5% 10K_0402_5%
PCH_SPI_SO_R 3 6 EC_SPI_SO
EC_SPI_SO <26>
2
PCH_SPI_SO_R 4 5 PCH_SPI_SO QC1A
1
15_0804_8P4R_5% SMBCLK 6 1
PCH_SMBCLK <17,18,19,22> 11/28_Change PWR rail from +3VS to +3V_PRIM
RPH12 2N7002DWH_SOT363-6
PCH_SPI_HOLD# 1 8 PCH_SPI_SIO3 SB00000I700 +3V_PRIM
5
PCH_SPI_SI_R 2 7 PCH_SPI_SI
PCH_SPI_SI_R 3 6 EC_SPI_SI QC1B
EC_SPI_SI <26>
4 5 SMBDATA 3 4 SML0CLK RC49 1 2 499_0402_1%
PCH_SMBDATA <17,18,19,22>
15_0804_8P4R_5% 2N7002DWH_SOT363-6 SML0DATA RC50 1 2 499_0402_1%
SB00000I700
PCH_SPI_WP# 2 1 PCH_SPI_SIO2 +3VS
RC388 15_0402_5% RPC7
<Cocoa_1020> SML1CLK 1 8
+3V_SPI SML1DATA 2 7
SPI ROM ( 8MByte Only) CC8 add level shift SMBDATA 3 6
UC2 1 2 0.1U_0402_16V7K SMBCLK 4 5
PCH_SPI_CS0#_R 1 8
/CS VCC
2
PCH_SPI_SO_R 2 7 PCH_SPI_HOLD# 2N7002DWH_SOT363-6 1K_0804_8P4R_5%

PCH_SPI_WP# 3 DO(IO1) /HOLD(IO3) 6 PCH_SPI_CLK_R
4 /WP(IO2) CLK 5 PCH_SPI_SI_R SML1CLK 6 1
GND DI(IO0) EC_SMB_CK2 <10,19,22,26,37> +3V_SPI
QC2A 5
W25Q64FVSSIQ_SO8 SA000039A30 SB00000I700
PCB Footprint = ACES_91960-0084L_8P-T PCH_SPI_SIO2 RC3901 @ 2 1K_0402_1%
Use socket footprint SML1DATA 3 4
EC_SMB_DA2 <10,19,22,26,37>
QC2B PCH_SPI_SIO3 RC3911 2 1K_0402_1%
SPI ROM: 2N7002DWH_SOT363-6 @
Main:SA000039A30, S IC FL 64M W25Q64FVSSIQ SOIC
8P SPI ROM SB00000I700
B RC368 2nd :SA00007LA10, S IC FL 64M GD25B64CSIGR SOP B
15_0402_5% 8P SPI ROM
PCH_SPI_CLK 2 1
3rd :SA000099300, S IC FL 64M N25Q064A13ESEDFF
PCH_SPI_CLK_R
SO8W 8P SPI
<DB> PWR Rail @
PCH_SPI_CLK_R <26>
PCH_SPI_CS0#_R 1 2
EMI@ +3V_PRIM +3VALW RC357 1K_0402_5%
1 2
CC9
10P_0402_50V8J
@EMI@
2
RC81 RC82
10K_0402_5% 10K_0402_5%
PCH_SPI_SIO3 RC51 1 ES@ 2 1K_0402_1%
2
SB00000I700
1
SMBCLK 1 6
From WW36 MOW for SKL-U ES sample
TP_SMBCLK <27>
QC7A
2N7002DWH_SOT363-6
5
SMBDATA 4 3 +3VS_PGPPA
TP_SMBDATA <27>
QC7B SB00000I700
2N7002DWH_SOT363-6 PM_CLKRUN# 1 2
RC107 8.2K_0402_5%
EON SA000046400 S IC FL 64M EN25Q64-104HIP SOP 8P SERIRQ 1 2

MXIC SA00006N100 S IC FL 64M MX25L6473EM2I-10G SOP 8P RC122 8.2K_0402_5%
WINBOND SA000039A30 S IC FL 64M W25Q64FVSSIQ SOIC 8P SPI ROM
Micron SA00005L100 S IC FL 64M N25Q064A13ESEC0F SO8W 8P
A Follow 543016_SKL_U_Y_PDG_0_9 A
Security Classification
2014/12/11
Compal Secret Data
2015/12/31 Title
SKL-U(3/12)SPI,ESPI,SMB,LPC
5 4 3 2 1
5 4 3 2 1
UC1G SKL-U
Rev_0.53 +3V_PRIM
D AUDIO D
1
HDA_SYNC BA22 UMA DIS
HDA_BIT_CLK AY22 HDA_SYNC/I2S0_SFRM
HDA_SDOUT BB22 HDA_BLK/I2S0_SCLK RC127
HDA_SDO/I2S0_TXD
SDIO/SDXC PROJECT_ID 0
HDA_SDIN0 BA21 10K_0402_5% 1
<24> HDA_SDIN0 HDA_SDI0/I2S0_RXD
AY21 AB11 PX@
T35 TP@
2
HDA_RST# AW22 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB13 VRAMCLK_SEL
HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0 900MHz 1000MHz
J5 AB12 PROJECT_ID
AY20 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 W12
I2S1_SFRM GPP_G3/SD_DATA2 VRAM Clock 0
1
AW20 W11 1
I2S1_TXD GPP_G4/SD_DATA3 W10 RC128
SOC_GPIOF1 AK7 GPP_G5/SD_CD# W8 10K_0402_5% +3V_PRIM
T38 TP@ GPP_F1/I2S2_SFRM GPP_G6/SD_CLK UMA@
T39 TP@ SOC_GPIOF0 AK6 W7
AK9 GPP_F0/I2S2_SCLK GPP_G7/SD_WP
2
GPP_F2/I2S2_TXD
2
AK10 BA9 X76@
GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 BB9 RC900
GPP_A16/SD_1P8_SEL
10K_0402_5%
H5 AB7 SD_RCOMP RC76 2 1 200_0402_1%
D7 GPP_D19/DMIC_CLK0 SD_RCOMP
1
GPP_D20/DMIC_DATA0
D8 AF13 SOC_GPIOF17 T235 TP@ VRAMCLK_SEL
C8 GPP_D17/DMIC_CLK1 GPP_F23
GPP_D18/DMIC_DATA1
2
X76@
<10,24> HDA_SPKR HDA_SPKR AW5 RC901
GPP_B14/SPKR
10K_0402_5%
7 OF 20
1
SKL-U_BGA1356
C C
HDA for AUDIO

RPC9 <26> ME_FLASH_EN RC367 1 2 0_0402_5%
1 8
<24> HDA_SYNC_AUDIO 2 7 HDA_SYNC
<24> HDA_RST_AUDIO# 3 6 HDA_RST#
2
4 5 HDA_SDOUT +3V_HDA
G
<24> HDA_SDOUT_AUDIO
33_0804_8P4R_5% 1 2 RC380 1 3 HDA_SDOUT
1K_0402_1% QC380
S
@ MESS138W-G_SOT323-3
2 1 HDA_BIT_CLK @
<24> HDA_BITCLK_AUDIO
RC383 33_0402_5%
EMI@ HDA_SDOUT:
ME Flash Descriptor Security Override
CC143 22P_0402_50V8J Low : Disabled(Default)
@EMI@
High : Enabled
SKL_ULT
EMI request UC1I
Rev_0.53
CSI-2
A36 C37
B36 CSI2_DN0 CSI2_CLKN0 D37
B C38 CSI2_DP0 CSI2_CLKP0 C32 B
D38 CSI2_DN1 CSI2_CLKN1 D32
C36 CSI2_DP1 CSI2_CLKP1 C29
D36 CSI2_DN2 CSI2_CLKN2 D29
A38 CSI2_DP2 CSI2_CLKP2 B26
B38 CSI2_DN3 CSI2_CLKN3 A26
CSI2_DP3 CSI2_CLKP3
C31 E13 CSI2_COMP RC80 2 1 100_0402_1%
D31 CSI2_DN4 CSI2_COMP B7
CSI2_DP4 GPP_D4/FLASHTRIG T63 TP@
C33
D33 CSI2_DN5
A31 CSI2_DP5 EMMC
B31 CSI2_DN6 AP2

A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1
B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3
CSI2_DP7 GPP_F15/EMMC_DATA2 AN3
A29 GPP_F16/EMMC_DATA3 AN1
B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
C28 CSI2_DP8 GPP_F18/EMMC_DATA5 AM4
D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
A27 CSI2_DP9 GPP_F20/EMMC_DATA7
B27 CSI2_DN10 AM2
C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3
D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4
CSI2_DP11 GPP_F12/EMMC_CMD
9 OF 20 AT1 EMMC_RCOMP 2 1
EMMC_RCOMP RC89 200_0402_1%
SKL-U_BGA1356
A A
2014/05/19
Compal Secret Data
2015/12/31 Title
SKL-U(4/12)HDA,EMMC,SDIO,CSI2
Size Document Number Rev
RepairLap.com
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
5 4 3 2 1
5 4 3 2 1
+RTCVCC
RC91 1 2 20K_0402_5% PCH_SRTCRST#
CC10 1 2 1U_0402_6.3V6K
CLRP1 1 2 SHORT PADS CLR ME UC1J SKL_ULT

Rev_0.53
CLOCK SIGNALS
RC93 1 2 20K_0402_5% PCH_RTCRST#
CLK_PEG_VGA# D42
<36> CLK_PEG_VGA# CLK_PEG_VGA CLKOUT_PCIE_N0
CC11 1 2 1U_0402_6.3V6K GPU C42
<36> CLK_PEG_VGA VGA_CLKREQ# CLKOUT_PCIE_P0
<37> VGA_CLKREQ# AR10
CLRP2 1 2 GPP_B5/SRCCLKREQ0#
SHORT PADS CLR CMOS
CLK_PCIE_LAN# B42
<23> CLK_PCIE_LAN# CLK_PCIE_LAN CLKOUT_PCIE_N1
LAN A42 F43
D
SM_INTRUDER# <23> CLK_PCIE_LAN LAN_CLKREQ# CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N D
RC941 2 1M_0402_5% <23> LAN_CLKREQ# AT7 E43
GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P
CLK_PCIE_WLAN# D41 BA17 SUSCLK
PCH_RTCRST# 2 <32> CLK_PCIE_WLAN# CLK_PCIE_WLAN CLKOUT_PCIE_N2 GPD8/SUSCLK SUSCLK <32>
@ 1 CLR_CMOS# <26> WLAN C41
<32> CLK_PCIE_WLAN MINI1_CLKREQ# CLKOUT_PCIE_P2 PCH_XTAL24_IN
0_0402_5% R1088 <32> MINI1_CLKREQ# AT8 E37
GPP_B7/SRCCLKREQ2# XTAL24_IN
1
PCH_SRTCRST# 2 @ 1 E35 PCH_XTAL24_OUT
D40 XTAL24_OUT
0_0402_5% R1089 Clear CMOS close to RAM door CLKOUT_PCIE_N3
@ CardReader C40 E42 XCLK_BIASREF RC96 1 2 2.7K_0402_1%
CLKOUT_PCIE_P3 XCLK_BIASREF +1.0V_CLK5_F24NS
JCMOS1 CR_CLKREQ# AT10
0_0603_5% GPP_B8/SRCCLKREQ3# AM18 PCH_RTCX1
2
B40 RTCX1 AM20 PCH_RTCX2

A40 CLKOUT_PCIE_N4 RTCX2
CLKREQ_PCIE#4 AU8 CLKOUT_PCIE_P4 AN18 PCH_SRTCRST#
+3VS GPP_B9/SRCCLKREQ4# SRTCRST# AM16 PCH_RTCRST#
E40 RTCRST#
E38 CLKOUT_PCIE_N5 @
1 2 CLKREQ_PCIE#4 CLKREQ_PCIE#5 AU7 CLKOUT_PCIE_P5 XCLK_BIASREF RC97 1 2 60.4_0402_1%
GPP_B10/SRCCLKREQ5#
RC165 10K_0402_5% From 545659_SKL_PCH_U_Y_EDS_R0_7
1 2 CLKREQ_PCIE#5
RC105 10K_0402_5% <Cocoa_1027> 10 OF 20 <DB> stuf f f or cannonl ake 60oh m1 %
RPC10 check un-use GPIO for termination guidance
8 1 LAN_CLKREQ# SKL-U_BGA1356 <SI> change to SJ10000Q300 , CL=9p
7 2 MINI1_CLKREQ#
6 3 CR_CLKREQ# PCH_XTAL24_IN PCH_RTCX2
5 4
10K_0804_8P4R_5%
1 @ 2 VGA_CLKREQ# <DB> unpop, PD at GPU side PCH PLTRST Buf f er<DB> Romove PLT_RST# buf f er PCH_XTAL24_OUT 1 2 PCH_RTCX1 1 2
+3V_PRIM RC109 10K_0402_5% RC99 1 2 0_0402_5% RC92 1M_0402_5% RC98 10M_0402_5%
+3VS YC1 SJ10000IZ00 YC2

+3VALW_DSW CC145
@ 24MHZ 12PF 20PPM X3G024000DC1H 32.768KHZ 9PF 10PPM 9H03200055
C 1 2 1 2 C
@ 3 1
RPC11 3 1
5
UC8 SJ10000Q800
PCH_PWROK DS12 PLT_RST#_PCH 0.1U_0402_16V7K GND GND
8 1 1
P
IN1
CC15
6.8P_0402_50V8J
6.8P_0402_50V8J
CC16
7 2 LAN_WAKE# 2 1 PCH_PWROK 4 PLT_RST# 1 1
O PLT_RST# <23,26,28,32,36> 4 2
CC12
22P_0402_50V8J
22P_0402_50V8J
CC13
6 3 PCH_RSMRST# 2
IN2
G
5 4 SYS_RESET#
CK0402101V05_0402-2 SN74AHC1G08DCKR_SC70-5
3
10K_0804_8P4R_5% ESD@ 2 2
SCV00001K00
2 1 SYS_RESET#
CLRP3 SHORT PADS <Cocoa_1020>
1 @ 2 SUSCLK 32M use these part (SJ10000NM00, SJ10000MH00) just can meet <50k ohm spec
RC100 1K_0402_5% 24M: SJ10000DI00, SJ10000CS00
2 1 PCH_DPWROK
RC101 100K_0402_5%
<PV> change CC15,CC16 to 6.8p
<MV> change CC15,CC16 to 8.2p
TP@T254
TP@T255
TP@T256
TP@T257
TP@T258
+3VALW_DSW UC1K SKL-U
Rev_0.53
SYSTEM POWER MANAGEMENT
1 2 PM_BATLOW# AT11 PM_SLP_S0#
RC103 8.2K_0402_5% GPP_B12/SLP_S0# AP15 PM_SLP_S3#
PLT_RST#_PCH GPD4/SLP_S3# PM_SLP_S4# PM_SLP_S3# <12,26,35>
1 2 WAKE# AN10 BA16
SYS_RESET# GPP_B13/PLTRST# GPD5/SLP_S4# PM_SLP_S5# PM_SLP_S4# <12,26,35,49>
RC104 1K_0402_5% T296 TP@ B5 AY16
AC_PRESENT_R PCH_RSMRST# SYS_RESET# GPD10/SLP_S5# PM_SLP_S5# <26>
1 2 <26> PCH_RSMRST# AY17
RC106 10K_0402_5% RSMRST# AN15 PM_SLP_SUS#
SLP_SUS# PM_SLP_SUS# <13,26>
@ <DB> RC106 unpop , follow module design T95 TP@ RC102 1 @ 2 1K_0402_5% H_CPUPWRGD A68 AW15 SLP_LAN#
TP@T87
B EC_VCCST_PG B65 PROCPWRGD SLP_LAN# BB17 SLP_WLAN# B
VCCST_PWRGD GPD9/SLP_WLAN# TP@T88
Only For Power Sequence Debug AN16 PM_SLP_A#
+3V_PRIM SYS_PWROK B6 GPD6/SLP_A#
<26> SYS_PWROK SYS_PWROK
PCH_PWROK BA20 BA15 PBTN_OUT#
<26> PCH_PWROK PCH_PWROK GPD3/PWRBTN# PBTN_OUT# <26>
PCH_DPWROK_R BB20 AY15 AC_PRESENT_R 2 1
DSW_PWROK GPD1/ACPRESENT PM_BATLOW# ACIN <26,37>
@ AU13 RC108 0_0402_5%
RC1151 2 10K_0402_5% SOC_VRALERT# PCH_SUSWARN# AR13 GPD0/BATLOW#
<26> PCH_SUSWARN# SUSACK#_R GPP_A13/SUSWARN#/SUSPWRDNACK
<26> SUSACK# 2 1 AP11
RC110 0_0402_5% GPP_A15/SUSACK# AU11 EC_PCIE_WAKE#
GPP_A11/PME# EC_PCIE_WAKE# <26,32>
WAKE# BB15 AP16 SM_INTRUDER#
+3VALW_DSW <32> WAKE# LAN_WAKE# WAKE# INTRUDER#
AM15
AW17 GPD2/LAN_WAKE# AM10 EXT_PWR_GATE#
GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# TP@T298
AT15 AM11 SOC_VRALERT#
T94 TP@ GPD7/RSVD GPP_B2/VRALERT#
11 OF 20
@ ESD@
DS13
RC111 2 1 100K_0402_5% PBTN_OUT# SCV00001K00
SKL-U_BGA1356
1 2 H_CPUPWRGD
CK0402101V05_0402-2 <DB> add ESD protection

@ESD@
DS14
SCV00001K00
1 2 SUSACK#
CK0402101V05_0402-2 DC3 SCS00003500

CH751H-40PT_SOD323-2
@ESD@ PCH_RSMRST# 1 2 PCH_PWROK
DS15
SCV00001K00
1 2 SYS_PWROK
11/28 add RSMRST protect circuit
2 1 SPOK <48>
DC4 SCS00003500
CK0402101V05_0402-2 CH751H-40PT_SOD323-2
<26> PCH_DPWROK 2 1 PCH_DPWROK_R

A RC112 0_0402_5% A
+1.0V_VCCST
From EC(open-drain)
1
RC113
1K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
2
RC1161 2 60.4_0402_1% EC_VCCST_PG

<26,35> EC_VCCST_PG_R
SKL-U(5/12)CLK,GPIO
RepairLap.com
5 4 3 2 1
5 4 3 2 1
UC1F SKL-U +3VS

Rev_0.53
LPSS ISH
<DB>
AN8
AP7 GPP_B15/GSPI0_CS# P2 DGPU_PWR_EN RC3821 2 10K_0402_5%
GPP_B16/GSPI0_CLK GPP_D9 TS_GPIO_CPU <20>
AP8 P3
GSPI0_MOSI AR7 GPP_B17/GSPI0_MISO GPP_D10 P4
GPP_B18/GSPI0_MOSI GPP_D11 @
P1 +3V_PRIM
AM5 GPP_D12
AN7 GPP_B19/GSPI1_CS# M4
D GPP_B20/GSPI1_CLK GPP_D5/ISH_I2C0_SDA D
SOC_GPIOB21 AP5 N3 RPC14
GSPI1_MOSI AN5 GPP_B21/GSPI1_MISO GPP_D6/ISH_I2C0_SCL SOC_GPIOB21 1 8
<DB> add TP by BIOS GPP_B22/GSPI1_MOSI
12/11_Delete TP
N1 2 7
TP@T129 UART_0_CRXD_DTXD AB1 GPP_D7/ISH_I2C1_SDA N2 WL_OFF# 3 6
TP@T128 UART_0_CTXD_DRXD AB2 GPP_C8/UART0_RXD GPP_D8/ISH_I2C1_SCL <5,26> NMI_DBG#_CPU NMI_DBG#_CPU 4 5
W4 GPP_C9/UART0_TXD AD11
WL_OFF# AB3 GPP_C10/UART0_RTS# GPP_F10/I2C5_SDA/ISH_I2C2_SDA AD12 10K_0804_8P4R_5%
<32> WL_OFF# GPP_C11/UART0_CTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL
TP@T133 UART_2_CRXD_DTXD AD1
TP@T132 UART_2_CTXD_DRXD AD2 GPP_C20/UART2_RXD U1
AD3 GPP_C21/UART2_TXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA U2
UART_2_CTXD_DRXD AD4 GPP_C22/UART2_RTS# GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL U3
GPP_C23/UART2_CTS# GPP_D15/ISH_UART0_RTS#
1
U4
R5194 GPP_D16/ISH_UART0_CTS#/SML0BALERT#
@ 0_0402_5% U7 AC1 DGPU_PWR_EN
GPP_C16/I2C0_SDA GPP_C12/UART1_RXD/ISH_UART1_RXD DGPU_PWR_EN <26,38,55,56>
U6 AC2 DGPU_HOLD_RST#
UART_2_CRXD_DTXD GPP_C17/I2C0_SCL GPP_C13/UART1_TXD/ISH_UART1_TXD DGPU_HOLD_RST# <36>
AC3
2
U8 GPP_C14/UART1_RTS#/ISH_UART1_RTS# AB4
GPP_C18/I2C1_SDA GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPU_PGD <56>
U9
GPP_C19/I2C1_SCL AY8
AH9 GPP_A18/ISH_GP0 BA8
AH10 GPP_F4/I2C2_SDA GPP_A19/ISH_GP1 BB7
GPP_F5/I2C2_SCL GPP_A20/ISH_GP2 BA7 ODD_PWR RPC12 +3VS
GPP_A21/ISH_GP3 ODD_DA# ODD_PWR <30>
AH11 AY7 ODD_DA# <30> 1 8
AH12 GPP_F6/I2C3_SDA GPP_A22/ISH_GP4 AW7 EC_SCI# 2 7
GPP_F7/I2C3_SCL GPP_A23/ISH_GP5 <Cocoa_1027> <5,26> EC_SCI#
AP13 SOC_GPIOA12 T122 TP@ ODD_PWR 3 6
AF11 GPP_A12/BM_BUSY#/ISH_GP6 Follow #544669 GPIO I/O setting ODD_DA# 4 5
AF12 GPP_F8/I2C4_SDA
GPP_F9/I2C4_SCL 6 OF 20 <Cocoa_1127> remove EC_LID_OUT# function 10K_0804_8P4R_5%
SKL-U_BGA1356
C +3VS
CPU THERMAL SENSOR C
<Cocoa_1020>
Follow BDW
0.1U_0402_16V7K
Functional Strap Definitions Strap Pin
CC127
1 Thermal sensor SMBus address -->100-1_100xb : 0x4C
+3VS
(x=0)Write Address(0x98h)
(x=1)Read Address(0x99h)
2
SPKR (Internal Pull Down): @ UC3
RC117 1 2 100K_0402_5% HDA_SPKR 1 8 EC_SMB_CK2
HDA_SPKR <8,24> VDD SCLK EC_SMB_CK2 <7,19,22,26,37>
TOP Swap Override
@ H_THERMDA 2 7 EC_SMB_DA2
GSPI0_MOSI +3VS D+ SDATA EC_SMB_DA2 <7,19,22,26,37>
RC118 1 2 4.7K_0402_5% CC14
0 = Disable TOP Swap mode.---> AAX05 Use 1 2 H_THERMDC 3 6 THERMAL_ALERT# 2 1
D- ALERT# +3VS
@ 2200P_0402_50V7K RC44 10K_0402_5%
1 = Enable TOP Swap Mode. RC201 1 2 150K_0402_1% GSPI1_MOSI 1 2 CPU_THERM# 4 5
RC45 33K_0402_5% THERM# GND
1105_Modify schematic NCT7718W_MSOP8

SA000067P00
GSPI0_MOSI (Internal Pull Down): Thermal sensor:
Main:SA000067P00, S IC NCT7718W MSOP 8P THEMAL SENSOR(Nuvoton)
<Cocoa_1020> 2nd : SA00007WP00, S IC F75397M MSOP 8P THEMAL SENSOR(Fintek)
No Reboot 1K ohm for 400kHz speed/ 0.5k ohm for 1MHz speed 3rd : SA007810140, S IC G781P8F MSOP 8P TEMP. SENSOR(GMT)
0 = Disable No Reboot mode. --> AAX05 Use
1 = Enable No Reboot Mode. (PCH will disable the TCO

Timer system reboot feature). This function is useful
when running ITP/XDP. <DB>
Delete Win7 debug port
B B
GSPI1_MOSI (Internal Pull Down):
Boot BIOS Strap Bit
0 = SPI Mode --> AAX05 Use
1 = LPC Mode
A A

SKL-U(6/12)GPIO
RepairLap.com
5 4 3 2 1
5 4 3 2 1
UC1H SKL-U
Rev_0.53
SSIC / USB3
<DB> Change to 0.22uF for Gen3 PCIE/USB3/SATA
H8 USB3_RX1_N <31>
USB3_1_RXN G8
PEG_PRX_C_DTX_N0 H13 USB3_1_RXP C13
USB3_RX1_P <31> USB2.0/USB3.0
<36> PEG_PRX_C_DTX_N0 PCIE1_RXN/USB3_5_RXN USB3_1_TXN USB3_TX1_N <31>
<36> PEG_PRX_C_DTX_P0 PEG_PRX_C_DTX_P0 G13 D13
PCIE1_RXP/USB3_5_RXP USB3_1_TXP USB3_TX1_P <31>
CC119 0.22U 6.3V K X5R 0402 2 1 PX@ PEG_PTX_DRX_N0 B17
<36> PEG_PTX_C_DRX_N0 PCIE1_TXN/USB3_5_TXN
CC146 0.22U 6.3V K X5R 0402 2 1 PX@ PEG_PTX_DRX_P0 A17 J6
<36> PEG_PTX_C_DRX_P0 PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_1_RXN H6
PEG_PRX_C_DTX_N1 G11 USB3_2_RXP/SSIC_1_RXP B13
D <36> PEG_PRX_C_DTX_N1 D
PEG_PRX_C_DTX_P1 F11 PCIE2_RXN/USB3_6_RXN USB3_2_TXN/SSIC_1_TXN A13
<36> PEG_PRX_C_DTX_P1 PCIE2_RXP/USB3_6_RXP USB3_2_TXP/SSIC_1_TXP
CC128 0.22U 6.3V K X5R 0402 2 1 PX@ PEG_PTX_DRX_N1 D16
<36> PEG_PTX_C_DRX_N1 PCIE2_TXN/USB3_6_TXN
CC93 0.22U 6.3V K X5R 0402 2 1 PX@ PEG_PTX_DRX_P1 C16 J10
<36> PEG_PTX_C_DRX_P1 PCIE2_TXP/USB3_6_TXP USB3_3_RXN/SSIC_2_RXN H10
PEG_PRX_C_DTX_N2 H16 USB3_3_RXP/SSIC_2_RXP B15
PEG <36> PEG_PRX_C_DTX_N2
PEG_PRX_C_DTX_P2 PCIE3_RXN USB3_3_TXN/SSIC_2_TXN
<36> PEG_PRX_C_DTX_P2 G16 A15
CC124 0.22U 6.3V K X5R 0402 2 1 PX@ PEG_PTX_DRX_N2 D17 PCIE3_RXP USB3_3_TXP/SSIC_2_TXP
<36> PEG_PTX_C_DRX_N2 PCIE3_TXN
CC92 0.22U 6.3V K X5R 0402 2 1 PX@ PEG_PTX_DRX_P2 C17 E10
<36> PEG_PTX_C_DRX_P2 PCIE3_TXP USB3_4_RXN F10
PEG_PRX_C_DTX_N3 G15 USB3_4_RXP C15
<36> PEG_PRX_C_DTX_N3 PCIE4_RXN USB3_4_TXN
<36> PEG_PRX_C_DTX_P3 PEG_PRX_C_DTX_P3 F15 D15
CC129 0.22U 6.3V K X5R 0402 2 1 PX@ PEG_PTX_DRX_N3 B19 PCIE4_RXP USB3_4_TXP
<36> PEG_PTX_C_DRX_N3 PCIE4_TXN
CC118 0.22U 6.3V K X5R 0402 2 1 PX@ PEG_PTX_DRX_P3 A19 AB9
<36> PEG_PTX_C_DRX_P3 PCIE4_TXP USB2N_1 USB20_N1 <31>
AB10 USB2.0/USB3.0
USB2P_1 USB20_P1 <31>
<23> PCIE_PRX_DTX_N5 PCIE_PRX_DTX_N5 F16
PCIE_PRX_DTX_P5 E16 PCIE5_RXN AD6
LAN <23> PCIE_PRX_DTX_P5
PCIE_PTX_DRX_N5 PCIE5_RXP USB2N_2 USB20_N2 <31>
CC18 2 1 0.1U_0402_16V7K C19 AD7 USB2.0
<23> PCIE_PTX_C_DRX_N5 PCIE5_TXN USB2P_2 USB20_P2 <31>
CC17 2 1 0.1U_0402_16V7K PCIE_PTX_DRX_P5 D19
<23> PCIE_PTX_C_DRX_P5 PCIE5_TXP AH3
USB2N_3 USB20_N3 <33>
<32> PCIE_PRX_DTX_N6 PCIE_PRX_DTX_N6 G18 AJ3 USB2.0 ( on small board )
PCIE6_RXN USB2P_3 USB20_P3 <33>
<32> PCIE_PRX_DTX_P6 PCIE_PRX_DTX_P6 F18
CC20 2 1 0.1U_0402_16V7K PCIE_PTX_DRX_N6 D20 PCIE6_RXP AD9
WLAN <32> PCIE_PTX_C_DRX_N6
CC19 2 1 0.1U_0402_16V7K PCIE_PTX_DRX_P6 C20 PCIE6_TXN USB2N_4 AD10
USB20_N4 <32>
<32> PCIE_PTX_C_DRX_P6 PCIE6_TXP USB2P_4 USB20_P4 <32> WLAN
<30> SATA_PRX_DTX_N0 F20 AJ1
PCIE7_RXN/SATA0_RXN USB2N_5 USB20_N5 <20>
<30> SATA_PRX_DTX_P0 E20 AJ2 Camera
PCIE7_RXP/SATA0_RXP USB2P_5 USB20_P5 <20>
HDD B21 USB2
<30> SATA_PTX_DRX_N0 PCIE7_TXN/SATA0_TXN
A21 AF6
<30> SATA_PTX_DRX_P0 PCIE7_TXP/SATA0_TXP USB2N_6 USB20_N6 <20>
C AF7 Touch Screen C
USB2P_6 USB20_P6 <20>
<30> SATA_PRX_DTX_N1 G21
F21 PCIE8_RXN/SATA1A_RXN AH1
<30> SATA_PRX_DTX_P1 PCIE8_RXP/SATA1A_RXP USB2N_7 USB20_N7 <33>
ODD D21 AH2 Card Reader
<30> SATA_PTX_DRX_N1 PCIE8_TXN/SATA1A_TXN USB2P_7 USB20_P7 <33>
C21
<30> SATA_PTX_DRX_P1 PCIE8_TXP/SATA1A_TXP AF8
E22 USB2N_8 AF9
E23 PCIE9_RXN USB2P_8
B23 PCIE9_RXP AG1
A23 PCIE9_TXN USB2N_9 AG2
PCIE9_TXP USB2P_9
F25 AH7
E25 PCIE10_RXN USB2N_10 AH8
D23 PCIE10_RXP USB2P_10
C23 PCIE10_TXN AB6 USB2_COMP RC119 1 2 113_0402_1%
PCIE10_TXP USB2_COMP AG3 USB2_ID
RC1201 2 100_0402_1% PCIE_RCOMPN F5 USB2_ID AG4 USB2_VBUSSENSE
PCIE_RCOMPP E5 PCIE_RCOMPN USB2_VBUSSENSE
PCIE_RCOMPP A9 USB_OC0#
T291 TP@ XDP_PRDY# D56 GPP_E9/USB2_OC0# C9 USB_OC1# <SI> follow EDS to add 1K ohm PD
XDP_PREQ# D61 PROC_PRDY# GPP_E10/USB2_OC1# D9 USB_OC2#
<5> XDP_PREQ# PROC_PREQ# GPP_E11/USB2_OC2#
T154 TP@ SOC_GPIOA7 BB11 B9 USB_OC3# USB2_ID RC20 1 2 0_0402_5%
GPP_A7/PIRQA# GPP_E12/USB2_OC3#
E28 J1 DEVSLP0 T243 TP@
E27 PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 J2 DEVSLP1 USB2_VBUSSENSE 1 2
D24 PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 J3 DEVSLP2 RC21 0_0402_5%
PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2 T241 TP@ <DB> PU
C24
E30 PCIE11_TXP/SATA1B_TXP H2 SATA_GP0
F30 PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0 H3 ODD_PLUG#
B PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 ODD_PLUG# <30> B
A25 G4 SATA_GP2
B25 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2
PCIE12_TXP/SATA2_TXP H1 SATA_LED#
GPP_E8/SATALED# SATA_LED# <33>
8 OF 20 +3VS
SKL-U_BGA1356
DEVSLP1 1 2
SOC_GPIOA7 RC3621 2 10K_0402_5%
RC361 10K_0402_5%
GPIO DEVICE CONTROL
When PCIE8/SATA1A is used RPC13
USB_OC0# USB2 Port 1 and Port 2 SATA_LED# 1 8
as SATA Port 1 (ODD), then SATA_GP0 2 7
PCIE11/SATA1B (M.2 SSD) USB_OC1# USB2 Port 3 SATA_GP2 3 6
cannot be used as SATA ODD_PLUG# 4 5
Port 1. USB_OC2# NA 10K_0804_8P4R_5%
USB_OC3# NA +3V_PRIM
DEVSLP0 NA RPC20
USB_OC1# 1 8
DEVSLP1 NGFF SSD KEY B USB_OC3# 2 7
USB_OC0# 3 6
USB_OC2# 4 5
DEVSLP2 NA
10K_0804_8P4R_5%
SATA_GP0 NA
A NA A
SATA_GP1 1128_Add pull high resistor
SATA_GP2 ODD_PLUG#
2014/05/19
Compal Secret Data
2015/12/31 Title
SKL-U(7/12)PCIE,USB,SATA
RepairLap.com
5 4 3 2 1
5 4 3 2 1
+1.0V_PRIM TO +1.0V_VCCSTU
+1.2V_VDDQ +1.0VS_VCCIO
UC1N SKL-U
Rev_0.53
1211_Delete jump RC147 +5VALW +1.0V_PRIM +1.0VS_VCCIO +1.0V_VCCSTU CPU POWER 3 OF 4
<DB> Delete RC145
AU23 AK28
AU28 VDDQ_AU23 VCCIO AK30
R5188 1 @ 2 0_0603_5% AU35 VDDQ_AU28 VCCIO AL30
VDDQ_AU35 VCCIO
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 AU42 AL42
VDDQ_AU42 VCCIO
CC98
CC97
0.1U_0402_25V6
I (Max) : 0.04 A(+1.0V_VCCSTU) 1 BB23 AM28
VDDQ_BB23 VCCIO
0.1U_0402_25V6
CC96
D 1@ RON(Max) : 25 mohm BB32 AM30 D
VDDQ_BB32 VCCIO
CC151
@ BB41 AM42
2 2 V drop : 0.001 V BB47 VDDQ_BB41 VCCIO
2 BB51 VDDQ_BB47 AK23
2 VDDQ_BB51 VCCSA +VCC_SA
AK25
UC5 VCCSA G23
1 14 AM40 VCCSA G25
VIN1 VOUT1 +1.2V_VDDQC VDDQC VCCSA
RC142 1 2 0_0402_5% 2 13 G27
<26,35,49> SYSON VIN1 VOUT1 A18 VCCSA G28
+1.0V_VCCST VCCST VCCSA
RC144 1 @ 2 0_0402_5% EN_1.0V_VCCSTU 3 12 1 2 J22
<9,26,35,49> PM_SLP_S4# ON1 CT1 CC95 A22 VCCSA J23
+1.0VS_VCCIO VCCSTG_A22 VCCSA
RC168 1 2 0_0402_5% 4 11 10P_0402_50V8J J27
<13,26,35,49> SUSP# VBIAS GND AL23 VCCSA K23
+1.2V_VCCSFR_OC VCCPLL_OC VCCSA
RC194 1 @ 2 0_0402_5% EN_1.8VS 5 10 1 2 K25
<9,26,35> PM_SLP_S3# ON2 CT2 @ CC94 K20 VCCSA K27
+1.0V_VCCSFR VCCPLL_K20 VCCSA
6 9 1000P_0402_50V7K K21 K28
+1.8V_PRIM 7 VIN2 VOUT2 8 VCCPLL_K21 VCCSA K30
VIN2 VOUT2 +1.8VS VCCSA
15 AM23 VCCIO_SENSE T124 TP@
GPAD VCCIO_SENSE AM22 VSSIO_SENSE
VSSIO_SENSE T125 TP@
EM5209VF_DFN14_2X3 <Cocoa_1113>
1U_0402_6.3V6K
1 SA00007PM00 @ESD@ 1 1 H21 VSSSA_SENSE
CC99 CC156 Per VSSSA_SENSE H20 VCCSA_SENSE
VSSSA_SENSE <52>
CC100 VCCSA_SENSE <52>
I (Max) : 0.536 A(+1.8VS) 543977_SKL_PDDG_Rev0_91, 14 OF 20 VCCSA_SENSE
@ 0.1U_0402_25V6 change CC95 value from
2 RON(Max) : 25 mohm 0.1U_0402_25V6 2 2
V drop : 0.013 V 1000pf to 10pf for meet SKL-U_BGA1356
<= 65us timing for
1210_Delete jump RC146 +1.0V_VCCSTU power rail.
C C
<DB> change +1.35V_VDDQ
+1.0V_VCCSTU +1.0V_VCCST
RC140 1 2 0_0402_5%
PSC Side
+1.0V_PRIM TO +1.0VS_VCCSTG / +1.0VS_VCCIO
1U_0402_6.3V6K
1
CC48
+5VALW +1.0V_PRIM I (Max) : 3 A(+1.0VS_VCCIO) +1.0VS_VCCIO
2
RON(Max) : 6.2 mohm near pin A22
V drop : 0.019 V @
0.1U_0402_25V6
1U_0402_6.3V6K
1 1 Imax : 2.77 A CC89 1 2 0.1U_0402_25V6

CC88
CC117
<PV> change short pad

UC6 RC208 Follow 544669_SKL_U__DDR3L_RVP7_Schematic_Rev1.0
1 +1.0VS_VCCIO
2@ 2 2 VIN1
VIN2 RC189 +1.0V_VCCSFR +1.0VS_VCCIO
7 6 +1.0VS_VCCSTG_IO 1 2 0_0805_5% CC90 1 2 0.1U_0402_25V6
VIN thermal VOUT
PSC Side BSC Side
3 Imax : 3 A RC143 1 2 0_0402_5%
VBIAS
1U_0402_6.3V6K
SUSP# RC186 1 2 0_0402_5% 4 5 1
ON GND
1U_0402_6.3V6K
B
1 B
CC56
RC187 1 2 0_0402_5%
<26> EC_S0IX_EN
CC55
@ TPS22961DNYR_WSON8
2
2
Part Number = SA00007XR00
For Verify S0IX <Cocoa_1027>
connect to EC, check /w EC <DB> change +1.35V_VDDQ
RC208 Follow 544669_SKL_U__DDR3L_RVP7_Schematic_Rev0_53
<DB> change +1.35V_VDDQ
+1.0VS_VCCIO +1.2V_VDDQ +1.2V_VDDQC +1.2V_VDDQ
BSC Side PSC Side PSC Side BSC Side
RC208 BSC Side
1 2 0_0603_5%
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0201_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CC27
CC28
CC29
CC30
CC31
CC32
CC33
CC34
CC35
CC36
CC47
CC37
CC38
CC39
CC40
CC41
CC42
CC43
CC44
CC45
CC46
CC47 Follow 543016_SKL_U_Y_PDG_0_9
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
+1.35V_VDDQ_CPU : 10UF/6.3V/0603 *6
A 1UF/6.3V/0402 * 4 A
2014/12/11
Compal Secret Data
2015/12/31 Title
SKL-U(8/12)Power
RepairLap.com
5 4 3 2 1
5 4 3 2 1
+1.0V_PRIM
+1.0V_PRIM
+1.0V_PRIM +1.0V_APLL +3V_PRIM +3V_HDA
1U_0201_6.3V6K
1
UC1O SKL-U
22U_0603_6.3V6M
22U_0603_6.3V6M
1U_0402_6.3V6K
CC91
Rev_0.53 1209_follow G group GPIO
CPU POWER 4 OF 4
RC148 1 2 0_0603_5% RC150 1 2 0_0402_5% 1 1 1 powe rail to +3V_PRIM
2
22U_0603_6.3V6M
22U_0603_6.3V6M
CC147
CC148
CC61
AB19
AB20 VCCPRIM_1P0 AK15
1 1 VCCPRIM_1P0 VCCPGPPA +3V_PGPPA
CC142
CC134
1U_0402_6.3V6K
1 1 near pin K15,L15 @ @ P18 AG15 +3V_PGPPB
CC63 2 2 @2 VCCPRIM_1P0 VCCPGPPB Y16
VCCPGPPC +3V_PGPPC
CC72
@ @ 1U_0201_6.3V6K +1.0V_PRIM AF18 Y15 +3V_1.8V_PGPPD
2 2 AF19 VCCPRIM_CORE VCCPGPPD T16
2 2 +1.0VO_DSW VCCPRIM_CORE VCCPGPPE +3V_PGPPE
V20 AF16 +1.8V_PRIM
V21 VCCPRIM_CORE VCCPGPPF AD15
VCCPRIM_CORE VCCPGPPG +3V_PRIM For SD CARD
D D
+1.0V_PRIM AL1 V19 +3V_PRIM
DCPDSW_1P0 VCCPRIM_3P3_V19
1U_0402_6.3V6K
Follow 543016_SKL_U_Y_PDG_1_0 1 +1.0V_MPHYAON K17 T1 +1.0V_DTS
L1 VCCMPHYAON_1P0 VCCPRIM_1P0_T1
+3V_PGPPA VCCMPHYAON_1P0
1U_0402_6.3V6K
CC85
+1.0V_CLK5_F24NS AA1 +1.8V_PRIM
+3V_PRIM N15 VCCATS_1P8
2 +1.0V_PRIM VCCMPHYGT_1P0_N15
CC68
1 N16 AK17 +3V_PRIM_RTC
RC152 1 2 0_0603_5% N17 VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3
P15 VCCMPHYGT_1P0_N17 AK19
near pin N18 VCCMPHYGT_1P0_P15 VCCRTC_AK19 +RTCVCC
22U_0603_6.3V6M
22U_0603_6.3V6M
P16 BB14
2 VCCMPHYGT_1P0_P16 VCCRTC_BB14
1 1
CC135
CC130
+1.0V_PRIM K15 BB10 CC71 1 2 0.1U_0402_10V7K

RC197 1 2 0_0402_5% L15 VCCAMPHYPLL_1P0 DCPRTC
@ @ VCCAMPHYPLL_1P0 A14
2 2 VCCCLK1 +1.0V_CLK6_24TBT
+3V_SPI +1.0V_APLL V15
VCCAPLL_1P0 K19
VCCCLK2
1U_0402_6.3V6K
1 +1.0V_PRIM AB17
Y18 VCCPRIM_1P0_AB17 L21
CC67 VCCPRIM_1P0_Y18 VCCCLK3 +1.0V_APLL
@ RC154 1 2 0_0402_5%
+1.0V_PRIM +3VALW_DSW AD17 N20 +1.0V_CLK4_F100OC
2 AD18 VCCDSW_3P3_AD17 VCCCLK4
AJ17 VCCDSW_3P3_AD18 L19
<DB>Check Power Rail VCCDSW_3P3_AJ17 VCCCLK5 +1.0V_CLK5_F24NS
+1.0V_CLK4_F100OC +3V_PGPPB
+3V_HDA AJ19 A10 +1.0V_CLK6_24TBT
VCCHDA VCCCLK6
1U_0201_6.3V6K
1
RC190 1 2 0_0603_5% near pin AF20, AJ16 AN11 PRIMCORE_VID0 T130 TP@
+3V_SPI VCCSPI GPP_B0/CORE_VID0
CC141
RC161 1 2 0_0402_5% AN13 PRIMCORE_VID1 T131 TP@
AF21,T19, T20 GPP_B1/CORE_VID1
22U_0603_6.3V6M
22U_0603_6.3V6M
+1.0V_PRIM AF20
2 VCCSRAM_1P0
1U_0402_6.3V6K
1 1 1 AF21
VCCSRAM_1P0
CC136
CC137
T19
VCCSRAM_1P0
CC102
T20
@ @ VCCSRAM_1P0
2 2 2 AJ21
+3V_PRIM VCCPRIM_3P3_AJ21
+1.0V_PRIM AK20
C +1.0V_PRIM VCCPRIM_1P0_AK20 <DB> RTC BAT Conn C
+1.0V_PRIM N18
+3V_PGPPC VCCAPLLEBB 15 OF 20
+RTCBATT
+1.0V_PRIM
SKL-U_BGA1356
JRTC1
Imax : 2.57A RC163 1 2 0_0402_5% near pin N15, N16,
1U_0402_6.3V6K
22U_0603_6.3V6M
22U_0603_6.3V6M
1U_0402_6.3V6K N17,P15,P16 1 1 1 20mils
CC81
CC82
1 2 1
- +
1U_0402_6.3V6K
CC80
1
RTC Battery
CC73
2 2 2
CC76
near pin AF18, 2

AF19,V20,V21 @ MAX. 8000mil
2 Per 543016_SKL_U_Y_PDG_0_9
CONN@
VCCRTC does not exceed 3.2 V From PDG
<Diner-DB> change to +3V_PRIM LOTES_AAA-BAT-054-K01
CC7 Close UC1.AK19. SP07000H700
+3V_1.8V_PGPPD +1.8V_PRIM
Power Rail Voltage +RTCBATT_R +RTCBATT
+1.0V_MPHYAON +RTCVCC
1K_0402_5%
RC1721 2 0_0402_5% RC2061 @ 2 0_0402_5% +CHGRTC 3.383V(MAX) RC19
DC1 15mils 15mils
1U_0402_6.3V6K
RC175 1 2 0_0402_5% 1 15mils 2 2 1

@ BAT54C(VF) 240 mV 1
CC103
1 3 +3VL
1U_0402_6.3V6K
1 CC7
2 +3VL_RTC 3.143V 1U_0201_6.3V6K BAV70W 3P C/C_SOT-323
CC87
2 SC600000B00
2 Result : Pass
+3V_PGPPE
B B
+1.0V_CLK6_24TBT RC167 1 2 0_0402_5%
+3VALW TO +3V_PRIM
1U_0402_6.3V6K
1
RC169 1 2 0_0603_5%
CC74
I (Max) : 0.46 A(+3V_PRIM)+3VALW +3V_PRIM

22U_0603_6.3V6M
22U_0603_6.3V6M
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1
+5VALW +3VALW
RDS(Typ) : 65 mohm
CC138
CC139
V drop : 0.03 V
CC86
CC75
@ @ @ @ 1 2 0_0805_5%
2 2 2 2 RC393
1U_0402_6.3V6K
1U_0402_6.3V6K
+3V_PRIM_RTC 1@ 1@ For NON-DS3
CC52
CC50
For DS3 +3V_PRIMJP 1 @ 2 0_0805_5%
0.1U_0402_25V6
RC159 1
2 2
CC51
RC171 1 2 0_0402_5%
0.1U_0201_10V6K
+1.0V_DTS
1U_0402_6.3V6K
1 1 For DS3
2
CC78
UC4
CC77
1 14
RC162 1 2 0_0402_5% RC191 1 2 0_0402_5% 2 VIN1 VOUT1 13
2 2 <26,35,51> PCH_PWR_EN VIN1 VOUT1 @
RC174 1 @ 2 0_0402_5% EN_3V_PRIM 3 12 CC53 1 2
<9,26> PM_SLP_SUS# ON1 CT1 1000P_0402_50V7K
4 11
VBIAS GND
RC392 1 2 5 10 CC1491 2
<12,26,35,49> SUSP# 0_0402_5% ON2 CT2 1000P_0402_50V7K
6 9
7 VIN2 VOUT2 8
Follow 543016_SKL_U_Y_PDG_0_9 VIN2 VOUT2
15
+1.0V_PRIM +3V_PRIM +1.8V_PRIM +1.2V_VDDQ GPAD
EM5209VF_DFN14_2X3 +1.2V_VCCSFR_OC
A
+3VS +3VS_PGPPA SA00007PM00 A
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0201_10V6K
1 RC141 1 @ 2 0_0402_5%
CC150
1 1 1 1 1 1 1
CC111
CC112
CC113
CC114
CC116
CC115
CC49
RC178 1 2 0_0402_5%
@ @ @ @ @ @ 2
2 2 2 2 2 2 2
+3VALW +3VALW_DSW

RC173 1 2 0_0603_5% 2014/12/11 2015/12/31 Title
SKL-U(9/12)Power
RepairLap.com
Follow 543016_SKL_U_Y_PDG_0_9 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
5 4 3 2 1
5 4 3 2 1
+VCC_CORE +VCC_CORE +VCC_GT +VCC_GT

UC1M SKL-U
UC1L SKL-U Rev_0.53
Rev_0.53 CPU POWER 2 OF 4
CPU POWER 1 OF 4
N70
A30 G32 A48 VCCGT N71
A34 VCC_A30 VCC_G32 G33 A53 VCCGT VCCGT R63
D D
AK33 VCC_A44 VCC_G37 G38 A66 VCCGT VCCGT R66
AK35 VCC_AK33 VCC_G38 G40 AA63 VCCGT VCCGT R67
AK37 VCC_AK35 VCC_G40 G42 AA64 VCCGT VCCGT R68
AK38 VCC_AK37 VCC_G42 J30 AA66 VCCGT VCCGT R69
AK40 VCC_AK38 VCC_J30 J33 AA67 VCCGT VCCGT R70
AL33 VCC_AK40 VCC_J33 J37 AA69 VCCGT VCCGT R71
AL37 VCC_AL33 VCC_J37 J40 AA70 VCCGT VCCGT T62
AL40 VCC_AL37 VCC_J40 K33 AA71 VCCGT VCCGT U65
AM32 VCC_AL40 VCC_K33 K35 AC64 VCCGT VCCGT U68
AM33 VCC_AM32 VCC_K35 K37 AC65 VCCGT VCCGT U71
AM35 VCC_AM33 VCC_K37 K38 AC66 VCCGT VCCGT W63
VCC_AM38 VCC_K42 VCCGT VCCGT
G30
VCC_G30 VCC_K43
K43 Trace Length < 25 mils AC69
VCCGT VCCGT
W66
AC70 W67
K32 E32 AC71 VCCGT VCCGT W68
T123 TP@ RSVD_K32 VCC_SENSE VCCSENSE <52> VCCGT VCCGT
E33 J43 W69
VSS_SENSE VSSSENSE <52> VCCGT VCCGT
T121 TP@ AK32 J45 W70
RSVD_AK32 B63 SOC_SVID_ALERT# J46 VCCGT VCCGT W71
AB62 VIDALERT# A63 SOC_SVID_CLK J48 VCCGT VCCGT Y62
VCCOPC_AB62 VIDSCK SOC_SVID_CLK <52> VCCGT VCCGT
P62 D64 SOC_SVID_DAT J50
V62 VCCOPC_P62 VIDSOUT J52 VCCGT
VCCOPC_V62 VCCGT
For CPU2+3e SKU VCCSTG_G20
G20 +1.0VS_VCCIO J53
VCCGT VCCGTX_AK42
AK42
H63 J55 AK43
VCC_OPC_1P8_H63 J56 VCCGT VCCGTX_AK43 AK45
G61 J58 VCCGT VCCGTX_AK45 AK46
VCC_OPC_1P8_G61 J60 VCCGT VCCGTX_AK46 AK48
C AC63 K48 VCCGT VCCGTX_AK48 AK50 C
AE63 VCCOPC_SENSE K50 VCCGT VCCGTX_AK50 AK52
VSSOPC_SENSE K52 VCCGT VCCGTX_AK52 AK53
AE62 K53 VCCGT VCCGTX_AK53 AK55
AG62 VCCEOPIO K55 VCCGT VCCGTX_AK55 AK56
VCCEOPIO K56 VCCGT VCCGTX_AK56 AK58
AL63 K58 VCCGT VCCGTX_AK58 AK60
AJ62 VCCEOPIO_SENSE K60 VCCGT VCCGTX_AK60 AK70
VSSEOPIO_SENSE 12 OF 20 L62 VCCGT VCCGTX_AK70 AL43
VCCGT VCCGTX_AL43
L63
VCCGT VCCGTX_AL46
AL46 For CPU2+3e SKU
L64 AL50
SKL-U_BGA1356 VCCGT VCCGTX_AL50
L65 AL53
L66 VCCGT VCCGTX_AL53 AL56
L67 VCCGT VCCGTX_AL56 AL60
L68 VCCGT VCCGTX_AL60 AM48
L69 VCCGT VCCGTX_AM48 AM50
M62 VCCGT VCCGTX_AM53 AM56
N63 VCCGT VCCGTX_AM56 AM58
N64 VCCGT VCCGTX_AM58 AU58
N66 VCCGT VCCGTX_AU58 AU63
N67 VCCGT VCCGTX_AU63 BB57
N69 VCCGT VCCGTX_BB57 BB66
SVID ALERT VCCGT VCCGTX_BB66
+1.0V_VCCST VCCGT_SENSE J70 AK62 VCCGTX_SENSE
Place the PU <52> VCCGT_SENSE VCCGT_SENSE VCCGTX_SENSE T155 TP@
VSSGT_SENSE J69 AL61 VSSGTX_SENSE T219 TP@
resistors close to CPU <52> VSSGT_SENSE VSSGT_SENSE VSSGTX_SENSE
13 OF 20
1
B B
Trace Length < 25 mils SKL-U_BGA1356
RC179
56_0402_5%
2
SOC_SVID_ALERT# 1 2 (To VR)

SOC_SVID_ALERT#_R <52>
RC180 220_0402_5%
+1.0V_VCCST
SVID DATA Place the PU

resistors close to CPU
1
RC181
100_0402_1%
2
SOC_SVID_DAT
SOC_SVID_DAT <52> (To VR)
A A
2014/05/19
Compal Secret Data
2015/12/31 Title
SKL-U(10/12)Power,SVID
RepairLap.com
5 4 3 2 1
5 4 3 2 1
D D
UC1P SKL-U UC1Q SKL-U
Rev_0.53 Rev_0.53 UC1R SKL-U
GND 1 OF 3 GND 2 OF 3
GND 3 OF 3 Rev_0.53
A5 AL65 AT63 BA49 F8 L18
A67 VSS VSS AL66 AT68 VSS VSS BA53 G10 VSS VSS L2
A70 VSS VSS AM13 AT71 VSS VSS BA57 G22 VSS VSS L20
AA2 VSS VSS AM21 AU10 VSS VSS BA6 G43 VSS VSS L4
AA4 VSS VSS AM25 AU15 VSS VSS BA62 G45 VSS VSS L8
AA65 VSS VSS AM27 AU20 VSS VSS BA66 G48 VSS VSS N10
AA68 VSS VSS AM43 AU32 VSS VSS BA71 G5 VSS VSS N13
AB15 VSS VSS AM45 AU38 VSS VSS BB18 G52 VSS VSS N19
AB16 VSS VSS AM46 AV1 VSS VSS BB26 G55 VSS VSS N21
AD13 VSS VSS AM68 AV71 VSS VSS BB43 G63 VSS VSS P17
AD16 VSS VSS AM71 AW10 VSS VSS BB55 G66 VSS VSS P19
AD19 VSS VSS AM8 AW12 VSS VSS BB6 H15 VSS VSS P20
AD20 VSS VSS AN20 AW14 VSS VSS BB60 H18 VSS VSS P21
AD21 VSS VSS AN23 AW16 VSS VSS BB64 H71 VSS VSS R13
AD62 VSS VSS AN28 AW18 VSS VSS BB67 J11 VSS VSS R6
AD8 VSS VSS AN30 AW21 VSS VSS BB70 J13 VSS VSS T15
AE64 VSS VSS AN32 AW23 VSS VSS C1 J25 VSS VSS T17
AE67 VSS VSS AN37 AW30 VSS VSS D10 J35 VSS VSS T21
AE68 VSS VSS AN38 AW32 VSS VSS D11 J38 VSS VSS T4
C AE69 VSS VSS AN40 AW34 VSS VSS D14 J42 VSS VSS U10 C
AF1 VSS VSS AN42 AW36 VSS VSS D18 J8 VSS VSS U63
AF10 VSS VSS AN58 AW38 VSS VSS D22 K16 VSS VSS U64
AF15 VSS VSS AN63 AW41 VSS VSS D25 K18 VSS VSS U66
AF17 VSS VSS AP10 AW43 VSS VSS D26 K22 VSS VSS U67
AF63 VSS VSS AP23 AW49 VSS VSS D39 K64 VSS VSS V16
AG16 VSS VSS AP28 AW51 VSS VSS D44 K65 VSS VSS V17
AG17 VSS VSS AP32 AW53 VSS VSS D45 K66 VSS VSS V18
AG18 VSS VSS AP35 AW55 VSS VSS D47 K67 VSS VSS W13
AG21 VSS VSS AP58 AW60 VSS VSS D58 K71 VSS VSS Y17
AG71 VSS VSS AP63 AW62 VSS VSS D6 L11 VSS VSS Y19
AH13 VSS VSS AP68 AW64 VSS VSS D62 L16 VSS VSS Y20
AH6 VSS VSS AP70 AW66 VSS VSS D66 L17 VSS VSS Y21
AH63 VSS VSS AR11 AW8 VSS VSS D69 VSS VSS
AH64 VSS VSS AR15 AY66 VSS VSS E11
AH67 VSS VSS AR16 B10 VSS VSS E15 18 OF 20
AJ15 VSS VSS AR20 B14 VSS VSS E18
VSS VSS VSS VSS SKL-U_BGA1356
AJ20 AR28 B22 E46
AK11 VSS VSS AR42 B34 VSS VSS E53
B AK27 VSS VSS AR5 B58 VSS VSS F1 B
AK63 VSS VSS AR50 B62 VSS VSS F13
AK8 VSS VSS AR55 BA1 VSS VSS F23
AL2 VSS VSS AR58 BA10 VSS VSS F27
AL35 VSS VSS AT2 BA2 VSS VSS F33
AL52 VSS VSS AT4 F68 VSS VSS F40
AL58 VSS VSS AT56 VSS VSS BA41
AL64 VSS VSS AT58 VSS
VSS VSS
16 OF 20 17 OF 20
SKL-U_BGA1356 SKL-U_BGA1356
A A
2014/05/19
Compal Secret Data
2015/12/31 Title
SKL-U(11/12)GND
RepairLap.com
5 4 3 2 1
5 4 3 2 1
D D
UC1S SKL-U
Rev_0.53
RESERVED SIGNALS-1
T272 TP@ E68 BB68 T156 TP@

B67 CFG[0] RSVD_TP_BB68 BB69
T273 TP@ CFG[1] RSVD_TP_BB69 T157 TP@
T274 TP@ D65
D67 CFG[2] AK13
<5> CFG3 CFG[3] RSVD_TP_AK13 T158 TP@
CFG4 E70 AK12 T159 TP@
C68 CFG[4] RSVD_TP_AK12
T275 TP@ CFG[5]
T276 TP@ D68 BB2
C67 CFG[6] RSVD_BB2 BA3
T277 TP@ CFG[7] RSVD_BA3
T278 TP@ F71
G69 CFG[8]
T279 TP@ CFG[9]
T281 TP@ F70 AU5 T162 TP@
G68 CFG[10] TP5 AT5
T280 TP@ CFG[11] TP6 T163 TP@
T283 TP@ H70
G71 CFG[12]
T282 TP@ CFG[13]
T284 TP@ H69 D5
G70 CFG[14] RSVD_D5 D4
T285 TP@ CFG[15] RSVD_D4 B2 UC1T SKL-U
RSVD_B2 T166 TP@
T286 TP@ E63 C2 T167 TP@
CFG[16] RSVD_C2 Rev_0.53
T287 TP@ F63 SPARE
CFG[17] B3
RSVD_B3 T170 TP@
T288 TP@ E66 A3 T252 TP@ AW69 F6
F66 CFG[18] RSVD_A3 AW68 RSVD_AW69 RSVD_F6 E3
T289 TP@ CFG[19] RSVD_AW68 RSVD_E3
C AW1 T174 TP@ AU56 C11 C
CFG_RCOMP E60 RSVD_AW1 AW48 RSVD_AU56 RSVD_C11 B11
CFG_RCOMP E1 C7 RSVD_AW48 RSVD_B11 A11
RSVD_E1 T179 TP@ RSVD_C7 RSVD_A11
XDP_ITP_PMODE E8 E2 T183 TP@ U12 D12
<5> XDP_ITP_PMODE ITP_PMODE RSVD_E2 RSVD_U12 RSVD_D12
U11 C12
AY2 BA4 H11 RSVD_U11 RSVD_C12 F52
RSVD_AY2 RSVD_BA4 RSVD_H11 RSVD_F52 T227 TP@
T192 TP@ AY1 BB4
RSVD_AY1 RSVD_BB4 20 OF 20
T194 TP@ D1 A4 T195 TP@
D3 RSVD_D1 RSVD_A4 C4
T196 TP@ RSVD_D3 RSVD_C4 T197 TP@ SKL-U_BGA1356
T198 TP@ K46 BB5

K45 RSVD_K46 TP4
T200 TP@ RSVD_K45 A69 T201 TP@
AL25 RSVD_A69 B69
RSVD_AL25 RSVD_B69 T203 TP@
AL27
RSVD_AL27 AY3 RC182 1 2 0_0402_5%
C71 RSVD_AY3
T205 TP@ RSVD_C71
T206 TP@ B70 D71 T207 TP@
RSVD_B70 RSVD_D71 C70
RSVD_C70 T208 TP@
T209 TP@ F60
RSVD_F60 C54
RSVD_C54 T210 TP@
T211 TP@ A52 D54 T301 TP@
RSVD_A52 RSVD_D54
T213 TP@ BA70 AY4

BA68 RSVD_TP_BA70 TP1 BB3
T300 TP@ RSVD_TP_BA68 TP2
T217 TP@ J71 AY71 1 RC183 2 0_0402_5%

J68 RSVD_J71 VSS_AY71 AR56 PM_ZVM#
B T218 TP@ RSVD_J68 ZVM# T225 TP@ B
For 2+3e Solution
F65 AW71 T333 TP@
T220 TP@
G65 VSS_F65 RSVD_TP_AW71 AW70 PM_ZVM#
T222 TP@ VSS_G65 RSVD_TP_AW70 T223 TP@
PM_MSM#
T224 TP@ F61 AP56 PM_MSM# T230 TP@ +1.0V_VCCST
E61 RSVD_F61 MSM# C64 SKL_CNL#
T226 TP@ RSVD_E61 PROC_SELECT#
19 OF 20 1 @ 2
RC184 100K_0402_5%
SKL-U_BGA1356
Follow 544669_SKL_U_DDR3L_RVP7_schematic_rev1.0
CFG_RCOMP 1 2
RC185 49.9_0402_1%
CFG4 1 2
RC193 1K_0402_1%
A A
Display Port Presence Strap
1 : Disabled; No Physical Display Port

CFG4 attached to Embedded Display Port Security Classification
2014/05/19
Compal Secret Data
2015/12/31 Title
0 : Enabled; An external Display Port device is SKL-U(12/12)RSVD
connected to the Embedded Display Port THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RepairLap.com
5 4 3 2 1
5 4 3 2 1
REVERSE TYPE (5.2 mm)

CHANNEL-A <6>
<6>
DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK0
DDR_A_CLK#0
137
139
JDIMM1A
CK0(T)
CK0#(C)
STD
DQ0
DQ1
8
7
DDR_A_D0
DDR_A_D4
Interleaved Memory
DDR_A_CLK1 138 20 DDR_A_D3
<6> DDR_A_CLK1 CK1(T) DQ2
DDR_A_CLK#1 140 21 DDR_A_D7
<6> DDR_A_CLK#1 CK1#(C) DQ3 4 DDR_A_D1
DDR_A_CKE0 109 DQ4 3 DDR_A_D5
<6> DDR_A_CKE0 DDR_A_CKE1 CKE0 DQ5 DDR_A_D2
110 16
TOP: JDIMM1 CONN Non-ECC DIMM <6> DDR_A_D[0..15]
<6>
<6>
DDR_A_CKE1
DDR_A_CS#0
DDR_A_CS#0 149
CKE1
S0#
DQ6
DQ7
DQS0(T)
17
13
DDR_A_D6
DDR_A_DQS0
DDR_A_DQS0 <6>
DDR_A_CS#1 157 11 DDR_A_DQS#0
<6> DDR_A_D[16..31] <6> DDR_A_CS#1 S1# DQS0#(C) DDR_A_DQS#0 <6>
162
D +3VS +3VS +3VS S2#/C0 D
165 28 DDR_A_D8
<6> DDR_A_D[32..47] S3#/C1 DQ8 DDR_A_D12
29
DDR_A_ODT0 155 DQ9 41 DDR_A_D14
<6> DDR_A_D[48..63] <6> DDR_A_ODT0 ODT0 DQ10
1
1
DDR_A_ODT1 161 42 DDR_A_D10
<6> DDR_A_ODT1 ODT1 DQ11 DDR_A_D9
RD1 RD4 RD2 24
@ 0_0402_5% @ 0_0402_5% @ 0_0402_5% JDIMM1B DDR_A_BG0 115 DQ12 25 DDR_A_D13
STD <6> DDR_A_BG0 DDR_A_BG1 BG0 DQ13 DDR_A_D11
113 38
<6> DDR_A_BG1 DDR_A_BA0 BG1 DQ14 DDR_A_D15
111 141 150 37
+1.2V_VDDQ +1.2V_VDDQ <6> DDR_A_BA0
2
2
SA0_CHA_DIM1 SA1_CHA_DIM1 SA2_CHA_DIM1 112 VDD1 VDD11 142 DDR_A_BA1 145 BA0 DQ15 34 DDR_A_DQS1
VDD2 VDD12 <6> DDR_A_BA1 BA1 DQS1(T) DDR_A_DQS#1 DDR_A_DQS1 <6>
117 147 32
VDD3 VDD13 DDR_A_MA0 DQS1#(C) DDR_A_DQS#1 <6>
118 148 144
VDD4 VDD14 <6> DDR_A_MA0 A0
1
1
123 153 DDR_A_MA1 133 50 DDR_A_D21
VDD5 VDD15 <6> DDR_A_MA1 DDR_A_MA2 A1 DQ16 DDR_A_D17
RD3 RD5 RD6 8/26 124 154 132 49
0_0402_5% 0_0402_5% 0_0402_5% 129 159 131 62
130 160 128 63
135 163 126 46
VDD9 VDD19 <6> DDR_A_MA5 A5 DQ20
2
2 +3V_PRIM_DA 136 DDR_A_MA6 127 45 DDR_A_D20

VDD10 <6> DDR_A_MA6 DDR_A_MA7 A6 DQ21 DDR_A_D19
122 58
<6> DDR_A_MA7 DDR_A_MA8 A7 DQ22 DDR_A_D22
255 258 125 59
VDDSPD VTT +0.6V_0.6VS <6> DDR_A_MA8 DDR_A_MA9 121 A8 DQ23 55 DDR_A_DQS2
<6> DDR_A_MA9 A9 DQS2(T) DDR_A_DQS2 <6>
0.1U_0402_10V6K
164 257 DDR_A_MA10 146 53 DDR_A_DQS#2
PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM
2.2U_0402_6.3V6M
+0.6V_DDR_VREFCA VREFCA VPP1 259
+2.5V <6> DDR_A_MA10 DDR_A_MA11 120 A10_AP DQS2#(C) DDR_A_DQS#2 <6>
2 2 VPP2 <6> DDR_A_MA11 A11
DDR_A_MA12 119 70 DDR_A_D25
<6> DDR_A_MA12 A12 DQ24
CD1
CD2
1 99 DDR_A_MA13 158 71 DDR_A_D28
VSS VSS <6> DDR_A_MA13 DDR_A_MA14_WE# A13 DQ25 DDR_A_D30
2 102 151 83
1 1 VSS VSS <6> DDR_A_MA14_WE# DDR_A_MA15_CAS# A14_WE# DQ26 DDR_A_D31
5 103 9/8 Modify 156 84
SPD ADDRESS FOR CHANNEL A : 6
9
VSS
VSS
VSS
VSS
106
107
<6>
<6>
DDR_A_MA15_CAS#
DDR_A_MA16_RAS#
DDR_A_MA16_RAS# 152 A15_CAS#
A16_RAS#
DQ27
DQ28
66
67
DDR_A_D24
DDR_A_D29
WRITE ADDRESS: 0XA0 PLACE NEAR TO PIN
10
14
VSS
VSS
VSS
VSS
167
168
<6> DDR_A_ACT#
DDR_A_ACT# 114
ACT#
DQ29
DQ30
79
80
DDR_A_D27
DDR_A_D26
READ ADDRESS: 0XA1 15
18
VSS
VSS
VSS
VSS
171
172
<6> DDR_A_PAR
DDR_A_PAR
DDR_A_ALERT#
143
116 PARITY
DQ31
DQS3(T)
76
74
DDR_A_DQS3
DDR_A_DQS#3 DDR_A_DQS3 <6>
SA0 = 0; SA1 = 0; SA2 = 0. 19
22
VSS
VSS
VSS
VSS
175
176
+1.2V_VDDQ RD7 2
240_0402_1%
<6> DDR_A_ALERT#
1 DIMM1_CHA_EVENT#
DDR_DRAMRST#_R
134
108
ALERT#
EVENT#
DQS3#(C)
174 DDR_A_D32
DDR_A_DQS#3 <6>
<6,18> DDR_DRAMRST#_R
C
DDR4 POR OPERATING SPEED: 1867 MT/S 23
26
VSS
VSS
VSS
VSS
180
181
RESET# DQ32
DQ33
173
187
DDR_A_D37
DDR_A_D34 C
VSS VSS DQ34
STRETCH GOAL IS 2133 MT/S 27
30 VSS VSS
184
185
<7,18,19,22> PCH_SMBDATA
PCH_SMBDATA
PCH_SMBCLK
254
253 SDA DQ35
186
170
DDR_A_D39
DDR_A_D36
VSS VSS <7,18,19,22> PCH_SMBCLK SCL DQ36 DDR_A_D33
31 188 169
35 VSS VSS 189 SA2_CHA_DIM1 166 DQ37 183 DDR_A_D35
36 VSS VSS 192 SA1_CHA_DIM1 260 SA2 DQ38 182 DDR_A_D38
Layout Note: Layout Note: VSS VSS SA1 DQ39
39 193 SA0_CHA_DIM1 256 179 DDR_A_DQS4
Place near JDIMM1.257,259 Place near JDIMM1.258 40 VSS VSS 196 SA0 DQS4(T) 177 DDR_A_DQS#4 DDR_A_DQS4 <6>
VSS VSS DQS4#(C) DDR_A_DQS#4 <6>
43 197
44 VSS VSS 201 92 195 DDR_A_D44
47 VSS VSS 202 91 CB0_NC DQ40 194 DDR_A_D45
48 VSS VSS 205 101 CB1_NC DQ41 207 DDR_A_D42
+2.5V +0.6V_0.6VS 51 VSS VSS 206 105 CB2_NC DQ42 208 DDR_A_D43
10uF*2 10uF*2 VSS VSS CB3_NC DQ43
52 209 88 191 DDR_A_D41
1uF*2 1uF*1 56 VSS VSS 210 87 CB4_NC DQ44 190 DDR_A_D40
57 VSS
VSS
VSS
VSS
213 For ECC DIMM 100 CB5_NC
CB6_NC
DQ45
DQ46
203 DDR_A_D46
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_25V6
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 60 214 104 204 DDR_A_D47

@ESD@ 61 VSS VSS 217 97 CB7_NC DQ47 200 DDR_A_DQS5
VSS VSS DQS8(T) DQS5(T) DDR_A_DQS5 <6>
CD3
CD4
CD5
CD6
CC159
CD7
CD8
CD9
64 218 95 198 DDR_A_DQS#5

VSS VSS DQS8#(C) DQS5#(C) DDR_A_DQS#5 <6>
65 222
2 2 2 2 2 2 2 2 68 VSS VSS 223 216 DDR_A_D53
69 VSS VSS 226 12 DQ48 215 DDR_A_D48
72 VSS VSS 227
+1.2V_VDDQ 33 DM0#/DBI0# DQ49 228 DDR_A_D54
73 VSS VSS 230 54 DM1#/DBI1# DQ50 229 DDR_A_D50
85 VSS VSS 239 DDR_DRAMRST#_R 241 DM6#/DBI6# DQ55 221 DDR_A_DQS6
VSS VSS DM7#/DBI7# DQS6(T) DDR_A_DQS#6 DDR_A_DQS6 <6>
86 243 96 219
VSS VSS DM8#/DBI8# DQS6#(C) DDR_A_DQS#6 <6>
89 244
90 VSS VSS 247
Layout Note: VSS VSS 2
93 248 CD10
PLACE THE CAP near JDIMM1. 164 94 VSS VSS 251 0.1U_0402_10V6K 237 DDR_A_D60
+3V_PRIM +3V_PRIM_DA 98 VSS VSS 252 @ESD@ DQ56 236 DDR_A_D57
VSS VSS 1 DQ57 DDR_A_D59
B 9/8 Modify base on ESD Request DQ58
249 B
1 2 262 261 250 DDR_A_D62
RD32 0_0402_5% GND GND DQ59 232 DDR_A_D56
DQ60 233 DDR_A_D61
+0.6V_DDR_VREFCA FOX_AS0A827-H2RB-7H DQ61 245 DDR_A_D58
2.2uF*1 DQ62 246 DDR_A_D63
0.1uF*1 PLACE NEAR TO SODIMM DQ63 242 DDR_A_DQS7
CONN@ DQS7(T) DDR_A_DQS7 <6>
2 2 240 DDR_A_DQS#7
DQS7#(C) DDR_A_DQS#7 <6>
CD11 CD12
1
0.1U_0402_10V6K
1
2.2U_0402_6.3V6M Part Number:LTCX0069GA0 FOX_AS0A827-H2RB-7H
Part Value:S SOCKET FOX AS0A827-H2RB-7H 260P DDR4 +1.2V_VDDQ
CONN@
DIMM Side CPU Side
2
RD8 +0.6V_DDR_VREFCA +0.6V_VREFCA
Layout Note:
Place near JDIMM1 @ 2 1K_0402_1%
CD13
1
0.1U_0402_10V6K
1
1 RD9 2
VREF traces should be at least 20 mils
10uF*6 2_0402_1% wide with 20 mils spacing to other
+1.2V_VDDQ 1uF*8 +1.2V_VDDQ 2
1 signals
330uF*1
2
CD15
+1.2V_VDDQ RD10 CD14 0.022U_0402_25V7K
2
1K_0402_1% 0.1U_0402_10V6K
1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1
CD93
CD16
CD17
CD18
CD19
CD20
CD21
CD22
CD23
CD95
A 1 RD11 A
CD96
CD24
CD25
CD26
CD27
CD28
CD29
CD30
CD31
CD94
24.9_0402_1%
C174 +
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Part Number = SF000006S00
1
330U_2.5V_M
2
@

P18-DDRIV_CHA: DIMM0
RepairLap.com
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS v0.2
5 4 3 2 1
5 4 3 2 1
CHANNEL-B STD (5.2 mm)

TOP: JDIMM2 CONN Non-ECC DIMM Interleaved Memory <6> DDR_B_D[0..15]
<6> DDR_B_CLK0
<6> DDR_B_CLK#0
<6> DDR_B_CLK1
DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
DDR_B_CLK#1
137
139
138
140
JDIMM2A
CK0(T)
CK0#(C)
CK1(T)
STD
DQ0
DQ1
DQ2
8
7
20
21
DDR_B_D15
DDR_B_D10
DDR_B_D11
DDR_B_D12
<6> DDR_B_CLK#1 CK1#(C) DQ3 DDR_B_D14
4
+3VS +3VS +3VS <6> DDR_B_D[16..31] DDR_B_CKE0 DQ4 DDR_B_D9
109 3
<6> DDR_B_CKE0 DDR_B_CKE1 CKE0 DQ5 DDR_B_D8
110 16
<6> DDR_B_D[32..47] <6> DDR_B_CKE1 CKE1 DQ6 DDR_B_D13
17
DQ7
1
1
DDR_B_CS#0 149 13 DDR_B_DQS1
D <6> DDR_B_D[48..63] <6> DDR_B_CS#0 DDR_B_CS#1 S0# DQS0(T) DDR_B_DQS#1 DDR_B_DQS1 <6> D
RD19 RD20 RD21 157 11
<6> DDR_B_CS#1 S1# DQS0#(C) DDR_B_DQS#1 <6>
0_0402_5% 0_0402_5% @ 0_0402_5% JDIMM2B 162
@ STD S2#/C0 DDR_B_D0
165 28
111 141 S3#/C1 DQ8 29 DDR_B_D5
+1.2V_VDDQ +1.2V_VDDQ
2
2
SA0_CHB_DIM2 2 SA1_CHB_DIM2 SA2_CHB_DIM2 112 VDD1 VDD11 142 DDR_B_ODT0 155 DQ9 41 DDR_B_D7
VDD2 VDD12 <6> DDR_B_ODT0 DDR_B_ODT1 ODT0 DQ10 DDR_B_D6
117 147 161 42
VDD3 VDD13 <6> DDR_B_ODT1 ODT1 DQ11 DDR_B_D4
118 148 24
VDD4 VDD14 DQ12
1
1
123 153 DDR_B_BG0 115 25 DDR_B_D1
VDD5 VDD15 <6> DDR_B_BG0 DDR_B_BG1 BG0 DQ13 DDR_B_D3
RD22 RD23 RD24 8/26 124 154 113 38
VDD6 VDD16 <6> DDR_B_BG1 DDR_B_BA0 BG1 DQ14 DDR_B_D2
0_0402_5% @ 0_0402_5% 0_0402_5% 129 159 150 37
VDD7 VDD17 <6> DDR_B_BA0 DDR_B_BA1 BA0 DQ15 DDR_B_DQS0
130 160 145 34
VDD8 VDD18 <6> DDR_B_BA1 BA1 DQS1(T) DDR_B_DQS#0 DDR_B_DQS0 <6>
135 163 32
DDR_B_DQS#0 <6>
2
VDD9 VDD19 DQS1#(C)

2
2
+3V_PRIM_DB 136 DDR_B_MA0 144
VDD10 <6> DDR_B_MA0 DDR_B_MA1 A0 DDR_B_D20
133 50
<6> DDR_B_MA1 DDR_B_MA2 A1 DQ16 DDR_B_D17
255 258 132 49
VDDSPD VTT +0.6V_0.6VS <6> DDR_B_MA2 DDR_B_MA3 131 A2 DQ17 62 DDR_B_D19
<6> DDR_B_MA3 A3 DQ18
0.1U_0402_10V6K
164 257 DDR_B_MA4 128 63 DDR_B_D22
2.2U_0402_6.3V6M
+0.6V_DDRB_VREFCA VREFCA VPP1 259
+2.5V <6> DDR_B_MA4 DDR_B_MA5 126 A4 DQ19 46 DDR_B_D21
2 2 VPP2 <6> DDR_B_MA5 A5 DQ20
DDR_B_MA6 127 45 DDR_B_D16
PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM <6> DDR_B_MA6 A6 DQ21
CD60
CD61
1 99 DDR_B_MA7 122 58 DDR_B_D18
VSS VSS <6> DDR_B_MA7 DDR_B_MA8 A7 DQ22 DDR_B_D23
2 102 125 59
1 1 VSS VSS <6> DDR_B_MA8 DDR_B_MA9 A8 DQ23 DDR_B_DQS2
5 103 121 55
VSS VSS <6> DDR_B_MA9 A9 DQS2(T) DDR_B_DQS2 <6>
SPD ADDRESS FOR CHANNEL B : 6
9 VSS VSS
106
107
<6> DDR_B_MA10
DDR_B_MA10
DDR_B_MA11
146
120 A10_AP DQS2#(C)
53 DDR_B_DQS#2
DDR_B_DQS#2 <6>
VSS VSS <6> DDR_B_MA11 A11
WRITE ADDRESS: 0XA4 PLACE NEAR TO PIN
10
14 VSS VSS
167
168
<6>
<6>
DDR_B_MA12
DDR_B_MA13
DDR_B_MA12
DDR_B_MA13
119
158 A12 DQ24
70
71
DDR_B_D25
DDR_B_D24
VSS VSS A13 DQ25
READ ADDRESS: 0XA3 15
18 VSS
VSS
VSS
VSS
171
172 9/8 Modify
<6>
<6>
DDR_B_MA14_WE#
DDR_B_MA15_CAS#
DDR_B_MA14_WE#
DDR_B_MA15_CAS#
151
156 A14_WE#
A15_CAS#
DQ26
DQ27
83
84
DDR_B_D31
DDR_B_D27
DDR_B_MA16_RAS# DDR_B_D28
SA0 = 0; SA1 = 1; SA2 = 0. 19
22 VSS
VSS
VSS
VSS
175
176
<6> DDR_B_MA16_RAS#
152
A16_RAS# DQ28
DQ29
66
67 DDR_B_D29
23 180 DDR_B_ACT# 114 79 DDR_B_D30
DDR4 POR OPERATING SPEED: 1867 MT/S 26 VSS
VSS
VSS
VSS
181
<6> DDR_B_ACT# ACT# DQ30
DQ31
80 DDR_B_D26
27 184 DDR_B_PAR 143 76 DDR_B_DQS3
STRETCH GOAL IS 2133 MT/S 30 VSS
VSS
VSS
VSS
185
<6>
<6>
DDR_B_PAR
DDR_B_ALERT#
DDR_B_ALERT#
DIMM2_CHB_EVENT#
116 PARITY
ALERT#
DQS3(T)
DQS3#(C)
74 DDR_B_DQS#3 DDR_B_DQS3
DDR_B_DQS#3
<6>
<6>
31 188 RD25 2 1 134
C 35 VSS VSS 189
+1.2V_VDDQ 240_0402_1% DDR_DRAMRST#_R 108 EVENT# 174 DDR_B_D37 C
VSS VSS <6,17> DDR_DRAMRST#_R RESET# DQ32 DDR_B_D33
Layout Note: Layout Note: 36 192 173
39 VSS VSS 193 DQ33 187 DDR_B_D35
Place near JDIMM2.257,259 Place near JDIMM2.258 40 VSS VSS 196 PCH_SMBDATA 254 DQ34 186 DDR_B_D38
VSS VSS <7,17,19,22> PCH_SMBDATA PCH_SMBCLK SDA DQ35 DDR_B_D32
43 197 253 170
VSS VSS <7,17,19,22> PCH_SMBCLK SCL DQ36 DDR_B_D36
44 201 169
47 VSS VSS 202 SA2_CHB_DIM2 166 DQ37 183 DDR_B_D34
48 VSS VSS 205 SA1_CHB_DIM2 260 SA2 DQ38 182 DDR_B_D39
+2.5V +0.6V_0.6VS 51 VSS VSS 206 SA0_CHB_DIM2 256 SA1 DQ39 179 DDR_B_DQS4
10uF*2 10uF*2 VSS VSS SA0 DQS4(T) DDR_B_DQS4 <6>
52 209 177 DDR_B_DQS#4
1uF*2 1uF*1 56 VSS VSS 210 DQS4#(C) DDR_B_DQS#4 <6>
57 VSS VSS 213 92 195 DDR_B_D44
VSS VSS CB0_NC DQ40
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1 1 1 1 1 1 1 60 214 91 194 DDR_B_D45

61 VSS VSS 217 101 CB1_NC DQ41 207 DDR_B_D42
VSS VSS CB2_NC DQ42
CD62
CD63
CD64
CD65
CD66
CD67
CD68
64 218 105 208 DDR_B_D47

2 2 2 2 2 2 2 68 VSS VSS 223 87 CB4_NC DQ44 190 DDR_B_D41
69 VSS VSS 226
For ECC DIMM 100 CB5_NC DQ45 203 DDR_B_D43
73 VSS VSS 230 97 CB7_NC DQ47 200 DDR_B_DQS5
VSS VSS DQS8(T) DQS5(T) DDR_B_DQS#5 DDR_B_DQS5 <6>
77 231 95 198
VSS VSS DQS8#(C) DQS5#(C) DDR_B_DQS#5 <6>
78 234
81 VSS VSS 235 216 DDR_B_D48
82 VSS VSS 238 12 DQ48 215 DDR_B_D53
85 VSS VSS 239
+1.2V_VDDQ 33 DM0#/DBI0# DQ49 228 DDR_B_D54
86 VSS VSS 243 54 DM1#/DBI1# DQ50 229 DDR_B_D51
93 VSS VSS 248 DDR_DRAMRST#_R 199 DM4#/DBI4# DQ53 224 DDR_B_D55
Layout Note: VSS VSS DM6#/DBI6# DQ55
98 252 241 221 DDR_B_DQS6
PLACE THE CAP WITHIN 200 MILS VSS VSS 96 DM7#/DBI7# DQS6(T) 219 DDR_B_DQS#6 DDR_B_DQS6 <6>
2 DM8#/DBI8# DQS6#(C) DDR_B_DQS#6 <6>
FROM THE JDIMM2 262 261 CD92
GND GND 0.1U_0402_10V6K
@ESD@
B FOX_AS0A827-H2SB-7H 1 237 DDR_B_D60 B
DQ56 236 DDR_B_D57
+0.6V_DDRB_VREFCA DQ57 249 DDR_B_D58
2.2uF*1 CONN@ DQ58 250 DDR_B_D62
0.1uF*1 DQ59 232 DDR_B_D56
2 2 Part Number:LTCX0069FA0 DQ60 233 DDR_B_D61
Part Value:S SOCKET FOX AS0A827-H2SB-7H 260P DDR4 PLACE NEAR TO SODIMM DQ61
DQ62
245 DDR_B_D59
CD69 CD70 246 DDR_B_D63
DQ63 242 DDR_B_DQS7
0.1U_0402_10V6K 2.2U_0402_6.3V6M DQS7(T) DDR_B_DQS7 <6>
1 1 +1.2V_VDDQ 240 DDR_B_DQS#7
+3V_PRIM +3V_PRIM_DB DQS7#(C) DDR_B_DQS#7 <6>
1 2
RD33 0_0402_5% FOX_AS0A827-H2SB-7H
CONN@
Layout Note:
2
DIMM Side CPU Side
2
CD71
Place near JDIMM2 @ 0.1U_0402_10V6K RD26
1
1K_0402_1%
+0.6V_DDRB_VREFCA +0.6V_B_VREFDQ
1
10uF*6
1 RD27 2
+1.2V_VDDQ 1uF*8 +1.2V_VDDQ 2_0402_1%
330uF*1 VREF traces should be at least 20 mils
2 wide with 20 mils spacing to other
2
2 1 signals
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
RD28 CD72
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CD81 1K_0402_1% 0.1U_0402_10V6K CD82

1
CD73
CD74
CD75
CD76
CD77
CD78
CD79
CD80
0.1U_0402_10V6K 0.022U_0402_25V7K
1 2
CD83
CD84
CD85
CD86
CD87
CD88
CD89
CD90
A A
2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
RD29
24.9_0402_1%
@ @
1
P19-DDRIV_CHB: DIMM0
RepairLap.com
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS v0.2
5 4 3 2 1
5 4 3 2 1
<5,6,7,9,10,11,13,17,18,20,21,22,23,24,26,28,32,33,34,35,36,37,38,52,55,56> +3VS +3VS
D D
C C
<CPU CTRL>
EDP_HPD
<5> EDP_HPD
1
RT11
100K_0402_5%
2
RTD2132 SMBus revrse to PCH
RT193 1 2 0_0201_5% CIICSCL1

<7,10,22,26,37> EC_SMB_CK2
RT194 1 2 0_0201_5% CIICSDA1
<7,10,22,26,37> EC_SMB_DA2
RT195 1 @ 2 0_0201_5%
<7,17,18,22> PCH_SMBCLK
RT196 1 @ 2 0_0201_5%
<7,17,18,22> PCH_SMBDATA
L Layout notes
CC97~CC102 must closed to connector
CT102 1 2 .1U_0402_16V7K EDP_CPU_AUX

<5> EDP_CPU_AUX_C
CT101 1 2 .1U_0402_16V7K EDP_CPU_AUX# <CPU by PASS eDP> <eDP to connector>
<5> EDP_CPU_AUX#_C
B CT98 1 2 .1U_0402_16V7K EDP_CPU_LANE_P0 B
<5> EDP_CPU_LANE_P0_C
RP9 SD309000080
CT97 1 2 .1U_0402_16V7K EDP_CPU_LANE_N0 0_0804_8P4R_5% eDP@
<5> EDP_CPU_LANE_N0_C
EDP_AUX 4 5 LCD_CLK
<CPU> EDP_CPU_LANE_N0 1 8 EDP_LANE_N0 EDP_AUX# 3 6 LCD_DATA
LCD_CLK <20>
LCD_DATA <20>
CT103 1 2 .1U_0402_16V7K EDP_CPU_LANE_P1 EDP_CPU_LANE_P0 2 7 EDP_LANE_P0 EDP_LANE_N0 2 7 LVDS_TXN2_LN0
<5> EDP_CPU_LANE_P1_C LVDS_TXN2_LN0 <20>
eDP@ EDP_CPU_AUX 3 6 EDP_AUX EDP_LANE_P0 1 8 LVDS_TXP2_LP0
LVDS_TXP2_LP0 <20>
CT100 1 2 .1U_0402_16V7K EDP_CPU_LANE_N1 EDP_CPU_AUX# 4 5 EDP_AUX#
<5> EDP_CPU_LANE_N1_C
eDP@ eDP@ SD309000080 0_0804_8P4R_5%
RP6
EDP_HPD EDP_HPD_PANEL
4
DB phase : RT34 1 2 0_0201_5% 2 Layout notes
add eDP Lan1 for FHD Delete BKL_PWM_CPU and DP_INT_PWM
EDP_HPD_PANEL <20> L RP6 RP9 RP10 must closed to connector
20141117 20141113
EDP_CPU_LANE_P1 1 2 LVDS_TXP1_LP1
LVDS_TXP1_LP1 <20>
RT16 0_0402_5%
@ EDP_CPU_LANE_N1 1 2 LVDS_TXN1_LN1
LVDS_TXN1_LN1 <20>
RT14 1 2 0_0402_5% RT17 0_0402_5%
CT24
@
+3VS 1 2
0.1U_0402_16V7K
5
UT3 DB phase : Layout notes

<RTS2132> TS_BKOFF# 1 L
P
B 4 add eDP Lan1 for FHD RT16~RT19 must closed to connector

Y EC_TS_BKOFF# <20> <LVDS Panel>
<EC CTRL> <26> EC_BKOFF#
EC_BKOFF# 2
A
20141117
G
A LVDS@ A
TC7SH08FUF_SSOP5
3
1
RT12 PD 100K on LVDS page

100K_0402_5%
LVDS@
2

1 2
RT15 0_0402_5%
LVDS Translator-RTD2132N
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-D707P v0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2 1
RepairLap.com
5 4 3 2 1
LVDS Power +3VS <SI> change to standard par SA00006Y800 (Dif f er ent f oot pri nt) <5,6,7,9,10,11,13,17,18,19,21,22,23,24,26,28,32,33,34,35,36,37,38,52,55,56> +3VS +3VS
N6U@
UG1 +19.5VB
<38,47,48,49,50,53,55,56> +19.5VB
1 +LCDVDD
5 VOUT
VIN W=60mils <7,13,23,26,27,30,33,35,48,49,50,51,55> +3VALW +3VALW
INVPWR_B+ +19.5VB
0.1U_0402_16V7K
2 SM010014520 3000ma W=60mils
GND
CG3
4 1 1 220ohm@100mhz
EN CG2 JPHW1@
DCR 0.04
3 1 2
1 2 /OC 4.7U_0603_6.3V6K 1 2
<5> ENVDD_CPU 2 2
R172 0_0402_5% G524B1T11U_SOT23-5 JUMP_43X79
SA00006Y800
+3VS 1 1 6U@
0_0201_5% Main SA00006Y800 @EMI@ C117 C118 FU1 1 2
680P_0402_50V7K 68P_0402_50V8J
D
RG1 1 @ 2 2nd SA00007U000 FUSE 0438.500WR 0.5A 32V UL/CSA FAST D
3rd SA000079400 2 2 SP040004X00
1
CG1 UG1
eDP@ 6U@
1500P_0402_50V7K 2 G524B2T11U SOT-23
SA00007BW00
Camera
1 2
R170 0_0402_5%
L12 @EMI@ @ESD@ SCA00000U10
USB20_N5_R D7
1 2
<11> USB20_N5 1 2 USB20_P5_R 2
Part Number = SM070003Y00 1
4 3 USB20_P5_R USB20_N5_R 3
<11> USB20_P5 4 3
WCM-2012-900T_4P
PESD5V0U2BT_SOT23-3
1 2
R171 0_0402_5%
C593 2 1 220P_0402_50V7K INVTPWM

LCD/LED PANEL Conn.
C594 2 1 220P_0402_50V7K DISPOFF#
C C
<DB>LA1/LA2 closed to Aduio codec
EMI@ SM01000B600
D_MIC_CLK 1 2 D_MIC_L_CLK
<24> D_MIC_CLK LA1 FBMA-L10-160808-301LMT_2P
D_MIC_DATA 1 2 D_MIC_L_DATA
<24> D_MIC_DATA R175 0_0402_5%
@ESD@
D3
SCA00000U10
D_MIC_L_CLK 2 CONN@
1 JLVDS1
D_MIC_L_DATA 3 1
2 1 41
3 2 G1 42
PESD5V0U2BT_SOT23-3 4 3 G2 43
EDP_CPU_LANE_P1 <19> LVDS_TXP1_LP1 4 G3
EDP_CPU_LANE_N1 <19> LVDS_TXN1_LN1 5 44
6 5 G4 45
7 6 G5 46
EDP_CPU_LANE_P0 <19> LVDS_TXP2_LP0 7 G6
EDP_CPU_LANE_N0 <19> LVDS_TXN2_LN0 8
9 8
10 9
EDP_CPU_AUX <19> LCD_CLK 10
EDP_CPU_AUX# 11
<19> LCD_DATA 11
12
13 12
13
Touch Screen
14
1 2 INVTPWM 15 14
<5> BKL_PWM_CPU +LCDVDD 15
R259 0_0402_5% 16
16
1
LVDS@ 17
<19> EDP_HPD_PANEL 17
R163 18
19 18
<DB> for 5V/3V TS option 100K_0402_5%
20 19
USB20_P6_R 21 20
Touch screen
2
+3VALW +5VALW R166 33_0402_5% USB20_N6_R 22 21
B
EC_TS_BKOFF# 1 2 DISPOFF# DISPOFF# 23 22 B
<19> EC_TS_BKOFF# 23
Touch Screen Power INVTPWM 24
24
1
TS_GPIO 25
25
1
@ TS@ 26
RTS2 RTS3 R5176 27 26
INVPWR_B+ 27
100K_0402_5% 100K_0402_5% 10K_0402_5% 28
29 28
2
30 29
+VCC_TOUCH
2
31 30
31
1
TS@ 32
D 32
1
RTS1 TS@ +3VS_CAMERA 33

QTS1 2 USB20_N5_R 34 33
1K_0402_5% TOUCH_ON# <26> 34
2N7002K_SOT23 G Camera USB20_P5_R 35
TS@CTS2 36 35
S
2
1 2 D_MIC_L_CLK 37 36
+VCC_TOUCH_IN D_MIC_L_DATA 38 37
38
2
R260 39
0.047U_0402_16V7K 39
G
TS_GPIO_CPU 1 @ 2 TS_GPIO 40
<10> TS_GPIO_CPU 40
1 3 RG4 1 @ 2 0_0402_5% +3VS 0_0402_5%
D
R5187 STARC_107K40-000001-G2
TS@ 1 TS_GPIO_EC 1 2 SP01000XE00
<26> TS_GPIO_EC
CTS1 TS@ RG5 1 TS@ 2 0_0402_5% +5VS 0_0402_5%
0.1U_0402_16V4Z QTS2
S TR LP2301ALT1G 1P SOT-23-3 JP@ JPHW4
2 <PV> Touch GPIO control by EC 1 2
1 2 1 2
@ R36 0_0603_5%
JUMP_43X39
6U@
1 2 FG3 SA00004ZA00 +3VS_CAMERA
R5175 0_0402_5%
+VCC_TOUCH D6
JP@ JPHW3 3
1 2 L13 USB20_P6_R 2 OUT
1 2 1 1
1 @EMI@ 2 USB20_N6_R 1 1 @ 6U@
<11> USB20_N6 1 2 +3VS IN
USB20_N6_R 3 C5221 C5222
JUMP_43X39 Part Number = SM070003Y00 2
GND .1U_0402_16V7K 4.7U 6.3V M X5R
TS6U@ 4 3 USB20_P6_R 2 2 SE00000SO00
<11> USB20_P6 4 3 PESD5V0U2BT_SOT23-3
A SA00004ZA00 FG2 A
WCM-2012-900T_4P @ESD@ SCA00000U10
3 AP2330W-7_SC59-3
OUT 1 2
1 1
TS6U@ @ 1 +VCC_TOUCH_IN R173 0_0402_5%
C5223 CTS3 IN
0.1U 16V K X7R 2
2 2 GND
4.7U 6.3V M X5R
SE00000SO00
AP2330W-7_SC59-3
LVDS Connector
5 4 RepairLap.com 3
2
Size
Date:
Document Number
LA-C707P
Wednesday, May 11, 2016
1
Sheet 20 of 60
Rev
v0.2
5 4 3 2 1
+3VS
PCH_DPB_P0 0.1U_0402_16V7K 1 2 CG27 PCH_DPB_P0_C +HDMI_CRT_5V
<5> PCH_DPB_P0 <22> +HDMI_CRT_5V
PCH_DPB_N0 0.1U_0402_16V7K 1 2 CG28 PCH_DPB_N0_C
<5> PCH_DPB_N0
<5,6,7,9,10,11,13,17,18,19,20,22,23,24,26,28,32,33,34,35,36,37,38,52,55,56> +3VS +3VS
PCH_DPB_P1 0.1U_0402_16V7K 1 2 CG29 PCH_DPB_P1_C
<5> PCH_DPB_P1
<CPU> PCH_DPB_N1 0.1U_0402_16V7K 1 2 CG30 PCH_DPB_N1_C +5VS
<5> PCH_DPB_N1 <20,24,26,27,30,34,35,52,53,56> +5VS
1
RG47
<5> PCH_DPB_P2
PCH_DPB_N2 0.1U_0402_16V7K 1 2 CG32 PCH_DPB_N2_C 1M_0402_5%
<5> PCH_DPB_N2
2
<5> PCH_DPB_P3
2
D PCH_DPB_N3 0.1U_0402_16V7K 1 2 CG34 PCH_DPB_N3_C D
<5> PCH_DPB_N3
1 6 HP_DETECT
<5> PCH_DDPB_HPD
20K_0402_5%
QG1A 1
5
6
7
8
5
6
7
8
2N7002KDW_SOT363-6
1
SB00000I700 CM17@
5V Level RG56 220P_0402_50V7K
QG1B SB00000I700 2
2N7002KDW_SOT363-6
4
3
2
1
4
3
2
1
3 4
2
RP3 RP4
470_0804_8P4R_5% 470_0804_8P4R_5%
5
+3VS
DB phase :
For ESD request
<Diner SI> change to 8.2 ohm and parallel 0.47p by EMI request
20141117
<PV> change to 10 ohm by EMI request +3VS
@ESD@
D21
<DB> Delete Choke add parallel 150ohm HDMI_R_CK+ 1 1 HDMI_R_CK+
10 9
HDMI_R_CK- 2 2 9 8 HDMI_R_CK-
PCH_DPB_P3_C RG59 1 2 8.2_0402_1% HDMI_R_CK+
HDMI_R_D0+ 4 4 7 7 HDMI_R_D0+
2
C HDMI_R_D0- 5 5 6 6 HDMI_R_D0- C
5
CG71
0.47P_0402_50V 3 3
1 PCH_DDPB_CLK 4 3 HDMI_SCLK
8 <5> PCH_DDPB_CLK
PCH_DPB_N3_C RG60 1 2 8.2_0402_1% HDMI_R_CK-
QG2B SB00000I700
2N7002DWH_SOT363-6
L05ESDL5V0NA-4_SLP2510P8-10-9 +3VS
PCH_DPB_N0_C RG63 1 2 8.2_0402_1% HDMI_R_D0- SC300002C00
2
CG72
0.47P_0402_50V @ESD@
1 D22 PCH_DDPB_DAT 1 6 HDMI_SDATA
<5> PCH_DDPB_DAT
PCH_DPB_P0_C RG61 1 2 8.2_0402_1% HDMI_R_D0+ HDMI_R_D1- 1 1 10 9 HDMI_R_D1-
QG2A SB00000I700
HDMI_R_D1+ 2 2 9 8 HDMI_R_D1+ 2N7002DWH_SOT363-6
PCH_DPB_P1_C RG65 1 2 8.2_0402_1% HDMI_R_D1+
HDMI_R_D2- 4 4 7 7 HDMI_R_D2-
2
HDMI_R_D2+ 5 5 6 6 HDMI_R_D2+ +HDMI_CRT_5V
CG73
0.47P_0402_50V 3 3
1 +3VS
PCH_DPB_N1_C RG64 1 2 8.2_0402_1% HDMI_R_D1- 8 RG105
1 8 HDMI_SDATA
2 7 HDMI_SCLK
PCH_DPB_P2_C RG70 1 2 8.2_0402_1% HDMI_R_D2+ L05ESDL5V0NA-4_SLP2510P8-10-9 3 6 PCH_DDPB_DAT
B SC300002C00 4 5 PCH_DDPB_CLK B
2
2.2K_0804_8P4R_5%
CG74 HDMI Conn.
0.47P_0402_50V SC300002800
1 @ESD@ DG1
PCH_DPB_N2_C RG66 1 2 8.2_0402_1% HDMI_R_D2- HP_DETECT 1 1 10 9 HP_DETECT CONN@
JHDMI1
HDMI_SDATA 2 2 9 8 HDMI_SDATA HP_DETECT 19
18 HP_DET
+HDMI_CRT_5V +5V
HDMI_SCLK 4 4 7 7 HDMI_SCLK 17
HDMI_SDATA 16 DDC/CEC_GND
5 5 HDMI_SCLK SDA
6 6 15
14 SCL
L Layout notes 3 3 13 Utility
HDMI Chock 2nd : SM070003K00 40 mils HDMI_R_CK- 12 CEC
8 @ @ 11 CK-
CK_shield
10P_0402_50V8J
10P_0402_50V8J
W=40mils 1 1 HDMI_R_CK+ 10
IP4292CZ10-TB CM26 CM27 HDMI_R_D0- 9 CK+
FG1 +HDMI_CRT_5V D0-
8
HDMI_R_D0+ 7 D0_shield
3 2 2 HDMI_R_D1- 6 D0+
OUT 5 D1-
1 HDMI_R_D1+ 4 D1_shield 23
+5VS IN D1+ GND1
1 HDMI_R_D2- 3 22
2 2 D2- GND2 21
GND HDMI_R_D2+ 1 D2_shield GND3 20
CG46 D2+ GND4
0.1U_0402_16V7K 2 ACON_HMRBL-AK120D
A AP2330W-7_SC59-3 A
DC232004700
SA00004ZA00

HDMI Conn/Level shift
RepairLap.com
v0.2
5 4 3 2 1
5 4 3 2 1
+5VS
DP to CRT converter
<20,21,24,26,27,30,34,35,52,53,56> +5VS
<5,6,7,9,10,11,13,17,18,19,20,21,23,24,26,28,32,33,34,35,36,37,38,52,55,56> +3VS +3VS
<21> +HDMI_CRT_5V +HDMI_CRT_5V
+3VS_CRT
For Power consumption
Measurement
+3VS <PV> change short pad +3VS_CRT_DVDD @ CRT@ CRT@ CRT@
+3VS +3VS_CRT C40 C41 C42 C43
D D
10U_0603_6.3V6M
0.1U_0402_16V4Z
1 1 1 1
1U_0402_6.3V6K
JPHW2 R34 1 2 0_0603_5%
1 2
1 2 0.1U_0402_25V6
JUMP_43X39 2 2 2 2
JP@
+3VS_CRT +3VS_CRT_DVDD
CRT@ CRT@
C45 C46 CRT@ CRT@
1 1 C47 C48
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1
0.1U_0402_16V4Z
10U_0603_6.3V6M
2 2
2 2 <SI> change to +HDMI_CRT_5V for SVTP test fail
+HDMI_CRT_5V
1
100K_0402_5%
CRT@
1
2
3
4
R35 CRT@
C CRT@ R38 C
20
2.2K_0804_8P4R_5%
2
U4104
9
RTD2168_SMB_SCL R53 1 2 0_0402_5%
RTD2168_SMB_SDA EC_SMB_CK2 <7,10,19,26,37>
R54 1 2 0_0402_5%
DVCC_33
DVCC_33
VDD_DAC_33
EC_SMB_DA2 <7,10,19,26,37>
8
7
6
5
<5> DDI2_HPD 1
HPD R39 1 @ 2 0_0402_5% 2014-11-24
DDI2_AUX_DN_C CRT_DATA PCH_SMBCLK <7,17,18,19> follow vendor suggest change 36 ohm
CRT@ C49 1 2 0.1U_0402_16V7K 27 6 R40 1 @ 2 0_0402_5% <KBL SI> Change ESD diode package
<5> DDI2_AUX_DN DDI2_AUX_DP_C AUX_N VGA_SDA CRT_CLK PCH_SMBDATA <7,17,18,19>
CRT@ C52 1 2 0.1U_0402_16V7K 26 4
<5> DDI2_AUX_DP AUX_P VGA_SCL HSYNC_R
8 HSYNC HSYNC 1 CRT@ 2 D4&D5 Only Pop for 6U SKU India Country
CRT@ C50 2 1 0.1U_0402_16V7K PCH_DPC_P0_C 29 HSYNC 7 VSYNC L5 36_0402_1%
<5> PCH_DPC_P0 PCH_DPC_N0_C LANE0P VSYNC D4
CRT@ C53 2 1 0.1U_0402_16V7K 30 SC300001G00
<5> PCH_DPC_N0 LANE0N VGA_RED VSYNC_R HSYNC_R VSYNC_R
15 VSYNC 1 CRT@ 2 6 3
CRT@ C51 2 1 0.1U_0402_16V7K PCH_DPC_P1_C 31 RED_P L6 36_0402_1% I/O4 I/O2
<5> PCH_DPC_P1 LANE1P 1 1
CRT@ C54 2 1 0.1U_0402_16V7K PCH_DPC_N1_C 32 12 VGA_GRN CRT@ CRT@ +HDMI_CRT_5V 6UINDESD@
<5> PCH_DPC_N1 LANE1N GREEN_P C56 C57
10 VGA_BLU 10P_0402_50V8J 10P_0402_50V8J 5 2
BLUE_P 2 2 VDD GND
22 POL1_SDA
POL1_SDA 23 POL1_SCL
POL2_SCL +3VS_CRT +3VS_CRT CRT_CLK 4 1 CRT_DATA
+VCCK_1V2 19 2 RTD2168_SMB_SCL I/O3 I/O1
VCCK_12 SMB_SCL 3 RTD2168_SMB_SDA L Layout notes
CRT@ CRT@ +3VS_CRT_DVDD 24 SMB_SDA R61,R62,R58,R59 close to RTD2168 AZC099-04S.R7G_SOT23-6
C58 C59 CRT@ CRT@ AVCC_33 R55,R57,R60,R56 close to CONN
1 1
1
C60 C61 +VCCK_1V2 25
AVCC_12
10U_0603_6.3V6M
1 1 CRT@ 21 LDO_EN_1V2 CRT@

C63 LDO_EN D5
0.1U_0402_16V4Z
28 @ R42 R43 SC300001G00

2.2U_0402_6.3V6M
0.1U_0402_16V4Z
2 2 1 RRX 4.7K_0402_5% 4.7K_0402_5% VGA_RE 6 3 VGA_GR

0.1U_0402_16V4Z
CRT@ 18 XTALOUT_2168 I/O4 I/O2

1
2
2 2 R44 11 XO +HDMI_CRT_5V 6UINDESD@
13 BLUE_N 17 XTALIN_2168
2
12K_0402_1%
14 GREEN_N XI/CKIN POL1_SDA POL1_SCL 5 2

16 GND_DAC VDD GND
33 RED_N
2
EPAD_GND
1
4 1 VGA_BL
CRT@ I/O3 I/O1
RTD2168-CG_QFN32
R45 @ R46
B
4.7K_0402_5% 4.7K_0402_5% AZC099-04S.R7G_SOT23-6 B
2
Part Number = SA000077U00
R47
XTALOUT_2168
1M_0402_5%
XTALIN_2168
50 impedance CRT Connector
CONN@
+3VS_CRT |← → | 6
JCRT1
X1
Crystal
@ CRT@ SM01000LU00 11
3 4 VGA_RED L7 1 2 BLM15BA220SN1D 0402 VGA_RE 1
OUT GND 7
1
C64 2 1 C65 CRT@ SM01000LU00 CRT_DATA 12

GND IN CRT@ VGA_GRN L8 1 2 BLM15BA220SN1D 0402 VGA_GR 2
1
18P_0402_50V8J
18P_0402_50V8J
1 R48 8 G 16
27MHZ_10PF_X3G027000BA1H-U 4.7K_0402_5% CRT@ SM01000LU00 HSYNC_R 13 17
VGA_BLU VGA_BL G
L9 1 2 BLM15BA220SN1D 0402 3
2
R49 75_0402_1%
R50 75_0402_1%
R51 75_0402_1%
@ +HDMI_CRT_5V 9
2 C66 C67 C68 C69 C70 C71 VSYNC_R 14
1
LDO_EN_1V2 1 1 1 1 1 1 W=40mils 1 C72 4
0.1U_0201_10V6K
10
22P_0402_50V8
22P_0402_50V8
22P_0402_50V8
22P_0402_50V8
22P_0402_50V8
22P_0402_50V8
@ CRT_CLK 15
5
1
2 2 2 2 2 2 2
2
@ @ C-K_80454-5K1-152
@ R52 CRT@ CRT@ CRT@ DC060004S10
4.7K_0402_5%
2
CRT@ CRT@ CRT@ CRT@ CRT@ CRT@

A A

DP to CRT RTD2168
Custom v0.2
5 4 3 2 1
RepairLap.com
5 4 3 2 1
+LAN_VDD_3V3 Rising time LDO mode Switcing mode

J1
JP@ LL1 SMT @
1
1 2
2 need>0.5mS and <100mS 8/15 Change to LDO Mode
CL21 SMT @
+3VALW JUMP_43X79
@ UG5
LL2 @ SMT
CL8,CL23 @ SMT +LAN_VDD_1V0 CL13 & CL15 close UL1 Pin22
5 1 +LAN_VDD_3V3 @
IN OUT LL1 1 2 0_0603_5%
2
CL14 & CL27 close UL1 Pin30
RL35 GND
1 @ 2 1 4 3 LL2
0_0201_5% SS EN +LAN_REGOUT 1 2
1U_0402_6.3V6K
0.1U_0402_16V7K
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
4.7U_0603_6.3V6K
@ CL28 2.2UH +-5% NLC252018T-2R2J-N
0.1U_0402_16V7K
APL3512_SOT23-5 giga8111@ 1 1 1 1 1 1 1 1 1
D
1500P_0402_50V7K 2 D
CL8
CL23
1 @ @
@ CL11 CL12 CL13 CL14 CL15 CL26 CL27
CL21 giga8111@ giga8111@
2 2 2 2 2 2 2 2 2
2
giga8111@
Place CL11~CL12 close UL1 Pin 3,8 EC_LAN_ISOLATEB#_R 2 1
LL2, CL8, CL23 for 8161 1K_0402_5% RM6
+3VS
1
CL8 & CL18 close LL2
2
+LAN_VDD_3V3 +VDDREG @ CL29
2
0.1U_0402_16V7K 8151/8166 Co-Lay UL1 RM11
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
giga8111@
0.1U_0402_16V7K
0.1U_0402_16V7K
RTL8151GH +LAN_VDD_3V3=40mil 15K_0402_5%

1 1 1 1 1 1 giga8111@ 100_8166@ SA000084T00
1
CL10
CL16
0.1U_0402_16V7K
UL1 +LAN_VDD_1V0 +VDDREG=40mil
CL20 @ CL19 CL9 CL5 L
@ +LAN_REGOUT=60mil
2 2 2 2 2 2 LAN_MDIP0 1 3
LAN_MDIN0 2 MDIP0 AVDD10 8
0923 PV CNG from DP00 to E500
@giga8111@ LAN_MDIP1 4 MDIN0 AVDD10 30 +LAN_VDD_3V3 XTLI
LAN_MDIN1 5 MDIP1 AVDD10 22 +LAN_VDD_3V3
LAN_MDIP2 6 MDIN1 DVDD10 2 1 XTLO
LAN_MDIN2 7 MDIP2 11 +LAN_VDD_3V3 1M_0402_5% RL7
MDIN2 AVDD33
1
LAN_MDIP3 9 32
LAN_MDIN3 10 MDIP3 AVDD33 RL10 RL15
MDIN3 23 +VDDREG 1 2 10K_0402_5%
CL9 & CL5 close to UL1: Pin 11,32 CL10& CL16 close to UL1: Pin 23 VDDREG(VDD33) 24 +LAN_REGOUT
LAN_CLKREQ# 2 RL6 Rshort@
1 0_0201_5% LAN_CLKREQ#_R 12 REGOUT 0_0603_5%
CL19 close to UL1: Pin 32 <9> LAN_CLKREQ# RTL8111G
2
PLT_RST# 19 CLKREQB 21 EC_PME#
<9,26,28,32,36> PLT_RST# PERSTB LANWAKEB EC_PME# <26>
3
CL20 close to UL1: Pin 11 20 EC_LAN_ISOLATEB#_R YL1
CLK_PCIE_LAN 15 ISOLATEB
2 2
OSC
OSC
<9> CLK_PCIE_LAN REFCLK_P
10P_0402_50V8J
10P_0402_50V8J
CLK_PCIE_LAN# 16 27 LAN_ACT# EC control 08/17 Add 0ohm
<9> CLK_PCIE_LAN# REFCLK_N LED0 26 LED1/GPO TH1 CL25 CL24
PCIE_PTX_C_DRX_P5 13 LED1/GPO 25 LAN_LINK#
GND
GND
<11> PCIE_PTX_C_DRX_P5 HSIP LED2(LED1) 1 1
PCIE_PTX_C_DRX_N5 14
<11> PCIE_PTX_C_DRX_N5 PCIE_PRX_DTX_P5 HSIN
C CR11 1 2 0.1U_0402_10V7K PCIE_PRX_C_DTX_P5 17 28 XTLI C
<11> PCIE_PRX_DTX_P5 PCIE_PRX_DTX_N5 HSOP CKXTAL1
CR13 1 2 0.1U_0402_10V7K PCIE_PRX_C_DTX_N5 18 29 XTLO
<11> PCIE_PRX_DTX_N5
4
HSON CKXTAL2
RSET 31 33
RSET GND 25MHZ 10PF 5YEA25000102IF50Q3
2
SP050005L00 Footprint SJ10000E500
RL11
TSL1 100_8166@ 2.49K_0402_1% SA000063500
25 XGND RL55 1 2 0_0805_5%
Rshort@
+V_DAC 1 LANGND 24
(SA000063500) 8166GSH 10/100
1
LAN_MDIN3 2 TCT1 MCT1 23 RJ45_TX3- RP5
LAN_MDIP3 3 TD1+ MX1+ 22 RJ45_TX3+ 1 8 (SA000084T00) 8111HSH-CG Giga
Swap P/N 08/16 TD1- MX1- 2 7
4
TCT2 MCT2
21 3 6 11/18 modify vendor review results
LAN_MDIN2 5 20 RJ45_TX2- 4 5
LAN_MDIP2 6 TD2+ MX2+ 19 RJ45_TX2+
TD2- MX2-
7
TCT3 MCT3
18
75_0804_8P4R_1%
SD300002E80 2
11/15 change CONN.
LAN_MDIN1 8 17 RJ45_RX1- CL2 +LAN_VDD_3V3
LAN_MDIP1 9 TD3+ MX3+ 16 RJ45_RX1+ SE167100J80
TD3- MX3- 10P_1808_3KV JLAN1
10 15 1 10
LAN_MDIN0 11 TCT4 MCT4 14 RJ45_TX0- A2_AmberLED+
TD4+ MX4+ 1
LAN_MDIP0 12 13 RJ45_TX0+ CL3 EMI@ LAN_ACT# 2 1 LAN_ACT#_R 9
TD4- MX4- A1_AmberLED-
3
120P_0402_50V8J RL31 510_0402_5%

YSLC05CH_SOT23-3
LANGND 1 RJ45_TX3- 8
TSL1 DL1 ESD@ 2 @ TX3-
2 1 CAP_LAN-8700GS giga8111@ SCA00000U10 CL35 RJ45_TX3+ 7
@EMI@ S X'FORM_ LAN-8100G 1G TX3+
SP050008V00 68P_0402_50V8J
CL1 CL4 SP050008Y00 2 RJ45_RX1- 6
RX1-
1
0.01U_0402_16V7K
2
0.1U_0402_16V7K 2016-03-03:Change Single Source RJ45_TX2- 5
(SP050008V00) 10/100 TX2-
1
(SP050008Y00) Giga RJ45_TX2+ 4

TX2+
RJ45_RX1+ 3
RX1+
B
11/17 reserver for ESD request @ESD@
RJ45_TX0- 2
TX0- 13 B
@ESD@ GND1
DM13 RJ45_TX0+ 1 14
DM12 TX0+ GND2
LAN_MDIP0 4 3 LAN_MDIN0 LAN_MDIP2 4 3 LAN_MDIN2
4 3 4 3 11
B2_WhiteLED+
LAN_LINK# 2 1 LAN_LINK#_R 12
RL30 510_0402_5% B1_WhiteLED-
1 CONN@ LANGND
powe rail need to check powe rail need to check @
CL34
5 2 68P_0402_50V8J
+LAN_VDD_3V3 5 2 +LAN_VDD_3V3 Vbus GND 2
Vbus GND
LAN_MDIP1 6 1 LAN_MDIN1 LAN_MDIP3 6 1 LAN_MDIN3

6 1 6 1
YSUSB2.0-5_SOT-23-6-6 YSUSB2.0-5_SOT-23-6-6
SC300001400 SC300001400
A
CR RTS5237S move to S/B A

LAN 8151/8166_ CR RTS5238
5 4 RepairLap.com 3
2
Size
Date:
Document Number
LA-D707P
1
Sheet 23 of 60
Rev
v0.2
5 4 3 2 1
<PV> change short pad <DB> Change PWR Rail
<5,6,7,9,10,11,13,17,18,19,20,21,22,23,26,28,32,33,34,35,36,37,38,52,55,56> +3VS +3VS +3VS +DVDD +DVDD_IO +1.8VS +3VS
Need to check 20141110
<12> +1.8VS +1.8VS
RA2 1 Rshort@ 2 0_0603_5% 1 @ 2
+5VS LA3
<20,21,26,27,30,34,35,52,53,56> +5VS
.1U_0402_16V7K
CA5
10U_0603_6.3V6M
CA6
.1U_0402_16V7K
CA7
10U_0603_6.3V6M
CA8
SUPPRE_ KC FBMA-10-100505-101T 0402
L Layout notes 1 1 1 1 PCB Footprint = R_0402
1 2
CA5 CA6 close Pin1
UA1 CA7 CA8 close Pin9 LA7 0_0402_5%
2 2 2 2
20 1
CA9 CA10 close Pin26
MIC1_R DVDD +DVDD CA12 CA13 close Pin40
19 9 +DVDD_IO <7/1>LA3/LA4/LA5/LA6 change to 0-ohm.
MIC1_L DVDD_IO
CA1 1 2 4.7U_0402_6.3V6M INT_MICR_C 18 26 +5VS_AVDD <9/1>LA3/LA4/LA5/LA6 change to 0-ohm short-pad
INT_MIC RA3 1 2 1K_0402_5% CA4 1 2 4.7U_0402_6.3V6M INT_MICL_C 17 MIC2_R AVDD1 40
MIC2_L AVDD2 +1.8VS_AVDD
D <PV> change short pad <DB> Change PWR Rail D
31 41 +5VS_PVDD
30 MIC1_VREFO_L PVDD1 46 +5VS_AVDD +5VS
<26> MUTE_LED_IN MIC1_VREFO_R PVDD2 +1.8VS_AVDD +1.8VS
+MIC2_VREFO 29
MIC2_VREFO
1
LA4 1 Rshort@ 2 0_0603_5%
11/24 modify mute LED that controled by EC 23 45 SPK_R+ LA5 1 2 0_0402_5%
10K_0402_5% LINE2_R SPK_OUT_R+
.1U_0402_16V7K
CA9
4.7U_0603_6.3V6K
CA10
24 44 SPK_R-
LINE2_L SPK_OUT_R-
.1U_0402_16V7K
CA12
4.7U_0603_6.3V6K
CA13
RA30 1 2
Internal Speaker 1 2
2
16 42 SPK_L+ Need to check 20141110
MONO_OUT SPK_OUT_L+ SPK_L-
SPK_OUT_L-
43 change 30 ohm from vendor suggest
PC_BEEP 12 2 1
PCBEEP 20141120 2 1
+3VS 10 33 HPOUT_R RA4 1 2 30_0402_1% HP_OUTR
<8> HDA_SYNC_AUDIO SYNC HPOUT_R 32 HPOUT_L RA5 1 2 30_0402_1% HP_OUTL
Headphone
HDA_RST_AUDIO# 11 HPOUT_L
<8> HDA_RST_AUDIO# RESET#
2 CPVDD +3VS 1 @ 2 5 GNDA
SDATA_OUT SDATA_IN RA7 HDA_SDOUT_AUDIO <8>
RA6 8 1 2 22_0402_5% GNDA
ALDO_CAP SDATA_IN HDA_SDIN0 <8>
CA17 4.7K_0402_5% CA11 1 2 10U_0603_6.3V6M 7
LDO3-CAP 6 +5VS_PVDD +5VS
4.7U_0603_6.3V6K BCLK HDA_BITCLK_AUDIO <8>
1 CA14 1 2 2.2U_0402_6.3V6M ACPVEE 34 LA6 SM01000NS00
CPVDD 36 CPVEE 22 1 2
CBN 35 CPVDD LINE1_L 21 TAI-TECH HCB2012VF-601T20 0805
CBN LINE1_R
.1U_0402_16V7K
CA20
.1U_0402_16V7K
CA21
10U_0603_6.3V6M
CA22
10U_0603_6.3V6M
CA23
CA15 1 2 2.2U_0402_6.3V6M CBP 37 48 MIC_JD
CBP SPDIFO/GPIO2
3
1 1 2 2
15 JDREF RA9 2 1 20K_0402_1% DA8
2 JDREF 28 AVREF CA16 2 1 .1U_0402_16V7K
<20> D_MIC_DATA GPIO0/DMIC_DATA VREF YSLC05CH_SOT23-3
3 27 CA18 1 2 10U_0603_6.3V6M SCA00002900
<20> D_MIC_CLK GPIO1/DMIC_CLK LDO1_CAP 2 2 1 1
39 CA19 1 2 10U_0603_6.3V6M
LDO2_CAP
PLUG_IN# RA10 1 2 39.2K_0402_1% SENSEA 13 25 2 RA29 1 100K_0402_5%
14 SENSE_A AVSS1 38
SENSE_B AVSS2
1
4 GNDA
DVSS
47
PDB Thermal Pad
49 add 100k from vendor suggest
+1.8VS +DVDD 20141120
1
C ALC3227-CG_MQFN48P_6X6 AVREFCA24 1 2 2.2U_0402_6.3V6M C

1
@ PCB Footprint = ACES_50278-00401-001_4P

RA25
<SI> QA2 change from NMOS to BJT
<PV> QA2 change to QA1.
2.2K_0402_5% 1K_0402_5%
RA26 GNDA GNDA
Internal SPK <DB> change foorprint
2 2

2
B
JSPK1
SPK_R- RA13 1 Rshort@ 2 0_0603_5% SPK_R-_CONN 1
1
E
HDA_RST_AUDIO# 3 1 PD# SPK_R+ RA14 1 Rshort@ 2 0_0603_5% SPK_R+_CONN 2

2
C
SPK_L- RA15 1 Rshort@ 2 0_0603_5% SPK_L-_CONN 3 5

Part Number = SB000008E10 QA1 @ SPK_L+ RA16 1 Rshort@ 2 0_0603_5% SPK_L+_CONN 4 3 GND 6
4 GND
1
MMBT3904WH_SOT323-3
Power down (PD#) power stage for save power E-T_3703K-F04N-03R
1 2 10K_0402_5% CONN@
<26> EC_MUTE# RA11 0V: Power down power stage
wide 40 MIL
220P_0402_50V7K
220P_0402_50V7K
220P_0402_50V7K
220P_0402_50V7K
DA3 SP02000H310
CH751H-40PT_SOD323-2 3.3V: Power up power stage
2
@SCS00003500 1 1 1 1
@EMI@ C123
@EMI@ C124
@EMI@ C125
@EMI@ C126
2 2 2 2
Reserve for ESD request.

INT_MIC_R HP_OUTR_R HP_OUTL_R
GNDA
3
PC Beep
3
DA4
YSLC05CH_SOT23-3 DA6
SCA00002900 YSLC05CH_SOT23-3
ESD@ SCA00000U10
1 2 PC_BEEP_R @ESD@
EC Beep <26> EC_BEEP#
CA31
.1U_0402_16V7K RA19 +MIC2_VREFO
Jack detect
1
B B
47K_0402_5%
1
SB Beep <8,10> HDA_SPKR 1 2 1 2 1 2 PC_BEEP Combo Mic = High
1
CA33 CA34
Normal HP = Low
1
.1U_0402_16V7K .1U_0402_16V7K
RA17
RA20 2.2K_0402_5%
10K_0402_5%
L
2
Layout notes MIC_JD 1 2 INT_MIC
2
RA18
Close chip Pin12
10U_0603_6.3V6M
CA32
22K_0402_5%
2
GNDA
COMBO AUDIO JACK

CONN@
JHP
RA27 1 2 0_0402_5% HPR, HPL, 15mil Keep 30mil
INT_MIC RA21 1 2 0_0402_5% INT_MIC_R 3
HP_OUTL RA22 1 2 0_0402_5% HP_OUTL_R 1

RA28 1 2 0_0402_5%
PLUG_IN# 5
1 2
CA40 @EMI@ 6
.1U_0402_16V7K HP_OUTR RA23 1 2 0_0402_5% HP_OUTR_R 2
4
7
GND
100P_0402_50V8J
CA35
10P_0402_50V8J
CA36
10P_0402_50V8J
CA37
1 2 1 1 1
1
CA38 @EMI@ YUQIU_PJ750-F07J1BE-A

A .1U_0402_16V7K RA24 @EMI@ DC2301411240 A
@EMI@
@EMI@
22K_0402_5%
2 2 2
1 2 GNDA
2
CA39 @EMI@
.1U_0402_16V7K Pin6 and Pin5
Normal OPEN
1 2 GNDA GNDA GNDA GNDA
CA29 EMI@
.1U_0402_16V7K
1 2 Security Classification Compal Secret Data Compal Electronics, Inc.

CA30 EMI@ 2013/01/04 2015/01/04 Title
.1U_0402_16V7K
AUDIO ALC3227-CG
GNDA
5 4 RepairLap.com 3
2
Size
C
Date:
Document Number

LA-D707P
1
Sheet 24 of 60
Rev
v0.2
A B C D E
WIN 7 Debug Solution

Option 1 : For Closed Chassis Platforms
1 1
2 2
3 3
4 4

DC Interface
RepairLap.com
Custom v0.2
A B C D E
5 4 3 2 1
7,9,10,11,13,17,18,19,20,21,22,23,24,28,32,33,34,35,36,37,38,52,55,56> +3VS +3VS

+3VL

+3VALW_EC
LK1
S SUPPRE_ TAI-TECH HCB1005KF-221T15 0402
+3VALW_EC EC Board ID (UMA, Dis, phase) control table
0.1U_0402_16V7K
0.1U_0402_16V7K
1 2 +3VALW_EC 1 2 +EC_VCCA
<45> +3VALW_EC +3VALW_EC RK4 DB SI PV MV Note
2
CK1
CK2
RK1 0_0603_5% 1 1 1
RK2
<13,33,46,47,48> +3VL +3VL
CK3 100K_0402_1%
UMA 15Kohm 27Kohm 43Kohm 75Kohm
ECAGND
0.1U_0402_16V7K
2 2 2 Dis 20Kohm 33Kohm 56Kohm 100Kohm
1
BOARD_ID
Current
+3V_EC_VDD DB_UMA_15kohm:SD034150280, S RES 1/16W 15K +-1% 0402
2
ESD@ DB_DIS_20kohm:SD034200280, S RES 1/16W 20K +-1% 0402
D
CK4
1 RK3 2 +3VL PX@ UMA@ SI_UMA_27kohm:SD034270280, S RES 1/16W 27K +-1% 0402 Reserve EC_CLR_CMOS for clear CMOS D
2 1 PLT_RST# 0_0402_5% RK4 RK4 SI_DIS_33kohm:SD034330280, S RES 1/16W 33K +-1% 0402
(2016-03-04 : Confirm intel platform not support
56K +-1% 0402 PV_UMA_43kohm:SD034430280, S RES 116W 43K +-1% 0402 EC Clear CMOS function)
SD034560280 43K +-1% 0402 PV_DIS_56kohm:SD034560280, S RES 1/16W 56K +-1% 0402
1
0.1U_0402_16V7K SD034430280 MV_UMA_75kohm:SD034750280, S RES 1/16W 75K +-1% 0402 RK106 1 2 0_0402_5% CLR_CMOS# <9>
111
125
MV_DIS_100kohm:SD034100380, S RES 1/16W 100K +-1% 0402 @
22
33
96
67
UK1
1
Board ID control @
<SI> un-mount RC , Internal PU in 9022
VCC_LPC
VCC
VCC
VCC
VCC0
VCC
AVCC
D
@ EC_CLR_CMOS 2 Q51
+3VALW_EC RK7 2 1 330K_0402_5% EC_RST# G 2N7002K_SOT23-3
2
TOUCH_ON# 1 21 EC_VCCST_PG_R S
<20> TOUCH_ON# GATEA20/GPIO00 EC_VCCST_PG/GPIO0F EC_VCCST_PG_R <9,35>
@ 1 2 EC_KBRST# 2 23 2014-11-13: R483
<7> EC_KBRST# EC_BEEP# <24>
3
CK5 0.1U_0402_16V7K SERIRQ 3 KBRST#/GPIO01 BEEP#/GPIO10 26 EC_FAN_PWM1 Pin64 from BOARD_ID to X no support KBL
@
<7,28> SERIRQ SERIRQ EC_FAN_PWM/GPIO12 EC_FAN_PWM1 <34> Pin66 from X to BOARD_ID 10K_0402_5%
LPC_FRAME# 4 PWM Output 27 EC_CLR_CMOS Pin76 Pin97 swap
<7,28> LPC_FRAME# LPC_AD3 LPC_FRAME# AC_OFF/GPIO13 Pin84 from PM_SLP_S4# to USB_ON#
5
<7,28> LPC_AD3 Pin68 from +1.05V_VS_PG_PWR to MINI1_LED#
1
LPC_AD2 7 LPC_AD3
Pin70 NC , no support
<7,28> LPC_AD2 LPC_AD1 LPC_AD2 Pin72 NC , no support
8 63 B/I#
<7,28> LPC_AD1 LPC_AD0 LPC_AD1 VCIN1_BATT_TEMP/AD0/GPIO38 VGA_AC_BATT B/I# <46> Pin86 NC , no suppout
10 LPC & MISC 64
<7,28> LPC_AD0 LPC_AD0 VCIN1_BATT_DROP/AD1/GPIO39 VGA_AC_BATT <37>
65 ADP_I
CLK_PCI_LPC ADP_I/AD2/GPIO3A BOARD_ID ADP_I <45,47>
12 AD Input 66
<7> CLK_PCI_LPC
<9,23,28,32,36> PLT_RST#
PLT_RST# 13 CLK_PCI_EC AD_BID/AD3/GPIO3B 75 ADP_ID
ADP_ID <45>
<SI> EC request to add RK9
EC_RST# 37 PCIRST#/GPIO05 AD4/GPIO42 76 EC_PME#_EC_R R5178 1 2 0_0201_5%
EC_RST# AD5/GPIO43 EC_PME# <23>
EC_SCI# 20 VR_HOT# 1 2 0_0402_5% PROCHOT# <5>
<5,10> EC_SCI# EC_SCI#/GPIO0E <52> VR_HOT#
1 @ 2 PM_CLKRUN#_R 38 RK8
<7> PM_CLKRUN# CLKRUN#/GPIO1D
<9,32> EC_PCIE_WAKE# RK10 1 2 0_0402_5%
RK6 0_0402_5% 68
DA0/GPIO3C NMI_DBG# MINI1_LED# <32>
DA Output 70
<27> KSI[0..7] EN_DFAN1/DA1/GPIO3D
1
VR_PWRGD D
KSI0 55 71
KSI0/GPIO30 DA2/GPIO3E EC_MUTE# VR_PWRGD <52> H_PROCHOT#_EC 2
KSI1 56 72
KSI1/GPIO31 DA3/GPIO3F EC_MUTE# <24>
KSI2 57 G
KSI3 58 KSI2/GPIO32 83 EC_SMB_CK3 @ QK1 S
EC_SMB_CK3 <37>
3
KSI4 59 KSI3/GPIO33 EC_MUTE#/PSCLK1/GPIO4A 84 EC_SMB_DA3 2N7002_SOT23-3
C KSI4/GPIO34 USB_EN#/PSDAT1/GPIO4B EC_SMB_DA3 <37> C
@ KSI5 60 85 VR_ON
KSI5/GPIO35 PSCLK2/GPIO4C VR_ON <35,52>
1 2 VCIN1_ACOK_R KSI6 61 PS2 Interface 86 WLAN_OFF_LED#
<47> VCIN1_ACOK KSI6/GPIO36 PSDAT2/GPIO4D WLAN_OFF_LED# <27>
R4958 0_0402_5% KSI7 62 87 TP_CLK
<27> KSO[0..17] KSI7/GPIO37 TP_CLK/GPIO4E TP_DATA TP_CLK <27>
KSO0 39 88
KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <27>
KSO1 40 RK9 1 2 0_0402_5%
KSO2 41 KSO1/GPIO21
1 2 VCIN1_AC_IN_R KSO3 42 KSO2/GPIO22 97 ENBKL +3VALW
R5094 0_0402_5% KSO4 43 KSO3/GPIO23 ENKBL/GPXIOA00 98 ENBKL <5>
KSO4/GPIO24 WOL_EN/GPXIOA01 ME_Flash_EN WL_PWREN_EC <30> TP_CLK
KSO5 44 99 RK12 1 2 4.7K_0402_5%
KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 VCIN0_PH ME_Flash_EN <8>
KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH1/GPXIOD00 VCIN0_PH <45>
TP_DATA RK13 1 2 4.7K_0402_5%
KSO8 47 KSO7/GPIO27
KSO8/GPIO28 SPI Device Interface
VCIN1_AC_IN 1 @ 2 VCIN1_AC_IN_R KSO9 48 119
KSO9/GPIO29 MISO/GPIO5B EC_SPI_SO <7>
R4960 0_0402_5% KSO10 49 120
KSO10/GPIO2A MOSI/GPIO5C EC_SPI_CLK EC_SPI_SI <7> +3VL
KSO11 50 SPI Flash ROM SPICLK/GPIO58 126
For Solve tPCH04(Min 9ms) Sequence Timing KSO12 51 KSO11/GPIO2B 128
KSO12/GPIO2C SPICS#/GPIO5A EC_SPI_CS0# <7>
KSO13 52
KSO14 53 KSO13/GPIO2D RP12
KSO15 54 KSO14/GPIO2E 73 PCH_PWR_EN 8 1
KSO15/GPIO2F EC_CIR_RX/AD6/GPIO40 TS_GPIO_EC <20>
KSO16 81 74 SYS_PWROK PLT_RST# 7 2
KSO16/GPIO48 SYS_PWROK/AD7/GPIO41 SYS_PWROK <9>
KSO17 82 89 EC_S0IX_EN EC_ON 6 3
KSO17/GPIO49 GPIO50 BAT_CHG_LED EC_S0IX_EN <12>
90 5 4
BATT_CHG_LED#/GPIO52 CAP_LOCK# BAT_CHG_LED <45>
91
CAPS_LED#/GPIO53 PWR_LED# CAP_LOCK# <27>
77 GPIO 92 100K_0804_8P4R_5%
<46,47> EC_SMB_CK1 EC_SMB_CLK1/GPIO44 PWR_LED#/GPIO54 PWR_LED# <33>
78 93 ACIN ACIN <9,37>
<46,47> EC_SMB_DA1 EC_SMB_DAT1/GPIO45 BATT_LOW_LED#/GPIO55
RK15 1 2 0_0402_5% EC_SMB_CK2_R 79 95 SYSON PBTN_OUT# R295 1 @ 2 1K_0402_5%
<7,10,19,22,37> EC_SMB_CK2 EC_SMB_CLK2/GPIO46 SYSON/GPIO56 SYSON <12,35,49>
RK16 1 2 0_0402_5% EC_SMB_DA2_R 80 121 BT_ON_EC
<7,10,19,22,37> EC_SMB_DA2 EC_SMB_DAT2/GPIO47 VR_ON/GPIO57 PCH_DPWROK BT_ON_EC <32> EC_CLR_CMOS
127 1 @ 2
DPWROK_EC/GPIO59 PCH_DPWROK <9>
SM Bus RK107 10K_0402_5%
<DB> for leakage of LED light
PM_SLP_S3# PCH_RSMRST# PCH_RSMRST# <9> +3VALW_EC
<9,12,35> PM_SLP_S3# 6 100
+5VS 2014-11-13: PM_SLP_S5# 14 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 101 USB_ON#
Pin16 from MINI1_LED# to PM_SLP_SUS# <9> PM_SLP_S5# GPIO07 GPXIOA04 USB_ON# <31,33>
B SUSACK# 15 102 VCIN1_PH LID_SW# RK18 2 1 47K_0402_5% B
Pin29 from PM_SLP_SUS# remove <9> SUSACK# GPIO08 VCIN1_ADP_PROCHOT/GPXIOA05 VCIN1_PH <45> +3VS
Pin25 from EC_INVT_PWM remove
<9,13> PM_SLP_SUS# PM_SLP_SUS# 16 103 H_PROCHOT#_EC
Pin19 from EC_+1.05VS_PG to GPU_HOT# PCH_SUSWARN# 17 GPIO0A VCOUT1_PROCHOT#/GPXIOA06 104 MAINPWON
Pin21 from GPU_HOT# to EC_+1.05VS_PG <9> PCH_SUSWARN# GPIO0B VCOUT0_MAIN_PWR_ON/GPXIOA07 MAINPWON <48>
Pin25 from EC_INVT_PWM remove WLAN_ON_LED# 18 105 EC_BKOFF# EC_BKOFF# <19> EC_SMB_CK1 8 1 RP11
RK28 Pin122 from GPU_THERMAL_DET# to PBTN_OUT# <27> WLAN_ON_LED# GPIO0C BKOFF#/GPXIOA08
19 GPIO GPO 106 RK25 1 2 0_0402_5% DGPU_PWR_EN <10,38,55,56> EC_SMB_DA1 7 2
2 1 MUTE_LED_OUT
Pin123 from X to PM_SLP_S4# <37,56> GPU_PROCHOT# 25 AC_PRESENT/GPIO0D GPXIOA09 107 PCH_PWR_EN EC_SMB_CK2 6 3
Pin18 remove
<24> MUTE_LED_IN PWM2/GPIO11 PCH_PWR_EN/GPXIOA10 PCH_PWR_EN 2014-11-13:
<13,35,51>
Pin36 remove no support USB CHR FAN_SPEED1 28 108 +1.0V_VS_PG_PWR EC_SMB_DA2 5 4
<34> FAN_SPEED1 FAN_SPEED1/GPIO14 PWR_VCCST_PG/GPXIOA11 +1.0V_VS_PG_PWR <50> Pin108 from USB_ON# to +1.05V_VS_PG_PWR
100K_0402_5% VCIN1_ACOK_R 29 Pin106 NC , no support
E51TXD_P80DATA 30 FANFB1/GPIO15 2014-11-18 2.2K_0804_8P4R_5%
<32> E51TXD_P80DATA EC_TX/GPIO16 Pin108 from +1.05V_VS_PG_PWR to VGA_AC_BATT
E51RXD_P80CLK 31 110 VCIN1_AC_IN_R
RK26 <32> E51RXD_P80CLK EC_RX/GPIO17 VCIN1_AC_IN/GPXIOD01 2014-11-24
PCH_PWROK 32 112 EC_ON Pin108 from VGA_AC_BATT to 1.05V_VS_PG_PWR
<9> PCH_PWROK PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON <48>
2 1 E51TXD_P80DATA AC_LED# 34 114 ON/OFF# EC_SCI# 10K_0402_5% 2 @ 1 RK14
<45> AC_LED# SUSP_LED#/GPIO19 ON/OFF#/GPXIOD03 ON/OFF# <33>
36 GPI 115 LID_SW#
<27> MUTE_LED_OUT NUM_LED#/GPIO1A LID_SW#/GPXIOD04 LID_SW# <33>
100K_0402_5% 116 SUSP#
SUSP#/GPXIOD05 VCIN1_AC_IN SUSP# <12,13,35,49>
117
GPXIOD06 118 EC_PECI RK17 1 243_0402_1% RK23 100K_0402_5%
PBTN_OUT# PECI/GPXIOD07 H_PECI <5>
<9> PBTN_OUT# 122 SYSON 1 @ 2
PM_SLP_S4# 123 PBTN_OUT#/GPIO5D 124 +V18R 2014-11-25
<9,12,35,49> PM_SLP_S4# PM_SLP_S4#/GPIO5E V18R/VCC_IO2 +3VALW_EC Reserve for co-lay Nuvoton NPCE388N
RK19 100K_0402_5% 1 RK27 100K_0402_5%
AGND
1 @ 2 PCH_DPWROK CK8 SUSP# 1 @ 2

GND
GND
GND
GND
GND
1 @ 2 PCH_PWROK 4.7U_0603_6.3V6K
RK20 100K_0402_5% KB9022QD_LQFP128_14X14 2
11
24
35
94
113
69
+3VALW_EC
20mil
EC_SPI_CLK RC369 1 2 PCH_SPI_CLK_R
PCH_SPI_CLK_R <7>
1
LK2 EMI@ 15_0402_5%

RK21 ECAGND 2 1
10K_0402_5% TAI-TECH HCB1005KF-221T15 0402 CC128 RC369 place near EC Side CC144
22P_0402_50V8J
@EMI@
2
ECAGND <45>
A A
NMI_DBG# 1 2 NMI_DBG#_CPU <5,10> EMI request
DK2 SCS00003500
CH751H-40PT_SOD323-2

EC ENE-KB9022
Custom v0.2
RepairLap.com
5 4 3 2 1
<7,13,20,23,26,30,33,35,48,49,50,51,55> +3VALW +3VALW
<12,13,20,30,31,33,35,38,48,49> +5VALW +5VALW
TP Button BD Connector
+3VALW <26> KSI[0..7]
CONN@ KSI7
JTP1
KSI6
KSI5
Keyboard conn
1 KSI4
2 1 KSI3
<26> TP_CLK 2
3 KSI2 JKB1
<26> TP_DATA 3
4 KSI1 KSI1 1
5 4 KSI0 KSI7 2 1
<7> TP_SMBCLK 5 2
6 KSI6 3
<7> TP_SMBDATA 6 3
7 KSO9 4
8 G1 KSI4 5 4
G2 KSI5 6 5
<26> KSO[0..17] 6
JXT_FP202DH-006M10M KSO17 KSO0 7
PS2+SMBus 7
2
1 1 SP01001YK00 KSO16 KSI2 8

DM5 KSO15 KSI3 9 8
YSLC05CH_SOT23-3 C135 C136 KSO14 KSO5 10 9
SCA00000U10 KSO13 KSO1 11 10
ESD@ 2 2 KSO12 KSI0 12 11
12
470P_0402_50V8J
470P_0402_50V8J
KSO11 KSO2 13
<SI> add 470p for EMI issue KSO10 KSO4 14 13
KSO9 KSO7 15 14
KSO8 KSO8 16 15
1
KSO7 KSO6 17 16
KSO6 KSO3 18 17
KSO5 KSO12 19 18
KSO4 KSO13 20 19
@ @ KSO3 KSO14 21 20
KSO2 KSO11 22 21
KSO1 KSO10 23 22
KSO0 KSO15 24 23
KSO16 25 24
KSO17 26 25
27 26
+5VS 27
CAP_LOCK# R203 1 2 3.3K_0402_5% 28
<26> CAP_LOCK# 28
<26> MUTE_LED_OUT R207 1 2 3.3K_0402_5% 29
+5VALW +5VALW WLAN_OFF_LED# 30 29
WLAN_ON_LED# 31 30 33
32 31 G1 34
+5VS 32 G2
1 ACES_50690-0320N-P01
@EMI@ CAP_LOCK# CONN@ SP01001RG00
C134 MUTE_LED_OUT
470P_0402_50V8J
2
2014-11-24 1 1
BOM control
CC122 CC123
1
Amber White 2
100P_0402_50V8J
2
100P_0402_50V8J
ESD@ ESD@
R157 R158
3.3K_0402_5% 3.3K_0402_5%
2
<26> WLAN_OFF_LED# WLAN_ON_LED# <26>

ESD@
KSI0 C193 2 1 100P_0402_50V8J

KB/TP
B v0.2
RepairLap.com
5 4 3 2 1
<5,6,7,9,10,11,13,17,18,19,20,21,22,23,24,26,32,33,34,35,36,37,38,52,55,56> +3VS +3VS
D D
TPM2.0 Screw Hole

+3VS H4 H1 H2 H14 H12 H6 H5 H3
H_2P5 H_2P5 H_2P5 H_2P8 H_2P8 H_2P5 H_2P5 H_2P8
R26 1 TPM@2 0_0402_5% +3VS_TPM HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
@ @ @ @ @ @ @ @
1
0.1U_0402_16V4Z
1 TPM@ 1 @ 1 @ 1
@ C35 C36 C37
C34
0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2
C C
0.1U_0402_16V4Z
H15 H16 H17 H11 H9 H10

@ H_5P0 H_5P0 H_5P0 H_5P0 H_5P0 H_5P0
U4
26 5 HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
<7,26> LPC_AD0 LAD0 VDD
23 10
20 19
17 24 @ @ @ @ @ @
<7,26> LPC_AD3
1
LAD3 VDD
22
<7,26> LPC_FRAME# LFRAME#
16
<9,23,26,32,36> PLT_RST# LRESET#
27 1
<7,26> SERIRQ SERIRQ NC
21 2
<7> CLK_PCI_TPM LCLK NC 3
R29 1 @ 2 4.7K_0402_5% 6 NC 8
+3VS_TPM GPIO NC
1 @ 2 7 9 R28 2 TPM@1 PLT_RST# H19 H8 H18 H7
R27 PP NC 12 0_0402_5% H_2P4X3P0N H_2P4N H_2P4X3P0N H_2P5
4.7K_0402_5% 4 NC 13
11 GND NC 14 HOLEA HOLEA HOLEA HOLEA
18 GND NC 15
GND NC
1
25 28
R31 GND NC @ @ @ @
B B
1
TPM@4.7K_0402_5% SLB9665TT2.0-FW-5.00_TSSOP28
2
FD3 FD4 FD2 FD1
SLB9665 (SA00007XU00 )-->TPM2.0 @ @ @ @
1
SLB9660 (SA00007AB00 ) -->TPM1.2 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80
A A

TPM/Screw
v0.2
5 4 3 2 1
RepairLap.com
5 4 3 2 1
BOM control
Plat f or m Silego P/N Compal PN 25MHz(A) 32.768KHz 24MHz(B) 27MHz 8MHz Remark
D
Intel ULT UMA SLG3NB3455VTR SA00008IQ00 1 1 1 X X GCLKUMA@ D
Intel ULT Dis SLG3NB3456VTR SA00008J800 1 1 1 1 X GCLKPX@
Base on A32 32.768KHz use 10ppm, G-CLK 25MHz X'TAL use 10ppm.
C C
B B
A A

5 4
RepairLap.com 3
2
Size
Date:
GCLK
Document Number
LA-D707P
1
Sheet 29 of 60
Rev
v0.2
5 4 3 2 1
<20,21,24,26,27,34,35,52,53,56> +5VS +5VS
2.5" SATA HDD <12,13,20,27,31,33,35,38,48,49>
<7,13,20,23,26,27,33,35,48,49,50,51,55>
+5VALW
+3VALW
+5VALW
+3VALW
<32> +3VS_WLAN_R +3VS_WLAN_R

D D
<PV> change short pad <DB> change JHDD pin define

CONN@
+5VS JHDD
+5VS_HDD1 1
2 1
R201 1 2 0_0603_5% C155 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P0 3 2
+5VS_HDD1 <11> SATA_PTX_DRX_P0 3
<11> SATA_PTX_DRX_N0 C156 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N0 4
R202 1 2 0_0603_5% 5 4
C153 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N0 6 5 9
<11> SATA_PRX_DTX_N0 C154 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_P0 7 6 G1 10
<11> SATA_PRX_DTX_P0 8 7 G2
8
2
ACES_51524-0080N-001
<SI> add 470p for EMI issue C140
470P_0402_50V8J SP01001A900
1
EMI@
C C
2.5" SATA ODD

+5VS
+5VS_ODD
B U20 CONN@ B
10U_0603_6.3V6M
C227
10U_0603_6.3V6M
1 1 1 14 JODD
@ 2 VIN1 VOUT1 13 CS11 2 1 0.01U_0402_16V7K SATA_PTX_C_DRX_P1 1
VIN1 VOUT1 <11> SATA_PTX_DRX_P1 1
C229
C226 <11> SATA_PTX_DRX_N1 CS14 2 1 0.01U_0402_16V7K SATA_PTX_C_DRX_N1 2

3 12 1 2 3 2
2 2 <10> ODD_PWR ON1 CT1 3
CS15 2 1 0.01U_0402_16V7K SATA_PRX_C_DTX_N1 4
4 11 560P_0402_50V7K <11> SATA_PRX_DTX_N1 CS18 2 1 0.01U_0402_16V7K SATA_PRX_C_DTX_P1 5 4
+5VALW VBIAS GND +3VS_WLAN_R <11> SATA_PRX_DTX_P1 5
C230 6
5 10 2 1 1 @ 2 7 6
<26> WL_PWREN_EC ON2 CT2 <11> ODD_PLUG# 0_0201_5% R5192 8 7
+3VALW +5VS_ODD 8
6 9 100P_0402_50V8J 2 1 9
7 VIN2 VOUT2 8 1 @ 2 10 9
VIN2 VOUT2 <10> ODD_DA# 10
1U_0402_10V4Z
1 DC6 0_0201_5% R5193

10U_0603_6.3V6M
C228
C223
1 15 CH751H-40PT_SOD323-2 2 1 11
GPAD SCS00003500 12 GND
1 GND
1U_0402_10V4Z
C224
EM5209VF DFN 14P DUAL LOAD SW DC7

2 CH751H-40PT_SOD323-2 ACES_51524-0100N-001
2 SA00007PM00 1
SCS00003500
2 ESD@ SP01001AI00
CS7
2 0.1U_0402_16V7K
A A

HDD/ODD Conn
B v0.2
5 4 3 2 1
RepairLap.com
A B C D E
<12,13,20,27,30,33,35,38,48,49> +5VALW +5VALW

<11> USB3_TX1_N USB3_TX1_N 2 1 CS2 USB3_TX1_C_N 1 2 USB3TXDN1_C_R
0.1U_0402_16V7K RS2 0_0402_5%
USB3.0 need support 3.5A
2
change USB PWR SW SA00007AO00
RG75 +USB_VCCA
@ 150_0402_5% +5VALW low active
US1 W=100mils
1000P_0402_50V7K
150U_B2_6.3VM_R45M
W=100mils 1
0.1U_0402_16V7K
1
OUT
47U_0805_6.3V6M
1 5
IN 2
1 GND 1 1
<11> USB3_TX1_P USB3_TX1_P 2 1 CS1 USB3_TX1_C_P 1 2 USB3TXDP1_C_R CS3 4 1 1 1 @
EN @ +
CS6
CS22
0.1U_0402_16V7K RS1 0_0402_5% 0.1U_0402_16V7K 3
2 OCB CS4 CS5
LM1,LM2 2nd : SM070003K00 SY6288D20AAC_SOT23-5 2 2 2 2

1 2 USB3RXDN1_C <DB> Delete Choke add parallel 150ohm SA00007AO00
<11> USB3_RX1_N
RS6 0_0402_5%
2
<26,33> USB_ON# USB_ON# 1 2 DB Phase
RG76 RS4 0_0402_5%
@ 150_0402_5% add CS22 reserve
20141113
1
ESD@
1 2 USB3RXDP1_C DM1 SCA00000U10
<11> USB3_RX1_P
RS3 0_0402_5% 2 USB20_N1_C +USB_VCCA
1
3 USB20_P1_C
YSLC05CH_SOT23-3 <DB> change JUSB1 footprint

2 LM3 2nd : SM070002J00 USB2.0/USB3.0 port 1 2
<SI> change to 0504 choke JUSB1 CONN@

ESD@ DM2 1
USB3RXDN1_C 1 1 USB3RXDN1_C USB20_N1_C VBUS
10 9 2
LM3 SM070003Z00 USB20_P1_C 3 D-
4 3 USB20_P1_C USB3RXDP1_C 2 2 USB3RXDP1_C D+
9 8 4
<11> USB20_P1 GND
USB3RXDN1_C 5
USB3TXDN1_C_R 4 4 USB3TXDN1_C_R USB3RXDP1_C SSRX-
7 7 6 10
1 2 USB20_N1_C 7 SSRX+ GND 11
<11> USB20_N1 GND GND
USB3TXDP1_C_R5 5 6 6 USB3TXDP1_C_R USB3TXDN1_C_R 8 12
MCM1012B900F06BP_4P USB3TXDP1_C_R 9 SSTX- GND 13
3 3 SSTX+ GND
TAITW_PUBAU1-09FNLS1NN4H0
8
TVWDF1004AD0 DFN ESD

SC300002800
3 USB2.0 port x 1 3
+USB_VCCA
D29 ESD@ CONN@
SCA00000U10 JUSB2
<SI> change to 0504 choke 2 USB20_N2_C 1
1 USB20_N2_C 2 VBUS
3 USB20_P2_C USB20_P2_C 3 D-
LM5 SM070003Z00 4 D+
4 3 USB20_N2_C SHIELD
<11> USB20_N2
YSLC05CH_SOT23-3 5
6 GND
1 2 USB20_P2_C 7 GND
<11> USB20_P2 GND
8
MCM1012B900F06BP_4P GND
TAITW_PUBAU0-04FLBSCNN4H0
LM5 2nd : SM070002J00
4 4

USB 3.0/2.0 conn
B v0.2
A B C D E
RepairLap.com
5 4 3 2 1
<5,6,7,9,10,11,13,17,18,19,20,21,22,23,24,26,28,33,34,35,36,37,38,52,55,56> +3VS +3VS
<12,13,20,27,30,31,33,35,38,48,49> +5VALW +5VALW
<7,13,20,23,26,27,30,33,35,48,49,50,51,55> +3VALW +3VALW
<30> +3VS_WLAN_R +3VS_WLAN_R
D D
+3VS_WLAN
JWLAN1
2
+3VS_WLAN
RN7 DB Phase
4.7K_0402_5%
1 2 For RF request
3 1_GND 3.3V_2 4 20141117
<11> USB20_P4
1
5 3_USB_D+ 3.3V_4 6 +3VS_WLAN
<11> USB20_N4 5_USB_D- LED1#_6 MINI1_LED# <26>
7 8
9 7_GND N/C_8 10
9_N/C N/C_10
1
100P_0402_50V8J
0.1U_0402_25V6
11 12 R5179 R5180
13 11_N/C N/C_12 14 @RF@ @RF@
15 13_N/C N/C_14 16
DB Phase
For RF request
2
15_N/C LED2#_16
1
0.1U_0402_25V6
100P_0402_50V8J
0.1U_0402_25V6
100P_0402_50V8J
17 18 @RF@ @RF@ @RF@ @RF@
19 17_N/C GND_18 20 20141117 R5181 R5182 R5183 R5184
21 19_N/C N/C_20 22
2
+3VS_WLAN 23 21_N/C N/C_22
23_N/C
25 24
33_GND N/C_32
1
<11> PCIE_PTX_C_DRX_P6 27 26
RN3 29 35_PERp0 N/C_34 28
<11> PCIE_PTX_C_DRX_N6 37_PERn0 N/C_36
10K_0402_5% 31 30
39_GND CLink Reset_38 E51TXD_P80DATA <26>
33 32
<11> PCIE_PRX_DTX_P6 41_PETp0 CLink DATA_40 E51RXD_P80CLK <26>
35 34
<11> PCIE_PRX_DTX_N6
2
37 43_PETn0 CLink CLK_42 36

39 45_GND COEX3_44 38
<9> CLK_PCIE_WLAN 47_REFCLKP0 COEX2_46
41 40
<9> CLK_PCIE_WLAN# 49_REFCLKN0 COEX1_48
43 42 RN14 1 2 0_0201_5% SUSCLK <9>
45 51_GND SUSCLK_50 44
<9> MINI1_CLKREQ# 53_CLKREK0# PERST0#_52 PLT_RST# <9,23,26,28,36> +3VS_WLAN_R +3VS_WLAN
<9,26> EC_PCIE_WAKE# RN13 1 2 0_0201_5% 47 46 BT_ON_EC <26>
49 55_PEWake0# W_DISABLE2#_54 48
C WL_OFF# <10> C
MC_WAKE# 51 57_GND W_DISABLE1#_56 50
53 59_N/C N/C_58 52 R271
55 61_N/C N/C_60 54 1 2
63_GND N/C_62
0.1U_0402_16V7K
57 56
65_N/C RESERVED_64
1
+3VS_WLAN
10P_0402_50V8J
10P_0402_50V8J
CN3
R5185
R5186
59 58 0_0805_5% 1 1
@RF@ @RF@ 61 67_N/C N/C_66 60 CN2
63 69_GND N/C_68 62
2
65 71_N/C N/C_70 64 22U_0603_6.3V6K
DB Phase 67 73_N/C 3.3V_72 66 2 2
For RF request 75_GND 3.3V_74
20141117 GND
68
69 <MV > connect to +3VS_WLAN
GND 70
NC_70 71
NC_71
LOTES_APCI0019-P003H
CONN@ SP070010DA0
NGFF and WLAN
+3VS +3VS_WLAN
2
B B
@
RL25
100K_0402_5%
2
G
1 3 MC_WAKE#
<9> WAKE#
D
@
QB8
2N7002H_SOT23-3
Unpop QB4 and RL23 for not support OBFF
A A

WLAN-BT
5 4 RepairLap.com 3
2
Size
Date:
Document Number
LA-D707P
1
Sheet 32 of 60
Rev
v0.2
A B C D E
<13,26,46,47,48> +3VL +3VL
Powert Button Connector <12,13,20,27,30,31,35,38,48,49> +5VALW +5VALW
<5,6,7,9,10,11,13,17,18,19,20,21,22,23,24,26,28,32,34,35,36,37,38,52,55,56> +3VS +3VS
<7,13,20,23,26,27,30,35,48,49,50,51,55> +3VALW +3VALW
+3VL
1 1
11/26 change CONN.
@EMI@ 1 LID_SW#
C166 0.1U_0402_16V7K
IO BD Connector ( USB2.0,Card reader,HDD & PWR LED )
1 C139
2
<DB> change JPWR footprint by DFB request
CC125 <SI> add 470p for EMI issue EMI@1 2
470P_0402_50V8J
JPWR 100P_0402_50V8J CONN@

1 2 JIO1
1 ESD@
<26> LID_SW# 2 +5VALW 1
3 2 5 2 1
<26> ON/OFF# 3 G1 2
4 6 3
4 G2 +3VL 4 3
E-T_6916K-Q04N-03R 5 4
CONN@ 6 5
R215 +3VS 6
SP01000TB10 +3VALW 7
PCB Footprint = HB_A090420-SAHR21_4P ON/OFF# 2 1 USB20_N7_C 8 7
USB20_P7_C 9 8
Card reader 10 9
100K_0402_5% USB20_N3_C 11 10
2
@ USB20_P3_C 12 11
@ PJ6 USB2.0 ( on small BD ) 13 12
PJ9 <26,31> USB_ON# 13
14
1
2 SHORT PADS SHORT PADS 14 2
SATA_LED# 15
<11> SATA_LED# 15
Layout notes PWR_LED# 16
L PJ9 place Top layer,
<26> PWR_LED# 17
18
16
17
DB phase : 1 1 18
PJ6 place Bottom layer EMI@ EMI@
modify pin define C138 C137 19
20141114 G1 20
2 2 G2
470P_0402_50V8J
470P_0402_50V8J
CVILU_CF31181D0R4-10-NH
<SI> add 470p for EMI issue SP011411241
LM4 SM070003Z00
4 3 USB20_N3_C
<11> USB20_N3
3 3.3P_0402_50V8J CC152 3
1 2 USB20_P3_C
<11> USB20_P3
EMI@
MCM1012B900F06BP_4P
<MV> add AC cap

<SI> change to 0504 choke
LM6 SM070003Z00
4 3 USB20_N7_C
<11> USB20_N7
3.3P_0402_50V8J CC154
1 2 USB20_P7_C
<11> USB20_P7
EMI@
MCM1012B900F06BP_4P
4 4

IO CON
B v0.2
A B C D E
RepairLap.com
A B C D E
<5,6,7,9,10,11,13,17,18,19,20,21,22,23,24,26,28,32,33,35,36,37,38,52,55,56> +3VS +3VS
<20,21,24,26,27,30,35,52,53,56> +5VS +5VS
1 1
+5VS
+3VS
<DB> change FAN pin define
1A 40 mils
R5177 Layout notes
1 2 +FAN1 L C4801 C5214 close to CONN
CONN@
1
JFAN1
0_0603_5% RE50 6
5 GND2
10U_0603_10V6M 10K_0402_5% GND1
C4801
0.1U_0402_16V7K
C5214
1 1
+FAN1 4
2
3 4
Close to Connector <26> FAN_SPEED1 3
1 2
2 2 <26> EC_FAN_PWM1 2
CE24 1
0.01U_0402_25V7K 1
ACES_50271-0040N-001
2 SP02000TS00
+FAN1
2 2
RE51
1 @ 2 EC_FAN_PWM1
10K_0402_5%
3 3
4 4

FAN
B v0.2
A B C D E
RepairLap.com
A B C D E
+5VS
@RF@
10U_0603_6.3V6M
22U_0805_6.3V6M
0.1U_0402_25V6
1 1 1
C575
CC140
CC163
+5VALW
+3VALW 2 2 2 @ESD@
Q21
1 14
VIN1 VOUT1 VR_ON <26,52>
2 13
+5VALW VIN1 VOUT1
1 1
6
SUSP# 3 12 C554 1 2 100P_0402_50V8J For meet tPLT17 & tCPU28 power down sequence.
ON1 CT1
4 11
tPLT17 : 1us (Max)
VBIAS GND tCPU28 : 1us (Max) 2 @
<12,13,26,49> SUSP# SUSP# 5 10 C557 1 2 680P_0402_50V7K Q5002A
ON2 CT2
DMN65D8LDW-7_SOT363-6
1
6 9 SB00000I700
7 VIN2 VOUT2 8
VIN2 VOUT2 +3VALW
15
GPAD
+3VS
1
1 1 1 1 1 EM5209VF DFN 14P DUAL LOAD SW
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
CC161
CC160
CC157
CC162
CC158
SA00007PM00 1 R5096
EC_VCCST_PG_R <9,26>
10U_0603_6.3V6M
C570
100K_0402_1%
3
2 2 2 2 2 @
2
2 Q5002B
@
PM_SLP_S3_H 5 SB00000I700
@ESD@ @ESD@ @ESD@ @ESD@ @ESD@
4
6
PM_SLP_S3# 2 @
<9,12,26> PM_SLP_S3# Q5003A
DMN65D8LDW-7_SOT363-6 SUSP#
1
2 SB00000I700 2
6
For +1.8V_PRIM Discharge 2
@
Q5004A
For meet tPLT15 power down sequence(Un-Stuf f)
tPLT15 : 1us (Max) DMN65D8LDW-7_SOT363-6
+5VALW +1.8V_PRIM SB00000I700
1
1
1
+3VALW
R5092 R5093
100K_0402_1% 22_0603_1%
1
SYSON <12,26,49>
2
3 2
R5095
3
100K_0402_1%
Q5001B @
2
DMN65D8LDW-7_SOT363-6 Q5004B
@
PCH_PWR_EN# 5 SB00000I700 PM_SLP_S4_H 5 DMN65D8LDW-7_SOT363-6
SB00000I700
3
@
4
4
Q5003B
6
5 SB00000I700
<9,12,26,49> PM_SLP_S4#
4
2
3 <13,26,51> PCH_PWR_EN Q5001A 3
1
SB00000I700
4 4

DC Interface
RepairLap.com
Custom v0.2
A B C D E
1 2 3 4 5
U666A @
AC Coupling Capacitor
A
<DB> PCIe Gen3: Recommended value is 220 nF A
PCIe Gen1 and Gen2 only: Recommended value is 100 nF
AF30 AH30 PEG_PRX_DTX_P0 0.22U 6.3V K X5R 0402 2 1 PX@ C5187

<11> PEG_PTX_C_DRX_P0 PCIE_RX0P PCIE_TX0P PEG_PRX_C_DTX_P0 <11>
AE31 AG31 PEG_PRX_DTX_N0 0.22U 6.3V K X5R 0402 2 1 PX@ C5188
<11> PEG_PTX_C_DRX_N0 PCIE_RX0N PCIE_TX0N PEG_PRX_C_DTX_N0 <11>
AE29 AG29 PEG_PRX_DTX_P1 0.22U 6.3V K X5R 0402 2 1 PX@ C5189

AD28 AF28 PEG_PRX_DTX_N1 0.22U 6.3V K X5R 0402 2 1 PX@ C5190
AD30 AF27 PEG_PRX_DTX_P2 0.22U 6.3V K X5R 0402 2 1 PX@ C5191

AC31 AF26 PEG_PRX_DTX_N2 0.22U 6.3V K X5R 0402 2 1 PX@ C5192
AC29 AD27 PEG_PRX_DTX_P3 0.22U 6.3V K X5R 0402 2 1 PX@ C5193

AB28 AD26 PEG_PRX_DTX_N3 0.22U 6.3V K X5R 0402 2 1 PX@ C5194
No Use GPU Display Port outpud
AB30 AC25
AA31 PCIE_RX4P PCIE_TX4P AB25
PCIE_RX4N PCIE_TX4N U666F @
+VGA_CORE
AA29 Y23
Y28 PCIE_RX5P PCIE_TX5P Y24
PCIE_RX5N PCIE_TX5N AB11 R1676 1 R70@ 2 0_0402_5%
VARY_BL AB12 R1675 1 R70@ 2 0_0402_5%
Y30 AB27 DIGON
W31 PCIE_RX6P PCIE_TX6P AB26
PCIE_RX6N PCIE_TX6N
W29 Y27 AL15

V28 PCIE_RX7P PCIE_TX7P Y26 TXCAP_DPA3P AK14
PCIE_RX7N PCIE_TX7N TXCAM_DPA3N
B B
AH16
V30 W24 TX0P_DPA2P AJ15
U31 NC#V30 NC#W24 W23 TX0M_DPA2N
NC#U31 NC#W23 AL17
TX1P_DPA1P AK16
U29 V27 TX1M_DPA1N
T28 NC#U29 NC#V27 U26 AH18
NC#T28 NC#U26 TX2P_DPA0P AJ17
TX2M_DPA0N
PCI EXPRESS INTERFACE

T30 U24 AL19
R31 NC#T30 NC#U24 U23 NC_TXOUT_L3P AK18
NC#R31 NC#U23 NC_TXOUT_L3N
R29 T26 TMDP

P28 NC#R29 NC#T26 T27
NC#P28 NC#T27 AH20
TXCBP_DPB3P AJ19
P30 T24 TXCBM_DPB3N
N31 NC#P30 NC#T24 T23 AL21
NC#N31 NC#T23 TX3P_DPB2P AK20
TX3M_DPB2N
N29 P27 AH22
M28 NC#N29 NC#P27 P26 TX4P_DPB1P AJ21
NC#M28 NC#P26 TX4M_DPB1N
AL23
M30 P24 TX5P_DPB0P AK22
L31 NC#M30 NC#P24 P23 TX5M_DPB0N
NC#L31 NC#P23 AK24
NC_TXOUT_U3P AJ23
L29 M27 NC_TXOUT_U3N
K30 NC#L29 NC#M27 N26
NC#K30 NC#N26
C ? PRO S3
216-0841018 A0 SUN C
CLOCK
CLK_PEG_VGA AK30
<9> CLK_PEG_VGA PCIE_REFCLKP
CLK_PEG_VGA# AK32
<9> CLK_PEG_VGA# PCIE_REFCLKN +1.0VS_VGA
CALIBRATION <DB> CHANGE TO +1.0VS_VGA

Y22 R5159 1 PX@ 2 1.69K_0402_1%
PCIE_CALR_TX
R1400 1 PX@ 2 1K_0402_5% N10 AA22 R717 1 PX@ 2 1K_0402_1%
TEST_PG PCIE_CALR_RX
GPU_RST# AL27
PERSTB
216-0841018 A0 SUN PRO S3

+3VS_VGA +3VS SA000098V10
1
@
R1681 R1691
0_0402_5% 0_0402_5%
SD028000080
2
2
5
U6 PX@
DGPU_HOLD_RST# 2 SA00000OH00
P
<10> DGPU_HOLD_RST# B 4 GPU_RST#

PLT_RST# 1 Y
<9,23,26,28,32> PLT_RST# A
G
DC5 SCS00003500
1
MC74VHC1G08DFT2G_SC70-5 PX@ 1 2
3
R1631 R70@
100K_0402_5% CH751H-40PT_SOD323-2
D D
2
R1146 1 R30@ 2 0_0402_5%

VGA_PWRGD <56>
Security Classification Compal Secret Data

Title
Issued Date 2013/01/11 Deciphered Date 2013/12/31
SUN_PCIE/DP
RepairLap.com DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom v0.2
Date:
LA-D707P
Wednesday, May 11, 2016 Sheet 36 of 60
1 2 3 4 5
1 2 3 4 5
+3VS_VGA
+1.8VS_VGA
EC_SMB_DA2 1 @ 2 VGA_SMB_DA3
PS_0[3:1]=001 Strap Name :
R162 0_0402_5% PS_0[5:4]=11
1
U666B @ U? PS_0[1] ROM_CONFIG[0]
1
EC_SMB_CK2 1 @ 2 VGA_SMB_CK3 PX@
R164 0_0402_5% PX@R327 PX@R328
Resistor Divider Lookup Lable R5165
10K_0402_5% 10K_0402_5% 8.45K_0402_1%
PS_0[2] ROM_CONFIG[1]
AF2 R_pu (ohm) R_pd (ohm) Bitd [3:1] PS_0[3] ROM_CONFIG[2]
2
NC#AF2
2
PX@ AF4 PS_0
2
NC#AF4
PS_0[4] N/A
1
6 1 VGA_SMB_DA3 1 N9 AG3
<7,10,19,22,26> EC_SMB_DA2 T401
1 L9 DBG_DATA16 NC#AG3 AG5
NC 4.75k 000 <DB> use Gen3 PX@
Q2416A
T302
1 AE9 DBG_DATA15 NC#AG5 R5166
PS_0[5] AUD_PORT_CONN_PINSTRAP[0]
ME2N7002D1KW-G 2N_SOT363-6
T303
1 Y11 DBG_DATA14 DPA
AH3
8.45k 2k 001 C=NC 2K_0402_1%
T304 DBG_DATA13 NC#AH3
SB00000I700 1 AE8 AH1 4.53k 2k 010
T305
2
DBG_DATA12 NC#AH1
5
PX@ 1 AD9
T306 DBG_DATA11
1 AC10 AK3 6.98k 4.99k 011
A
VGA_SMB_CK3 T307 DBG_DATA10 NC#AK3 A
3 4 1 AD7 AK1
<7,10,19,22,26> EC_SMB_CK2 T308 DBG_DATA9 NC#AK1
1 AC8 DVO 4.53k 4.99k 100
T309 DBG_DATA8
Q2416B 1 AC7 AK5
T310 DBG_DATA7 NC#AK5
ME2N7002D1KW-G 2N_SOT363-6 1 AB9 AM3 3.24k 5.62k 101
T311 DBG_DATA6 NC#AM3
SB00000I700 1 AB8
T312 DBG_DATA5 +1.8VS_VGA
1 AB7 AK6 3.4k 10k 110 PS_1[3:1]=000 Strap Name :
T313 DBG_DATA4 NC#AK6
1 AB4 AM5 <DB> use Gen3
T314 DBG_DATA3 NC#AM5
1 AB2 DPB 4.75k NC 111 PS_1[5:4]=11
T315 DBG_DATA2
1
1 Y8 AJ7 PS_1[1] STRAP_BIF_GEN3_EN_A
+3VS_VGA +3VS_VGA T316 DBG_DATA1 NC#AJ7
1 Y7 AH6 0402 1% resistors are equired PX@
T317 DBG_DATA0 NC#AH6 R5167 PS_1[2] TRAP_BIF_CLK_PM_EN
AK8 8.45K_0402_1%
NC#AK8 AL7 Capacitor Divider Lookup Lable PS_1[3] N/A
2
NC#AL7
2
R1444 1 @ 2 100K_0402_5% ACIN PS_1

R1445 1 PX@ 2 4.7K_0402_5% VGA_AC_BATT_R PS_1[4] STRAP_TX_CFG_DRV_FULL_SWING
R1451
1
@ W6 Cap (nF) Bitd [5:4]
10K_0402_5% V6 NC#W6 PX@
VGA_AC_BATT_R NC#V6 V4 R5168
PS_1[5] STRAP_TX_DEEMPH_EN
C=NC
1
AC6 NC#V4 U5 2K_0402_1%

AC5 NC#AC5 NC#U5 680nF 00
2
NC#AC6
6
W3 82nF 01
@ Q16A AA5 NC#W3 V2
AA6 NC#AA5 NC#V2
2 NC#AA6 DPC
Y4
10nF 10
NC#Y4 W5
NC#W5 NC 11
1
3
R1459 1 R70@ 2 4.7K_0402_5% U1 AA3 PLL_ANALOG_OUT R1469 1 @ 2

+1.8VS_VGA NC#U1 NC#AA3 +1.8VS_VGA
@ Q16B W1 Y2 16.2K_0402_1% PS_2[3:1]=000 Strap Name :
R1460 1 R70@ 2 4.7K_0402_5% U3 NC#W1 NC#Y2
5 Y6 NC#U3 J8
<26> VGA_AC_BATT
AA1 NC#Y6 NC#J8 PS_2[5:4]=11
NC#AA1 PS_2[1] N/A
R=NC
4
PS_2[2] N/A
PS_2
PS_2[3] STRAP_BIOS_ROM_EN
I2C
<56> +VGA_VDDIO PS_2[4] STRAP_BIF_VGA_DIS
1
R1 1
R3 SCL +1.8VS_VGA +3VS_VGA PX@ PX@
1 2 SDA C5203 R5164
PS_2[5] N/A
B B
R174 0_0402_5% AM26 R1673 1 R70@ 2 R1674 1 R30@ 2 0.082U_0402_16V6K 4.75K_0402_1%
R AK26 0_0402_5% 0_0402_5% 2
GENERAL PURPOSE I/O
2
AVSSN#AK26
2
T292 1 R169 1 @ 2 0_0402_5% GPU_GPIO0 U6
R5189 1 R70@ 2 0_0402_5% GPU_GPIO1 U10 GPIO_0 AL25
+VGA_CORE GPIO_1 G
+3VS_VGA 1 2 R176 1 R70@ 2 0_0402_5% GPU_GPIO2 T10 AJ25 PX@ @
R1463 10K_0402_5% VGA_SMB_DA3 U8 GPIO_2 AVSSN#AJ25 R1461 R1462
R1440 1 @ 2 GPU_GPIO6 VGA_SMB_CK3 U7 SMBDATA AH24 10K_0402_5% 10K_0402_5%
<26,56> GPU_PROCHOT#
1
1K_0402_5% ACIN 1 @ 2 GPU_GPIO5 T9 SMBCLK B AG25 GPU_SVD
2 <9,26> ACIN GPIO_5_AC_BATT AVSSN#AG25
1 @ 2 @ R165 0_0402_5% GPU_GPIO6 T8
R1464 10K_0402_5% C442 VGA_AC_BATT_R 1 2 T7 GPIO_6 DAC1 AH26 GPU_SVC +1.8VS_VGA
0.1U_0402_10V6K R1661 0_0402_5% P10 GPIO_7_BLON HSYNC AJ27
1 2
PS_3[3:1]=000 Strap Name :
1 P4 GPIO_8_ROMSO VSYNC R5191
REAK CURRENT CONTROL ( Topaz only ) GPIO_9_ROMSI PS_3[5:4]=11
1
P2 4.7K_0402_5% PS_3[1] BOARD_CONFIG[0] (Memory ID)
N6 GPIO_10_ROMSCK AD22 PX@ R1467 R1468 X76@
N5 GPIO_11 RSET
GPIO_12 10K_0402_5% @ PX@
10K_0402_5% R5174 PS_3[2] BOARD_CONFIG[1] (Memory ID)
N3 AG24 8.45K_0402_1%
R177 1 R70@ 2 0_0402_5% Y9 GPIO_13 AVDD AE22
+VGA_CORE PS_3[3] BOARD_CONFIG[2] (Memory ID)
2
+3VS_VGA +1.8VS_VGA GPU_VID3 N1 GPIO_14_HPD2 AVSSQ PS_3
M4 GPIO_15_PWRCNTL_0 AE23
GPIO_16 VDD1DI PS_3[4] AUD_PORT_CONN_PINSTRAP[1]
1
GPU_GPIO17 R6 AD23
R178 1 R70@ 2 0_0402_5% GPU_GPIO18 W10 GPIO_17_THERMAL_INT VSS1DI X76@
2 GPIO_18 PS_3[5] AUD_PORT_CONN_PINSTRAP[2]
2
@R30@ GPIO19_CTF M2 R5169

R1455 C439
2
@R30@ GPU_VID1 P8 GPIO_19_CTF FutureASIC/SEYMOUR/PARK
AM12
C=NC 4.75K_0402_1%
P7 GPIO_20_PWRCNTL_1 CEC_1
10K_0402_5% @ @R30@ 0.1U_0402_10V6K C441 11/15 :
2
1 GPIO_21
R1454
1
0.1U_0402_10V6K follow AMD check list R167 non-pop by vendor N8 GPIO_22_ROMCSB
10K_0402_5% AK10 AK12 SVI2_SVD R1664 1 R70@ 2 0_0402_5% GPU_SVD
GPU_SVD <56>
1
@ R167 0_0402_5% AM10 GPIO_29 RSVD#AK12 AL11 SVI2_SVT R1665 1 R70@ 2 0_0402_5% GPU_SVT
VGA_CLKREQ#_R N7 GPIO_30 RSVD#AL11 SVI2_SVC R1666 1 R70@ GPU_SVC GPU_SVT <56>
UV4 @R30@ 1 2 AJ11 2 0_0402_5%
<9> VGA_CLKREQ# CLKREQB RSVD#AJ11 GPU_SVC <56>
33_0402_5% A1 A2 33_0402_5%
GPU_VID3 R1449 1 @R30@ 2 GPU_VID3_GPIO15 B1 VCCA VCCB B2 R1452 1 @R30@ 2 GPU_SVD JTAG_TRSTB L6
1
GPU_VID1 R1450 1 @R30@ 2
33_0402_5%
GPU_VID1_GPIO20 C1
D2
A1
A2
B1
B2
C2
D1
R1453 1 @R30@ 2
33_0402_5%
GPU_SVC @ C5213
68P_0402_50V8J
JTAG_TDI
JTAG_TCK
L5
L3
JTAG_TRSTB
JTAG_TDI (default)
GPU Side DIR GND PWR IC JTAG_TMS L1 JTAG_TCK AL13
JTAG_TMS GENLK_CLK
2
2 T70
SN74LVC2T45YZPR_DSBGA8 1 JTAG_TDO
TESTEN
K4
K7 JTAG_TDO GENLK_VSYNC
AJ13 Memory ID Memory Type Conf i gur a t i o
n Size R5174 R5169 X76 P/N
@R30@ @ @R30@ AF24 TESTEN
R1457 R1456 2 1 NC#AF24 AG13
SWAPLOCKA
10K_0402_5% 10K_0402_5% C366 10U_0603_6.3V6M AH12 000 SA00009HF00 Micron MT41J256M16LY-091G:N 2GB NC 4.75K
1
R179 1 R70@ 2 0_0402_5% AB13 SWAPLOCKB

C +VGA_CORE GENERICA C
W8
GENERICB
2 @R30@ 1 DIR 2
@R30@
1
R180 1 R70@ 2 0_0402_5% W9
W7 GENERICC AC19 PS_0
001 SA00008DN00 Hynix H5TC4G63CFR-N0C 2GB 8.45K 2K
+3VS_VGA GENERICD PS_0
R1458 10K_0402_5% C440 0.1U_0402_10V6K AD10
GENERICE
AJ9
AL9 NC#AJ9 PS_1
AD19 PS_1
010 SA00009I400 Micron MT41K512M16HA-107G:A 4GB 4.53K 2K X7667032L04
NC#AL9 AE17 PS_2
PS_2
GPU_VID3
GPU_VID1
R1662
R1663
1 R30@
1 R30@
2 0_0402_5%
2 0_0402_5%
GPU_SVD
GPU_SVC
R181 1 R70@ 2 0_0402_5%
1
AC14
AB16 HPD1 AE20 PS_3
011 SA00009IB00 Hynix H5TC8G63CMR-11C 4GB 6.98K 4.99K X7667032L03
T318 PX_EN PS_3
AE19
100 SA000076P80 Samsung K4W4G1646E-BC1A 2GB 4.53K 4.99K X7662732L03
1 AC16 TS_A
T221 DBG_VREFG
+3VS_VGA 101 3.24K 5.62K
@ RP34
DDC/AUX
AE6
110 3.4K 10K
1 8 JTAG_TRSTB PLL/CLOCK DDC1CLK AE5
DDC1DATA
2 7 JTAG_TDI 111 4.75K NC
3 6 JTAG_TMS AD2
4 5 JTAG_TCK AUX1P AD4
AUX1N
10K_8P4R_5% AC11 +VGA_CORE +3VS +3VS_VGA
DDC2CLK AC13 +3VS_VGA
DDC2DATA @PX@
R1447 1 PX@ 2 XO_IN XTALIN AM28 AD13 R1667 1 R70@ 2 0_0402_5% RP13
XTALOUT AK28 XTALIN AUX2P AD11 R1668 1 R70@ 2 0_0402_5% 8 1 THS_SCL
10K_0402_5% XTALOUT AUX2N
R1448 1 PX@ 2 XO_IN2 7 2 THS_SDA ME2N7002D1KW-G 2N_SOT363-6
2
XO_IN AC22 AD20 FB_GND R1669 1 R70@ 2 0_0402_5% +3VS_VGA 6 3 EC_SMB_DA3 @PX@
10K_0402_5% XO_IN NC#AD20 VGA_VSSSENSE <56>
R1442 1 R30@ 2 10K_0402_5% XO_IN2 AB22 AC20 FB_VDDC R1670 1 R70@ 2 0_0402_5% 5 4 EC_SMB_CK3
GPIO19_CTF XO_IN2 NC#AC20 VGA_VCCSENSE <56> EC_SMB_CK3
R1446 1 PX@ 2 @PX@ 1 6
EC_SMB_CK3 <26>
10K_0402_5% Enable MLPS AE16 2 1 @PX@ 2.2K_0804_8P4R_5%
R1443 1 PX@ 2 VGA_CLKREQ# NC#AE16 AD16 CV271 0.1U_0402_16V4Z UV13 Q2415A
NC#AD16
5
10K_0402_5% VGA_VSSSENSE R1672 1 PX@ 2 10_0402_5% 1 8 THS_SCL SB00000I700 @PX@
R1439 1 PX@ 2 TESTEN SEYMOUR/FutureASIC AC1 VDD SCL
1K_0402_5% +1.8VS_VGA THERM_D+ T4 DDCVGACLK AC3 VGA_VCCSENSE R1677 1 PX@ 2 10_0402_5% +VGA_CORE THERM_D+ 2 7 THS_SDA 4 3EC_SMB_DA3
THERM_D- DPLUS THERMAL DDCVGADATA D+ SDA EC_SMB_DA3 <26>
L54 PX@ SM010009U00 T2
1 2 13mA DMINUS THERM_D- 3 6 Q2415B ME2N7002D1KW-G 2N_SOT363-6
BLM15BD121SN1D_0402 D- ALERT# SB00000I700
D D
GPIO28 R5 @PX@ 4 5
PX@ PX@C414 2 1 10U_0603_6.3V6M +TSVDD AD17 GPIO28_FDO 2 1 T_CRIT# GND 2 @PX@ 1
TSVDD +3VS_VGA +3VS_VGA
XTALIN R349 1 2 XTALOUT AC17 RV133 2.2K_0402_5% RV134 2.2K_0402_5%
10M_0402_5% PX@C421 2 1 1U_0402_6.3V4Z TSVSS NCT7718W_MSOP8
CV272 GPU_GPIO17
SA000067P00 1 @ 2
PX@C438 2 1 0.1U_0402_10V6K THERM_D+ 1 2 THERM_D- R168 0_0402_5%
PX@ Y6 Address:1001100xb (x is R/W bit)
4 3 216-0841018 A0 SUN PRO?S3 2200P_0402_50V7K
NC OSC @PX@
1 2
OSC NC
PX@
C341
2 27MHZ 10PF +-10PPM 7V27000050
SJ100009700
2 PX@
C350
Title
8.2P_0402_50V_NPO 8.2P_0402_50V_NPO
Issued Date 2013/01/11 Deciphered Date 2013/12/31 SUN_MSIC
RepairLap.com
1 1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Date:
LA-D707P
1 2 3 4 5
1 2 3 4 5
+1.5VS to +1.5VS_VGA (2.096A) U666E @ U?

+1.5VS_VGA
AA27 A3
370mA (HDMI) No Use GPU Display Port outpud AB24 GND GND A30
Delete +1.5VS to +1.5VS_VGA power switch +1.8VS_VGA
188mA (Display Port) AB32
AC24
GND
GND
GND
GND
AA13
AA16
GND GND
2
R319 1 2 +DP_VDDR U666G @ U? AC26 AB10
PX@ 0_0603_5% AC27 GND GND AB15
GND GND
C446
C447
R4102 DP POWER NC/DP POWER AD25 AB6
10_0603_5% AD32 GND GND AC9
1 1 GND GND
A AG15 AE11 AE27 AD6 A
31
AG16 DP_VDDR#AG15 NC#AE11 AF11 AF32 GND GND AD8
DP_VDDR#AG16 NC#AF11 GND GND
0.1U_0402_10V6K
AF16 AE13 AG27 AE7
1U_0402_6.3V4Z
2 2 AG17 DP_VDDR#AF16 NC#AE13 AF13 AH32 GND GND AG12
DP_VDDR#AG17 NC#AF13 GND GND
@
5 PXS_PWREN# AG18 AG8 K28 AH10
AG19 DP_VDDR#AG18 NC#AG8 AG10 K32 GND GND AH28
QV4101B PX@ AF14 DP_VDDR#AG19 NC#AG10 L27 GND GND B10
4
ME2N7002D1KW-G 2N_SOT363-6 DP_VDDR#AF14 M32 GND GND B12
SB00000I700 N25 GND GND B14
N27 GND GND B16
<DB> CHANGE TO +1.0VS_VGA P25 GND GND B18
AG20 AF6 P32 GND GND B20
AG21 DP_VDDC#AG20 NC#AF6 AF7 R27 GND GND B22
+1.0VS_VGA AF22 DP_VDDC#AG21 NC#AF7 AF8 T25 GND GND B24
280mA AG22 DP_VDDC#AF22 NC#AF8 AF9 T32 GND GND B26
R320 1 2 +DP_VDDC AD14 DP_VDDC#AG22 NC#AF9 U25 GND GND B6
0_0603_5% DP_VDDC#AD14 U27 GND GND B8
GND GND
C450
C451
V32 C1
W25 GND GND C32
1 1 GND GND
AG14 AE1 W26 E28
AH14 DP_VSSR NC#AE1 AE3 W27 GND GND F10
DP_VSSR NC#AE3 GND GND
0.1U_0402_10V6K
AM14 AG1 Y25 F12
1U_0402_6.3V4Z
2 2 AM16 DP_VSSR NC#AG1 AG6 Y32 GND GND F14
DP_VSSR NC#AG6 GND GND
@
AM18 AH5 F16
AF23 DP_VSSR NC#AH5 AF10 GND F18
AG23 DP_VSSR NC#AF10 AG9 GND F2
AM20 DP_VSSR NC#AG9 AH8 GND F20
AM22 DP_VSSR NC#AH8 AM6 M6 GND F22
AM24 DP_VSSR NC#AM6 AM8 N13 GND GND F24
AF19 DP_VSSR NC#AM8 AG7 N16 GND GND F26
AF20 DP_VSSR NC#AG7 AG11 N18 GND GND F6
AE14 DP_VSSR NC#AG11 N21 GND GND
GND F8
DP_VSSR P6 GND GND G10
P9 GND GND G27
R12 GND GND G31
B
AF17 AE10 R15 GND GND G8 B
+3VS to +3VS_VGA (25mA) DPAB_CALR NC#AE10 R17
R20
GND
GND
GND
GND
H14
H17
T13 GND GND H2
+1.8V_PRIM to +1.8VS_VGA (311mA)
PX@
<Diner SI> change to NC & 470p ? S3
216-0841018 A0 SUN PRO
T16
T18
GND
GND
GND
GND
H20
H6
U4103 JG3 JP@ T21 GND GND J27
1 14
60mA 1 2 T6 GND GND J31
+3VS VIN1 VOUT1 1 2 +3VS_VGA GND GND
2 13 U15 K11
VIN1 VOUT1 GND GND
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_25V6
1 1 1 U17 K2
2 @PX@ JUMP_43X39 GND GND
C4111
C4124
CC164
DGPU_PWR_EN 3 12 C4112 1 U20 K22
ON1 CT1 470P_0402_50V7K U9 GND GND K6
4 11 V13 GND GND
2 PX@ +5VALW VBIAS GND 2 PX@ 2 GND
@ESD@ V16
DGPU_PWR_EN 5 10 C4126 1 2 PX@ V18 GND
ON2 CT2 470P_0402_50V7K Y10 GND
6 9 JG18 JP@ Y15 GND
7 VIN2 VOUT2 8
818mA 1 2 Y17 GND
+1.8V_PRIM VIN2 VOUT2 1 2 +1.8VS_VGA GND
Y20
GND
0.1U_0402_16V7K
0.1U_0402_25V6
1 15 1 R11 A32
GPAD JUMP_43X39 GND VSS_MECH
2
C4123
C4125
T11 AM1
TPS22966DPUR_SON14_2X3 PX@ AA11 GND VSS_MECH AM32
SA00007PM00 R346 M12 GND VSS_MECH
2 PX@ 2 PX@ 10_0603_5% N11 GND
V11 GND
1
GND
1
D
Main: SA00004MM00, TI, TPS22966
2nd: SA00006FD00, A-Power, APE8990GN3B 2 PXS_PWREN# 216-0841018 A0 SUN ?PRO S3
G
3rd: AOS, AOZ1331 (engineering sample available on 2013/Jan/18) S PX@Q91
3
ME2N7002D1W-G 1N_SC70-3
SB00000Z600
C C
+1.0V_PRIM to +1.0VS_VGA (4.016A)

+1.0V_PRIM PX@ +1.0VS_VGA +5VALW +VGA_CORE
U4102
AO4354_SO8 <DB> CHANGE TO +1.0VS_VGA
2
8 1 PX@ PX@
7 2 R4113 R4114
2
0.1U_0402_16V7K
6 3 100K_0402_5% 470_0603_5%
10U_0603_6.3V6M
1U_0402_6.3V4Z
5 PX@
1 1 1
C4113
C4114
C4115
R4107
3 1
6 1
SB00000ZN00 10_0603_5% PXS_PWREN#
4
3 1
2 PX@ 2 PX@ 2 PX@
<10,26,55,56> DGPU_PWR_EN DGPU_PWR_EN 5 2 PXS_PWREN#

PX@ PX@
1
5 PXS_PWREN# Q4105B Q4105A
1
1 PX@ 2 0.95VSG_GATE PX@ PX@ R4115 SB00000I700 SB00000I700
+19.5VB
R4109 200K_0402_5% Q4102B 100K_0402_5%
4
1
1 SB00000I700
2
6
@ R4104 PX@C4122
1.5M_0402_5% 0.01U_0402_25V7K
D D
PXS_PWREN# 2 2
2
PX@
Q4102A
1
SB00000I700

Title
SUN_Power/GND
Date:
LA-D707P
1 2 3 4 5
1 2 3 4 5
+1.5VS_VGA
A
+VGA_CORE 10uF 1uF 0.1uF A
C365
C367
C375
C370
C371
C372
C373
C374
1 1 1 1 1 1 1 1
VDDC TBD 5 (1@) 10 (2@) 0 +PCIE_PVDD:
50mA (PCIE2.0) +1.8VS_VGA
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
2.2U_0402_6.3V5M
2.2U_0402_6.3V5M
2.2U_0402_6.3V5M
2.2U_0402_6.3V5M
2.2U_0402_6.3V5M
U666D @ U?
2 2 2 2 2 2 2 2
80mA (PCIE3.0)
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
AM30
VDDCI 3.5A 1 3 0 1A PCIE_PVDD
PCIE
MEM I/O
C380
C387
C394
H13 AB23 1 1 1
H16 VDDR1 NC#AB23 AC23
H19 VDDR1 NC#AC23 AD24
VDDR1 NC#AD24
10U_0603_6.3V6M
0.1U_0402_10V6K
J10 AE24
1U_0402_6.3V4Z
J23 VDDR1 NC#AE24 AE25 2 2 2
+1.0VS_VGA 10uF 1uF 0.1uF VDDR1 NC#AE25
PX@
PX@
PX@
J24 AE26
J9 VDDR1 NC#AE26 AF25
K10 VDDR1 NC#AF25 AG26
K23 VDDR1 NC#AG26
PCIE_VDDC 2.5A 2 (1@) 5 (1@) 0 K24 VDDR1
VDDR1
C3719
C3720
C3721
C3722
C3723
C389
C390
C391
C381
C392
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
K9 L23 <DB> CHANGE TO +1.0VS_VGA
L11 VDDR1 PCIE_VDDC L24
2 2 2 2 2 1 1 1 1 1 VDDR1 PCIE_VDDC
L12 L25
BIF_VDDC 1.4A 0 0 0 L13 VDDR1 PCIE_VDDC L26
+PCIE_VDDC:
VDDR1 PCIE_VDDC 1.88A (PCIE2.0) +1.0VS_VGA
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
L20 M22
1 1 1 1 1 2 2 2 2 2 VDDR1 PCIE_VDDC
PX@
PX@
PX@
PX@
PX@
L21 N22
VDDR1 PCIE_VDDC 2.5A (PCIE3.0)
PX@
PX@
PX@
PX@
PX@
L22 N23
SPLL_VDDC 100mA 1 1 1 VDDR1 PCIE_VDDC N24
PCIE_VDDC R22
PCIE_VDDC
C384
C386
C398
C399
C383
C403
C388
C3724
C3725
T22
+1.8VS_VGA 13mA PCIE_VDDC
1U_0402_6.3V6K
1U_0402_6.3V6K
LEVEL U22
TRANSLATION PCIE_VDDC 1 1 1 1 1 1 1 1 1
L56 PX@ V22
1 2 +VDD_CT AA20 PCIE_VDDC
+1.5VS_VGA 10uF 1uF 0.1uF VDD_CT
10U_0603_6.3V6M
10U_0603_6.3V6M
BLM15BD121SN1D_0402 AA21
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
VDD_CT 2 2 2 2 2 2 2 2 2
C404
C405
C422
SM010009U00 AB20 AA15
B VDD_CT VDDC B
PX@
PX@
PX@
PX@
PX@
PX@
PX@
@
@
AB21 CORE N15
1 1 1 VDD_CT VDDC N17
VDDR1 1.5A 3 5 5 +3VS_VGA VDDC R13
25mA I/O VDDC
10U_0603_6.3V6M
0.1U_0402_10V6K
R16
1U_0402_6.3V4Z
L24 PX@
2 2 2 1 2 +VDDR3 AA17 VDDC R18
VDDR3 VDDC
PX@
PX@
PX@
BLM15BD121SN1D_0402 AA18 Y21
VDDR3 VDDC
C410
C428
C429
C417
SM010009U00 AB17 T12
AB18 VDDR3 VDDC T15 +VGA_CORE
+1.8VS_VGA 10uF 1uF 0.1uF 1 1 1 1 VDDR3 VDDC T17
V12 VDDC T20
VDDR4 VDDC
10U_0603_6.3V6M
0.1U_0402_10V6K
Y12 U13
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2 2 2 2 U12 VDDR4 VDDC U16
PCIE_PVDD 100mA 1 1 1 VDDR4 VDDC
PX@
PX@
PX@
@
U18
VDDC V21
VDDC V15
VDDC V17
MPLL_PVDD 130mA 1 1 1 VDDC V20
VDDC
POWER
Y13
VDDC Y16
VDDC Y18
SPLL_PVDD 75mA 1 1 1 VDDC AA12
VDDC M11
VDDC N12 21A (VDDC + VDDCI (Merged) - PRO S3 (DDR3))
VDDC U11
VDDR4 (300mA) 0 0 0 VDDC
+1.8VS_VGA
L47 PX@ 90mA <DB> CHANGE TO +1.0VS_VGA
PLL
1 2 +MPLL_PVDD
VDD_CT 13mA 1 1 1
C406
C407
C433
0 +-5% 0603
SD013000080 1 1 1
1.4A +1.0VS_VGA
R21 R398
BIF_VDDC U21 +BIF_VDDC 1 2
+TSVDD 13mA 1 1 1 BIF_VDDC
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 2 L8 0_0805_5%
MPLL_PVDD
PX@
PX@
PX@
+1.8VS_VGA
C
75mA +VGA_CORE
C
C413
C415
C416
L48 PX@
+DP_VDDR 0 0 0 1 2 +SPLL_PVDD
ISOLATED
CORE I/O 1 1 1
C408
C409
BLM15BD121SN1D_0402 C434 M13

SM010009U00 H7 VDDCI M15
1 1 1 SPLL_PVDD VDDCI
10U_0603_6.3V6M
M16
1U_0402_6.3V4Z
1U_0402_6.3V4Z
+DP_VDDC 0 0 0 <DB> CHANGE TO +1.0VS_VGA VDDCI 2 2 2
M17
+1.0VS_VGA VDDCI
@
10U_0603_6.3V6M
0.1U_0402_10V6K
M18
1U_0402_6.3V4Z
2 2 2 L53 PX@ 100mA VDDCI M20

VDDCI
PX@
PX@
PX@
1 2 +SPLL_VDDC H8 M21
SPLL_VDDC VDDCI
C411
C412
C435
BLM15BD121SN1D_0402 N20
SM010009U00 J7 VDDCI
+3VS_VGA 10uF 1uF 0.1uF 1 1 1 SPLL_PVSS
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 2
VDDR3 25mA 0 2 (1@) 1
PX@
PX@
PX@
216-0841018 A0 SUN PRO S3
?
D D

Title
SUN_Power
Date:
LA-D707P
1 2 3 4 5
1 2 3 4 5
M_DA[63..0]
<41,42> M_DA[63..0]
M_MA[15..0]
<41,42> M_MA[15..0]
M_DQM[7..0]
<41,42> M_DQM[7..0]
M_DQS[7..0]
<41,42> M_DQS[7..0]
A A
M_DQS#[7..0]
<41,42> M_DQS#[7..0]
@
U666C U?
GDDR5/DDR3 GDDR5/DDR3
M_DA0 K27 K17 M_MA0
M_DA1 J29 DQA0_0 MAA0_0/MAA_0 J20 M_MA1
M_DA2 H30 DQA0_1 MAA0_1/MAA_1 H23 M_MA2
M_DA3 H32 DQA0_2 MAA0_2/MAA_2 G23 M_MA3
M_DA4 G29 DQA0_3 MAA0_3/MAA_3 G24 M_MA4
M_DA5 F28 DQA0_4 MAA0_4/MAA_4 H24 M_MA5
M_DA6 F32 DQA0_5 MAA0_5/MAA_5 J19 M_MA6
+1.5VS_VGA +1.5VS_VGA M_DA7 F30 DQA0_6 MAA0_6/MAA_6 K19 M_MA7
M_DA8 C30 DQA0_7 MAA0_7/MAA_7 G20 M_MA13
M_DA9 F27 DQA0_8 MAA0_8/MAA_13 L17 M_MA15
M_DA10 A28 DQA0_9 MAA0_9/MAA_15
DQA0_10
1
1
M_DA11 C28 J14 M_MA8
PX@ PX@ M_DA12 E27 DQA0_11 MAA1_0/MAA_8 K14 M_MA9
R363 R365 M_DA13 G26 DQA0_12 MAA1_1/MAA_9 J11 M_MA10
40.2_0402_1% 40.2_0402_1% M_DA14 D26 DQA0_13 MAA1_2/MAA_10 J13 M_MA11
M_DA15 F25 DQA0_14 MAA1_3/MAA_11 H11 M_MA12
2
M_DA16 A25 DQA0_15 MAA1_4/MAA_12 G11 M_BA2

DQA0_16 MAA1_5/MAA_BA2 M_BA2 <41,42>
+MVREFDA +MVREFSA M_DA17 C25 J16 M_BA0
DQA0_17 MAA1_6/MAA_BA0 M_BA0 <41,42>
M_DA18 E25 L15 M_BA1
DQA0_18 MAA1_7/MAA_BA1 M_BA1 <41,42>
M_DA19 D24 G14 M_MA14
DQA0_19 MAA1_8/MAA_14
1
M_DA20 E23 L16
MEMORY INTERFACE
1 1 DQA0_20 MAA1_9/RSVD
PX@ PX@ PX@ PX@ M_DA21 F23
R364 C467 R457 C514 M_DA22 D22 DQA0_21 E32 M_DQM0
100_0402_1% 1U_0402_6.3V4Z 100_0402_1% 1U_0402_6.3V4Z M_DA23 F21 DQA0_22 WCKA0_0/DQMA0_0 E30 M_DQM1
2 2 M_DA24 E21 DQA0_23 WCKA0B_0/DQMA0_1 A21 M_DQM2
2
M_DA25 D20 DQA0_24 WCKA0_1/DQMA0_2 C21 M_DQM3

M_DA26 F19 DQA0_25 WCKA0B_1/DQMA0_3 E13 M_DQM4
B
M_DA27 A19 DQA0_26 WCKA1_0/DQMA1_0 D12 M_DQM5 B
M_DA28 D18 DQA0_27 WCKA1B_0/DQMA1_1 E3 M_DQM6
M_DA29 F17 DQA0_28 WCKA1_1/DQMA1_2 F4 M_DQM7
M_DA30 A17 DQA0_29 WCKA1B_1/DQMA1_3
M_DA31 C17 DQA0_30 H28 M_DQS0
M_DA32 E17 DQA0_31 EDCA0_0/QSA0_0 C27 M_DQS1
M_DA33 D16 DQA1_0 EDCA0_1/QSA0_1 A23 M_DQS2
M_DA34 F15 DQA1_1 EDCA0_2/QSA0_2 E19 M_DQS3
M_DA35 A15 DQA1_2 EDCA0_3/QSA0_3 E15 M_DQS4
M_DA36 D14 DQA1_3 EDCA1_0/QSA1_0 D10 M_DQS5
PX@ PX@ M_DA37 F13 DQA1_4 EDCA1_1/QSA1_1 D6 M_DQS6
R5160 R455 M_DA38 A13 DQA1_5 EDCA1_2/QSA1_2 G5 M_DQS7
49.9_0402_1% 10_0402_1% M_DA39 C13 DQA1_6 EDCA1_3/QSA1_3
1 2 2 1 DRAM_RST M_DA40 E11 DQA1_7 H27 M_DQS#0
<41,42> DRAM_RST# DQA1_8 DDBIA0_0/QSA0_0B
M_DA41 A11 A27 M_DQS#1
M_DA42 C11 DQA1_9 DDBIA0_1/QSA0_1B C23 M_DQS#2
DQA1_10 DDBIA0_2/QSA0_2B
1
1 M_DA43 F11 C19 M_DQS#3

PX@ PX@ M_DA44 A9 DQA1_11 DDBIA0_3/QSA0_3B C15 M_DQS#4
C469 R5161 M_DA45 C9 DQA1_12 DDBIA1_0/QSA1_0B E9 M_DQS#5
120P_0402_50V8J 5.1K_0402_1% M_DA46 F9 DQA1_13 DDBIA1_1/QSA1_1B C5 M_DQS#6
2 M_DA47 D8 DQA1_14 DDBIA1_2/QSA1_2B H4 M_DQS#7
2
M_DA48 E7 DQA1_15 DDBIA1_3/QSA1_3B

M_DA49 A7 DQA1_16 L18 VRAM_ODT0
DQA1_17 ADBIA0/ODTA0 VRAM_ODT0 <41>
M_DA50 C7 K16 VRAM_ODT1
DQA1_18 ADBIA1/ODTA1 VRAM_ODT1 <42>
M_DA51 F7
M_DA52 A5 DQA1_19 H26 M_CLK0
DQA1_20 CLKA0 M_CLK0 <41>
M_DA53 E5 H25 M_CLK#0
DQA1_21 CLKA0B M_CLK#0 <41>
M_DA54 C3
M_DA55 E1 DQA1_22 G9 M_CLK1
Place close to GPU (within 25mm) M_DA56 G7 DQA1_23 CLKA1 H9 M_CLK#1
M_CLK1 <42>
and place componment close to each other M_DA57 G6 DQA1_24 CLKA1B M_CLK#1 <42>
M_DA58 G1 DQA1_25 G22 M_RAS#0
DQA1_26 RASA0B M_RAS#0 <41>
M_DA59 G3 G17 M_RAS#1
DQA1_27 RASA1B M_RAS#1 <42>
M_DA60 J6
M_DA61 J1 DQA1_28 G19 M_CAS#0
C C
DQA1_29 CASA0B M_CAS#0 <41>
M_DA62 J3 G16 M_CAS#1
DQA1_30 CASA1B M_CAS#1 <42>
M_DA63 J5
DQA1_31 H22 M_CS#0
CSA0B_0 M_CS#0 <41>
+MVREFDA K26 J22
MVREFDA CSA0B_1 M_CS#0_1 <41>
+MVREFSA J26 For 512 VRAM 2Rank Colay
MVREFSA G13 M_CS#1
CSA1B_0 M_CS#1 <42>
J25 K13
NC#J25 CSA1B_1 M_CS#1_1 <42>
R5162 1 PX@ 2 120_0402_1% K25 For 512 VRAM 2Rank Colay
MEM_CALRP0 K20 M_CKE0
CKEA0 M_CKE0 <41>
J17 M_CKE1
CKEA1 M_CKE1 <42>
G25 M_WE#0
WEA0B M_WE#0 <41>
DRAM_RST L10 H10 M_WE#1
DRAM_RST WEA1B M_WE#1 <42>
R460 @ 1 2 51.1_0402_1% C542 @1 2 0.1U_0402_16V4Z K8
R373 @ 1 2 51.1_0402_1% C541 @1 2 L7 CLKTESTA
0.1U_0402_16V4Z CLKTESTB
Route 50ohms single-ended/100ohm dif f and keep s hort

debug only, for clock observat i on,if not need, DNI. 216-0841018 A0 SUN PRO S3
?
D D

Title
SUN_MEM
Date:
LA-D707P
1 2 3 4 5
1 2 3 4 5
Memory Partition A - Lower 32 bits

M_DA[63..0]
<40,42> M_DA[63..0]
M_MA[15..0]
<40,42> M_MA[15..0]
M_DQM[7..0]
<40,42> M_DQM[7..0]
M_DQS[7..0]
<40,42> M_DQS[7..0]
M_DQS#[7..0]
<40,42> M_DQS#[7..0]
+1.5VS_VGA +1.5VS_VGA
A A
1
PX@ PX@
R452 R463
4.99K_0402_1% U1406 4.99K_0402_1% U1407
2
+FBA_VREF0 M8 E3 M_DA17 +FBA_VREF1 M8 E3 M_DA30
H1 VREFCA DQL0 F7 M_DA23 H1 VREFCA DQL0 F7 M_DA27
VREFDQ DQL1 F2 M_DA21 VREFDQ DQL1 F2 M_DA31
DQL2 DQL2
1
1 M_MA0 N3 F8 M_DA22 1 M_MA0 N3 F8 M_DA24
PX@ PX@ M_MA1 P7 A0 DQL3 H3 M_DA18 PX@ PX@ M_MA1 P7 A0 DQL3 H3 M_DA29
R453 C472 M_MA2 P3 A1 DQL4 H8 M_DA19 R464 C540 M_MA2 P3 A1 DQL4 H8 M_DA26
4.99K_0402_1% 0.1U_0402_10V6K M_MA3 N2 A2 DQL5 G2 M_DA16 4.99K_0402_1% 0.1U_0402_10V6K M_MA3 N2 A2 DQL5 G2 M_DA28
2 M_MA4 P8 A3 DQL6 H7 M_DA20 2 M_MA4 P8 A3 DQL6 H7 M_DA25
2
M_MA5 P2 A4 DQL7 M_MA5 P2 A4 DQL7
M_MA6 R8 A5 M_MA6 R8 A5
M_MA7 R2 A6 D7 M_DA5 M_MA7 R2 A6 D7 M_DA8
M_MA8 T8 A7 DQU0 C3 M_DA3 M_MA8 T8 A7 DQU0 C3 M_DA14
M_MA9 R3 A8 DQU1 C8 M_DA4 M_MA9 R3 A8 DQU1 C8 M_DA9
M_MA10 L7 A9 DQU2 C2 M_DA1 M_MA10 L7 A9 DQU2 C2 M_DA12
M_MA11 R7 A10/AP DQU3 A7 M_DA6 M_MA11 R7 A10/AP DQU3 A7 M_DA10
M_MA12 N7 A11 DQU4 A2 M_DA0 M_MA12 N7 A11 DQU4 A2 M_DA15
M_MA13 T3 A12 DQU5 B8 M_DA7 M_MA13 T3 A12 DQU5 B8 M_DA11
M_MA14 T7 A13 DQU6 A3 M_DA2 M_MA14 T7 A13 DQU6 A3 M_DA13
M_MA15 M7 A14 DQU7 M_MA15 M7 A14 DQU7
A15/BA3 +1.5VS_VGA A15/BA3 +1.5VS_VGA
M_BA0 M2 B2 M_BA0 M2 B2
<40,42> M_BA0 BA0 VDD BA0 VDD
M_BA1 N8 D9 M_BA1 N8 D9
M_BA2 M3 G7 M_BA2 M3 G7
K2 K2
VDD K8 VDD K8
VDD N1 VDD N1
M_CLK0 J7 VDD N9 M_CLK0 J7 VDD N9
B <40> M_CLK0 CK VDD CK VDD B
M_CLK#0 K7 R1 M_CLK#0 K7 R1
<40> M_CLK#0 CK VDD CK VDD
M_CKE0 K9 R9 M_CKE0 K9 R9
<40> M_CKE0 CKE/CKE0 VDD +1.5VS_VGA CKE/CKE0 VDD +1.5VS_VGA
VRAM_ODT0 K1 A1 VRAM_ODT0 K1 A1
<40> VRAM_ODT0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
M_CS#0 L2 A8 M_CS#0 L2 A8
<40> M_CS#0 CS/CS0 VDDQ CS/CS0 VDDQ
M_RAS#0 J3 C1 M_RAS#0 J3 C1
<40> M_RAS#0 RAS VDDQ RAS VDDQ
M_CAS#0 K3 C9 M_CAS#0 K3 C9
<40> M_CAS#0 CAS VDDQ CAS VDDQ
M_WE#0 L3 D2 M_WE#0 L3 D2
<40> M_WE#0 WE VDDQ WE VDDQ
E9 E9
VDDQ F1 VDDQ F1
M_DQS2 F3 VDDQ H2 M_DQS3 F3 VDDQ H2
M_DQS0 C7 DQSL VDDQ H9 M_DQS1 C7 DQSL VDDQ H9
DQSU VDDQ DQSU VDDQ
M_DQM2 E7 A9 M_DQM3 E7 A9
M_DQM0 D3 DML VSS B3 M_DQM1 D3 DML VSS B3
DMU VSS E1 DMU VSS E1
VSS G8 VSS G8
M_DQS#2 G3 VSS J2 M_DQS#3 G3 VSS J2
M_DQS#0 B7 DQSL VSS J8 M_DQS#1 B7 DQSL VSS J8
DQSU VSS M1 DQSU VSS M1
VSS M9 VSS M9
VSS P1 VSS P1
T2 VSS P9 DRAM_RST# T2 VSS P9
<40,42> DRAM_RST# RESET VSS RESET VSS
T1 T1
L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1
1
PX@ VRAM_ODT0 J1 B1 VRAM_ODT0 J1 B1
M_CLK0 R454 L1 NC/ODT1 VSSQ B9 PX@ M_CS#0_1 L1 NC/ODT1 VSSQ B9
<40> M_CS#0_1 NC/CS1 VSSQ NC/CS1 VSSQ
M_CLK#0 240_0402_1% M_CKE0 J9 D1 R456 M_CKE0 J9 D1
R465 2 PX@ 1 240_0402_1% L9 NC/CE1 VSSQ D8 240_0402_1% R466 2 PX@ 1 240_0402_1% L9 NC/CE1 VSSQ D8
2
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
2
VSSQ VSSQ
1
C E8 E8 C
R5171 R5170 VSSQ F9 VSSQ F9
40.2_0402_1% 40.2_0402_1% VSSQ G1 VSSQ G1
PX@ PX@ VSSQ G9 VSSQ G9
VSSQ VSSQ
2
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3
H5TC2G63FFR-11C_FBGA96 H5TC2G63FFR-11C_FBGA96
1 X76@ X76@
PX@
C506
0.01U_0402_25V7K
2 +1.5VS_VGA
+1.5VS_VGA
U1406 side
U1407 side
C491
C512
C511
C519
C510
C521
C532
C520
C480
C481
C482
C485
C483
C531
C486
C490
C496
C497
C498
C499
C518
C533
C516
C474
C475
C476
C477
C478
C534
C479
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
@
10U_0603_6.3V6M
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
@
@
D D

Title
SUN_VRAM
Size Document Number
A Lower Rev
Date:
LA-D707P
1 2 3 4 5
1 2 3 4 5
Memory Partition A - Upper 32 bits
+1.5VS_VGA
+1.5VS_VGA
1
1
PX@
PX@ R461
R458 4.99K_0402_1% U1409
4.99K_0402_1% U1408
2
A M_DA[63..0] +FBA_VREF3 M8 E3 M_DA49 A
<40,41> M_DA[63..0]
2
+FBA_VREF2 M8 E3 M_DA38 H1 VREFCA DQL0 F7 M_DA53
M_MA[15..0] H1 VREFCA DQL0 F7 M_DA36 VREFDQ DQL1 F2 M_DA51
<40,41> M_MA[15..0] VREFDQ DQL1 DQL2
1
F2 M_DA37 1 M_MA0 N3 F8 M_DA54
DQL2 A0 DQL3
1
M_DQM[7..0] M_MA0 N3 F8 M_DA35 PX@ PX@ M_MA1 P7 H3 M_DA50
<40,41> M_DQM[7..0] 1 A0 DQL3 A1 DQL4
PX@ PX@ M_MA1 P7 H3 M_DA39 R462 C539 M_MA2 P3 H8 M_DA55
M_DQS[7..0] R459 C473 M_MA2 P3 A1 DQL4 H8 M_DA32 4.99K_0402_1% 0.1U_0402_10V6K M_MA3 N2 A2 DQL5 G2 M_DA48
<40,41> M_DQS[7..0] A2 DQL5 2 A3 DQL6
4.99K_0402_1% 0.1U_0402_10V6K M_MA3 N2 G2 M_DA34 M_MA4 P8 H7 M_DA52
2
M_DQS#[7..0] 2 M_MA4 P8 A3 DQL6 H7 M_DA33 M_MA5 P2 A4 DQL7
<40,41> M_DQS#[7..0]
2
M_MA5 P2 A4 DQL7 M_MA6 R8 A5
M_MA6 R8 A5 M_MA7 R2 A6 D7 M_DA60
M_MA7 R2 A6 D7 M_DA41 M_MA8 T8 A7 DQU0 C3 M_DA59
M_MA8 T8 A7 DQU0 C3 M_DA44 M_MA9 R3 A8 DQU1 C8 M_DA63
M_MA9 R3 A8 DQU1 C8 M_DA43 M_MA10 L7 A9 DQU2 C2 M_DA56
M_MA10 L7 A9 DQU2 C2 M_DA45 M_MA11 R7 A10/AP DQU3 A7 M_DA62
M_MA11 R7 A10/AP DQU3 A7 M_DA42 M_MA12 N7 A11 DQU4 A2 M_DA57
M_MA12 N7 A11 DQU4 A2 M_DA46 M_MA13 T3 A12 DQU5 B8 M_DA61
M_MA13 T3 A12 DQU5 B8 M_DA40 M_MA14 T7 A13 DQU6 A3 M_DA58
M_MA14 T7 A13 DQU6 A3 M_DA47 M_MA15 M7 A14 DQU7
M_MA15 M7 A14 DQU7 A15/BA3 +1.5VS_VGA
A15/BA3 +1.5VS_VGA
M_BA0 M2 B2
M_BA0 M2 B2 M_BA1 N8 BA0 VDD D9
M_BA1 N8 D9 M_BA2 M3 G7
M_BA2 M3 G7 K2
<40,41> M_BA2 BA2 VDD VDD
K2 K8
VDD K8 VDD N1
VDD N1 M_CLK1 J7 VDD N9
M_CLK1 J7 VDD N9 M_CLK#1 K7 CK VDD R1
<40> M_CLK1 CK VDD CK VDD
M_CLK#1 K7 R1 M_CKE1 K9 R9
<40> M_CLK#1 CK VDD CKE/CKE0 VDD +1.5VS_VGA
M_CKE1 K9 R9
<40> M_CKE1 CKE/CKE0 VDD +1.5VS_VGA
VRAM_ODT1 K1 A1
VRAM_ODT1 K1 A1 M_CS#1 L2 ODT/ODT0 VDDQ A8
<40> VRAM_ODT1 ODT/ODT0 VDDQ CS/CS0 VDDQ
M_CS#1 L2 A8 M_RAS#1 J3 C1
B <40> M_CS#1 CS/CS0 VDDQ RAS VDDQ B
M_RAS#1 J3 C1 M_CAS#1 K3 C9
<40> M_RAS#1 RAS VDDQ CAS VDDQ
M_CAS#1 K3 C9 M_WE#1 L3 D2
<40> M_CAS#1 CAS VDDQ WE VDDQ
M_WE#1 L3 D2 E9
<40> M_WE#1 WE VDDQ VDDQ
E9 F1
VDDQ F1 M_DQS6 F3 VDDQ H2
M_DQS4 F3 VDDQ H2 M_DQS7 C7 DQSL VDDQ H9
M_DQS5 C7 DQSL VDDQ H9 DQSU VDDQ
DQSU VDDQ
M_DQM6 E7 A9
M_DQM4 E7 A9 M_DQM7 D3 DML VSS B3
M_DQM5 D3 DML VSS B3 DMU VSS E1
DMU VSS E1 VSS G8
VSS G8 M_DQS#6 G3 VSS J2
M_DQS#4 G3 VSS J2 M_DQS#7 B7 DQSL VSS J8
M_DQS#5 B7 DQSL VSS J8 DQSU VSS M1
DQSU VSS M1 VSS M9
VSS M9 VSS P1
M_CLK1 VSS P1 DRAM_RST# T2 VSS P9
M_CLK#1 DRAM_RST# T2 VSS P9 RESET VSS T1
<40,41> DRAM_RST# RESET VSS VSS
T1 L8 T9
L8 VSS T9 ZQ/ZQ0 VSS
ZQ/ZQ0 VSS
1
1
R5173 R5172 VRAM_ODT1 J1 B1
NC/ODT1 VSSQ
1
40.2_0402_1% 40.2_0402_1% VRAM_ODT1 J1 B1 PX@ M_CS#1_1 L1 B9

PX@ PX@ PX@ L1 NC/ODT1 VSSQ B9 R444 M_CKE1 J9 NC/CS1 VSSQ D1
<40> M_CS#1_1 NC/CS1 VSSQ NC/CE1 VSSQ
R410 M_CKE1 J9 D1 240_0402_1% R445 2 PX@ 1 240_0402_1% L9 D8
2
240_0402_1% R411 2 PX@ 1 240_0402_1% L9 NC/CE1 VSSQ D8 NCZQ1 VSSQ E2
2
NCZQ1 VSSQ E2 VSSQ E8
2
VSSQ E8 VSSQ F9
VSSQ F9 VSSQ G1
1 VSSQ VSSQ
PX@ G1 G9
C507 VSSQ G9 VSSQ
0.01U_0402_25V7K VSSQ 96-BALL
2 96-BALL SDRAM DDR3
C SDRAM DDR3 H5TC2G63FFR-11C_FBGA96 C
H5TC2G63FFR-11C_FBGA96 X76@
X76@
+1.5VS_VGA +1.5VS_VGA
U1408 side U1409 side

C495
C525
C524
C526
C513
C527
C536
C528
C504
C508
C505
C509
C529
C535
C530
C492
C501
C502
C503
C500
C523
C538
C522
C487
C484
C488
C489
C493
C537
C494
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
@
@
D D

Title
SUN_VRAM
A Upper Rev
Date:
LA-D707P
1 2 3 4 5
5 4 3 2 1
D D
@ 0 ohm
R
CPU GPU_PWRGD
PU801
DGPU_PWROK
+3VS 1. +3VS_VGA @
U4103 GPIO77
PU8
1.8V_PWRGD
DGPU_PWR_EN
C
GPIO78 EN C
PU801
2. VGA_CORE 0 ohm CPU
PXS_PWREN# DGPU_HOLD_RST#
NMOS 3. +1.05VS_VGA GPIO80
U4102 GPU_RST
+1.05VS GPU
B
PLT_RST# B
4. +1.5VS_VGA
U4102
+1.5VS
EN_1.8V
R 5. +1.8VS_VGA
PU8
C
A A

Issued Date Title
Deciphered Date
RSVD
D v0.2
5 4 3 2 1
RepairLap.com
5 4 3 2 1
D D
C C
B B
A A

Issued Date Title
Deciphered Date
HW Reserve
Custom v0.2
LA-D707P
5 4 RepairLap.com
3 2
Date: Wednesday, May 11, 2016 Sheet
1
44 of 60
5 4 3 2 1
+19.5V_ADPIN +19.5V_VIN
EMI@ PL1
5A_Z120_25M_0805_2P
1 2
D D
@ PJP1 DISEMI@PL2
ACES_51483-00801-001 5A_Z120_25M_0805_2P
1 1 2
1 2
2 3
1000P_0402_50V7K
@ PR1
3 4
1000P_0402_50V7K
100P_0402_50V8J
100P_0402_50V8J
0_0402_5%
4 5 1 2 ACIN_LED
5 6 <26> AC_LED#
1
EMI@ PC1
EMI@ PC2
EMI@ PC3
EMI@ PC4
ADP_SIGNAL
6 7 Charge_LED
7 8
1
ACIN_LED
2
9 8
10 GND PR2
GND 100K_0402_5%
2
PR3
10K_0402_5%
ADP_SIGNAL1 2
ADP_ID <26> PR4
3
3
2K_0402_5%
1000P_0402_50V7K
100P_0402_50V8J
<26> BAT_CHG_LED 1 2 Charge_LED
GLZ3.6B_LL34-2
1
10K_0402_5%
PR5
PD3
@ PC5
PC6
2
2
PR6
2
100K_0402_5%
2
ESD@ PD1 ESD@ PD2
1
C L30ESD24VC3-2_SOT23-3 L30ESD24VC3-2_SOT23-3 C
2014-10-06: ADP_I <26,47>

Change EC Power Rail Name
+3VALW_EC
1
PR7 PR8
16.2K_0402_1% 5.9K_0402_1%
2
VCIN0_PH <26> VCIN1_PH <26>
1
PH1 PR9
100K_0402_1%_NCP15WF104F03RC 10K_0402_1%
2
ECAGND <26>
B B
Initail Recovery Initail Recovery
OTP 92 C 56 C 45W UMA 0.65V 0.45V
65W DIS 0.95V 0.67V
A A

DC Conn
RepairLap.com
5 4 3 2 1
5 4 3 2 1
EMI@ PL3
D 5A_Z120_25M_0805_2P +14.8V_BATT D
+14.8V_BATT+ 1 2
@ PJPB1 EMI@ PL4

TAITW_PMPCR3-08MLBS1ZZ4H4 5A_Z120_25M_0805_2P
1 1 2
1 2
2 3
3 4
1000P_0402_50V7K
1U_0603_25V6
@EMI@ PC10
@EMI@ PC9
EMI@ PC7
4 5 1000P_0402_50V7K EMI@ PC8
5 6
1
0.01U_0402_50V7K
2
6 7
7 8
2
8 9
GND 10
GND PR10
100_0402_5%
1 2
EC_SMB_DA1 <26,47>
PR11
100_0402_5%
1 2
EC_SMB_CK1 <26,47>
+3VL
1
PR13
PR12 100K_0402_5%
C C
100_0402_5%
2
1 2
B/I# <26>
3
3
ESD@ PD4 ESD@ PD5
1
1
L30ESD24VC3-2_SOT23-3 L30ESD24VC3-2_SOT23-3
B B
A A

BATT Conn
RepairLap.com
5 4 3 2 1
A B C D
+19.5VB
Protection for reverse input
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
@EMI@ PC226
@EMI@ PC227
@EMI@ PC228
@EMI@ PC229
@EMI@ PC230
@EMI@ PC231
@EMI@ PC232
@EMI@ PC233
@EMI@ PC234
@EMI@ PC235
@EMI@ PC236
@EMI@ PC237
@EMI@ PC238
@EMI@ PC239
Vgs = 20V
1
@ PQ201 D
2 Vds = 60V
G Id = 250mA
2
S 2N7002KW_SOT323-3
3
@ PR201 @ PR202
1M_0402_5% 3M_0402_5%
1 2 1 2 Rds(on) typ = 35mohm max max Power loss 0.22W for 90W;0.12W for 65W system
Vgs = 20V CSR rating: 1W Rds(on) = 35mohm max
1
Vds = 30V VACP-VACN spec < 80.64mV Vgs = 20V 1
Need check the SOA for inrush Vds = 30V

+19.5V_VIN PQ202
ID = 7.7A (Ta=70C)
PQ203
PQ204 ID = 7.7A (Ta=70C)
MDU1512RH_POWERDFN56-8-5P1 AON7506_DFN33-8-5 P2
1 1 PR203 EMI@ PL201 CHG_B+ AON7506_DFN33-8-5
2 2 0.01_1206_1% 1UH_2.8A_30%_4X4X2_F 1
5 3 3 5 1 4 1 2 2
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
5 3
2200P_0402_50V7K
EMI@ PC206
0.1U_0402_25V6
2 3
0.1U_0402_25V6
@EMI@PC205
4
4
1
1
0_0402_5%
PC203
PC204
0.01U_0402_50V7K
Isat: 4A
PC201
@ PR204
4
1
1
+19.5V_VIN
PC202 DCR: 27mohm
PC207
2
2
2
VF = 0.5V
2
2
3
2
PD201
CHG_ACDRV_R
0.1U_0402_25V6
BAS40CW_SOT323-3
0.1U_0402_25V6
Rds(on) = 30mohm max CHG_BATDRV 1 2CHG_BATDRV_R
1
Vgs = 20V
1
PC208
PC210
PR205
1 1
5
1 2 Vds = 30V
10_1206_1%
AON7408L_DFN8-5
PC211 4.12K_0603_1%
0.047U_0402_25V7K ID = 7A (Ta=70C) Support max charge 3.5A
PR206
2
PC209 1 2
0.1U_0402_25V6
7X7X3 Power loss: 0.245W
PQ205
VF = 0.37V Isat: 6.5A
1
CSR rating: 1W
2.2_0603_5%
DCR: 30mohm
PR207
PD202 4 VSRP-VSRN spec < 81.28mV
2
RB751V-40_SOD323-2
CHG_ACP
@ PR215
CHG_VCC
2
0_0402_5%
3
2
1
+14.8V_BATT
4.12K_0603_1%
4.12K_0603_1%
2
CHG_DH 1 2 PL202 2
CHG_REGN
1
PC212 PR210
PR208
PR209
CHG_BST
CHG_DH
1 2 10UH_3.5A_20%_7X7X3_M 0.01_1206_1%
CHG_LX
CHG_LX 1 2 CHG 1 4
1U_0603_25V6K 1 2
CHG_ACN
2 3
2
PC213
1CHG_CSON1
1CHG_CSOP1
5
680P_0402_50V7K 4.7_1206_5%
AON7408L_DFN8-5
1U_0603_25V6K
20
19
18
17
16
10U_0805_25V6K
10U_0805_25V6K
@EMI@PC220 @EMI@ PR211
0.1U_0402_25V6
0.1U_0402_25V6
VCC
PHASE
HIDRV
BTST
REGN
PC214
PC215
1
1
PQ206
21
PAD
PC216
PC217
2
1 15 DL_CHG 4
2
ACN LODRV
2
1
2 14
ACP GND PR212
3
2
1
10_0603_1%
2
CHG_CMSRC 3 13 CHG_SRP
1 2 CHG_CSOP1
CMSRC SRP
1
PU201 PR213
BQ24725ARGRR_QFN20_3P5X3P5 6.8_0603_1%
CHG_ACDRV 4 12 CHG_SRN
1 2 CHG_CSON1
2
ACDRV SRN PC221
.1U_0402_16V7K
+3VL 1 2 5 11 CHG_BATDRV
PR214 100K_0402_1% ACOK ACDET BATDRV
IOUT
SDA
SCL
ILIM
<26> VCIN1_ACOK
6
10
PR216 +3VL
3 620K_0402_1% 3
CHG_ILIM 1 2
100K_0402_1%
0.01U_0402_50V7K
CHG_ACDET
1
CHG_IOUT
PR217
PC222
PR218
422K_0402_1%
+19.5V_VIN 1 2
2
2
@ PR224
0_0402_5%
2200P_0402_50V7K
1 2
EC_SMB_CK1 <26,46>
66.5K_0402_1%
100P_0402_50V8J
1
@ PR225
PC223
1
PC224
PR222
0_0402_5%
1 2
EC_SMB_DA1 <26,46>
2
PR223
2
0_0402_5%
1 2
ADP_I <26,45>
1
Vin Dectector
PC225 @
Min. Typ Max. 100P_0402_50V8J
2
4 L-->H 17.16V 17.63V 18.12V Close EC chip

4
H-->L 16.76V 17.22V 17.70V
VILIM = 20*ILIM*Rsr
ILIM = 3.3*100/(100+620)/20/0.01
= 2.29 A Security Classification Compal Secret Data Compal Electronics, Inc.
CHARGER(BQ24725)
A
RepairLap.com B
C
Size
Date:
Document Number

D
Sheet 47 of 60
Rev
v0.2
5 4 3 2 1
ENTRIP1 ENTRIP2
ENLDO (V) ENM (V) (V) (V) LDO5 LDO3 +5VALW +3VALW
Module model information
Low Low X X Off Off Off Off
RT8243A_V1.mdd ">1.6V"
=>High Low X X On On Off Off
">1.6V" ">2.3V"
=>High =>High Off Off On On Off Off
D ">1.6V" ">2.3V" D
ENTRIPx adjustment range: 0.5V~3V,

=>High =>High Off On On On Off On
floating or over 4.5V will shutdown channel. ">1.6V" ">2.3V"
=>High =>High On On On On On On
">1.6V" ">2.3V"
=>High =>High On Off On On On Off
PR38 PR39
13.3K_0402_1% 30K_0402_1%
1 2 1 2
100K_0402_1%
113K_0402_1%
PR40 PR43 Trace width need
+19.5VB_3V/5V
PR42 56K_0402_1%
20K_0402_1% 20K_0402_1% +19.5VB_3V/5V
1 2 1 2 meet LDO5 demand Vout=VFB * (1+(R1/R2))
1
+19.5VB VFB=2V
@ PJB1
1 2 Vout=2*(1+(30K(PR39)/20K(PR43)))
1 2
Vout=5V
2200P_0402_50V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
ENTRIP22
ENTRIP12
JUMP_43X79 +3VALW
PR41
PR44
4.7U_0805_25V6-K
4.7U_0805_25V6-K
0.1U_0402_25V6
1
FB_3V
FB_5V
@EMI@ PC34
PC44
PC36
FB=1.98V(Min) FB=1.98V(Min)
1
1
EMI@ PC35
PC33
PC39
2.006V(Typ) 2.006V(Typ)
10K_0402_1%
<9> SPOK 2.03V(Max) 2.03V(Max)
2
PR111
2
1
FB2
ENTRIP2
TON
ENTRIP1
FB1
2
21
C 6 PAD C
PR46 PGOOD 20
2.2_0603_5% BYP1 PR45 PC37
4
4
1 2 1 2 BST_3V 7 2.2_0603_5% 0.1U_0402_25V6
BOOT2 19 BST_5V 1 2 1 2
D1
D1
D1
G1
G1
D1
D1
D1
PC38 PU2 BOOT1
0.1U_0402_25V6 UG_3V 8 RT8243AZQW_WQFN20_3X3
PL9 10 9 UGATE2 18 UG_5V 9 10
3.3UH_6.3A_20%_7X7X3_M D1 D2/S1 UGATE1 D2/S1 D1 PL8
1 2 LX_3V LX_3V 9 2.2UH_7.8A_20%_7X7X3_M
+3VALWP PHASE2 17 LX_5V PQ8 LX_5V 1 2 +5VALWP
G2
G2
S2
S2
S2
S2
S2
S2
PHASE1
1
680P_0402_50V7K 4.7_1206_5%
PQ7 AON7934_DFN3X3A8-10
680P_0402_50V7K 4.7_1206_5%
@EMI@ PR47
AON7934_DFN3X3A8-10 LG_3V 10
5
5
LGATE2
@EMI@ PC42 @EMI@ PR48

16 LG_5V
ENLDO
LGATE1
LDO5
LDO3
ENM
VIN
220U 6.3VM_R15
220U 6.3VM_R15
1
2
2
+
PC40
PC45 0.1U_0603_25V7K
11
12
13
14
15
1
PC43
@ PJP10
1
JUMP_43X39 Typ: 175mA
ENM
2
@EMI@ PC41
+19.5VB_3V/5V +3VLP 1 2
+3VL
2
1 2 2
2
Rds(on):12.4mΩ ~15.8mΩ
1
PC46
4.7U_0603_10V6K
2
PR49 @ PJP11
499K_0402_1% JUMP_43X39 Typ: 225mA
1 2 +VLP 1 2 @ PJP2
Vout=VFB * (1+(R1/R2)) 1 2 +VL 1 2
VFB=2V +3VALWP 1 2 +3VALW
1
150K_0402_1%
B JUMP_43X118 B
Vout=2*(1+(13.3K(PR38)/20K(PR40)))
1
PC47
Vout=3.3V
PR50
4.7U_0603_10V6K @ PJP3
1 2
+5VALWP +5VALW
2
1 2
2
JUMP_43X118
PR51
2.2K_0402_5%
1 2 ENM
<26> EC_ON
ENLDO threshold ON: 1.2min 1.6typ 2max @ PR52
OFF: 0.9min 0.95typ 1max 0_0402_5%
5V=375KHz 3V=400KHz (Vin=12 ~ 25v)
1 2 (By Rton= 56K ohm)
<26> MAINPWON
B+ threshold ON: 5.19min 6.92typ 8.65max
4.7U_0603_10V6K
OFF: 3.89min 4.11typ 4.33max

1
+5VALWP Ipeak=9.26A ; Imax=6.5A

1
PC48
PR53
402K_0402_1% Delta I=3.483A=>1/2Delta I=1.742A
VIN rising threshold: 5.1typ 5.5max Rds(on)=15.8m ohm(max) ; Rds(on)=12.4m ohm(typical)
falling threshold: 3.5min 4.5max
2
OCP =11.11A
2
+3.3VALWP Ipeak=4.26A ; Imax=3A

Delta I=1.92A=>1/2Delta I=0.96A
Rds(on)=15.8m ohm(max) ; Rds(on)=12.4m ohm(typical) TDC:4.9A Fsw:321KHz
OCP = 5.1A H-MOS PD:0.4173W ∆ T:13.4℃
A L-MOS PD:0.3442W ∆ T:10℃ A
Choke PD:1.9613W ∆ T:30℃
OVP margin for Vos:9% @ 330uF cap, 8% @ 220uF
TDC:4.31A Fsw:375KHz
H-MOS PD:0.3736W ∆ T:12℃
L-MOS PD:0.2713W ∆ T:7.9℃
Choke PD:1.5158W ∆ T:24℃ Security Classification Compal Secret Data Compal Electronics, Inc.
OVP margin for Vos:8% @ 330uF cap, 6% @ 220uF Issued Date 2015/10/09 Deciphered Date 2018/10/09 Title
3VALW/5VALW
5 4
RepairLap.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3 2
Custom
Date: Wednesday, May 11, 2016

LA-D707P
1
Sheet 48 of 60
Rev
v0.2
5 4 3 2 1

RT8207M_V1.mdd For Single layer
RT8207M_V2.mdd For Dual layer
D D
Pin19 need pull separate from +1.35VP.

If you have +1.35V and +0.675V sequence question, 0.675Volt +/- 5%
you can change from +1.35VP to +1.35VS. TDC 0.7A
@ PJB2
1 2 +19.5VB_1.35VP PR54 Peak Current 1A
+19.5VB 1 2 2.2_0603_5%
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
BST_1.35VP_R 1 2 BST_1.35VP
JUMP_43X79 +1.2VP
1
@EMI@ PC49
PC50
PC51
+0.6VSP
1
PC52 UG_1.35VP
2
0.1U_0603_25V7K
10U_0603_6.3V6M
10U_0603_6.3V6M
LX_1.35VP
1
PC53
PC54
16
17
18
19
20
2
PHASE
UGATE
BOOT
VLDOIN
VTT
21
PAD
LG_1.35VP 15 1
Vout=Vref * (1+(R1/R2))
LGATE VTTGND
Vref=0.75V
1
14 2 Vout=0.75*(1+(6.04K(PR58)/10K(PR60)))
D1
D1
D1
G1
PGND VTTSNS
PL11
1UH_11A_20%_7X7X3_M
PR55
11.5K_0402_1%
Vout=1.2V
1 2LX_1.35VP 10 9 1 2 CS_1.35VP 13 3
+1.2VP D1 D2/S1 PC55 CS GND
1
1U_0402_6.3V6K
1 2 12 4 VTTREF_1.35VP
G2
S2
S2
S2
@EMI@ PR56 PR57 VDDP VTTREF
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
4.7_1206_5% 5.1_0603_5%
5
8
1
1 2 VDD_1.35VP 11 5
+5VALW +1.2VP
1 2
VDD VDDQ
1
PC56
PC57
PC58
PC59
PC61
PC62
PGOOD
PC60
TON
2
1
@EMI@ PC64 0.033U_0402_16V7K
FB
S5
S3
2
C 680P_0402_50V7K PC63 C
2
1U_0402_6.3V6K
10
6
PQ11 PU3
AON7934_DFN3X3A8-10 PR65 RT8207PGQW_WQFN20_3X3
FB_1.35VP
5.1_0603_5%
TON_1.35VP
EN_0.675VSP
Rds(on):12.4mΩ ~15.8mΩ 1 2 PR58
EN_1.35VP
6.04K_0402_1%
@ DDR_PWROK PR59 1 2 +1.2VP
PAD 470K_0402_1%
+19.5VB_1.35VP 1 2
VFB=0.75V
1
+1.35VP Ipeak=7.4A ; Imax=6A @ PR1815
0_0402_5%
Delta I=2.2A=>1/2Delta I=1.1A (F=521K Hz) 2.5V PG Enable 1.2V +2.5V_PG 1 2 PR60
Rds(on)=15.8m ohm(max) ; Rds(on)=12.4m ohm(typical) 10K_0402_1%
2
1 2
OCP = 8.88 <12,26,35,49> SYSON
0.1U_0402_10V7K
@ PR61
0_0402_5%
1
Choke: 7x7x3
PC65
Rdc=8.3mohm(Typ), 10mohm(Max)
2
2014/12/23 @
Switching Frequency: 285kHz change from SUSP# to SM_PG_CTRL @ PR62
Ipeak=10A 0_0402_5% @ PJP4
1 2 JUMP_43X118
Iocp~13A <12,13,26,35> SUSP# 1 2
+1.2VP +1.2V_VDDQ
OVP: 110%~120% 1 2
VFB=0.75V, Vout=1.3545V @ PR63
0_0402_5%
1 2
<6> SM_PG_CTRL
1
@ PJP5
@ PC66 JUMP_43X39
0.1U_0402_10V7K 1 2
+0.6VSP +0.6V_0.6VS
2
1 2
Mode Level +0.675VSP VTTREF_1.35V
S5 L off off
S3 L off on
S0 H on on
B B
Note: S3 - sleep ; S5 - power off

SY8032_V2.mdd
@ PJM5
Note: JUMP_43X39
When design Vin=5V, please stuff snubber PCM21
+2.5VP
1
1 2
2
+2.5V
22U_0603_6.3V6M
to prevent Vin damage PUM2
1 2 SY8032ABC_SOT23-6
@ PJM4 PLM3
JUMP_43X39 1UH_2.3A_+-20%_2.5X2X1.2_F
+3VALW 1 2 4 3 LX_2.5V 1 2
1 2 IN LX +2.5VP
68P_0402_50V8J
@ PRM27 1 2 5 2
0_0402_5% +3VALW PG GND Vout=0.6V * (1+(R1/R2))
1
Vout=0.6*(1+(32.4K(PRM23)/10K(PRM26)))
PCM22
22U_0603_6.3V6M
22U_0603_6.3V6M
1 2 PRM21 6 1
<9,12,26,35> PM_SLP_S4# FB EN
1
1
PCM23
PCM24
100K_0402_5%
Vout=2.5V
1
@ PRM24 Enable 1.2V +2.5V_PG @EMI@ PRM22 PRM23

2
0_0402_5% 4.7_0402_5% 32.4K_0402_1%

1 2 EN_2.5V
<12,26,35,49> SYSON
2
Rup
2
0.1U_0402_16V7K
1
PCM25
1
PRM25 FB_2.5V
1M_0402_1%
Imax= 2A, Ipeak= 3A
2
A @ FB=0.6V A
2
@EMI@ PCM26
680P_0402_50V7K PRM26
2
10K_0402_1%
Rdown Vout=0.6V* (1+Rup/Rdown)
2

Issued Date 2018/10/09 Title
2015/10/09 Deciphered Date
1.2VP/0.6VSP/2.5VP(RT8207P/SY8032A)
5 4 RepairLap.com 3
2
Custom

1
Sheet 49 of 60
Rev
v0.2
A B C D
1 1
Confirm HW side
+3V_PRIM
+1.0V_PRIM
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
@EMI@ PR605 @EMI@ PC602
PR611 4.7_1206_5% 680P_0603_50V7K
+1.0V_VS_PG_PWR <26>
1
PC615
PC616
PC617
PC618
EMI@ PL1207 100K_0402_5% 1 2 SNUB_1V 1 2
5A_Z120_25M_0805_2P
PU601
2
+19.5VB 1 2 +19VB_1V 2
IN PG
9 @ PR606 PC603 (Common Part SH00000YE00) @ @ @ @
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
0_0402_5% 0.1U_0201_10V6K
2200P_0402_50V7K
3 1 BST_1V 1 2 BST_1V_R 1 2
IN BS PL602
1
EMI@ PC604
@EMI@ PC605
PC606
PC607
4 6 LX_1V 3 2
IN LX
330P_0402_50V7K
14K_0402_1%
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
5 19 4 1
IN LX
1
PR608
PC608
PC609
PC610
PC611
PC612
7 20 1UH_11A_20%_7X7X3_M
GND LX
8 14 FB_1V R1
2
GND FB
2
@ PR603 18 17 LDO3V_1V
0_0402_5% GND VCC
1
1 2 EN_1V 11 10
<51> +1.8V_PG EN NC PC613 FB=0.6V
1
ILMT_1V 13 12 2.2U_0402_6.3V6M
2
ILMT NC
1
1
1M_0402_1%
@ PC601
PR601
0.1U_0402_25V6 15 16 PR610
2
+3VALW BYP NC R2 20K_0402_1%

2
2
21
+3VALW
2
PAD
Vout=0.6V* (1+R1/R2)
2
SY8286RAC_QFN20_3X3
1
=0.6*(1+(14K(PR608)/20K(PR610)))
1
PC614
@ PR607 1U_0402_6.3V6K
Vout=1.0V
2
0_0402_5%
EN :H>0.8V ; L<0.4V
2
EN pin don't floating

If have pull down resistor at HW side,
1
please delete PR601. @ PR609

0_0402_5%
2
The current limit is set to 6A, 9A or 12A when this pin

is pull low, floating or pull high.
3 3
4 4

1.0VS(SY8286)
A
RepairLap.com
B
C
Custom

D
Sheet 50 of 60
Rev
v0.2
5 4 3 2 1
D D
PC94
22U_0603_6.3V6M
@ PJP9
1 2
Imax= 2A, Ipeak= 3A 1 2
FB=0.6V +1.8VSP 1 2 +1.8V_PRIM
PU6 JUMP_43X79
@ PJB4 SY8032ABC_SOT23-6 PL15
JUMP_43X39 1UH_2.8A_30%_4X4X2_F
+3VALW 1 2 IN_1.8V 4 3 LX_1.8V 1 2
1 2 IN LX +1.8VSP
1 2 5 2
C
2015/01/06 +3V_PRIM PG GND
C
PGOOD from +3VS
68P_0402_50V8J
22U_0603_6.3V6M
22U_0603_6.3V6M
PR1814 6 1
FB EN
1
PC95
PC96
PC97
100K_0402_5%
change to +3V_PRIM <50> +1.8V_PG
1
@EMI@ PR92
PR93 20K_0402_1%
2
4.7_0603_5%
1 2 EN_1.8V
<13,26,35> PCH_PWR_EN Rup
2
2
0.1U_0402_16V7K
@ PR94
SNUB_1.8V
1
1M_0402_1%
PR95
0_0402_5% @ PC98
1
FB_1.8V
2
1
@EMI@
2014/12/13
2
PC99
change net name to PCH_PWR_EN 680P_0402_50V7K PR96
Vout=0.6V * (1+(R1/R2))
2
10K_0402_1%
Rdown Vout=0.6*(1+(20K(PR92)/10K(PR96)))
Vout=1.8V
2
Note:
When design Vin=5V, please stuff snubber
B
to prevent Vin damage B
Vout=0.6V* (1+Rup/Rdown)
A A

1.8VS(SY8032A)
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B v0.2
Date: Sheet 51 of 60
5 4 3 2 1
RepairLap.com
1 2 3 4 5
RDRPSP(PR1149)= Load line*(PR1146+PH1105+PR1145)/(gm * DCR) /(PH1105+PR1145)

PR1101=2*PR1106/(10*IOUTmax*Load line) RIccMAX2ph(PR1104)= (IccMAX2Ph+32)*200kohm/ 127 Load line@SA= 10.3m
U22 Iout@GT=31A U22 IccMAX@GT= 31A gm=1mS
PR1101=25.5kohm PR1104= 100K PR1149=1.78K
RLIMSP(PR1147)= 1.3V/(gm*(PH1105+PR1145)*IoutLIMIT*DCR/(PR1146+PH1105+PR1145))
PR1106=Iout limit*Load line/10 Load line=(PR1108+(PR1107+PH901/(PR1107*PH901)))*Iout tltal*DCR/PR1109 OCP@SA= 9.6A
U22 OCP@GT=40A U22 Load line@GT= 3.1m gm=1mS
PR1106=12.4kohm PR1109 , PR1110@GT=84.5K PR1147=24K
RIOUTSP(PR1144)= 2V/(gm*(PH1105+PR1145)*ICCMAX*DCR/(PR1146+PH1105+PR1146))
IOUTSP@SA= 5A
A gm=1mS A
PR1144=69.8K
close to CPU @ PC1136 +1.0V_VCCST
2200P_0402_50V7K
0.015U_0402_25V7K 1.5K_0402_1%
PR1154 1 2
100_0402_1%
1
1 2 @ PR1152 PR1150 Place
PR1148
0_0402_5% 0_0402_5% close CSN_SA <53>
1000P_0402_50V7K
24K_0402_1%
499_0402_1%
15P_0402_50V8J
45.3_0402_1%
0.1U_0402_25V6
1 2 1 2
<12> VSSSA_SENSE to PL1206
1
110_0402_1%
100_0402_1%
PC1105
1
1000P_0402_50V7K
PC1134
PC1132
PR1147
PR1139
@ PR1140
PR1138
@ PR1162
PC1137 PH1105
0.01U_0402_50V7K
1000P_0402_50V7K PR1149 100K_0402_1%_B25/50 4250K
2
1
PC1130
1.78K_0402_1%
2
1
1
PC1133
PC1131
<12> VCCSA_SENSE 1 2 1 2
1 2
2
program IccMax_2ph CSN_SA_R
VR_HOT#
2
1 2 @ PR1151 PC1135
+VCC_SA
2
DIFFOUT_GT 0_0402_5% 1000P_0402_50V7K PR1145 PR1164
470P_0402_50V7K49.9_0402_1%
PR1153 1 2 12K_0402_1% 49.9_0402_1%

1
100_0402_1% PR1146 1 2 SOC_SVID_CLK <14>

PR1102
close to CPU 7.5K_0603_1%
2
1 2 @ PR1165
SWN_SA <53>
1
1
649_0402_1%
PR1155 0_0402_5%
PR1103
20K_0402_1% PR1143 1 2 SOC_SVID_ALERT#_R <14>

2
PR1104 +VCC_GT PR1159 1 2 10K_0402_1%
PSYS_MON
100K_0402_1% 100_0402_1% PC1129 1 2 PR1163
+3VS
1
PC1102
1 2 470P_0402_50V8J 10_0402_1%
2
close to CPU @ PR1157 1 2 VR_PWRGD <26> 1 2 SOC_SVID_DAT <14>

0_0402_5%
2
1 2 VSP_GT PR1144 @ PR1142

<14> VCCGT_SENSE
FB_GT 69.8K_0402_1% 0_0402_5% 1 2 VR_HOT# <26>
1
4.7K_0402_1%
PC1139 1 2 1 2 VR_ON <26,35>

1000P_0402_50V7K PR1156 PR1161 2015/01/05
1
PR1105
1.24K_0402_1% PR1141=43.2k for debug 100_0402_1% change PR1141 from 51.1k to
2
15P_0402_50V8J
1 2 1 2 VSN_GT PR1141
VSN_SA
VSP_SA
<14> VSSGT_SENSE
PR1160 VR_PWRGD_R 51.1K_0402_1%
43.2k, to set the Vboot voltage
CSN_SA
CSP_SA
IOUT_SA
ILIM_SA
COMP_SA
from 0V to 1.2V
1
PC1103
100_0402_1% @ PR1158 1 2 1 2
B 1 2 0_0402_5% VR_ON_R 1 2 B
SWN_CORE <53>
2
PC1138 PWM_SA <53>

2
1
3300P_0402_25V7K
12K_0402_1%
close to CPU 3300P_0402_50V7-K PR1136
1
PC1104
PR1135
DRON <53> 7.5K_0603_1%
PR1101
0.01U_0402_50V7K
0.022U_0402_25V7K
25.5K_0402_1%
2
COMP_GT 1 2
53
52
51
50
49
48
47
46
45
44
43
42
41
40
2
1
1
PC1126
PC1127
Place PC1101 CSN_CORE_R
VSN_2ph
VSP_2ph
EPAD
PSYS
VSP_1b
VSN_1b
COMP_1b
ILIM_1b
CSN_1b
CSP_1b
IOUT_1b
VR_RDY
EN
PWM/ADDR_VBOOT
1
close 1 2 470P_0402_50V8J PR1137
2
1 2 IOUT_GT 52.3K_0402_1% PH1104
to PL1203 PR1106 1 2 100K_0402_1%_B25/50 4250K
1
12.4K_0402_1% 1 39 Place
DIFFOUT_GT 2 IOUT_2ph DRON 38 SCLK_CORE PC1128 close
2
PH901 PR1107 FB_GT 3 DIFFOUT_2ph/ICCMax_2ph SCLK 37 ALERT#_CORE 82P_0402_50V8J
220K_0402_5%_B25/50 4700K 75K_0402_1% COMP_GT 4 FB_2ph ALERT# 36 SDIO_CORE 1 2
to PL1205
COMP_2ph SDIO CSN_CORE <53>
820P_0402_25V7
33P_0402_50V8J
ILIM_GT 5 35 VR_HOT_CORE
2
CSCOMP_GT 6 ILIM_2ph VR_HOT# 34 IOUT_CORE

CSCOMP_2ph IOUT_1a
1
1
PC1108
PC1107
CSCOMP_GT_R CSSUM_GT 7 33 CSP_CORE

CSSUM_2ph CSP_1a
0.01U_0402_50V7K
CSREF_GT 8 32 CSN_CORE
CSP2_GT 9 CSREF_2ph CSN_1a 31 ILIM_CORE 1 2
2
CSP2_2ph ILIM_1a
1
CSP1_GT 10 30 COMP_CORE 1 2 1 2
CSP1_2ph COMP_1a
1
PC1109
TSENSE_GT 11 29 VSN_CORE PC1125

TSENSE_2ph VSN_1a
0.1U_0402_25V6
PR1108 VRMP 12 28 VSP_CORE PC1124 PR1133 1000P_0402_50V7K
LG2/ICCMAX_1a
LG3/ICCMAX_1b
165K_0402_1% 13 VRMP VSP_1a 27 TSENSE_CORE 8200P_0402_25V7K2.49K_0402_1% 1 2
2
VCC TSENSE_1ph
1
PC1112
PR1109 CPU core_VCC 1 2

2
1
LG1/ROSC
84.5K_0603_1% PC1119 PR1134
<52,53> SWN1_GT 1 2 0.1U_0402_25V6 PC1123 28K_0402_1%
2
PVCC
15P_0402_50V8J
BST1
BST2
BST3
SW1
SW2
SW3
HG1
HG2
HG3
2
PR1111
2K_0402_1% PC1120 PR1131
1 2 CSP1_GT PU1101 2200P_0402_50V7K 100_0402_1%
<52,53> SWN1_GT
14
15
16
17
18
19
20
21
22
23
24
25
26
1 2 1 2
1
NCP81206MNTXG_QFN52_6X6 @ PR1129
Place close to PL1203 PR1112 PC1110 +19VB_CPU 0_0402_5% close to CPU
10_0402_1% 0.1U_0402_25V6 PR1117 +5VS 1 2 1 2 VSSSENSE <14>
2
<53> CSN1_GT 1 2 1K_0402_1%

1U_0603_10V6K
1 2 1 2 PR1127
1
C C
0.01U_0402_50V7K
CSREF_GT 1K_0402_1% PC1122

+5VS
2
1
PC1113
PC1114
PR1243 PR1118 1000P_0402_50V7K

1K_0402_1% 2.2_0603_5% PR1128
2
1 2 CSP2_GT 2.1K_0402_1%
1
1 2 1 2
2014/12/24 BST_CORE <53> PR1132
VCCSENSE <14>
PR1243 change to 1k ohm UG_CORE <53>

1 2 1 2
@ PR1130
0_0402_5%
100_0402_1%
1 2
LX_CORE <53> +VCC_CORE
LG_CORE <53>
TSENSE_GT PC1121 PR1242
1 2 1000P_0402_50V7K 2.1K_0402_1% close to CPU
1
<53> BST1_GT TSENSE_CORE

<53> UG1_GT PR1123
1
PR1115 <53> LX1_GT 11K_0402_1%
1.07K_0402_1% <53> LG1_GT
PR1125
2
+5VS
100K_0402_1%_B25/50 4250K
1.07K_0402_1%
TSENSE_GT_R
472mV/120uA=3.933K Act i ve Poi nt 110 degr eeC = 4. 206K
100K_0402_1%_B25/50 4250K
Place N27484288 TSENSE_CORE_R
1
2
21.5K_0402_1%
2.2U_0603_10V6K
close
1
PH1102
PR1120
PC1116
to PQ1201
1
PR1116
PH1103
61.9K_0402_1%
2
PR1126 Place
2
PR1121 61.9K_0402_1% close

472mV/120uA=3.933K 29.4K_0402_1% to PQ1205
2
Act i ve Poi nt 110 degr eeC = 4. 206K
2
NCP81206 Operat i ng Fr equency Rosc=21. 5K

I/A and GT are around 450KHz and SA is 600KHz
IccMAX@SA= 5A RDRPSP(PR1128)= Load line*(PR1136+PH1104+PR1135)/(gm * DCR) /(PH1104+PR1135)

D
PR1123= 11K Load line@VCORE= 2.1m D
Refer IccMAX table in datasheet gm=1mS
PR1128=2.1K
IccMAX@VCORE= 28A RIOUTSP(PR1137)= 2V/(gm*(PH1104+PR1135)*ICCMAX*DCR/(PR1136+PH1104+PR1135))
RIccMAX@VCORE= 24.9K IOUTSP@VCORE= 28A
Refer IccMAX table in datasheet gm=1mS
PR1137=64.9K
RLIMSP(PR1134)= 1.3V/(gm*(PH1104+PR1135)*IoutLIMIT*DCR/(PR1136+PH1104+PR1135)) Title
OCP@VCORE= 35A VCC_CORE_U22(NCP81206)
1 2 RepairLap.com 3
gm=1mS
PR1134=33.2K
4
Size
Date:
Document Number

5
Sheet 52 of 60
Rev
v0.2
1 2 3 4 5
+19VB_CPU
Input Capacitor: EMI@ PL1201
5A_Z120_25M_0805_2P
10uF_0805_X5R_25V 1 2
+19.5VB
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
100U_25V_NC_6.3X6
0.1U_0402_25V6
MDU1516URH_POWERDFN56-8-5
@EMI@ PC1384
EMI@ PC1385
1
1
PC1201
PC1202
PC1203
PC1204
EMI@ PL1202
5
+
PC1205
5A_Z120_25M_0805_2P
1 2
2
2
PQ1201
Total VCC_GT Output Capacitor: +VCC_GT
4 13 X 22uF_0603_X5R + 1 X 330uF
<52> UG1_GT
13 X 22uF_0603_X5R on CPU back side
A GT_CORE A
FSW = 450kHz +VCC_GT <14,52,54>

DCR = 1.19 mohm +/- 5%
3
2
1
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
PR1119
2.2_0603_5%
TDC@GT_CORE = 18A 1 1 1 1 1 1 1 1 1 1
PC1301
PC1302
PC1303
PC1304
PC1305
PC1306
PC1307
PC1308
PC1309
@ PC1310
<52> BST1_GT 1 2 BST1_GT_R
H=5.8mm TYP MAX
H/S Rds(on) = 11.7 mohm , 14 mohm
1
PC1115 2 2 2 2 2 2 2 2 2 2
0.22U_0603_25V7K PL1203 +VCC_GT L/S Rds(on) = 2.7 mohm , 3.3 mohm
0.24UH_22A_+-20%_7X7X3_M
2
+VCC_GT
390U_2.5V_ESR10M_6.3X6
LX1_GT 1 4
<52> LX1_GT
@EMI@ PC1210 @EMI@ PR1210

2 3
4.7_1206_5%
AON6794_DFN5X6-8-5
Choke 0.24uH SH000010N00 1
PC2123
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
0.24uH (DCR 1.19 +-5%) +
1 1 1 1 1 1 1 1 1 1
PQ1202
PC1311
PC1312
@ PC1313
@ PC1317
PC1319
PC1320
PC1314
PC1316
PC1318
PC1315
1SNUB1_GT2
CSN1_GT <52> 2
<52> LG1_GT 4
2 2 2 2 2 2 2 2 2 2
680P_0603_50V7K
SWN1_GT <52>
3
2
1
2
2014/12/25
add 7 pcs 22uF cap for primary side, total 20 pcs
InputCapacitor: Total VCORE Output Capacitor:

B
10uF_0805_X5R_25V 20 X 22uF_0603_X5R + 2 X 330uF +VCC_CORE B
+19VB_CPU 13 X 22uF_0603_X5R on CPU back side.
100U_25V_NC_6.3X6
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
@EMI@ PC1387
EMI@ PC1386
5
1
+
PC1221
PC1222
PC1223
PC1224
PC1225
+VCC_CORE <14,52,54>
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
CPU_CORE
2
2
2
PQ1205
1 1 1 1 1 1 1 1 1 1
FSW = 450kHz
PC1351
PC1352
PC1353
PC1354
PC1355
PC1356
PC1357
PC1358
PC1359
PC1360
4
<52> UG_CORE
DCR = 1.19 mohm +/- 5%
2 2 2 2 2 2 2 2 2 2
TDC@VCC_CORE = 21A @ @ @ @ @ @ @ @
TYP MAX
3
2
1
PR1124
2.2_0603_5% H/S Rds(on) = 11.7 mohm , 14 mohm
<52> BST_CORE 1 2 BST_CORE_R L/S Rds(on) = 2.7 mohm , 3.3 mohm
H=5.8mm +VCC_CORE
1
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
PC1118
0.22U_0603_25V7K PL1205 +VCC_CORE 1 1 1 1 1 1 1 1 1 1
PC1361
PC1362
PC1363
PC1364
PC1365
PC1366
PC1367
PC1368
PC1369
PC1370
0.24UH_22A_+-20%_7X7X3_M
2
390U_2.5V_ESR10M_6.3X6
<52> LX_CORE LX_CORE 1 4
2 2 2 2 2 2 2 2 2 2
4.7_1206_5%
330U_D1_2VY_R9M
1
2 3 @ @ @ @
0.24uH (DCR 1.19 +-5%) 1 1
5
@EMI@ PR1230
PC1383
PC2124
+ +
AON6794_DFN5X6-8-5
Choke 0.24uH SH000010N00

1SNUB_CORE
2
2@ 2
PQ1206
CSN_CORE <52>
<52> LG_CORE 4
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
SWN_CORE <52>
680P_0603_50V7K
1 1 1 1 1
@EMI@ PC1230
PC2118
PC2119
PC2120
PC2121
PC2122
3
2
1
C 2 2 2 2 2 C
@ @ @ @ @
2015/5/19
ADD 5pcs cap on +Vcc_IA
Input Capacitor:
10uF_0805_X5R_25V SA_CORE
+19VB_CPU
FSW = 450kHz
10
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
@EMI@ PC1389
0.1U_0402_25V6
DCR = 6.2 mohm +/- 5%

EMI@ PC1388
PR1241 5 4
D1
S2 D1
1
1
PC1231
PC1232
2.2_0603_5%
1 2 6 3
TDC@SA_CORE = 4A
S2 D1
TYP MAX
2
7 2
S2 D1 H/S Rds(on) = 12.4 mohm , 15.8 mohm
1
D2/S1
PU1502 PC1241
NCP81253MNTBG_DFN8_2X2 0.22U_0603_25V7K LG_SA 8 1UG_SA +VCC_SA L/S Rds(on) = 8.4 mohm , 10.3 mohm
G2 G1 PL1206
2
1 8 UG_SA PQ1207 0.47UH_MMD05CZR47M_12A_20%

9
BST DRVH AON7934_DFN3X3A8-10

<52> PWM_SA 2 7 LX_SA 1 4
PWM SW +VCC_SA
4.7_1206_5%
Total VCORE Output Capacitor:

1
3 6 2 3
<52> DRON EN GND 8 X 22uF_0603_X5R
@EMI@PR1240
4 5 LG_SA 4 X 22uF_0603_X5R on CPU back side

+5VS
PAD
VCC DRVL
Choke 0.47uH SH000015M00
0.47uH (DCR 6.2 +-5%) +VCC_SA <12,52,54>
1SNUB_SA
2
1
CSN_SA <52>
9
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
PC1242
680P_0603_50V7K
2.2U_0603_10V6K 1 1 1 1 1 1 1 1
2
PC1391
PC1392
PC1393
PC1394
PC1395
PC1396
PC1397
PC1398
SWN_SA <52>
@EMI@PC1240
2 2 2 2 2 2 2 2
2
@ @ @
D 2014/12/31 D
change PU1502 VCC pin from +5VALW to +5VS

Total VCORE Output Capacitor: 2014/12/25
4 X 22uF_0603_X5R change 3pcs to un-mount
4 X 22uF_0603_X5R on CPU back side
Title
VCC_CORE_PowerStage
1 2 RepairLap.com 3 4
Size
Date:
Document Number

5
Sheet 53 of 60
Rev
v0.2
A
B
C
D
+VCC_CORE
5
5
2 1 2 1 2 1 2 1
2
1
PC2086 PC2076 PC2031 PC2021 PC2001

1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
2
1
PC2087 PC2077 PC2032 PC2022 PC2002

2 1 2 1 2 1 2 1
2
1
PC2088 PC2078 PC2033 PC2023 PC2003

2 1 2 1 2 1 2 1
2
1
VCC_CORE Place on CPU Back Side.
PC2089 PC2079 PC2034 PC2024 PC2004

22U_0603 * 13 pcs + 1U_0201*35 pcs

2 1 2 1 2 1 2 1
2
1
PC2090 PC2080 PC2035 PC2025 PC2005

2 1 2 1 2 1
2
1
PC2081 PC2036 PC2026 PC2006

1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
2
1
PC2082 PC2037 PC2027 PC2007

1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
2
1
4
4
PC2083 PC2038 PC2028 PC2008

1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
2
1
PC2084 PC2039 PC2029 PC2009

1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
2
1
PC2085 PC2040 PC2030 PC2010

1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2
1
PC2011
22U_0603_6.3V6M
2
1
PC2012
22U_0603_6.3V6M
2
1
PC2013
22U_0603_6.3V6M
2
1
PC2014
22U_0603_6.3V6M
Issued Date
3
3
+VCC_GT
2015/10/09
2
1
2 1
20150324
2
1
@ PC1321
22U_0603_6.3V6M PC2061 PC2041
1U_0201_6.3V6M 22U_0603_6.3V6M
2
1
2 1
2
1
@ PC1322
22U_0603_6.3V6M PC2062 PC2042
1U_0201_6.3V6M 22U_0603_6.3V6M
2
1
2 1
2
1
PC1323
22U_0603_6.3V6M PC2063 PC2043
1U_0201_6.3V6M 22U_0603_6.3V6M
2
1
2 1
2
1
@ PC1324
Compal Secret Data

VCC_GT Place on CPU Back Side.
22U_0603_6.3V6M PC2064 PC2044
Deciphered Date
1U_0201_6.3V6M 22U_0603_6.3V6M
2
1
2 1
2
1
PC1325
22U_0603 * 13 pcs + 1U_0201*12 pcs
22U_0603_6.3V6M PC2065 PC2045

1U_0201_6.3V6M 22U_0603_6.3V6M
2
1
2 1
2
2
2
1
PC1326
add 6 pcs cap for transient test
22U_0603_6.3V6M PC2066 PC2046
RepairLap.com
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1
2
1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS PC2067 PC2047
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1
2018/10/09
2
1
PC2068 PC2048
2014/12/25
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1
2
1
PC2069 PC2049
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1
2
1
Size
Title
Date:
+VCC_SA
PC2111 PC2070 PC2050

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1
2
1
PC2112 PC2071 PC2051

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
+VCC_SA
2 1 2 1
2
1
LA-D707P
PC2113 PC2072 PC2052

Document Number
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M

2
1
2 1
2
1
PC2101 2 1
PC2114 22U_0603_6.3V6M PC2053
1U_0201_6.3V6M PC2073 22U_0603_6.3V6M

2
1
2 1 1U_0201_6.3V6M
PC2102
PC2115 22U_0603_6.3V6M
1
1
1U_0201_6.3V6M
2
1
2 1
PC2103
Sheet
PC2116 22U_0603_6.3V6M
VCC_SA Place on CPU Back Side.
add 1 pcs 1uF cap for back side, total 13 pcs
1U_0201_6.3V6M
2
1
2 1
PC2104
54
PC2117 22U_0603_6.3V6M
22U_0603 * 4 pcs + 1U_0201 * 7 pcs
1U_0201_6.3V6M
VCC_CORE_PROCESSOR DECOUPLING
of 60
Rev
v0.2
A
B
C
D
A B C D
Confirm HW side
1
Vout=0.6V* (1+R1/R2) 1
<56> VRAM_PG +3VS =0.6*(1+(15K(PRW4)/10K(PRW7)))

VRAM_PG
Vout=1.5V
1
@DISEMI@ PRW2 @DISEMI@ PCW1
@DIS@ PRW3 4.7_1206_5% 680P_0603_50V7K
100K_0402_5% 1 2 SNUB_1.5V 1 2
@ PJB7 DIS@ PUW1
2
+19.5VB 1
1 2
2 +19VB_1.5V 2
IN PG
9 @ PRW1 DIS@ PCW4 (Common Part SH00000YE00)
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
0_0402_5% 0.1U_0201_10V6K
2200P_0402_50V7K
3 1 BST_1.5V 1 2 BST_1.5V_R 1 2
JUMP_43X79 IN BS
1
DIS@PCW14
DISEMI@ PCW2
@DISEMI@ PCW3
DIS@ PCW5
DIS@ PLW1
4
IN LX
6 LX_1.5V 3 2
+1.5VRAMP
330P_0402_50V7K
15K_0402_1%
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
DIS@ PRW4
5 19 4 1
IN LX
DIS@PCW10
DIS@ PCW6
DIS@ PCW7
DIS@ PCW8
DIS@ PCW9
7 20 1UH_11A_20%_7X7X3_M
GND LX
8 14 FB_1.5V R1
2
GND FB
2
DIS@ PRW5 18 17 LDO3V_1.5V
22K_0402_5% GND VCC
10,26,38,56> DGPU_PWR_EN
1
1 2 EN_1.5V 11 10
EN NC DIS@ PCW11 FB=0.6V
10K_0402_1%
ILMT_1.5V 13 12 2.2U_0402_6.3V6M
2
ILMT NC
1
DIS@ PRW7
DIS@ PCW12
DIS@ PRW6 15 16
1M_0402_1%
0.1U_0402_25V6 +3VALW BYP NC R2
2
21
+3VALW
2
PAD
2
2
EN :H>0.8V ; L<0.4V SY8286RAC_QFN20_3X3 2
1
1
EN pin don't floating @ PRW8 DIS@ PCW13
2
If have pull down resistor at HW side, 0_0402_5% 1U_0402_6.3V6K
@ PJW2
please delete PR601. JUMP_43X118
2
1 2
+1.5VRAMP 1 2 +1.5VS_VGA
1
@DIS@ PRW9
0_0402_5%
2
The current limit is set to 6A, 9A or 12A when this pin

is pull low, floating or pull high.
3 3
4 4

1.5VS_VGA(SY8286)
RepairLap.com
A B C D
A B C D E
<37> VGA_VSSSENSE <37> VGA_VCCSENSE
Maximum Current: 28A(TDC)

load line:1m ohm
1
slew rate:50mV/uS
@ PRV28 @ PRV29
0_0402_5% 0_0402_5%
2
1 LL=1m ohm 1
1 2
DIS@ PCV87
270P_0402_50V7K
DIS@ PRV33 DIS@ PRV34
5
10K_0402_1% 200K_0402_1%
1 2 1 2 DIS@ PRV37
DIS@ PQV1
124K_0402_1% GPU_B+
1 2 @ PRV6 GPU_B+
DIS@ PCV88 DIS@ PCV89 0_0603_5% @ PJB8 +19.5VB
470P_0402_50V7K 68P_0402_50V8J VGA_UGATE1 1 2 4 1 2
1 2 1 2 1 2
+5VS
10U_0805_25V6K
10U_0805_25V6K
FSW=400kHz JUMP_43X79
DIS@ PCV2
DIS@ PCV3
1
1
@DISEMI@ PCV4
3
2
1
1
@DISEMI@ PCV91 2200P_0402_50V7K + DIS@ PCV1
0.1U_0402_25V6
VGA_BOOT2
VGA_UGATE2
100U_25V_NC_6.3X6
2
VGA_TONSET
VGA_ISEN1P
VGA_ISEN1N
VGA_ISEN2N
VGA_ISEN2P
2
+5VS VGA_PHASE1 2
VGA_COMP
VGA_FB
DIS@ PRV10 DIS@ PLV2
2.2_0603_1% 0.22UH_24A_20%_ 7X7X4_M
VGA_BOOT1 1 2 VGA_BOOT1-1
1 2 1 4 +VGA_CORE
@DISEMI@ PRV9
DIS@ PCV9 2 3
13
12
11
10
4.7_1206_5%
0.22U_0603_25V7K
1
DIS@ PQV20 DIS@ PRV44
COMP
FB
VSEN
ISEN3N
ISEN3P
ISEN1P
PWM3
BOOT2
UGATE2
ISEN1N
ISEN2N
ISEN2P
TONSET
AON6794_DFN5X6-8-5 3.4K_0603_1%
53 1 2 1 2
GND
+VGA_VDDIO is pull high at HW Side 14 52 VGA_PHASE2 VGA_LGATE1 4 DIS@ PCV96
2
RGND PHASE2 .1U_0402_16V7K
VGA_IMON 15 51 VGA_LGATE2 VGA_SNB_APU1
IMON LGATE2
680P_0603_50V7K
@DISEMI@ PCV12
<37> +VGA_VDDIO
VGA_VREF 16 50 VGA_PVCC
3
2
1
V064 PVCC
1
2
DIS@ PRV43 DIS@ PCV93 17 49 VGA_LGATE1
4.7K_0402_1% 2.2U_0603_10V7K IMONA LGATE1
2 2
1 2 18 48 VGA_PHASE1
VDDIO DIS@ PUV1 PHASE1
VGA_ISEN1N-1
2
<36> VGA_PWRGD 19 47 VGA_UGATE1

@ PRV45 0_0402_5% PWROK UGATE1 DIS@ VGA_ISEN1P
1 2 20 RT8880CGQW_WQFN52_6X6 46 VGA_BOOT1 PRV41 +5VS
<37> GPU_SVC SVC BOOT1 2.2_0402_1%
1 2 21 45 VGA_PVCC 1 2 DIS@ PRV53
<37> GPU_SVD SVD LGATEA1
@ PRV48 0_0402_5% 910_0402_1%
28.7K_0402_1%
<37> GPU_SVT 1 2 22 44 VGA_ISEN1N1 2

SVT PHASEA1
1
DIS@ PRV47
VGA_VCC 1 2
2.2U_0603_10V7K
@ PRV50 0_0402_5% 23 43
OFS UGATEA1
1
1
2.2U_0603_10V7K
@DIS@ PCV99 PRV42
1
+5VS
DIS@ PCV94
DIS@ PCV95
.1U_0402_16V7K 24 42 2.2_0603_5% @DIS@ PCV97
OFSA BOOTA1 DIS@ 0.1U_0402_25V6
2
2
VGA_SET1 25 41
2
SET1 PWMA2
VGA_SET2 26 40 Maximum Current: 28A(TDC)
DIS@ PRV51 SET2 TONSETA
PGOODA
ISENA2N
ISENA1N
ISENA2P
ISENA1P
PGOOD
4.87K_0402_1% load line:1m ohm
COMPA
VSENA
OCP_L
1 2
IBIAS
VCC
FBA
slew rate:50mV/uS
EN
1
1
DIS@ PRV55
APU_core
27
28
29
30
31
32
33
34
35
36
37
38
39
21.5K_0402_1% <10> GPU_PGD
DIS@ PHV2
<26,37> GPU_PROCHOT#
Peak Current 46.5A
VGA_IBIAS
100K_0402_1%_B25/50 4250K
VGA_VCC
FSW=400kHz
2
2
VGA_VREF
1 2
DCR 0.98mohm +/-5%
PHV2 is next to PLV2 Pull high at HW side +3VS GPU_B+ H/S Rds(on) :8.3mohm , 10mohm
VGA_VCC DIS@ PRV59
L/S Rds(on) :2.3mohm , 2.8mohm
1
+5VS 10K_0402_1% DIS@ PRV61

DIS@ PCV98 10K_0402_1%
5
DIS@ PCV103
10U_0805_25V6K
DIS@ PCV100
10U_0805_25V6K
0.47U_0402_6.3V6K DIS@ PRV60 1 2 +3VS
2
100K_0402_1%
DIS@ PQV21
2
2
1
1 2 DGPU_PWR_EN <10,26,38,55> @ PRV67
3 DIS@ PRV74 @DIS@ PRV78 0_0603_5% 3
DIS@ PRV73 1K_0402_1% 0_0402_5% VGA_UGATE2 1 2 4
2
11K_0402_1%
1 2 VRAM_PG <55>
1
@DIS@ PCV102
0.1U_0402_25V6
@ PRV79
3
2
1
0_0402_5%
2
DIS@ PRV71 DIS@ PRV72 VGA_PHASE2 DIS@ PLV3

64.9K_0402_1% 31.6K_0402_1% DIS@ PRV27 0.22UH_24A_20%_ 7X7X4_M
2
2.2_0603_1%
VGA_BOOT2 1 2 VGA_BOOT2-1 1 2 1 4
1
@DISEMI@ PRV70
VGA_SET1 VGA_SET2
+VGA_CORE
4.7_1206_5%
DIS@ PCV26 2 3
2
5
0.22U_0603_25V7K
1
DIS@ PRV75 DIS@ PRV76 DIS@ PQV22 DIS@ PRV69
8.66K_0402_1% 470_0402_1% AON6794_DFN5X6-8-5 3.4K_0603_1%
1 2 1 2
1
VGA_LGATE2 4 DIS@ PCV106

Vset1=5*2.8k/(1k+124k+2.8k)=110mV APU_core
2
VGA_SNB_APU2 .1U_0402_16V7K
TDC 31A(1H1L) *2phase
VGA_ISEN2N-1
1
680P_0603_50V7K
@DISEMI@ PCV107
OCP_TDC (Respect to OCP_ SPIKE): 60% Peak Current 46.5A VGA_ISEN2P
3
2
1
FSW=300kHz
2
DVID Compensation: 0 DCR 0.98mohm +/-5%
DIS@ PRV77
910_0402_1%
VGA_ISEN2N 1 2
RSET:100%
1
@DIS@ PCV108
DVID Boost Compensation:22.5mV 0.1U_0402_25V6
2
Vset2=5*470/(1K+31.6k+470)=71mV
4 4
QRTH (for VDD) :Disable
DVID Compensation : 0
NB OLL Setting :0
OCPTRGDELAY (for VDD/VDDNB) : 40ms Security Classification Compal Secret Data Compal Electronics, Inc.
A B
RepairLap.com C
D
Size
Date:
VGA_CORE(RT8880A)
Document Number

E
Sheet 56 of 60
Rev
v0.2
5 4 3 2 1
+VGA_CORE
1 1 1
+ DIS@ PCV51 + DIS@ PCV52 + DIS@ PCV53
560U_2.5V_M 560U_2.5V_M 560U_2.5V_M
D 2 2 2 D
+VGA_CORE
1
1
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
PCV54 PCV55 PCV56 PCV57 PCV58 PCV59 PCV60 PCV61
2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M
2
2
+VGA_CORE
1
1
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
C PCV62 PCV63 PCV64 PCV65 PCV66 PCV67 PCV68 PCV69 C
2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M
2
2
+VGA_CORE
560u X 3
1
1
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ 2.2u X 16
PCV70 PCV71 PCV72 PCV73 PCV74 PCV75 PCV76 PCV84
10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M
10u X 8
2
2
1u X 3
0.1u X 2
+VGA_CORE
B B
1
DIS@ DIS@ DIS@ @DIS@

PCV77 PCV78 PCV79 PCV80
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
2
+VGA_CORE +VGA_CORE
1
DIS@ DIS@ @DIS@ @DIS@

PCV81 PCV82 PCV83 PCV85
0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 22U_0603_6.3V6M
2
A A

VGA_CORE_CHIP DECOUPLING
5 4
RepairLap.com 3 2 1
5 4 3 2 1
AC
Adapter 19.5V
CPU DC/DC
P.45 RT8243AZQW NCP81206 52~54
INPUTS OUTPUTS
VCC_SA
B+ VCC_GT
VCC_VORE
D ECON D
EN +3VALW SYSTEM DC/DC

Vout +1.8V_PRIM RT8243AZQW
Vout Vin SY8032A 48
Charger +19.5VB INPUTS OUTPUTS
Charge PCH_PWR_EN
Vin PGOOD +1.8V_PG
BQ24725 EN
P.51
B+ +5VALW/+3VALW
SYSTEM DC/DC
DC/DC RT8207P / 8032 49
P.47
(+5VALW/+3VALW) INPUTS OUTPUTS
+3VALW +1.2V_VDDQ
Vout +2.5V B+ +2.5V
Vout Vin SY8032A +0.6V_0.6VS
SYSTEM DC/DC
DC
PM_SLP_S4# PGOOD +2.5V_PG SY8286
Discharge EN 50
Battery P.49
INPUTS OUTPUTS
3S1P PGOOD
4S1P P.48 B+ +1.0V_PRIM
P.46 SYSTEM DC/DC
SPOK SY8032A 51
INPUTS OUTPUTS
Vout +0.6V_0.6VS +3VALW +1.8V_PRIM
Vin DDR4 Vout +1.2V_VDDQ SYSTEM DC/DC
S5RT8027P PGOOD
C C
+2.5V_PG EN RT8880 56~57

DDR_PWROK
SM_PG_CTRL EN S3 P.49 INPUTS OUTPUTS
B+ +VGA_CORE
Vout +1.0V_PRIM SYSTEM DC/DC

SY8286 55
Vin +1.0V_PRIM
INPUTS OUTPUTS
+1.8V_PG SY8286 PGOOD +1.0V_VS_PG_PWR B+ +1.5VS_VGA
EN
P.50
Vout +VCC_CORE
Vin NCP81206 Vout +VCC_GT
B B
VR_ON DC/DC Vout +VCC_SA

VR_ON (CPU_CORE)
PGOOD VR_PWRGD
P.52,53
Vin RT8880 Vout +VGA_CORE

DC/DC
EN
(VGA_CORE)PGOOD GPU_PGD
DGPU_PWR_EN P.56
Vout +1.5VS_VGA
Vin SY8286
A
DC/DC A
EN
(VGA_RAM) PGOOD VRAM_PG
DGPU_PWR_EN
P.55
5 4 RepairLap.com 3 2 1
5 4 3 2 1
Item Page# Title Date Issue Solution

Request Owner Description Description Rev.
Change PR1115 and PR1125 Value 0 ohm to 1.07K ohm
1 52 Change Value 11/06 Power (Set VR prochot# from 110C to 120C)
Change from 5x5 choke to 7x7 Change PL602 part number from SH00000Z200 to SH00000YE00
2 50 Change part number 11/06 Power follow Candy design
D D
Change from 5x5 choke to 7x7 Change PLW1 part number from SH00000Z200 to SH00000YE00
3 55 Change part number 11/06 Power follow Candy design
+3VL and +VL add Jump

4 48 Add Jump 11/18 Power For easy debug
Delete PG pin test point VRAM_PG
For VGA CORE sequence and VID error issue Add Net VRAM_PG
5 55 Add Net 11/18 EE
SKL_SI pop to unpop For VGA CORE sequence and VID error issue
PRV61 from unpop to pop
6 56 11/18 EE PRV78 and PCV102 from pop to unpop
unpop to pop
Add Net and R Add Net VRAM_PG

7 56 11/18 For VGA CORE sequence and VID error issue Add PRV79
EE
Change jump to Delete jump PJB9
8 47 ISN choke 11/24 EMI ISN issue Add ISN choke PL201
EMI
Add Bead footprint PL7
9 48 colay bead 11/24 EMI EMI power noise issue
Add Bead footprint PL10

C
10 49 colay bead 11/24 EMI EMI power noise issue C
Delete jump PJB3

Change jump to Add Bead PL1207
11 50 Bead 11/24 EMI EMI power noise issue
Change jump to Delete jump PJB5
12 53 Bead 11/24 EMI power noise issue Add Bead PL1201 PL1202
EMI
13 55 colay bead 11/24 EMI power noise issue Add Bead footprint PL1208
EMI
EMI power noise issue Add Bead footprint PL1209 and PL1210
14 56 colay bead 11/24 EMI
Change R Value Change PRW5 value from 0 ohm to 22K ohm

15 55 Change C unpop to pop 11/24 HW f i ne t une VRA Mpo wer s equence Change PCW12 from unpop to pop
EE
(VGA sequence)
Change Common part Change PC1331 PC1383 PC1390 from SGA20331E10 to SGA00009S00
16 53 11/6 Power (Change to Common part)
B B
SKL_PV
A A
Title
Power_PIR(SI)
RepairLap.com
C LA-D707P v0.2
5 4 3 2 1
5 4 3 2 1
P. I. R.
List
D
KBL_SI D
KBL_PV
C C
B B
A A
Title
Power_PIR(PV)

C LA-D707P v0.2
5 4 RepairLap.com
3 2
Date: Wednesday, May 11, 2016 Sheet
1
60 of 60

Compal Cdl50 La-D707p Rev 0.2

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Compal Cdl50 La-D707p Rev 0.2

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B C D E

Model Name : BDL50

Kabylake-U M/B Schematics Document

Project : Diner_Crepe1.1(15") (PV phase)

Security Classification Compal Secret Data Compal Electronics, Inc.

Dual Channel Interleaved

Port 7 Card reader

SLB9665TT2.0 Combo Jack

NCT7718W P.10 SPI ROM

Power rail Control (EC) Source (CPU)

+3V_PCH PCH_PWR_EN X EC TBC TBC TBC Thermal 0x4C

RO0000003HM S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF

2 USB 2.0/3.0 USB 2.0/3.0

[Diner-PWR Sequence_SKL-U22_DDR3L_Volume_NON CS]

G3->S0 S0->S3/DS3 S0/ DS3 ->S0 S0->S5

PCH_PWR_EN (SLP_SUS#) PCH_PWR_EN (SLP_SUS#)

EXT_PWR_GATE# If EXT_PWR_GATE# Toffmin is too small, Pwr EXT_PWR_GATE#

Security Classification Compal Secret Data Compal Electronics, Inc.

<22> PCH_DPC_N0 C50 E45

A7 GPP_E3/CPU_GP0 PCH_JTAG_TDI A56 SOC_XDP_TDO TP@ T265

RC11 2 @ 1 51_0402_5% SOC_XDP_TMS

RC13 2 @ 1 51_0402_5% SOC_XDP_TDI

RC15 2 1 51 +-1% 0402 SOC_XDP_TDO SD000008H80

RC364 2 @ 1 51_0402_5% CPU_XDP_TCK0

RC14 2 @ 1 51_0402_5% XDP_PREQ# XDP_PREQ# <11>

RC31 1 @ 2 1K_0402_5% XDP_ITP_PMODE XDP_ITP_PMODE <16>

4 RC365 2 @ 1 51_0402_1% SOC_XDP_TRST# 4

RC35 2 1 51_0402_1% CPU_XDP_TCK0 SD000008H80

RC37 2 @ 1 51_0402_5% PCH_JTAG_TCK1

RC366 1 @ 2 0_0402_5% CFG3 CFG3 <16> Security Classification

Interleaved Memory Interleaved Memory

RC904 0.1U_0201_10V6K 2 1 CC57

PLACE NEAR TO SoC

Security Classification Compal Secret Data Compal Electronics, Inc.

SML0ALERT# (Internal Pull Down):

to SPI ROM UC2 Source From

PCH_SPI_SO_R 2 7 PCH_SPI_HOLD# 2N7002DWH_SOT363-6 1K_0804_8P4R_5%

EON SA000046400 S IC FL 64M EN25Q64-104HIP SOP 8P SERIRQ 1 2

HDA for AUDIO

B31 CSI2_DN6 AP2

RC91 1 2 20K_0402_5% PCH_SRTCRST#

CLRP1 1 2 SHORT PADS CLR ME UC1J SKL_ULT

B40 RTCX1 AM20 PCH_RTCX2

+3VS YC1 SJ10000IZ00 YC2

CK0402101V05_0402-2 <DB> add ESD protection

CK0402101V05_0402-2 DC3 SCS00003500

<26> PCH_DPWROK 2 1 PCH_DPWROK_R

RC1161 2 60.4_0402_1% EC_VCCST_PG

UC1F SKL-U +3VS

1105_Modify schematic NCT7718W_MSOP8

0 = Disable No Reboot mode. --> AAX05 Use

1 = Enable No Reboot Mode. (PCH will disable the TCO

Boot BIOS Strap Bit

0 = SPI Mode --> AAX05 Use

Security Classification Compal Secret Data Compal Electronics, Inc.

1 1 Imax : 2.77 A CC89 1 2 0.1U_0402_25V6

<PV> change short pad

+1.0V_PRIM K15 BB10 CC71 1 2 0.1U_0402_10V7K

near pin AF18, 2

RC175 1 2 0_0402_5% 1 15mils 2 2 1

I (Max) : 0.46 A(+3V_PRIM)+3VALW +3V_PRIM

Security Classification Compal Secret Data Compal Electronics, Inc.

+VCC_CORE +VCC_CORE +VCC_GT +VCC_GT