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  • 070 - Rohit Kumar Jashwara - ECE-491 - EXP

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    This document summarizes an experiment measuring the lock range and capture range of a phase-locked loop (PLL) circuit using a multisim simulation. The PLL circuit contains a phase detector, low-pass filter, and voltage-controlled oscillator (VCO). By adjusting the VCO frequency to match the reference input frequency, the PLL is able to lock and maintain a constant phase relationship between the signals. The experiment aims to determine the range of frequency differences over which the PLL can lock by observing the output phase as the input frequency is varied.

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    070_Rohit kumar jashwara_ECE-491_EXP(4)

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    This document summarizes an experiment measuring the lock range and capture range of a phase-locked loop (PLL) circuit using a multisim simulation. The PLL circuit contains a phase detector, low-pass filter, and voltage-controlled oscillator (VCO). By adjusting the VCO frequency to match the reference input frequency, the PLL is able to lock and maintain a constant phase relationship between the signals. The experiment aims to determine the range of frequency differences over which the PLL can lock by observing the output phase as the input frequency is varied.

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    © All Rights Reserved
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    7 views6 pages

    070 - Rohit Kumar Jashwara - ECE-491 - EXP

    Uploaded by

    rohit
    This document summarizes an experiment measuring the lock range and capture range of a phase-locked loop (PLL) circuit using a multisim simulation. The PLL circuit contains a phase detector, low-pass filter, and voltage-controlled oscillator (VCO). By adjusting the VCO frequency to match the reference input frequency, the PLL is able to lock and maintain a constant phase relationship between the signals. The experiment aims to determine the range of frequency differences over which the PLL can lock by observing the output phase as the input frequency is varied.

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    © All Rights Reserved
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    of 6

    ANALOG COMUNICATION LAB

    (EC-491)

    WAME Rot kunan Torshudona

    BRANCH ECE
    YEAR 2o eom
    SEM 4t sem

    BATCH B
    Roil No Lo eoo %490Ho
    ExPERIMENT 4
    MEASUREMENT OFLOck RANGF
    CAPTURE RANJEUSING
    PHASE_LOckE toop
    Aiu Desan Vco a d eantune
    the leck equeny

    APpanatus Requied:
    CRO
    Pooer Cuppy
    I C 565
    Ree tofe, CapOlit e tue
    Thee
    A pu te a clat ed eep t e Lstese
    puLpoRe te to leek a Ocitate 0nto aA
    puovided tuput fu equeny. Ay cloRRdt reans
    tho4 tee ee eec bqek 4uom uput to
    eufpe
    Jn PL negatHue fhoguon y
    ,
    ?uoecd ich
    mak e 4 Co Contanng . Vco charge
    output fyoquorn cy baed on
    tuput vottage.
    J
    The put uno ofyeecttue PL openaion e
    to 2et he Vco oquenyto be eoacty equal
    t o a t othe RtouonceAaquon
    hen ttig koppene the loop te lad to be n
    LbckeThis
    Thic Peachieva.d b feedPug bbth tte
    Vco Output o d tLe
    yefeuehCe quenCy iuto
    hae dtoct The
    Pkase deter+e Coupayes
    .

    e e phase othe tu9o salls od outpu


    t

    pulsattg
    putsattg De 9avefeun e?th a u yele
    Aepeutforal t0 the phase iHeunce (ee)
    bettoeon two ignaA.

    The ue
    P Phase dleteeR-oy yeduce tte fLeq uen}
    eqees othe closed Leep yaeu to zoLO
    TeOutput te ptose cleteet6 fe apuo
    CLe7 th a
    Vayg duty cyele The gge tte
    e plase iHeuence becoe tte Cagen o
    Cele 9ets But Veo neocd gtofe e voutag e

    at 4 contuet vettoge tuput


    B loek Bfa9uam

    Jnput Ve Phose LOW


    pose
    gnal DerertOL AuppLihio 0upL
    14rte
    A

    Vco
    Cty ei+ Dfagsam

    dlc co
    Outpuf
    TC

    565
    Pyecauttons

    *Cheek feu looe Coutou Sfyes.


    *keee al kndLd n
    ninimum Pocitio.
    * Adjuuxt ContHef kndb Smbttly
    Beteuo Le tehBug o r tLe peen Suppy
    Venty the onneioM

    ConeLUston

    The behavou o PLL tudied ono

    Vefi ed tu
    uee qunnfug ge i Les-ec sage

    Cune CoptuHe ange.


    CIRCUIT DIAGRAM USING MULTISIM

    XSC1

    Ext Trig
    +
    _
    A B
    + _ + _

    A1
    PLL
    PLLin VCOout R3
    PDin PDout
    V1 LPFout
    1kΩ
    1mVpk
    1kHz PLL_VIRTUAL R4
    0° 10kΩ

    C1
    100nF

    OUTPUT

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