Energy Sources, Part A: Recovery, Utilization, and

Environmental Effects

ISSN: 1556-7036 (Print) 1556-7230 (Online) Journal homepage: https://www.tandfonline.com/loi/ueso20

High step-up interleaved dc/dc converter with high

efficiency

Haixiong Ye, Guangzhe Jin, Wang Fei & Noradin Ghadimi

To cite this article: Haixiong Ye, Guangzhe Jin, Wang Fei & Noradin Ghadimi (2020): High step-up
interleaved dc/dc converter with high efficiency, Energy Sources, Part A: Recovery, Utilization, and
Environmental Effects, DOI: 10.1080/15567036.2020.1716111

To link to this article: https://doi.org/10.1080/15567036.2020.1716111

Published online: 23 Jan 2020.

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ENERGY SOURCES, PART A: RECOVERY, UTILIZATION, AND ENVIRONMENTAL EFFECTS
https://doi.org/10.1080/15567036.2020.1716111

High step-up interleaved dc/dc converter with high efficiency

Haixiong Yea,b, Guangzhe Jina, Wang Feic, and Noradin Ghadimi d

a
Engineering Science and Technology College, Shanghai Ocean University, Shanghai, China; bElectronic and
Information Engineering College, Tongji University, Shanghai, China; cSuzhou JiuYu Intelligence Technology Co., LTD,
Changshu, China; dYoung Researchers and Elite Club, Ardabil Branch, Islamic Azad University, Ardabil, Iran

ABSTRACT ARTICLE HISTORY

In this paper, a new non-isolated Interleaved dc/dc converter with high- Received 13 July 2019
voltage conversion ratio is presented. The proposed converter combined Revised 14 October 2019
with interleaved converter techniques and voltage multiplier cell (diode/ Accepted 19 December 2019
capacitor/inductor). The voltage stress across the power semiconductors
KEYWORDS
(power MOSFETs/diodes) is decreased compared to SEPIC, conventional Non-isolated; dc/dc
boost converter. The low normalized stress causes to using the low rating converter; interleaved; high-
semiconductors. In fact, the overall efficiency of the proposed converter will voltage gain; low-voltage
be increased by using MOSFETs with lower resistance RDS(on) and lower stress
ranges for power diodes. To confirm the accuracy theoretical analysis of the
proposed converter and operation converter, a laboratory prototype in
about 190 W with operating at 40 kHz is built and tested.

Introduction
Nowadays, renewable sources and green power generation technology are gaining more and more
attention due to the serious problems of global warming, exhaust fossil fuels and the increasing need
to energy for the advanced government (Maalandish et al. 2018; Revathi and Mahalingam 2018;
Spiazzi et al. 2019). Since the output voltage of the renewable sources is low, so dc-dc high-voltage
gain should be used between the renewable sources and grid (Aghajani and Ghadimi 2018; Zhu, Ren,
and Wu 2017). The high-voltage gain dc-dc converter can be obtained with different ways, such as
using voltage multiplier units (switched capacitor/switched inductor), charge pump circuits, coupled
inductor method, voltage lift and etc. (Liu, Wang, and Ghadimi 2017). Hence, high-voltage gain dc-
dc converter with high-efficiency in one of the major steps to be addressed until can be increased the
voltage level and overall efficiency of the system (Gollou and Ghadimi 2017). Therefore, the design
of dc-dc converters in renewable energy sources helpful to pay attention to the voltage level, input
current ripple, the normalized voltage stress across semiconductors (power diode and power
MOSFET), overall cost, efficiency, power level, and converter volume (Hosseini Firouz and
Ghadimi 2016; Mirzapour et al. 2019). High-voltage gain dc-dc converters with interleaved techni-
ques capable to decrease the tolerances of the input current, significantly so that it is suitable for
renewable application such as it is easy to achieve more accurate measurements current of the PV
panel at the maximum power point (MPP) (Hamian et al. 2018). In addition, utilization of voltage
multiplier units, coupled inductor techniques and/or adding the snubber circuits probably causes to
increase the voltage gain and decrease the normalized voltage stress across the power semiconduc-
tors (power diode and power switch) (Cao et al. 2017; Schmitz, Martins, and Coelho 2017). In this
situation, due to decreased switches/diode maximum voltage stress, using low rating power compo-
nent (lower nominal value) causes to decrease the cost of the converter and also using lower RDS(on)
leads to reduce the conduction losses and increase the overall efficiency (Hosseinzadeh, Molavi, and

CONTACT Noradin Ghadimi ghadimi.nooradin@gmail.com; Haixiong Ye wlwangl2017@163.com Engineering Science

and Technology College, Shanghai Ocean University, Shanghai, 201306, China
© 2020 Taylor & Francis Group, LLC
2 H. YE ET AL.

Farzanehfard 2018). In addition, hard switching/soft switching performance and reverse-recovery of

the power switches antiparallel diodes, switching losses and EMI problems of the dc-dc converters
are other issues that can be investigated (Lee, Kim, and Choi 2013). The voltage gain of the dc-dc
converters can be increased significantly by introducing a coupled inductor techniques, nevertheless,
the leakage inductance leads to increase in the off-state maximum voltage across the power switch.
Various passive or active auxiliary circuits have been proposed to absorb the energy which is stored
in the leakage inductance (Hu and Gong 2014; Zhou et al. 2013). However, to decrease the spike of
the voltage stress on the power switch and increase the efficiency of the converter, supplementary
circuits should be added which these results increase the number of components and cost. With this
condition, conductive losses will be an important issue that will require more attention to pay
(Banaei and Sani 2018; Pourjafar et al. 2018). An active clamped high-voltage gain dc–dc converter
for high step-up applications is presented so that the existence active clamping circuit capable to
create ZVS turn-on of the power MOSFETs and ZCS turn-off of the power diodes as well as clamp
the maximum voltage which is produced by parasitic inductance (Lee, Kim, and Choi 2013). In
(Martinez et al. 2018) a dc-dc converter for HEVs applications is presented. HEVs have been using
conventional boost step-up topologies for some times, such as single-phase dc-dc boost converters
and some interleaved techniques of dc-dc boost converters with coupled inductors which uses
magnetic coupling techniques to decrease the volume and input current ripple. However, this
structure has some problems such as work in high duty cycle value, conductive losses, high normal-
ized voltage stress across power MOSFET and power diode. In (Farakhor, Abapour, and Sabahi
2018) a DC–DC converter with high-voltage gain and continuous input current is presented for
renewable applications. The main advantages of the converter consist of the high-voltage gain, low-
ripple input current, low-voltage stress across the main power MOSFET and high efficiency. As
a result, it is very suitable for sustainable energy sources. Voltage multiplier units are used to boost
the output voltage level. However, the losses of the power semiconductors and conductive losses are
one of the important issues which should be paying attention to them.
In this study, presents a new high step-up interleaved dc-dc converter for renewable applications.
The proposed converter based on combination of the voltage multiplier units and interleaved
techniques, also consist of low input current ripple which capable to obtain high-voltage gain and
high power level. In addition, the normalized voltage stress across the power MOSFETs and power
diodes is low due to the utilization of voltage multiplier units which this leads to the voltage of power
semiconductors clamp to capacitors of voltage multiplier units. As a result, using the power
MOSFETs and power diodes with low rating (low current/voltage) causes to decrease the total
power losses of the system. Also, using a power MOSFET with lower on state resistance Rds(on) leads
to decrease the cost and increase the efficiency of the converter. The experimental results are
provided in section 6 to confirm the accuracy of the theoretical analysis and operation of the
proposed converter.

Proposed structure and analysis of the operation modes

The schematic of the proposed converter is shown in Figure 1. The proposed converter is a non-
isolated high step-up interleaved dc/dc converter which consists of the input dc power supply and
two switches in each phase. Based on interleaved techniques and the combination of diode and
capacitor, the proposed converter have a high-voltage gain and low input current ripple. To simplify
the operation analysis of proposed converter at CCM and DCM operations, the below assumptions
are considered:

● The value of the input power supply is constant,

● All used elements of the proposed converter are ideal,
● All capacitors of the proposed converter are large enough, so the voltage of all capacitors
considered constant values in one switching period.
 ENERGY SOURCES, PART A: RECOVERY, UTILIZATION, AND ENVIRONMENTAL EFFECTS 3

Figure 1. The proposed structure.

Generally, in order to one switching period of the proposed converter (Ts) for each switch can be
considered two- time interval. In the first time interval (DTs), the switch is on-state and the second time
interval ((1-D)Ts), the switch is off-state. D is duty-cycle and Ts is a period of the proposed converter.

CCM (continuous conduction mode) operation

All equivalent circuits’ modes of the proposed converter at CCM operation are shown in Figure 2.
There is 4-modes in CCM operation. In CCM operation, switches S1 and S2 are on-state simulta-
neously. Generally, all equations are written for theoretical analysis of the proposed converter in
modes 1–4.
Mode 1 [t0
t
t1 ]
In this mode, the power switches S1 and S2 are turned-on and all power diodes are in reverse biased
condition expect the diodes D3. and D33. All inductors (L1, L2, L11, L22) are charged by the input
power supply (Vi). The current of all inductors is linearly increased. Requirement equations for
analysis of the proposed converter in this mode are written as follows:
VL1 ¼ VL11 ¼ Vi (1)

VL2 ¼ Vi þ VC1  VC2 þ VC3 (2)

4 H. YE ET AL.

Figure 2. The equivalent circuit of the proposed converter at CCM operation. (a) Mode 1, (b) Mode 1, (c) Mode 1, (d) Mode 1

VL22 ¼ Vi þ VC11  VC22 þ VC33 (3)

VD1 ¼ Vi  VC1 (4)

VD2 ¼ VC3 (5)

VD3 ¼ VD33 ¼ 0 (6)

VD4 ¼ VC2  Vi  Vo1 (7)

VD11 ¼ Vi  VC11 (8)

VD22 ¼ VC33 (9)

VD44 ¼ VC22  Vi  Vo2 (10)

Mode 2 [t1
t
t2 ]
In this mode, the power switch S1 and S2 remain turn-on and all diodes are in reverse biased
condition. The inductors L1 and L11 are charged by the input power supply (Vi) and the inductors L2
and L22 are charged by the charge stored in capacitors C1 and C11, respectively. By observing Figure
2b, the following equations are written as:
 ENERGY SOURCES, PART A: RECOVERY, UTILIZATION, AND ENVIRONMENTAL EFFECTS 5

VL1 ¼ VL11 ¼ Vi (11)

Mode3 [t2
t
t3 ]
In this mode, the power switch S1 and S2 remain turn-on and all diodes are in reverse biased condition
expect the diodes D2 and D22. The inductors L1 and L2 are charged by the input power supply (Vi). In
this mode like mode 2, Inductors L2 and L22 are charged by the charge stored in capacitors C2 and C22,
respectively. The charge stored in Co is discharged to load R. Using Figure 2c, the following equations
can be written as:
VL1 ¼ VL11 ¼ Vi (12)

VL2 ¼ Vi þ VC1  VC2 (13)

VL22 ¼ Vi þ VC11  VC22 (14)

VD2 ¼ VD22 ¼ 0 (15)

VD3 ¼ VC3 (16)

VD4 ¼ VC2 þ VC3  Vi  Vo1 (17)

VD33 ¼ VC33 (18)

VD44 ¼ VC22 þ VC33  Vi  Vo2 (19)
Mode 4 [t3
t
t4 ]
In this mode, the power switches S1 and S2 are turned-off and all diodes are in forward biased
expect the diodes D2 and D22. The stored energy in inductors L1 and L11 is discharged to the output
side. The stored energy in inductor L2 is discharged to the capacitors C1 and C3 which this item also
applies to inductor L22 and capacitors C11 and C33. By observing Figure 2d, can be written as
follows:
VL1 ¼ VC1 (20)

VL2 ¼ VC3  VC2 (21)

VL11 ¼ VC11 (22)

VL22 ¼ VC33  VC22 (23)

VS1 ¼ VC1 þ Vi (24)

VS11 ¼ VC11 þ Vi (25)
By applying the volt-second balancing law on the inductors in CCM operation (since the average
voltage is zero for each inductor in one period), the voltage of capacitors can be obtained as
(26)–(29).
DVi
VC1 ¼ VC2 ¼ VC3 ¼ (26)
1D
DVi
VC11 ¼ VC22 ¼ VC33 ¼ (27)
1D
2DVi
VCo1 ¼ VC1 þ VC2 ¼ (28)
1D
6 H. YE ET AL.

2DVi
VCo2 ¼ VC11 þ VC22 ¼ (29)
1D
Vo 1 þ 3D
MCCM ¼ ¼ (30)
Vi 1D
Using (26)–(30), can be written as follows:
Vo  Vi
D¼ (31)
Vo þ 3Vi
ðVo  Vi Þ
VC1 ¼ VC2 ¼ (32)
4
ðVo  Vi Þ
VCo1 ¼ VCo2 ¼ (33)
2
In addition, the relationship between the output current Io and input current Iin can be written as:
Iin 1 þ 3D
¼ (34)
Io 1D
Figure 3 illustrates the main waveforms of the proposed converter in CCM operation.

DCM (discontinuous conduction mode) operation

DCM operation of the proposed converter has three modes which modes 1 and 2 are similar to
modes 3 and 4 at CCM operation, respectively. Figure 4a illustrates the Equivalent circuit at DCM
operation (mode 3).

Mode 3 [t2
t
t3 ]
In this mode, the power switches S1 and S11 are turned-off and all diodes are in reverse bias. In this
mode, the stored voltage at the output capacitor (Co) is discharged to the output load (R). Based on
Figure 4a, the following equation can be written as:
VL1 ¼ VL2 ¼ VL11 ¼ VL22 ¼ 0 (35)
By applying the volt-second balancing law on the inductors L1 and L2 in DCM operation, can be
written as follows:
DVi þ D0 ðVC1 Þ ¼ 0 (36)
0
DðVC1 þ Vi  VC2 Þ þ D ðVC3  VC2 Þ ¼ 0 (37)
’
Using (31)–(36), D can be achieved as:
4DVi
D0 ¼ (38)
Vo  Vi
Since the average current of each capacitor is zero in one period, therefore, the average current of the
diodes D1, D2, D3, D4, D11, D22, D33, D44 and inductors L1, L2, L11, L22 can be expressed by:
ID1;2;3;4;11;22;33;44 ¼ Io (39)

1þD
IL1;11 ¼ Io (40)
1D
IL2;22 ¼ Io (41)
 ENERGY SOURCES, PART A: RECOVERY, UTILIZATION, AND ENVIRONMENTAL EFFECTS 7

Figure 3. The main waveforms of the proposed converter in CCM operation.

8 H. YE ET AL.

Figure 4. DCM operation analysis, (a) The power circuit of the proposed converter at DCM operation (Mode 3), (b) The main
waveforms of the proposed converter in CCM operation (c) Boundary condition of the proposed converter.

Based on mode 2 in DCM operation which is shown in Figure 2d, the current of diodes D1, D3, D4,
D11, D22, D44 will be zero before the power switch off-time is over.


IL1 þ IL2 þ IL11 þ IL22 ¼ 12 D0  I 0
(42)
¼ ID1 þ ID3 þ ID4 þ ID11 þ ID33 þ ID44
where I’ is the sum of the maximum current of the inductors L1, L2, L11, L22.
(
I 0 ¼ fDV i
s Ltot
(43)
Ltot ¼ L11 þ L12 þ L111 þ L122

Using (38)–(43), can be written as follows:

1 0 DVi 1þD
D  ¼ ð2 þ ÞIo (44)
2 fs Ltot 1D

1 4DVi DVi 1 þ D Vo
  ¼ ð2 þ Þ (45)
2 Vo  Vi fs Ltot 1D R

ð3  DÞfs Ltot Vo 2 þ ðD  3Þfs Ltot Vo Vi þ ð2D3 R  2D2 RÞVi 2 ¼ 0 (46)

Based on (46), the voltage gain of the proposed converter in DCM operation is obtained as:
 ENERGY SOURCES, PART A: RECOVERY, UTILIZATION, AND ENVIRONMENTAL EFFECTS 9

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2
ffi
ð2DÞ fs Ltot þ2RD2 ð1DÞ
2Dþ fs Ltot
MDCM ¼ (47)
2
During boundary conduction mode, the voltage gain of the proposed converter in CCM mode is
equal to DCM mode. Using (30) and (47), τ B can be obtained as:
Dð2  DÞð1  DÞ
τB ¼ (48)
2
Figure 4c illustrates the relationship between τ B and D. The proposed converter operates in CCM
mode, if τ  τ B otherwise, it will operate in DCM mode.

Analysis of the voltage/current stress across power MOSFETs and diodes, the
efficiency of proposed converter and inductor/capacitor design
The voltage/current stress on power switch
Using (24), (27), (34), (39)–(41), the voltage/current stress across the power switches of the proposed
converter can be expressed as
2D
IS ¼ Io (49)
1D
Also, the normalized voltage stress across the power switches versus difference voltage gain can be
obtained as:
Mþ3
MS1;11 ¼ (50)
4M
The normalized voltage stress across the power diodes versus difference voltage gain can be
obtained as:
M1
MDiodes ¼ (51)
4M

Inductor selection
If the peak-to-peak inductor current ripple is considered ΔIL. Using Figures 1 and 3, it can be
concluded that ΔIL= ri%IL, the following equation can be written for inductor selection:
( 2
L1 ¼ L11 ¼ rDV i
1 %Pi
T
Dð1DÞRVi 2 (52)
L2 ¼ L22 ¼ r2 %IL2 ½RPi ð1DÞ2Vi 2  T

Selection and calculation of the voltage ripple of the output capacitor

If the voltage ripple on the output capacitor considered by ΔVCo which is created from the current flows
(ΔICo) through the ESR (equivalent series resistant) and from the charging/discharging state (ΔVCo,cap),
therefore, ΔVCo,ESR and ΔVCo,cap can be expressed by:


ΔVCo;ESR ¼ ESRCo  ΔICo ¼ ESRCo  ðICo;off  ICo;on Þ
(53)
δCo ¼ arctanðωs  ESRCo Þ
ICo;on  DTs Vo  DTs
ΔVCo;cap ¼ ¼ (54)
Co R  Co
10 H. YE ET AL.

Figure 5. The current and voltage ripple of the output capacitor Co.

Using (53) and (54), the voltage ripple of the output capacitor is sum of the ΔVCo,ESR and ΔVCo,cap
which is shown in Figure 5. ΔVCo,ESR and ΔVCo,c can be obtained as:
(
ΔVCo ¼ ΔVCo;ESR þ ΔVCo;cap
Co Þ o DTs
(55)
¼ tanðδ
ωs  ðICo;off  ICo;on Þ þ VRC o

Calculation of the efficiency of the proposed converter

For calculation the efficiency of the proposed converter (ηConverter ), the parasitic resistance of power
components is defined as:

● rDS-on: on-state resistance of the power switches,

● rL1, rL2, rL11, rL22: the equivalent series resistance (ESR) of inductors L1, L2, L11, L22 respectively,
● rD: are the equivalent series resistance of all diodes,
● rC: the equivalent series resistance of all capacitors.

Therefore, the efficiency of the proposed converter can be obtained as:

Po Po
ηConverter ¼  100% ¼  100% (56)
Pin Po þ Plosses
The power loss of the power MOSFET (S) can be expressed by:
 ENERGY SOURCES, PART A: RECOVERY, UTILIZATION, AND ENVIRONMENTAL EFFECTS 11

(
PrDSON ¼ 4  rDSON  ISðrmsÞ 2
D2 Io 2 (57)
¼ 4rDSON
ð1DÞ2

Generally, the total power losses of the power MOSFET are the sum of the power loss of the power
MOSFET (when the power MOSFET is on-state) and switching losses. Hence, the power loss of each
power MOSFET (PMOSFET) can be calculated as
8
< PMOSFET ¼ PrDSON þ 22PSwitching
> 1

¼ ðrDSON  ISðrmsÞ Þ þ 12 ðCS VS 2  fS Þ (58)

>
: ¼ 4rDSON D2 2 Io 2 þ 1 CS ð Vi Þ2 fS
ð1DÞ 2 1D

The average current of the inductors is calculated in Equations (40) and (41). Therefore, the
Conduction losses of the inductors can be expressed by:
8
> rL1 ¼ rL11 ¼ rL1 ¼ rL11 ¼ rL
>
< PL ;L ;L ;L ¼ rL  IL 2 þ rL  IL 2
1 2 11 22 1 1ðrmsÞ 2 2ðrmsÞ

þr  þ (59)
L22  IL22ðrmsÞ
2 2
>
> L11 IL11ðrmsÞ r
: 1þD 2
¼ 2  rL 1D Io þ 2  rL  Io 2
The forward resistance losses (PRFðDiodesÞ ) and voltage losses (PVFðDiodesÞ ) of the diodes can be obtained as:

PLossesD1 ;D2 ;:::;D44 ¼ PRFD1 ;D2 ;:::;D44 þ PVFD1 ;D2 ;:::;D44 (60)
8
>
<P P
8
rFD ¼ ðrFDk IFDkðrmsÞ 2 Þ
1 ;D2 ;:::;D44 (61)
k¼1
>
: Io 2
¼ 6  ð1D Þ rFDk þ 2  ðIo Þ2 rFDk

Io Vi Vi
PVFD1 ;D2 ;:::;D44 ¼ 6  ð Þð Þ þ 2  Io ð Þ (62)
1D 1D 1D
The power losses of the capacitors can be obtained as:
8
< PRCapacitors ¼ rc  IrCoðrmsÞ þ 2rc  IrC1ðrmsÞ
2 2
>
þ2rc  IRC2ðrmsÞ þ 2rc  IrC3ðrmsÞ
2 2
(63)
>
: þ2r  I 2
c rCo1ðrmsÞ

Using (56)–(63), the overall efficiency of the proposed converter can be obtained as:
8
> ηConverter ¼ Po þPPo
 100%
>
> losses
>
> P ¼ a þ a þ a3 þ a4 þ a5 þ a6
>
>
losses 1 2
> a1 ¼ 4rDSON D2 Io þ 12 CS ð1D
2 2
Vi 2
>
> ð1DÞ
Þ fS
< 1þD 2
a2 ¼ 2  rL 1D Io þ 2  rL  Io 2 (64)
>
> Io 2 2
> a3 ¼ 6  ð1DÞ rFDk þ 2  ðIo Þ rFDk
>
>
>
> a4 ¼ rc  IrCoðrmsÞ þ 2rrC  IrC1ðrmsÞ 2 þ 2rrC  IrC2ðrmsÞ 2
2
>
>
>
:
þ2rc  IRC3ðrmsÞ 2 þ 2rc  IrCo1ðrmsÞ 2

where a1, a2, a3 and a4 are defined as:

a1 ! total power losses of the power MOSFETs,
a2 ! the conduction losses of the inductors,
a3 ! the forward voltage and voltage drop losses of the power diodes,
a4 ! the capacitors power losses.
12 H. YE ET AL.

Dynamic response of control method

In order to analyze the dynamic response of the control method of the proposed converter, the state-
space averaging (SSA) model has utilized to produce an average model based on the performance of the
proposed converter. Based on the operation of the proposed converter which is shown in Figure 2, can be
obtained to all state equations. For easy access to the state space model and all equations, some
assumptions are considered for the proposed converter as follows:

● All power MOSFETs and power diodes are ideal

● The input voltage source value is constant
● All inductors value are equal to each other L1 = L2 = L11 = L22 = L with parasitic series resistors
rL
● All capacitors value is equal to each other C1 = C2 = … = C22 = C33 = Co1 = Co2 = Co = C with
parasitic series resistors rC.

If the equation of the state space averaging model is defined as Equation (65); therefore, vector u is
equal to Vi (input voltage source) and matrix x will be defined as Equation (66). The response of this
method is the output voltage Vo.

x0 ¼ A1 x þ B1 u (65)

In addition, there are 13 state variables for the proposed converter. Matrix x will have 13 variables
which consist of inductors and capacitors that are defined as follows:

x ¼ ½iL1 iL11 iL2 iL22 VC1 VC2 VC3 VC11 VC22 VC33 VCo1 VCo2 VCo T (66)

Dynamic response of the proposed structure is investigated based on the small-signal frequency
response. For simplicity analysis of the proposed structure for observing the performance with the
dynamic variations, all inductors are considered equal to each other and all capacitors are the same.
Figure 6b illustrates the magnitude (dB) and frequency response of the proposed converter. The
block diagram of the closed-loop control system is shown in Figure 6a. The simple and common
controller PI is used to control the converter. Based on the designed control for the proposed
converter, the comparison between the output voltage and a desired value of the output value as
a reference voltage (Vo,ref) is considered. When there is a difference between the output values and
reference voltage, the duty cycle value will be controlled by the controller. PI controller has a gain
and the time constant which these values of the PI controller are achieved by a trade-off method.

Figure 6. Control and dynamic response of the proposed converter (a) Closed-loop step response of the proposed converter by
controlling the duty cycle values (b) Bode diagram for magnitude and phase versus switching frequency.
 ENERGY SOURCES, PART A: RECOVERY, UTILIZATION, AND ENVIRONMENTAL EFFECTS 13

Comparison study
In this section, the proposed converter is compared with other converters in terms of voltage gain,
normalized voltage/current stress across semiconductors (MOSFET/diode), number of devices and
efficiency which is shown in Table 1. Any high step-up converter that has low normalized voltage
stress across the semiconductor can be said that the converter capable to transfer power to a wide level.
The total number of devices has an impact on the overall cost of the converter. For decreasing the cost
of using devices in converters, designs should be such that the nominal values (nominal current/
nominal voltage) became lower. The power loss and overall cost will be large for a large number of
device converters with high nominal values on the devices. Generally, the overall efficiency of the
proposed converter is higher compared to other structures which are highlighted in Table 1.

The voltage conversion ratio versus duty-cycle

Figure 7a shows the voltage gain curve based on duty-cycle variations. The voltage gain of the
proposed converter is higher than the other structures (Banaei and Sani 2018; Pourjafar et al. 2018).
Generally, a larger duty-cycle value is required for obtaining a high-voltage gain in some famous
converters, for example, the conventional boost converter, conventional SEPIC, conventional inter-
leaved without voltage multiplier cell, etc. Therefore, the overall efficiency of these converters will be
reduced in rather high duty-cycle values. However, the voltage gain of the proposed converter is high
even in low quantities duty-cycle.

The normalized voltage stress across power MOSFET

Figure 7b shows the curve of the normalized voltage stress across power MOSFET versus duty-cycles
variations. The maximum voltage of the power MOSFETs of the proposed converter is limited to
0.25 when the voltage gain is increased. With regarding Figure 7b, it is clear that the normalized
voltage stress across power MOSFET of the proposed converter is lower than the other structures
(Banaei, Ardi, and Farakhor 2014; Ismail et al. 2008; Sabzali, Ismail, and Behbehani 2015) except
(Axelrod, Beck, and Berkovich 2015). Generally, using a MOSFET with low resistant on-state leads
to decrease the power loss of the power MOSFET. Therefore, the total losses of the converter will be
decreased and also, the efficiency of the converter will be high.

The normalized voltage stress across the power diode

Figure 7c shows the maximum voltage stress across power diode versus duty-cycle variations. The
normalized voltage stress value across the power diode of the proposed converter limited to 0.25
when the voltage gain is higher. Based on Figure 7c, it can be said that the normalized voltage stress
across power diode of the proposed converter is lower than the other structures (Axelrod, Beck, and
Berkovich 2015; Maheri et al. 2017). Using the lower nominal values (voltage/current) leads to
decrease in the overall cost of the converter.

Experimental results
Figure 8a,b show the efficiency of the proposed converter versus power level and load current
variations, respectively. In this section, the experimental results are provided to confirm the
theoretical analysis of the proposed converter. The cost and characteristics of the power devices
are shown in Table 2. Generally, the overall cost of the proposed converter is low. Based on Table 2,
it is clear that the used components have a low nominal value to transfer the specified power level.
 14
H. YE ET AL.

Table 1. The comparison between the proposed converter and the other structures.
Voltage Switch normalized Switch normalized Diodes normalized No. of No. of No. of No. of coupled No. of Power Eff.
Converter gain voltage stress current stress voltage stress switch diode inductor inductor capacitor [W] [%]
Conventional boot 1 1 1 1 1 1 1 0 1 - -
1D
Conventional SEPIC D 1 1 1 1 1 2 0 1 - -
1D
(Banaei and Sani 2018) 3D Mþ3 3D Mþ3 1 3 4 0 6 200 94.60
1D 3M 1D 3M
(Pourjafar et al. 2018) Nþ1 1 4 1 N 1 3 2 1 4 190 94.05
1D Nþ1 1D Nþ1 , Nþ1
(Lee, Kim, and Choi 2013) Nþ1 1 - Mþ3 4 N+1 3 0 N+2 200 94.6
1D Nþ1 pffiffi 3M
(Banaei, Ardi, and 2D Mþ2 2 D Mþ2 1 2 2 0 3 200 94.33
1D 2M 1D 2M
Farakhor 2014)
(Ismail et al. 2008) 2D M1 2 M1 1 3 1 0 3 190 92.45
1D M 1D M
(Sabzali, Ismail, and 2þD Mþ1 M1
pffiffiffiffiffi Mþ1 1 4 2 0 5 190 94.23
1D 3M M Mþ1 3M
Behbehani 2015) M2

(Maheri et al. 2017) 1þðNþ1ÞD MþNþ1 1 Mþ1 N+2 2N N+2 0 1 190 93.65
1D MðNþ2Þ ð1DÞ M
(Axelrod, Beck, and 1þNðDþ1Þ Mþ2 nþ3 Mþ2 1 2N+2 1 0 2N+2 190 93.95
1D 5M 4ð1DÞ 2:5M
Berkovich 2015)
Proposed converter 1þ3D Mþ3 2D Mþ3 2 8 4 0 9 190 94.85
1D 4M 1D 4M
 ENERGY SOURCES, PART A: RECOVERY, UTILIZATION, AND ENVIRONMENTAL EFFECTS 15

Figure 7. Comparison between the proposed structure and other structures. (a) The voltage gain versus duty-cycle variations, (b) the
normalized voltage stress across power MOSFET versus duty-cycle variations, (c) the normalized voltage stress across power diode
versus duty-cycle variations.

Figure 8. Prototype of the proposed converter and efficiency curve. (a) The measured efficiency of the proposed converter versus
power level. (b) The measured efficiency of the proposed converter versus load current. (c) Total losses of the components. (d)
Laboratory prototype.

The experimental and simulation results of the proposed converter with 190 W at operating 40
kHz are shown in Table 3. By observing achieved results, can be said that these values confirm each
other, reasonably well.
16 H. YE ET AL.

Table 2. Cost and characteristics of the components.

Components
Input voltage 24 V
Switching frequency 40 kHz
Inductor L1 & L11 1 mH
RInductor 33 mΩ
Inductor L2 & L22 580 µH
C1, C2, C3, C11, C22, C33 330 µF
Co1 & Co2 330 µF
Co 470 µF, 450 V
RCapacitor 33 mΩ
Power switch IRFP260
RDS(on) 50 mΩ
All diodes MUR1560

Table 3. Comparison between the simulation and experimental results of the proposed converter.
Peak voltage, Ave. and RMS current of the components Theo. Sim. Exp.
Peak voltage across switch S1 [V] 60 59.95 59.90
Average current switch S1 [A] 3.40 3.27 3.28
RMS current switch S1 [A] 4.35 4.23 4.25
Peak voltage across diode D1 [V] 60 59.8 59.7
Average current diode D1 [A] 1.14 1.09 1.10
RMS current diode D1 [A] 1.82 1.74 1.75

Figure 8a shows the efficiency of the proposed converter versus power level variations for D=
0.6. By observing Figure 8a, the maximum efficiency of the proposed converter will be achieved
about 120 W around which is equal to 96.7%. The efficiency is 94.85 for 190 W power level.
According to Figure 8b, the maximum efficiency is obtained in 0.68 A load current. For
a laboratory prototype, the maximum efficiency is obtained about 1.13 A load current. Based on
Figure 8a,b, the efficiency of the proposed converter is limited to 92.1% for high power levels, so the
overall efficiency has 4.6% tolerances in all power levels. By observing Figure 8c, the total losses of
the power components are shown. It is clear that the major losses of the converter related to power
semiconductors (power MOSFETs and power diodes). Figure 8d shows the laboratory prototype of
the proposed converter.
In order to confirm the accuracy of the theoretical analysis, the experimental results of the
laboratory prototype are shown in Figures 9 and 11. Figure 9a illustrates the laboratory prototype
of the proposed converter. Figure 9b shows the storage voltage on the capacitors C1 and C2 are about
35.6 V which confirms (26). Figure 9c illustrates the voltage waveforms of the capacitors Co1 and Co2.
The voltage values of the capacitors Co1 and Co2 are about 70 which is confirmed (26). Figure 9d
shows the output voltage which is about 162 V. Using the obtained value of the output voltage and
(30), can be said these values confirm each other well.
Figure 10 illustrates the maximum voltage across the power MOSFET S1 and power diodes D1, D2
and D4. Based on Figure 10a, it is clear that the spike voltage of the power MOSFET S1 is about
normal for this power level. In fact, the maximum voltage value is limited to the voltage value of the
capacitor which is used in the voltage multiplier cell. The maximum voltage of the power MOSFET
S1 is about 59.9 V which is confirmed main waveforms of the proposed converter that is shown in
Figure 3. Figure 10b shows the maximum voltage stress across the diode D1 which is about 59.7
V. Figure 10b,c shows the voltage stress across the power diodes D2 and D4, which are about 59.3
V and 59.4 V, respectively. These values are confirmed theoretical analysis which is shown in
Figure 3 as well as reasonably.
Generally, the normalized voltage stress across the power MOSFETs and diodes and also, the
spike of these power semiconductors is low. Therefore, using a MOSFET and diode with lower
 ENERGY SOURCES, PART A: RECOVERY, UTILIZATION, AND ENVIRONMENTAL EFFECTS 17

Figure 9. Experimental waveforms. (a) The laboratory prototype. (b) The voltage of the capacitors C1 and C2. (c) The voltage of
capacitors Co1 and Co2. (d) The output voltage Vo.

Figure 10. Experimental waveforms. (a) The maximum voltage of the MOSFET S1. (b) The maximum voltage of the diode D1. (c) The
maximum voltage of the diode D2. (d) The maximum voltage of the diode D4.

nominal voltage/current cause to decrease the power losses across the power semiconductors which
the major losses are included.
Figure 10 illustrates the current waveforms of the inductors L1, L2, L11 and L22. Based on Figure
11a, the average current of the inductor L1 is about 4.36 A. The current ripple of the inductor L1 is
about 0.32 A. The ripple of the inductor L1 is about 7.33% which is confirmed (52). By observing
Figure 11b, the average current of the inductor L2 is about 1.1 A which his peak-to-peak value is 0.8
A until 1.4 A. Based on Figure 11c, the average current of the inductor L11 is about 4.36 A as the
average current of the inductor L1. The peak-to-peak ripple of the inductor L11 is about 7.35% which
is confirmed (52). The average current of the inductor L22 is about 1.1 A which is shown in
Figure 11d.
18 H. YE ET AL.

Figure 11. Experimental waveforms. (a) The current of the inductor L1. (b) The current of the inductor L2. (c) The current of the
inductor L11. (d) The current of the inductor L22.

Figure 12. Dynamic response, (a) for 50% voltage drop at the input voltage value, (b) for 50% changes at the output load (load is
150%).
 ENERGY SOURCES, PART A: RECOVERY, UTILIZATION, AND ENVIRONMENTAL EFFECTS 19

In this section, two voltage sources are used at the input side which each source is 12 V and
output power is 182 W. As it can be seen from Figure 12, when one of the input sources is suddenly
failed, the output voltage has about 81 V changes. After a small time (about 750 ms), the output
voltage is decreased to 81 V and stays constant. Also, the output power is decreased to 90 W. As
a result, the voltage drop in the input source will not affect the load regulation.
Based on Figure 12b, it is clear that the changes of output load (when the output load is 150%)
have not effected on output voltage value. Generally, the output voltage has about 8% tolerances for
50% changes at the load. Therefore, it can be said that the proposed converter capable to maintain its
steady state.

Conclusions
In this paper, a new high step-up interleaved dc/dc converter with high-efficiency suitable for
renewable energy applications is presented. The proposed converter using voltage multiplier unit
(combination of diode/capacitor/inductor) for increasing the output voltage level. The normalized
voltage stress across the semiconductors (power diodes and MOSFETs) is low. Generally, the lower
on-state resistance of the power MOSFETs and the nominal value of the power diodes (pick voltage
and pick current) with a low value is used which this causes to increase the efficiency and decrease
the overall cost of the proposed converter. Generally, the overall cost of the proposed converter is
decreased using semiconductors with low nominal values. The experimental prototype of the
proposed converter is built and tested in 190 W which is output power is achieved 182 W with 40
kHz switching frequency. The maximum efficiency of the proposed converter is about 96.7% at 115
W. The experimental results illustrate that the proposed converter capable to achieve the overall
efficiency higher than about 92.1% in all power levels. The tolerances efficiency of the proposed
converter is about 4.6% for all power limits. As a result, the proposed converter is a good candidate
for renewable applications.

Funding
This work is supported by the 2019 Shanghai College and University Teachers’ Training Program - visiting the
university in China and the 2017 Doctoral Startup Scientific Research Foundation of Shanghai Ocean University under
[Grant No. A2-2006-00-200319].

ORCID
Noradin Ghadimi http://orcid.org/0000-0002-0867-9244

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